trap signals for "-serial mon:stdio"
[qemu.git] / target-sparc / int64_helper.c
1 /*
2 * Sparc64 interrupt helpers
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "helper.h"
22 #include "trace.h"
23
24 #define DEBUG_PCALL
25
26 #ifdef DEBUG_PCALL
27 static const char * const excp_names[0x80] = {
28 [TT_TFAULT] = "Instruction Access Fault",
29 [TT_TMISS] = "Instruction Access MMU Miss",
30 [TT_CODE_ACCESS] = "Instruction Access Error",
31 [TT_ILL_INSN] = "Illegal Instruction",
32 [TT_PRIV_INSN] = "Privileged Instruction",
33 [TT_NFPU_INSN] = "FPU Disabled",
34 [TT_FP_EXCP] = "FPU Exception",
35 [TT_TOVF] = "Tag Overflow",
36 [TT_CLRWIN] = "Clean Windows",
37 [TT_DIV_ZERO] = "Division By Zero",
38 [TT_DFAULT] = "Data Access Fault",
39 [TT_DMISS] = "Data Access MMU Miss",
40 [TT_DATA_ACCESS] = "Data Access Error",
41 [TT_DPROT] = "Data Protection Error",
42 [TT_UNALIGNED] = "Unaligned Memory Access",
43 [TT_PRIV_ACT] = "Privileged Action",
44 [TT_EXTINT | 0x1] = "External Interrupt 1",
45 [TT_EXTINT | 0x2] = "External Interrupt 2",
46 [TT_EXTINT | 0x3] = "External Interrupt 3",
47 [TT_EXTINT | 0x4] = "External Interrupt 4",
48 [TT_EXTINT | 0x5] = "External Interrupt 5",
49 [TT_EXTINT | 0x6] = "External Interrupt 6",
50 [TT_EXTINT | 0x7] = "External Interrupt 7",
51 [TT_EXTINT | 0x8] = "External Interrupt 8",
52 [TT_EXTINT | 0x9] = "External Interrupt 9",
53 [TT_EXTINT | 0xa] = "External Interrupt 10",
54 [TT_EXTINT | 0xb] = "External Interrupt 11",
55 [TT_EXTINT | 0xc] = "External Interrupt 12",
56 [TT_EXTINT | 0xd] = "External Interrupt 13",
57 [TT_EXTINT | 0xe] = "External Interrupt 14",
58 [TT_EXTINT | 0xf] = "External Interrupt 15",
59 };
60 #endif
61
62 void sparc_cpu_do_interrupt(CPUState *cs)
63 {
64 SPARCCPU *cpu = SPARC_CPU(cs);
65 CPUSPARCState *env = &cpu->env;
66 int intno = env->exception_index;
67 trap_state *tsptr;
68
69 /* Compute PSR before exposing state. */
70 if (env->cc_op != CC_OP_FLAGS) {
71 cpu_get_psr(env);
72 }
73
74 #ifdef DEBUG_PCALL
75 if (qemu_loglevel_mask(CPU_LOG_INT)) {
76 static int count;
77 const char *name;
78
79 if (intno < 0 || intno >= 0x180) {
80 name = "Unknown";
81 } else if (intno >= 0x100) {
82 name = "Trap Instruction";
83 } else if (intno >= 0xc0) {
84 name = "Window Fill";
85 } else if (intno >= 0x80) {
86 name = "Window Spill";
87 } else {
88 name = excp_names[intno];
89 if (!name) {
90 name = "Unknown";
91 }
92 }
93
94 qemu_log("%6d: %s (v=%04x)\n", count, name, intno);
95 log_cpu_state(env, 0);
96 #if 0
97 {
98 int i;
99 uint8_t *ptr;
100
101 qemu_log(" code=");
102 ptr = (uint8_t *)env->pc;
103 for (i = 0; i < 16; i++) {
104 qemu_log(" %02x", ldub(ptr + i));
105 }
106 qemu_log("\n");
107 }
108 #endif
109 count++;
110 }
111 #endif
112 #if !defined(CONFIG_USER_ONLY)
113 if (env->tl >= env->maxtl) {
114 cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
115 " Error state", env->exception_index, env->tl, env->maxtl);
116 return;
117 }
118 #endif
119 if (env->tl < env->maxtl - 1) {
120 env->tl++;
121 } else {
122 env->pstate |= PS_RED;
123 if (env->tl < env->maxtl) {
124 env->tl++;
125 }
126 }
127 tsptr = cpu_tsptr(env);
128
129 tsptr->tstate = (cpu_get_ccr(env) << 32) |
130 ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |
131 cpu_get_cwp64(env);
132 tsptr->tpc = env->pc;
133 tsptr->tnpc = env->npc;
134 tsptr->tt = intno;
135
136 switch (intno) {
137 case TT_IVEC:
138 cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG);
139 break;
140 case TT_TFAULT:
141 case TT_DFAULT:
142 case TT_TMISS ... TT_TMISS + 3:
143 case TT_DMISS ... TT_DMISS + 3:
144 case TT_DPROT ... TT_DPROT + 3:
145 cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG);
146 break;
147 default:
148 cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_AG);
149 break;
150 }
151
152 if (intno == TT_CLRWIN) {
153 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1));
154 } else if ((intno & 0x1c0) == TT_SPILL) {
155 cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2));
156 } else if ((intno & 0x1c0) == TT_FILL) {
157 cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
158 }
159 env->tbr &= ~0x7fffULL;
160 env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
161 env->pc = env->tbr;
162 env->npc = env->pc + 4;
163 env->exception_index = -1;
164 }
165
166 trap_state *cpu_tsptr(CPUSPARCState* env)
167 {
168 return &env->ts[env->tl & MAXTL_MASK];
169 }
170
171 static bool do_modify_softint(CPUSPARCState *env, uint32_t value)
172 {
173 if (env->softint != value) {
174 env->softint = value;
175 #if !defined(CONFIG_USER_ONLY)
176 if (cpu_interrupts_enabled(env)) {
177 cpu_check_irqs(env);
178 }
179 #endif
180 return true;
181 }
182 return false;
183 }
184
185 void helper_set_softint(CPUSPARCState *env, uint64_t value)
186 {
187 if (do_modify_softint(env, env->softint | (uint32_t)value)) {
188 trace_int_helper_set_softint(env->softint);
189 }
190 }
191
192 void helper_clear_softint(CPUSPARCState *env, uint64_t value)
193 {
194 if (do_modify_softint(env, env->softint & (uint32_t)~value)) {
195 trace_int_helper_clear_softint(env->softint);
196 }
197 }
198
199 void helper_write_softint(CPUSPARCState *env, uint64_t value)
200 {
201 if (do_modify_softint(env, (uint32_t)value)) {
202 trace_int_helper_write_softint(env->softint);
203 }
204 }