cputlb: Change tlb_flush() argument to CPUState
[qemu.git] / target-sparc / ldst_helper.c
1 /*
2 * Helpers for loads and stores
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "helper.h"
22
23 //#define DEBUG_MMU
24 //#define DEBUG_MXCC
25 //#define DEBUG_UNALIGNED
26 //#define DEBUG_UNASSIGNED
27 //#define DEBUG_ASI
28 //#define DEBUG_CACHE_CONTROL
29
30 #ifdef DEBUG_MMU
31 #define DPRINTF_MMU(fmt, ...) \
32 do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
33 #else
34 #define DPRINTF_MMU(fmt, ...) do {} while (0)
35 #endif
36
37 #ifdef DEBUG_MXCC
38 #define DPRINTF_MXCC(fmt, ...) \
39 do { printf("MXCC: " fmt , ## __VA_ARGS__); } while (0)
40 #else
41 #define DPRINTF_MXCC(fmt, ...) do {} while (0)
42 #endif
43
44 #ifdef DEBUG_ASI
45 #define DPRINTF_ASI(fmt, ...) \
46 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
47 #endif
48
49 #ifdef DEBUG_CACHE_CONTROL
50 #define DPRINTF_CACHE_CONTROL(fmt, ...) \
51 do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
52 #else
53 #define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
54 #endif
55
56 #ifdef TARGET_SPARC64
57 #ifndef TARGET_ABI32
58 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
59 #else
60 #define AM_CHECK(env1) (1)
61 #endif
62 #endif
63
64 #define QT0 (env->qt0)
65 #define QT1 (env->qt1)
66
67 #if !defined(CONFIG_USER_ONLY)
68 static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env,
69 target_ulong addr, int is_write,
70 int is_user, uintptr_t retaddr);
71 #include "exec/softmmu_exec.h"
72 #define MMUSUFFIX _mmu
73 #define ALIGNED_ONLY
74
75 #define SHIFT 0
76 #include "exec/softmmu_template.h"
77
78 #define SHIFT 1
79 #include "exec/softmmu_template.h"
80
81 #define SHIFT 2
82 #include "exec/softmmu_template.h"
83
84 #define SHIFT 3
85 #include "exec/softmmu_template.h"
86 #endif
87
88 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
89 /* Calculates TSB pointer value for fault page size 8k or 64k */
90 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
91 uint64_t tag_access_register,
92 int page_size)
93 {
94 uint64_t tsb_base = tsb_register & ~0x1fffULL;
95 int tsb_split = (tsb_register & 0x1000ULL) ? 1 : 0;
96 int tsb_size = tsb_register & 0xf;
97
98 /* discard lower 13 bits which hold tag access context */
99 uint64_t tag_access_va = tag_access_register & ~0x1fffULL;
100
101 /* now reorder bits */
102 uint64_t tsb_base_mask = ~0x1fffULL;
103 uint64_t va = tag_access_va;
104
105 /* move va bits to correct position */
106 if (page_size == 8*1024) {
107 va >>= 9;
108 } else if (page_size == 64*1024) {
109 va >>= 12;
110 }
111
112 if (tsb_size) {
113 tsb_base_mask <<= tsb_size;
114 }
115
116 /* calculate tsb_base mask and adjust va if split is in use */
117 if (tsb_split) {
118 if (page_size == 8*1024) {
119 va &= ~(1ULL << (13 + tsb_size));
120 } else if (page_size == 64*1024) {
121 va |= (1ULL << (13 + tsb_size));
122 }
123 tsb_base_mask <<= 1;
124 }
125
126 return ((tsb_base & tsb_base_mask) | (va & ~tsb_base_mask)) & ~0xfULL;
127 }
128
129 /* Calculates tag target register value by reordering bits
130 in tag access register */
131 static uint64_t ultrasparc_tag_target(uint64_t tag_access_register)
132 {
133 return ((tag_access_register & 0x1fff) << 48) | (tag_access_register >> 22);
134 }
135
136 static void replace_tlb_entry(SparcTLBEntry *tlb,
137 uint64_t tlb_tag, uint64_t tlb_tte,
138 CPUSPARCState *env1)
139 {
140 target_ulong mask, size, va, offset;
141
142 /* flush page range if translation is valid */
143 if (TTE_IS_VALID(tlb->tte)) {
144 CPUState *cs = CPU(sparc_env_get_cpu(env1));
145
146 mask = 0xffffffffffffe000ULL;
147 mask <<= 3 * ((tlb->tte >> 61) & 3);
148 size = ~mask + 1;
149
150 va = tlb->tag & mask;
151
152 for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
153 tlb_flush_page(cs, va + offset);
154 }
155 }
156
157 tlb->tag = tlb_tag;
158 tlb->tte = tlb_tte;
159 }
160
161 static void demap_tlb(SparcTLBEntry *tlb, target_ulong demap_addr,
162 const char *strmmu, CPUSPARCState *env1)
163 {
164 unsigned int i;
165 target_ulong mask;
166 uint64_t context;
167
168 int is_demap_context = (demap_addr >> 6) & 1;
169
170 /* demap context */
171 switch ((demap_addr >> 4) & 3) {
172 case 0: /* primary */
173 context = env1->dmmu.mmu_primary_context;
174 break;
175 case 1: /* secondary */
176 context = env1->dmmu.mmu_secondary_context;
177 break;
178 case 2: /* nucleus */
179 context = 0;
180 break;
181 case 3: /* reserved */
182 default:
183 return;
184 }
185
186 for (i = 0; i < 64; i++) {
187 if (TTE_IS_VALID(tlb[i].tte)) {
188
189 if (is_demap_context) {
190 /* will remove non-global entries matching context value */
191 if (TTE_IS_GLOBAL(tlb[i].tte) ||
192 !tlb_compare_context(&tlb[i], context)) {
193 continue;
194 }
195 } else {
196 /* demap page
197 will remove any entry matching VA */
198 mask = 0xffffffffffffe000ULL;
199 mask <<= 3 * ((tlb[i].tte >> 61) & 3);
200
201 if (!compare_masked(demap_addr, tlb[i].tag, mask)) {
202 continue;
203 }
204
205 /* entry should be global or matching context value */
206 if (!TTE_IS_GLOBAL(tlb[i].tte) &&
207 !tlb_compare_context(&tlb[i], context)) {
208 continue;
209 }
210 }
211
212 replace_tlb_entry(&tlb[i], 0, 0, env1);
213 #ifdef DEBUG_MMU
214 DPRINTF_MMU("%s demap invalidated entry [%02u]\n", strmmu, i);
215 dump_mmu(stdout, fprintf, env1);
216 #endif
217 }
218 }
219 }
220
221 static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
222 uint64_t tlb_tag, uint64_t tlb_tte,
223 const char *strmmu, CPUSPARCState *env1)
224 {
225 unsigned int i, replace_used;
226
227 /* Try replacing invalid entry */
228 for (i = 0; i < 64; i++) {
229 if (!TTE_IS_VALID(tlb[i].tte)) {
230 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
231 #ifdef DEBUG_MMU
232 DPRINTF_MMU("%s lru replaced invalid entry [%i]\n", strmmu, i);
233 dump_mmu(stdout, fprintf, env1);
234 #endif
235 return;
236 }
237 }
238
239 /* All entries are valid, try replacing unlocked entry */
240
241 for (replace_used = 0; replace_used < 2; ++replace_used) {
242
243 /* Used entries are not replaced on first pass */
244
245 for (i = 0; i < 64; i++) {
246 if (!TTE_IS_LOCKED(tlb[i].tte) && !TTE_IS_USED(tlb[i].tte)) {
247
248 replace_tlb_entry(&tlb[i], tlb_tag, tlb_tte, env1);
249 #ifdef DEBUG_MMU
250 DPRINTF_MMU("%s lru replaced unlocked %s entry [%i]\n",
251 strmmu, (replace_used ? "used" : "unused"), i);
252 dump_mmu(stdout, fprintf, env1);
253 #endif
254 return;
255 }
256 }
257
258 /* Now reset used bit and search for unused entries again */
259
260 for (i = 0; i < 64; i++) {
261 TTE_SET_UNUSED(tlb[i].tte);
262 }
263 }
264
265 #ifdef DEBUG_MMU
266 DPRINTF_MMU("%s lru replacement failed: no entries available\n", strmmu);
267 #endif
268 /* error state? */
269 }
270
271 #endif
272
273 static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)
274 {
275 #ifdef TARGET_SPARC64
276 if (AM_CHECK(env1)) {
277 addr &= 0xffffffffULL;
278 }
279 #endif
280 return addr;
281 }
282
283 /* returns true if access using this ASI is to have address translated by MMU
284 otherwise access is to raw physical address */
285 static inline int is_translating_asi(int asi)
286 {
287 #ifdef TARGET_SPARC64
288 /* Ultrasparc IIi translating asi
289 - note this list is defined by cpu implementation
290 */
291 switch (asi) {
292 case 0x04 ... 0x11:
293 case 0x16 ... 0x19:
294 case 0x1E ... 0x1F:
295 case 0x24 ... 0x2C:
296 case 0x70 ... 0x73:
297 case 0x78 ... 0x79:
298 case 0x80 ... 0xFF:
299 return 1;
300
301 default:
302 return 0;
303 }
304 #else
305 /* TODO: check sparc32 bits */
306 return 0;
307 #endif
308 }
309
310 static inline target_ulong asi_address_mask(CPUSPARCState *env,
311 int asi, target_ulong addr)
312 {
313 if (is_translating_asi(asi)) {
314 return address_mask(env, addr);
315 } else {
316 return addr;
317 }
318 }
319
320 void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align)
321 {
322 if (addr & align) {
323 #ifdef DEBUG_UNALIGNED
324 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
325 "\n", addr, env->pc);
326 #endif
327 helper_raise_exception(env, TT_UNALIGNED);
328 }
329 }
330
331 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) && \
332 defined(DEBUG_MXCC)
333 static void dump_mxcc(CPUSPARCState *env)
334 {
335 printf("mxccdata: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
336 "\n",
337 env->mxccdata[0], env->mxccdata[1],
338 env->mxccdata[2], env->mxccdata[3]);
339 printf("mxccregs: %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
340 "\n"
341 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64
342 "\n",
343 env->mxccregs[0], env->mxccregs[1],
344 env->mxccregs[2], env->mxccregs[3],
345 env->mxccregs[4], env->mxccregs[5],
346 env->mxccregs[6], env->mxccregs[7]);
347 }
348 #endif
349
350 #if (defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY)) \
351 && defined(DEBUG_ASI)
352 static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
353 uint64_t r1)
354 {
355 switch (size) {
356 case 1:
357 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt,
358 addr, asi, r1 & 0xff);
359 break;
360 case 2:
361 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt,
362 addr, asi, r1 & 0xffff);
363 break;
364 case 4:
365 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt,
366 addr, asi, r1 & 0xffffffff);
367 break;
368 case 8:
369 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt,
370 addr, asi, r1);
371 break;
372 }
373 }
374 #endif
375
376 #ifndef TARGET_SPARC64
377 #ifndef CONFIG_USER_ONLY
378
379
380 /* Leon3 cache control */
381
382 static void leon3_cache_control_st(CPUSPARCState *env, target_ulong addr,
383 uint64_t val, int size)
384 {
385 DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
386 addr, val, size);
387
388 if (size != 4) {
389 DPRINTF_CACHE_CONTROL("32bits only\n");
390 return;
391 }
392
393 switch (addr) {
394 case 0x00: /* Cache control */
395
396 /* These values must always be read as zeros */
397 val &= ~CACHE_CTRL_FD;
398 val &= ~CACHE_CTRL_FI;
399 val &= ~CACHE_CTRL_IB;
400 val &= ~CACHE_CTRL_IP;
401 val &= ~CACHE_CTRL_DP;
402
403 env->cache_control = val;
404 break;
405 case 0x04: /* Instruction cache configuration */
406 case 0x08: /* Data cache configuration */
407 /* Read Only */
408 break;
409 default:
410 DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
411 break;
412 };
413 }
414
415 static uint64_t leon3_cache_control_ld(CPUSPARCState *env, target_ulong addr,
416 int size)
417 {
418 uint64_t ret = 0;
419
420 if (size != 4) {
421 DPRINTF_CACHE_CONTROL("32bits only\n");
422 return 0;
423 }
424
425 switch (addr) {
426 case 0x00: /* Cache control */
427 ret = env->cache_control;
428 break;
429
430 /* Configuration registers are read and only always keep those
431 predefined values */
432
433 case 0x04: /* Instruction cache configuration */
434 ret = 0x10220000;
435 break;
436 case 0x08: /* Data cache configuration */
437 ret = 0x18220000;
438 break;
439 default:
440 DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
441 break;
442 };
443 DPRINTF_CACHE_CONTROL("ld addr:%08x, ret:0x%" PRIx64 ", size:%d\n",
444 addr, ret, size);
445 return ret;
446 }
447
448 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
449 int sign)
450 {
451 CPUState *cs = CPU(sparc_env_get_cpu(env));
452 uint64_t ret = 0;
453 #if defined(DEBUG_MXCC) || defined(DEBUG_ASI)
454 uint32_t last_addr = addr;
455 #endif
456
457 helper_check_align(env, addr, size - 1);
458 switch (asi) {
459 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
460 switch (addr) {
461 case 0x00: /* Leon3 Cache Control */
462 case 0x08: /* Leon3 Instruction Cache config */
463 case 0x0C: /* Leon3 Date Cache config */
464 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
465 ret = leon3_cache_control_ld(env, addr, size);
466 }
467 break;
468 case 0x01c00a00: /* MXCC control register */
469 if (size == 8) {
470 ret = env->mxccregs[3];
471 } else {
472 qemu_log_mask(LOG_UNIMP,
473 "%08x: unimplemented access size: %d\n", addr,
474 size);
475 }
476 break;
477 case 0x01c00a04: /* MXCC control register */
478 if (size == 4) {
479 ret = env->mxccregs[3];
480 } else {
481 qemu_log_mask(LOG_UNIMP,
482 "%08x: unimplemented access size: %d\n", addr,
483 size);
484 }
485 break;
486 case 0x01c00c00: /* Module reset register */
487 if (size == 8) {
488 ret = env->mxccregs[5];
489 /* should we do something here? */
490 } else {
491 qemu_log_mask(LOG_UNIMP,
492 "%08x: unimplemented access size: %d\n", addr,
493 size);
494 }
495 break;
496 case 0x01c00f00: /* MBus port address register */
497 if (size == 8) {
498 ret = env->mxccregs[7];
499 } else {
500 qemu_log_mask(LOG_UNIMP,
501 "%08x: unimplemented access size: %d\n", addr,
502 size);
503 }
504 break;
505 default:
506 qemu_log_mask(LOG_UNIMP,
507 "%08x: unimplemented address, size: %d\n", addr,
508 size);
509 break;
510 }
511 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, "
512 "addr = %08x -> ret = %" PRIx64 ","
513 "addr = %08x\n", asi, size, sign, last_addr, ret, addr);
514 #ifdef DEBUG_MXCC
515 dump_mxcc(env);
516 #endif
517 break;
518 case 3: /* MMU probe */
519 case 0x18: /* LEON3 MMU probe */
520 {
521 int mmulev;
522
523 mmulev = (addr >> 8) & 15;
524 if (mmulev > 4) {
525 ret = 0;
526 } else {
527 ret = mmu_probe(env, addr, mmulev);
528 }
529 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n",
530 addr, mmulev, ret);
531 }
532 break;
533 case 4: /* read MMU regs */
534 case 0x19: /* LEON3 read MMU regs */
535 {
536 int reg = (addr >> 8) & 0x1f;
537
538 ret = env->mmuregs[reg];
539 if (reg == 3) { /* Fault status cleared on read */
540 env->mmuregs[3] = 0;
541 } else if (reg == 0x13) { /* Fault status read */
542 ret = env->mmuregs[3];
543 } else if (reg == 0x14) { /* Fault address read */
544 ret = env->mmuregs[4];
545 }
546 DPRINTF_MMU("mmu_read: reg[%d] = 0x%08" PRIx64 "\n", reg, ret);
547 }
548 break;
549 case 5: /* Turbosparc ITLB Diagnostic */
550 case 6: /* Turbosparc DTLB Diagnostic */
551 case 7: /* Turbosparc IOTLB Diagnostic */
552 break;
553 case 9: /* Supervisor code access */
554 switch (size) {
555 case 1:
556 ret = cpu_ldub_code(env, addr);
557 break;
558 case 2:
559 ret = cpu_lduw_code(env, addr);
560 break;
561 default:
562 case 4:
563 ret = cpu_ldl_code(env, addr);
564 break;
565 case 8:
566 ret = cpu_ldq_code(env, addr);
567 break;
568 }
569 break;
570 case 0xa: /* User data access */
571 switch (size) {
572 case 1:
573 ret = cpu_ldub_user(env, addr);
574 break;
575 case 2:
576 ret = cpu_lduw_user(env, addr);
577 break;
578 default:
579 case 4:
580 ret = cpu_ldl_user(env, addr);
581 break;
582 case 8:
583 ret = cpu_ldq_user(env, addr);
584 break;
585 }
586 break;
587 case 0xb: /* Supervisor data access */
588 case 0x80:
589 switch (size) {
590 case 1:
591 ret = cpu_ldub_kernel(env, addr);
592 break;
593 case 2:
594 ret = cpu_lduw_kernel(env, addr);
595 break;
596 default:
597 case 4:
598 ret = cpu_ldl_kernel(env, addr);
599 break;
600 case 8:
601 ret = cpu_ldq_kernel(env, addr);
602 break;
603 }
604 break;
605 case 0xc: /* I-cache tag */
606 case 0xd: /* I-cache data */
607 case 0xe: /* D-cache tag */
608 case 0xf: /* D-cache data */
609 break;
610 case 0x20: /* MMU passthrough */
611 case 0x1c: /* LEON MMU passthrough */
612 switch (size) {
613 case 1:
614 ret = ldub_phys(cs->as, addr);
615 break;
616 case 2:
617 ret = lduw_phys(cs->as, addr);
618 break;
619 default:
620 case 4:
621 ret = ldl_phys(cs->as, addr);
622 break;
623 case 8:
624 ret = ldq_phys(cs->as, addr);
625 break;
626 }
627 break;
628 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
629 switch (size) {
630 case 1:
631 ret = ldub_phys(cs->as, (hwaddr)addr
632 | ((hwaddr)(asi & 0xf) << 32));
633 break;
634 case 2:
635 ret = lduw_phys(cs->as, (hwaddr)addr
636 | ((hwaddr)(asi & 0xf) << 32));
637 break;
638 default:
639 case 4:
640 ret = ldl_phys(cs->as, (hwaddr)addr
641 | ((hwaddr)(asi & 0xf) << 32));
642 break;
643 case 8:
644 ret = ldq_phys(cs->as, (hwaddr)addr
645 | ((hwaddr)(asi & 0xf) << 32));
646 break;
647 }
648 break;
649 case 0x30: /* Turbosparc secondary cache diagnostic */
650 case 0x31: /* Turbosparc RAM snoop */
651 case 0x32: /* Turbosparc page table descriptor diagnostic */
652 case 0x39: /* data cache diagnostic register */
653 ret = 0;
654 break;
655 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
656 {
657 int reg = (addr >> 8) & 3;
658
659 switch (reg) {
660 case 0: /* Breakpoint Value (Addr) */
661 ret = env->mmubpregs[reg];
662 break;
663 case 1: /* Breakpoint Mask */
664 ret = env->mmubpregs[reg];
665 break;
666 case 2: /* Breakpoint Control */
667 ret = env->mmubpregs[reg];
668 break;
669 case 3: /* Breakpoint Status */
670 ret = env->mmubpregs[reg];
671 env->mmubpregs[reg] = 0ULL;
672 break;
673 }
674 DPRINTF_MMU("read breakpoint reg[%d] 0x%016" PRIx64 "\n", reg,
675 ret);
676 }
677 break;
678 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
679 ret = env->mmubpctrv;
680 break;
681 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
682 ret = env->mmubpctrc;
683 break;
684 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
685 ret = env->mmubpctrs;
686 break;
687 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
688 ret = env->mmubpaction;
689 break;
690 case 8: /* User code access, XXX */
691 default:
692 cpu_unassigned_access(cs, addr, false, false, asi, size);
693 ret = 0;
694 break;
695 }
696 if (sign) {
697 switch (size) {
698 case 1:
699 ret = (int8_t) ret;
700 break;
701 case 2:
702 ret = (int16_t) ret;
703 break;
704 case 4:
705 ret = (int32_t) ret;
706 break;
707 default:
708 break;
709 }
710 }
711 #ifdef DEBUG_ASI
712 dump_asi("read ", last_addr, asi, size, ret);
713 #endif
714 return ret;
715 }
716
717 void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
718 int size)
719 {
720 SPARCCPU *cpu = sparc_env_get_cpu(env);
721 CPUState *cs = CPU(cpu);
722
723 helper_check_align(env, addr, size - 1);
724 switch (asi) {
725 case 2: /* SuperSparc MXCC registers and Leon3 cache control */
726 switch (addr) {
727 case 0x00: /* Leon3 Cache Control */
728 case 0x08: /* Leon3 Instruction Cache config */
729 case 0x0C: /* Leon3 Date Cache config */
730 if (env->def->features & CPU_FEATURE_CACHE_CTRL) {
731 leon3_cache_control_st(env, addr, val, size);
732 }
733 break;
734
735 case 0x01c00000: /* MXCC stream data register 0 */
736 if (size == 8) {
737 env->mxccdata[0] = val;
738 } else {
739 qemu_log_mask(LOG_UNIMP,
740 "%08x: unimplemented access size: %d\n", addr,
741 size);
742 }
743 break;
744 case 0x01c00008: /* MXCC stream data register 1 */
745 if (size == 8) {
746 env->mxccdata[1] = val;
747 } else {
748 qemu_log_mask(LOG_UNIMP,
749 "%08x: unimplemented access size: %d\n", addr,
750 size);
751 }
752 break;
753 case 0x01c00010: /* MXCC stream data register 2 */
754 if (size == 8) {
755 env->mxccdata[2] = val;
756 } else {
757 qemu_log_mask(LOG_UNIMP,
758 "%08x: unimplemented access size: %d\n", addr,
759 size);
760 }
761 break;
762 case 0x01c00018: /* MXCC stream data register 3 */
763 if (size == 8) {
764 env->mxccdata[3] = val;
765 } else {
766 qemu_log_mask(LOG_UNIMP,
767 "%08x: unimplemented access size: %d\n", addr,
768 size);
769 }
770 break;
771 case 0x01c00100: /* MXCC stream source */
772 if (size == 8) {
773 env->mxccregs[0] = val;
774 } else {
775 qemu_log_mask(LOG_UNIMP,
776 "%08x: unimplemented access size: %d\n", addr,
777 size);
778 }
779 env->mxccdata[0] = ldq_phys(cs->as,
780 (env->mxccregs[0] & 0xffffffffULL) +
781 0);
782 env->mxccdata[1] = ldq_phys(cs->as,
783 (env->mxccregs[0] & 0xffffffffULL) +
784 8);
785 env->mxccdata[2] = ldq_phys(cs->as,
786 (env->mxccregs[0] & 0xffffffffULL) +
787 16);
788 env->mxccdata[3] = ldq_phys(cs->as,
789 (env->mxccregs[0] & 0xffffffffULL) +
790 24);
791 break;
792 case 0x01c00200: /* MXCC stream destination */
793 if (size == 8) {
794 env->mxccregs[1] = val;
795 } else {
796 qemu_log_mask(LOG_UNIMP,
797 "%08x: unimplemented access size: %d\n", addr,
798 size);
799 }
800 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 0,
801 env->mxccdata[0]);
802 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 8,
803 env->mxccdata[1]);
804 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 16,
805 env->mxccdata[2]);
806 stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 24,
807 env->mxccdata[3]);
808 break;
809 case 0x01c00a00: /* MXCC control register */
810 if (size == 8) {
811 env->mxccregs[3] = val;
812 } else {
813 qemu_log_mask(LOG_UNIMP,
814 "%08x: unimplemented access size: %d\n", addr,
815 size);
816 }
817 break;
818 case 0x01c00a04: /* MXCC control register */
819 if (size == 4) {
820 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL)
821 | val;
822 } else {
823 qemu_log_mask(LOG_UNIMP,
824 "%08x: unimplemented access size: %d\n", addr,
825 size);
826 }
827 break;
828 case 0x01c00e00: /* MXCC error register */
829 /* writing a 1 bit clears the error */
830 if (size == 8) {
831 env->mxccregs[6] &= ~val;
832 } else {
833 qemu_log_mask(LOG_UNIMP,
834 "%08x: unimplemented access size: %d\n", addr,
835 size);
836 }
837 break;
838 case 0x01c00f00: /* MBus port address register */
839 if (size == 8) {
840 env->mxccregs[7] = val;
841 } else {
842 qemu_log_mask(LOG_UNIMP,
843 "%08x: unimplemented access size: %d\n", addr,
844 size);
845 }
846 break;
847 default:
848 qemu_log_mask(LOG_UNIMP,
849 "%08x: unimplemented address, size: %d\n", addr,
850 size);
851 break;
852 }
853 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n",
854 asi, size, addr, val);
855 #ifdef DEBUG_MXCC
856 dump_mxcc(env);
857 #endif
858 break;
859 case 3: /* MMU flush */
860 case 0x18: /* LEON3 MMU flush */
861 {
862 int mmulev;
863
864 mmulev = (addr >> 8) & 15;
865 DPRINTF_MMU("mmu flush level %d\n", mmulev);
866 switch (mmulev) {
867 case 0: /* flush page */
868 tlb_flush_page(CPU(cpu), addr & 0xfffff000);
869 break;
870 case 1: /* flush segment (256k) */
871 case 2: /* flush region (16M) */
872 case 3: /* flush context (4G) */
873 case 4: /* flush entire */
874 tlb_flush(CPU(cpu), 1);
875 break;
876 default:
877 break;
878 }
879 #ifdef DEBUG_MMU
880 dump_mmu(stdout, fprintf, env);
881 #endif
882 }
883 break;
884 case 4: /* write MMU regs */
885 case 0x19: /* LEON3 write MMU regs */
886 {
887 int reg = (addr >> 8) & 0x1f;
888 uint32_t oldreg;
889
890 oldreg = env->mmuregs[reg];
891 switch (reg) {
892 case 0: /* Control Register */
893 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) |
894 (val & 0x00ffffff);
895 /* Mappings generated during no-fault mode or MMU
896 disabled mode are invalid in normal mode */
897 if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
898 (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
899 tlb_flush(CPU(cpu), 1);
900 }
901 break;
902 case 1: /* Context Table Pointer Register */
903 env->mmuregs[reg] = val & env->def->mmu_ctpr_mask;
904 break;
905 case 2: /* Context Register */
906 env->mmuregs[reg] = val & env->def->mmu_cxr_mask;
907 if (oldreg != env->mmuregs[reg]) {
908 /* we flush when the MMU context changes because
909 QEMU has no MMU context support */
910 tlb_flush(CPU(cpu), 1);
911 }
912 break;
913 case 3: /* Synchronous Fault Status Register with Clear */
914 case 4: /* Synchronous Fault Address Register */
915 break;
916 case 0x10: /* TLB Replacement Control Register */
917 env->mmuregs[reg] = val & env->def->mmu_trcr_mask;
918 break;
919 case 0x13: /* Synchronous Fault Status Register with Read
920 and Clear */
921 env->mmuregs[3] = val & env->def->mmu_sfsr_mask;
922 break;
923 case 0x14: /* Synchronous Fault Address Register */
924 env->mmuregs[4] = val;
925 break;
926 default:
927 env->mmuregs[reg] = val;
928 break;
929 }
930 if (oldreg != env->mmuregs[reg]) {
931 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n",
932 reg, oldreg, env->mmuregs[reg]);
933 }
934 #ifdef DEBUG_MMU
935 dump_mmu(stdout, fprintf, env);
936 #endif
937 }
938 break;
939 case 5: /* Turbosparc ITLB Diagnostic */
940 case 6: /* Turbosparc DTLB Diagnostic */
941 case 7: /* Turbosparc IOTLB Diagnostic */
942 break;
943 case 0xa: /* User data access */
944 switch (size) {
945 case 1:
946 cpu_stb_user(env, addr, val);
947 break;
948 case 2:
949 cpu_stw_user(env, addr, val);
950 break;
951 default:
952 case 4:
953 cpu_stl_user(env, addr, val);
954 break;
955 case 8:
956 cpu_stq_user(env, addr, val);
957 break;
958 }
959 break;
960 case 0xb: /* Supervisor data access */
961 case 0x80:
962 switch (size) {
963 case 1:
964 cpu_stb_kernel(env, addr, val);
965 break;
966 case 2:
967 cpu_stw_kernel(env, addr, val);
968 break;
969 default:
970 case 4:
971 cpu_stl_kernel(env, addr, val);
972 break;
973 case 8:
974 cpu_stq_kernel(env, addr, val);
975 break;
976 }
977 break;
978 case 0xc: /* I-cache tag */
979 case 0xd: /* I-cache data */
980 case 0xe: /* D-cache tag */
981 case 0xf: /* D-cache data */
982 case 0x10: /* I/D-cache flush page */
983 case 0x11: /* I/D-cache flush segment */
984 case 0x12: /* I/D-cache flush region */
985 case 0x13: /* I/D-cache flush context */
986 case 0x14: /* I/D-cache flush user */
987 break;
988 case 0x17: /* Block copy, sta access */
989 {
990 /* val = src
991 addr = dst
992 copy 32 bytes */
993 unsigned int i;
994 uint32_t src = val & ~3, dst = addr & ~3, temp;
995
996 for (i = 0; i < 32; i += 4, src += 4, dst += 4) {
997 temp = cpu_ldl_kernel(env, src);
998 cpu_stl_kernel(env, dst, temp);
999 }
1000 }
1001 break;
1002 case 0x1f: /* Block fill, stda access */
1003 {
1004 /* addr = dst
1005 fill 32 bytes with val */
1006 unsigned int i;
1007 uint32_t dst = addr & 7;
1008
1009 for (i = 0; i < 32; i += 8, dst += 8) {
1010 cpu_stq_kernel(env, dst, val);
1011 }
1012 }
1013 break;
1014 case 0x20: /* MMU passthrough */
1015 case 0x1c: /* LEON MMU passthrough */
1016 {
1017 switch (size) {
1018 case 1:
1019 stb_phys(cs->as, addr, val);
1020 break;
1021 case 2:
1022 stw_phys(cs->as, addr, val);
1023 break;
1024 case 4:
1025 default:
1026 stl_phys(cs->as, addr, val);
1027 break;
1028 case 8:
1029 stq_phys(cs->as, addr, val);
1030 break;
1031 }
1032 }
1033 break;
1034 case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */
1035 {
1036 switch (size) {
1037 case 1:
1038 stb_phys(cs->as, (hwaddr)addr
1039 | ((hwaddr)(asi & 0xf) << 32), val);
1040 break;
1041 case 2:
1042 stw_phys(cs->as, (hwaddr)addr
1043 | ((hwaddr)(asi & 0xf) << 32), val);
1044 break;
1045 case 4:
1046 default:
1047 stl_phys(cs->as, (hwaddr)addr
1048 | ((hwaddr)(asi & 0xf) << 32), val);
1049 break;
1050 case 8:
1051 stq_phys(cs->as, (hwaddr)addr
1052 | ((hwaddr)(asi & 0xf) << 32), val);
1053 break;
1054 }
1055 }
1056 break;
1057 case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */
1058 case 0x31: /* store buffer data, Ross RT620 I-cache flush or
1059 Turbosparc snoop RAM */
1060 case 0x32: /* store buffer control or Turbosparc page table
1061 descriptor diagnostic */
1062 case 0x36: /* I-cache flash clear */
1063 case 0x37: /* D-cache flash clear */
1064 break;
1065 case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
1066 {
1067 int reg = (addr >> 8) & 3;
1068
1069 switch (reg) {
1070 case 0: /* Breakpoint Value (Addr) */
1071 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1072 break;
1073 case 1: /* Breakpoint Mask */
1074 env->mmubpregs[reg] = (val & 0xfffffffffULL);
1075 break;
1076 case 2: /* Breakpoint Control */
1077 env->mmubpregs[reg] = (val & 0x7fULL);
1078 break;
1079 case 3: /* Breakpoint Status */
1080 env->mmubpregs[reg] = (val & 0xfULL);
1081 break;
1082 }
1083 DPRINTF_MMU("write breakpoint reg[%d] 0x%016x\n", reg,
1084 env->mmuregs[reg]);
1085 }
1086 break;
1087 case 0x49: /* SuperSPARC MMU Counter Breakpoint Value */
1088 env->mmubpctrv = val & 0xffffffff;
1089 break;
1090 case 0x4a: /* SuperSPARC MMU Counter Breakpoint Control */
1091 env->mmubpctrc = val & 0x3;
1092 break;
1093 case 0x4b: /* SuperSPARC MMU Counter Breakpoint Status */
1094 env->mmubpctrs = val & 0x3;
1095 break;
1096 case 0x4c: /* SuperSPARC MMU Breakpoint Action */
1097 env->mmubpaction = val & 0x1fff;
1098 break;
1099 case 8: /* User code access, XXX */
1100 case 9: /* Supervisor code access, XXX */
1101 default:
1102 cpu_unassigned_access(CPU(sparc_env_get_cpu(env)),
1103 addr, true, false, asi, size);
1104 break;
1105 }
1106 #ifdef DEBUG_ASI
1107 dump_asi("write", addr, asi, size, val);
1108 #endif
1109 }
1110
1111 #endif /* CONFIG_USER_ONLY */
1112 #else /* TARGET_SPARC64 */
1113
1114 #ifdef CONFIG_USER_ONLY
1115 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1116 int sign)
1117 {
1118 uint64_t ret = 0;
1119 #if defined(DEBUG_ASI)
1120 target_ulong last_addr = addr;
1121 #endif
1122
1123 if (asi < 0x80) {
1124 helper_raise_exception(env, TT_PRIV_ACT);
1125 }
1126
1127 helper_check_align(env, addr, size - 1);
1128 addr = asi_address_mask(env, asi, addr);
1129
1130 switch (asi) {
1131 case 0x82: /* Primary no-fault */
1132 case 0x8a: /* Primary no-fault LE */
1133 if (page_check_range(addr, size, PAGE_READ) == -1) {
1134 #ifdef DEBUG_ASI
1135 dump_asi("read ", last_addr, asi, size, ret);
1136 #endif
1137 return 0;
1138 }
1139 /* Fall through */
1140 case 0x80: /* Primary */
1141 case 0x88: /* Primary LE */
1142 {
1143 switch (size) {
1144 case 1:
1145 ret = ldub_raw(addr);
1146 break;
1147 case 2:
1148 ret = lduw_raw(addr);
1149 break;
1150 case 4:
1151 ret = ldl_raw(addr);
1152 break;
1153 default:
1154 case 8:
1155 ret = ldq_raw(addr);
1156 break;
1157 }
1158 }
1159 break;
1160 case 0x83: /* Secondary no-fault */
1161 case 0x8b: /* Secondary no-fault LE */
1162 if (page_check_range(addr, size, PAGE_READ) == -1) {
1163 #ifdef DEBUG_ASI
1164 dump_asi("read ", last_addr, asi, size, ret);
1165 #endif
1166 return 0;
1167 }
1168 /* Fall through */
1169 case 0x81: /* Secondary */
1170 case 0x89: /* Secondary LE */
1171 /* XXX */
1172 break;
1173 default:
1174 break;
1175 }
1176
1177 /* Convert from little endian */
1178 switch (asi) {
1179 case 0x88: /* Primary LE */
1180 case 0x89: /* Secondary LE */
1181 case 0x8a: /* Primary no-fault LE */
1182 case 0x8b: /* Secondary no-fault LE */
1183 switch (size) {
1184 case 2:
1185 ret = bswap16(ret);
1186 break;
1187 case 4:
1188 ret = bswap32(ret);
1189 break;
1190 case 8:
1191 ret = bswap64(ret);
1192 break;
1193 default:
1194 break;
1195 }
1196 default:
1197 break;
1198 }
1199
1200 /* Convert to signed number */
1201 if (sign) {
1202 switch (size) {
1203 case 1:
1204 ret = (int8_t) ret;
1205 break;
1206 case 2:
1207 ret = (int16_t) ret;
1208 break;
1209 case 4:
1210 ret = (int32_t) ret;
1211 break;
1212 default:
1213 break;
1214 }
1215 }
1216 #ifdef DEBUG_ASI
1217 dump_asi("read ", last_addr, asi, size, ret);
1218 #endif
1219 return ret;
1220 }
1221
1222 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1223 int asi, int size)
1224 {
1225 #ifdef DEBUG_ASI
1226 dump_asi("write", addr, asi, size, val);
1227 #endif
1228 if (asi < 0x80) {
1229 helper_raise_exception(env, TT_PRIV_ACT);
1230 }
1231
1232 helper_check_align(env, addr, size - 1);
1233 addr = asi_address_mask(env, asi, addr);
1234
1235 /* Convert to little endian */
1236 switch (asi) {
1237 case 0x88: /* Primary LE */
1238 case 0x89: /* Secondary LE */
1239 switch (size) {
1240 case 2:
1241 val = bswap16(val);
1242 break;
1243 case 4:
1244 val = bswap32(val);
1245 break;
1246 case 8:
1247 val = bswap64(val);
1248 break;
1249 default:
1250 break;
1251 }
1252 default:
1253 break;
1254 }
1255
1256 switch (asi) {
1257 case 0x80: /* Primary */
1258 case 0x88: /* Primary LE */
1259 {
1260 switch (size) {
1261 case 1:
1262 stb_raw(addr, val);
1263 break;
1264 case 2:
1265 stw_raw(addr, val);
1266 break;
1267 case 4:
1268 stl_raw(addr, val);
1269 break;
1270 case 8:
1271 default:
1272 stq_raw(addr, val);
1273 break;
1274 }
1275 }
1276 break;
1277 case 0x81: /* Secondary */
1278 case 0x89: /* Secondary LE */
1279 /* XXX */
1280 return;
1281
1282 case 0x82: /* Primary no-fault, RO */
1283 case 0x83: /* Secondary no-fault, RO */
1284 case 0x8a: /* Primary no-fault LE, RO */
1285 case 0x8b: /* Secondary no-fault LE, RO */
1286 default:
1287 helper_raise_exception(env, TT_DATA_ACCESS);
1288 return;
1289 }
1290 }
1291
1292 #else /* CONFIG_USER_ONLY */
1293
1294 uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
1295 int sign)
1296 {
1297 CPUState *cs = CPU(sparc_env_get_cpu(env));
1298 uint64_t ret = 0;
1299 #if defined(DEBUG_ASI)
1300 target_ulong last_addr = addr;
1301 #endif
1302
1303 asi &= 0xff;
1304
1305 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1306 || (cpu_has_hypervisor(env)
1307 && asi >= 0x30 && asi < 0x80
1308 && !(env->hpstate & HS_PRIV))) {
1309 helper_raise_exception(env, TT_PRIV_ACT);
1310 }
1311
1312 helper_check_align(env, addr, size - 1);
1313 addr = asi_address_mask(env, asi, addr);
1314
1315 /* process nonfaulting loads first */
1316 if ((asi & 0xf6) == 0x82) {
1317 int mmu_idx;
1318
1319 /* secondary space access has lowest asi bit equal to 1 */
1320 if (env->pstate & PS_PRIV) {
1321 mmu_idx = (asi & 1) ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX;
1322 } else {
1323 mmu_idx = (asi & 1) ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX;
1324 }
1325
1326 if (cpu_get_phys_page_nofault(env, addr, mmu_idx) == -1ULL) {
1327 #ifdef DEBUG_ASI
1328 dump_asi("read ", last_addr, asi, size, ret);
1329 #endif
1330 /* env->exception_index is set in get_physical_address_data(). */
1331 helper_raise_exception(env, cs->exception_index);
1332 }
1333
1334 /* convert nonfaulting load ASIs to normal load ASIs */
1335 asi &= ~0x02;
1336 }
1337
1338 switch (asi) {
1339 case 0x10: /* As if user primary */
1340 case 0x11: /* As if user secondary */
1341 case 0x18: /* As if user primary LE */
1342 case 0x19: /* As if user secondary LE */
1343 case 0x80: /* Primary */
1344 case 0x81: /* Secondary */
1345 case 0x88: /* Primary LE */
1346 case 0x89: /* Secondary LE */
1347 case 0xe2: /* UA2007 Primary block init */
1348 case 0xe3: /* UA2007 Secondary block init */
1349 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1350 if (cpu_hypervisor_mode(env)) {
1351 switch (size) {
1352 case 1:
1353 ret = cpu_ldub_hypv(env, addr);
1354 break;
1355 case 2:
1356 ret = cpu_lduw_hypv(env, addr);
1357 break;
1358 case 4:
1359 ret = cpu_ldl_hypv(env, addr);
1360 break;
1361 default:
1362 case 8:
1363 ret = cpu_ldq_hypv(env, addr);
1364 break;
1365 }
1366 } else {
1367 /* secondary space access has lowest asi bit equal to 1 */
1368 if (asi & 1) {
1369 switch (size) {
1370 case 1:
1371 ret = cpu_ldub_kernel_secondary(env, addr);
1372 break;
1373 case 2:
1374 ret = cpu_lduw_kernel_secondary(env, addr);
1375 break;
1376 case 4:
1377 ret = cpu_ldl_kernel_secondary(env, addr);
1378 break;
1379 default:
1380 case 8:
1381 ret = cpu_ldq_kernel_secondary(env, addr);
1382 break;
1383 }
1384 } else {
1385 switch (size) {
1386 case 1:
1387 ret = cpu_ldub_kernel(env, addr);
1388 break;
1389 case 2:
1390 ret = cpu_lduw_kernel(env, addr);
1391 break;
1392 case 4:
1393 ret = cpu_ldl_kernel(env, addr);
1394 break;
1395 default:
1396 case 8:
1397 ret = cpu_ldq_kernel(env, addr);
1398 break;
1399 }
1400 }
1401 }
1402 } else {
1403 /* secondary space access has lowest asi bit equal to 1 */
1404 if (asi & 1) {
1405 switch (size) {
1406 case 1:
1407 ret = cpu_ldub_user_secondary(env, addr);
1408 break;
1409 case 2:
1410 ret = cpu_lduw_user_secondary(env, addr);
1411 break;
1412 case 4:
1413 ret = cpu_ldl_user_secondary(env, addr);
1414 break;
1415 default:
1416 case 8:
1417 ret = cpu_ldq_user_secondary(env, addr);
1418 break;
1419 }
1420 } else {
1421 switch (size) {
1422 case 1:
1423 ret = cpu_ldub_user(env, addr);
1424 break;
1425 case 2:
1426 ret = cpu_lduw_user(env, addr);
1427 break;
1428 case 4:
1429 ret = cpu_ldl_user(env, addr);
1430 break;
1431 default:
1432 case 8:
1433 ret = cpu_ldq_user(env, addr);
1434 break;
1435 }
1436 }
1437 }
1438 break;
1439 case 0x14: /* Bypass */
1440 case 0x15: /* Bypass, non-cacheable */
1441 case 0x1c: /* Bypass LE */
1442 case 0x1d: /* Bypass, non-cacheable LE */
1443 {
1444 switch (size) {
1445 case 1:
1446 ret = ldub_phys(cs->as, addr);
1447 break;
1448 case 2:
1449 ret = lduw_phys(cs->as, addr);
1450 break;
1451 case 4:
1452 ret = ldl_phys(cs->as, addr);
1453 break;
1454 default:
1455 case 8:
1456 ret = ldq_phys(cs->as, addr);
1457 break;
1458 }
1459 break;
1460 }
1461 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1462 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1463 Only ldda allowed */
1464 helper_raise_exception(env, TT_ILL_INSN);
1465 return 0;
1466 case 0x04: /* Nucleus */
1467 case 0x0c: /* Nucleus Little Endian (LE) */
1468 {
1469 switch (size) {
1470 case 1:
1471 ret = cpu_ldub_nucleus(env, addr);
1472 break;
1473 case 2:
1474 ret = cpu_lduw_nucleus(env, addr);
1475 break;
1476 case 4:
1477 ret = cpu_ldl_nucleus(env, addr);
1478 break;
1479 default:
1480 case 8:
1481 ret = cpu_ldq_nucleus(env, addr);
1482 break;
1483 }
1484 break;
1485 }
1486 case 0x4a: /* UPA config */
1487 /* XXX */
1488 break;
1489 case 0x45: /* LSU */
1490 ret = env->lsu;
1491 break;
1492 case 0x50: /* I-MMU regs */
1493 {
1494 int reg = (addr >> 3) & 0xf;
1495
1496 if (reg == 0) {
1497 /* I-TSB Tag Target register */
1498 ret = ultrasparc_tag_target(env->immu.tag_access);
1499 } else {
1500 ret = env->immuregs[reg];
1501 }
1502
1503 break;
1504 }
1505 case 0x51: /* I-MMU 8k TSB pointer */
1506 {
1507 /* env->immuregs[5] holds I-MMU TSB register value
1508 env->immuregs[6] holds I-MMU Tag Access register value */
1509 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1510 8*1024);
1511 break;
1512 }
1513 case 0x52: /* I-MMU 64k TSB pointer */
1514 {
1515 /* env->immuregs[5] holds I-MMU TSB register value
1516 env->immuregs[6] holds I-MMU Tag Access register value */
1517 ret = ultrasparc_tsb_pointer(env->immu.tsb, env->immu.tag_access,
1518 64*1024);
1519 break;
1520 }
1521 case 0x55: /* I-MMU data access */
1522 {
1523 int reg = (addr >> 3) & 0x3f;
1524
1525 ret = env->itlb[reg].tte;
1526 break;
1527 }
1528 case 0x56: /* I-MMU tag read */
1529 {
1530 int reg = (addr >> 3) & 0x3f;
1531
1532 ret = env->itlb[reg].tag;
1533 break;
1534 }
1535 case 0x58: /* D-MMU regs */
1536 {
1537 int reg = (addr >> 3) & 0xf;
1538
1539 if (reg == 0) {
1540 /* D-TSB Tag Target register */
1541 ret = ultrasparc_tag_target(env->dmmu.tag_access);
1542 } else {
1543 ret = env->dmmuregs[reg];
1544 }
1545 break;
1546 }
1547 case 0x59: /* D-MMU 8k TSB pointer */
1548 {
1549 /* env->dmmuregs[5] holds D-MMU TSB register value
1550 env->dmmuregs[6] holds D-MMU Tag Access register value */
1551 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1552 8*1024);
1553 break;
1554 }
1555 case 0x5a: /* D-MMU 64k TSB pointer */
1556 {
1557 /* env->dmmuregs[5] holds D-MMU TSB register value
1558 env->dmmuregs[6] holds D-MMU Tag Access register value */
1559 ret = ultrasparc_tsb_pointer(env->dmmu.tsb, env->dmmu.tag_access,
1560 64*1024);
1561 break;
1562 }
1563 case 0x5d: /* D-MMU data access */
1564 {
1565 int reg = (addr >> 3) & 0x3f;
1566
1567 ret = env->dtlb[reg].tte;
1568 break;
1569 }
1570 case 0x5e: /* D-MMU tag read */
1571 {
1572 int reg = (addr >> 3) & 0x3f;
1573
1574 ret = env->dtlb[reg].tag;
1575 break;
1576 }
1577 case 0x48: /* Interrupt dispatch, RO */
1578 break;
1579 case 0x49: /* Interrupt data receive */
1580 ret = env->ivec_status;
1581 break;
1582 case 0x7f: /* Incoming interrupt vector, RO */
1583 {
1584 int reg = (addr >> 4) & 0x3;
1585 if (reg < 3) {
1586 ret = env->ivec_data[reg];
1587 }
1588 break;
1589 }
1590 case 0x46: /* D-cache data */
1591 case 0x47: /* D-cache tag access */
1592 case 0x4b: /* E-cache error enable */
1593 case 0x4c: /* E-cache asynchronous fault status */
1594 case 0x4d: /* E-cache asynchronous fault address */
1595 case 0x4e: /* E-cache tag data */
1596 case 0x66: /* I-cache instruction access */
1597 case 0x67: /* I-cache tag access */
1598 case 0x6e: /* I-cache predecode */
1599 case 0x6f: /* I-cache LRU etc. */
1600 case 0x76: /* E-cache tag */
1601 case 0x7e: /* E-cache tag */
1602 break;
1603 case 0x5b: /* D-MMU data pointer */
1604 case 0x54: /* I-MMU data in, WO */
1605 case 0x57: /* I-MMU demap, WO */
1606 case 0x5c: /* D-MMU data in, WO */
1607 case 0x5f: /* D-MMU demap, WO */
1608 case 0x77: /* Interrupt vector, WO */
1609 default:
1610 cpu_unassigned_access(cs, addr, false, false, 1, size);
1611 ret = 0;
1612 break;
1613 }
1614
1615 /* Convert from little endian */
1616 switch (asi) {
1617 case 0x0c: /* Nucleus Little Endian (LE) */
1618 case 0x18: /* As if user primary LE */
1619 case 0x19: /* As if user secondary LE */
1620 case 0x1c: /* Bypass LE */
1621 case 0x1d: /* Bypass, non-cacheable LE */
1622 case 0x88: /* Primary LE */
1623 case 0x89: /* Secondary LE */
1624 switch(size) {
1625 case 2:
1626 ret = bswap16(ret);
1627 break;
1628 case 4:
1629 ret = bswap32(ret);
1630 break;
1631 case 8:
1632 ret = bswap64(ret);
1633 break;
1634 default:
1635 break;
1636 }
1637 default:
1638 break;
1639 }
1640
1641 /* Convert to signed number */
1642 if (sign) {
1643 switch (size) {
1644 case 1:
1645 ret = (int8_t) ret;
1646 break;
1647 case 2:
1648 ret = (int16_t) ret;
1649 break;
1650 case 4:
1651 ret = (int32_t) ret;
1652 break;
1653 default:
1654 break;
1655 }
1656 }
1657 #ifdef DEBUG_ASI
1658 dump_asi("read ", last_addr, asi, size, ret);
1659 #endif
1660 return ret;
1661 }
1662
1663 void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
1664 int asi, int size)
1665 {
1666 SPARCCPU *cpu = sparc_env_get_cpu(env);
1667 CPUState *cs = CPU(cpu);
1668
1669 #ifdef DEBUG_ASI
1670 dump_asi("write", addr, asi, size, val);
1671 #endif
1672
1673 asi &= 0xff;
1674
1675 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
1676 || (cpu_has_hypervisor(env)
1677 && asi >= 0x30 && asi < 0x80
1678 && !(env->hpstate & HS_PRIV))) {
1679 helper_raise_exception(env, TT_PRIV_ACT);
1680 }
1681
1682 helper_check_align(env, addr, size - 1);
1683 addr = asi_address_mask(env, asi, addr);
1684
1685 /* Convert to little endian */
1686 switch (asi) {
1687 case 0x0c: /* Nucleus Little Endian (LE) */
1688 case 0x18: /* As if user primary LE */
1689 case 0x19: /* As if user secondary LE */
1690 case 0x1c: /* Bypass LE */
1691 case 0x1d: /* Bypass, non-cacheable LE */
1692 case 0x88: /* Primary LE */
1693 case 0x89: /* Secondary LE */
1694 switch (size) {
1695 case 2:
1696 val = bswap16(val);
1697 break;
1698 case 4:
1699 val = bswap32(val);
1700 break;
1701 case 8:
1702 val = bswap64(val);
1703 break;
1704 default:
1705 break;
1706 }
1707 default:
1708 break;
1709 }
1710
1711 switch (asi) {
1712 case 0x10: /* As if user primary */
1713 case 0x11: /* As if user secondary */
1714 case 0x18: /* As if user primary LE */
1715 case 0x19: /* As if user secondary LE */
1716 case 0x80: /* Primary */
1717 case 0x81: /* Secondary */
1718 case 0x88: /* Primary LE */
1719 case 0x89: /* Secondary LE */
1720 case 0xe2: /* UA2007 Primary block init */
1721 case 0xe3: /* UA2007 Secondary block init */
1722 if ((asi & 0x80) && (env->pstate & PS_PRIV)) {
1723 if (cpu_hypervisor_mode(env)) {
1724 switch (size) {
1725 case 1:
1726 cpu_stb_hypv(env, addr, val);
1727 break;
1728 case 2:
1729 cpu_stw_hypv(env, addr, val);
1730 break;
1731 case 4:
1732 cpu_stl_hypv(env, addr, val);
1733 break;
1734 case 8:
1735 default:
1736 cpu_stq_hypv(env, addr, val);
1737 break;
1738 }
1739 } else {
1740 /* secondary space access has lowest asi bit equal to 1 */
1741 if (asi & 1) {
1742 switch (size) {
1743 case 1:
1744 cpu_stb_kernel_secondary(env, addr, val);
1745 break;
1746 case 2:
1747 cpu_stw_kernel_secondary(env, addr, val);
1748 break;
1749 case 4:
1750 cpu_stl_kernel_secondary(env, addr, val);
1751 break;
1752 case 8:
1753 default:
1754 cpu_stq_kernel_secondary(env, addr, val);
1755 break;
1756 }
1757 } else {
1758 switch (size) {
1759 case 1:
1760 cpu_stb_kernel(env, addr, val);
1761 break;
1762 case 2:
1763 cpu_stw_kernel(env, addr, val);
1764 break;
1765 case 4:
1766 cpu_stl_kernel(env, addr, val);
1767 break;
1768 case 8:
1769 default:
1770 cpu_stq_kernel(env, addr, val);
1771 break;
1772 }
1773 }
1774 }
1775 } else {
1776 /* secondary space access has lowest asi bit equal to 1 */
1777 if (asi & 1) {
1778 switch (size) {
1779 case 1:
1780 cpu_stb_user_secondary(env, addr, val);
1781 break;
1782 case 2:
1783 cpu_stw_user_secondary(env, addr, val);
1784 break;
1785 case 4:
1786 cpu_stl_user_secondary(env, addr, val);
1787 break;
1788 case 8:
1789 default:
1790 cpu_stq_user_secondary(env, addr, val);
1791 break;
1792 }
1793 } else {
1794 switch (size) {
1795 case 1:
1796 cpu_stb_user(env, addr, val);
1797 break;
1798 case 2:
1799 cpu_stw_user(env, addr, val);
1800 break;
1801 case 4:
1802 cpu_stl_user(env, addr, val);
1803 break;
1804 case 8:
1805 default:
1806 cpu_stq_user(env, addr, val);
1807 break;
1808 }
1809 }
1810 }
1811 break;
1812 case 0x14: /* Bypass */
1813 case 0x15: /* Bypass, non-cacheable */
1814 case 0x1c: /* Bypass LE */
1815 case 0x1d: /* Bypass, non-cacheable LE */
1816 {
1817 switch (size) {
1818 case 1:
1819 stb_phys(cs->as, addr, val);
1820 break;
1821 case 2:
1822 stw_phys(cs->as, addr, val);
1823 break;
1824 case 4:
1825 stl_phys(cs->as, addr, val);
1826 break;
1827 case 8:
1828 default:
1829 stq_phys(cs->as, addr, val);
1830 break;
1831 }
1832 }
1833 return;
1834 case 0x24: /* Nucleus quad LDD 128 bit atomic */
1835 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE
1836 Only ldda allowed */
1837 helper_raise_exception(env, TT_ILL_INSN);
1838 return;
1839 case 0x04: /* Nucleus */
1840 case 0x0c: /* Nucleus Little Endian (LE) */
1841 {
1842 switch (size) {
1843 case 1:
1844 cpu_stb_nucleus(env, addr, val);
1845 break;
1846 case 2:
1847 cpu_stw_nucleus(env, addr, val);
1848 break;
1849 case 4:
1850 cpu_stl_nucleus(env, addr, val);
1851 break;
1852 default:
1853 case 8:
1854 cpu_stq_nucleus(env, addr, val);
1855 break;
1856 }
1857 break;
1858 }
1859
1860 case 0x4a: /* UPA config */
1861 /* XXX */
1862 return;
1863 case 0x45: /* LSU */
1864 {
1865 uint64_t oldreg;
1866
1867 oldreg = env->lsu;
1868 env->lsu = val & (DMMU_E | IMMU_E);
1869 /* Mappings generated during D/I MMU disabled mode are
1870 invalid in normal mode */
1871 if (oldreg != env->lsu) {
1872 DPRINTF_MMU("LSU change: 0x%" PRIx64 " -> 0x%" PRIx64 "\n",
1873 oldreg, env->lsu);
1874 #ifdef DEBUG_MMU
1875 dump_mmu(stdout, fprintf, env);
1876 #endif
1877 tlb_flush(CPU(cpu), 1);
1878 }
1879 return;
1880 }
1881 case 0x50: /* I-MMU regs */
1882 {
1883 int reg = (addr >> 3) & 0xf;
1884 uint64_t oldreg;
1885
1886 oldreg = env->immuregs[reg];
1887 switch (reg) {
1888 case 0: /* RO */
1889 return;
1890 case 1: /* Not in I-MMU */
1891 case 2:
1892 return;
1893 case 3: /* SFSR */
1894 if ((val & 1) == 0) {
1895 val = 0; /* Clear SFSR */
1896 }
1897 env->immu.sfsr = val;
1898 break;
1899 case 4: /* RO */
1900 return;
1901 case 5: /* TSB access */
1902 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016"
1903 PRIx64 "\n", env->immu.tsb, val);
1904 env->immu.tsb = val;
1905 break;
1906 case 6: /* Tag access */
1907 env->immu.tag_access = val;
1908 break;
1909 case 7:
1910 case 8:
1911 return;
1912 default:
1913 break;
1914 }
1915
1916 if (oldreg != env->immuregs[reg]) {
1917 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1918 PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
1919 }
1920 #ifdef DEBUG_MMU
1921 dump_mmu(stdout, fprintf, env);
1922 #endif
1923 return;
1924 }
1925 case 0x54: /* I-MMU data in */
1926 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, val, "immu", env);
1927 return;
1928 case 0x55: /* I-MMU data access */
1929 {
1930 /* TODO: auto demap */
1931
1932 unsigned int i = (addr >> 3) & 0x3f;
1933
1934 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, val, env);
1935
1936 #ifdef DEBUG_MMU
1937 DPRINTF_MMU("immu data access replaced entry [%i]\n", i);
1938 dump_mmu(stdout, fprintf, env);
1939 #endif
1940 return;
1941 }
1942 case 0x57: /* I-MMU demap */
1943 demap_tlb(env->itlb, addr, "immu", env);
1944 return;
1945 case 0x58: /* D-MMU regs */
1946 {
1947 int reg = (addr >> 3) & 0xf;
1948 uint64_t oldreg;
1949
1950 oldreg = env->dmmuregs[reg];
1951 switch (reg) {
1952 case 0: /* RO */
1953 case 4:
1954 return;
1955 case 3: /* SFSR */
1956 if ((val & 1) == 0) {
1957 val = 0; /* Clear SFSR, Fault address */
1958 env->dmmu.sfar = 0;
1959 }
1960 env->dmmu.sfsr = val;
1961 break;
1962 case 1: /* Primary context */
1963 env->dmmu.mmu_primary_context = val;
1964 /* can be optimized to only flush MMU_USER_IDX
1965 and MMU_KERNEL_IDX entries */
1966 tlb_flush(CPU(cpu), 1);
1967 break;
1968 case 2: /* Secondary context */
1969 env->dmmu.mmu_secondary_context = val;
1970 /* can be optimized to only flush MMU_USER_SECONDARY_IDX
1971 and MMU_KERNEL_SECONDARY_IDX entries */
1972 tlb_flush(CPU(cpu), 1);
1973 break;
1974 case 5: /* TSB access */
1975 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
1976 PRIx64 "\n", env->dmmu.tsb, val);
1977 env->dmmu.tsb = val;
1978 break;
1979 case 6: /* Tag access */
1980 env->dmmu.tag_access = val;
1981 break;
1982 case 7: /* Virtual Watchpoint */
1983 case 8: /* Physical Watchpoint */
1984 default:
1985 env->dmmuregs[reg] = val;
1986 break;
1987 }
1988
1989 if (oldreg != env->dmmuregs[reg]) {
1990 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
1991 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
1992 }
1993 #ifdef DEBUG_MMU
1994 dump_mmu(stdout, fprintf, env);
1995 #endif
1996 return;
1997 }
1998 case 0x5c: /* D-MMU data in */
1999 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, val, "dmmu", env);
2000 return;
2001 case 0x5d: /* D-MMU data access */
2002 {
2003 unsigned int i = (addr >> 3) & 0x3f;
2004
2005 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, val, env);
2006
2007 #ifdef DEBUG_MMU
2008 DPRINTF_MMU("dmmu data access replaced entry [%i]\n", i);
2009 dump_mmu(stdout, fprintf, env);
2010 #endif
2011 return;
2012 }
2013 case 0x5f: /* D-MMU demap */
2014 demap_tlb(env->dtlb, addr, "dmmu", env);
2015 return;
2016 case 0x49: /* Interrupt data receive */
2017 env->ivec_status = val & 0x20;
2018 return;
2019 case 0x46: /* D-cache data */
2020 case 0x47: /* D-cache tag access */
2021 case 0x4b: /* E-cache error enable */
2022 case 0x4c: /* E-cache asynchronous fault status */
2023 case 0x4d: /* E-cache asynchronous fault address */
2024 case 0x4e: /* E-cache tag data */
2025 case 0x66: /* I-cache instruction access */
2026 case 0x67: /* I-cache tag access */
2027 case 0x6e: /* I-cache predecode */
2028 case 0x6f: /* I-cache LRU etc. */
2029 case 0x76: /* E-cache tag */
2030 case 0x7e: /* E-cache tag */
2031 return;
2032 case 0x51: /* I-MMU 8k TSB pointer, RO */
2033 case 0x52: /* I-MMU 64k TSB pointer, RO */
2034 case 0x56: /* I-MMU tag read, RO */
2035 case 0x59: /* D-MMU 8k TSB pointer, RO */
2036 case 0x5a: /* D-MMU 64k TSB pointer, RO */
2037 case 0x5b: /* D-MMU data pointer, RO */
2038 case 0x5e: /* D-MMU tag read, RO */
2039 case 0x48: /* Interrupt dispatch, RO */
2040 case 0x7f: /* Incoming interrupt vector, RO */
2041 case 0x82: /* Primary no-fault, RO */
2042 case 0x83: /* Secondary no-fault, RO */
2043 case 0x8a: /* Primary no-fault LE, RO */
2044 case 0x8b: /* Secondary no-fault LE, RO */
2045 default:
2046 cpu_unassigned_access(cs, addr, true, false, 1, size);
2047 return;
2048 }
2049 }
2050 #endif /* CONFIG_USER_ONLY */
2051
2052 void helper_ldda_asi(CPUSPARCState *env, target_ulong addr, int asi, int rd)
2053 {
2054 if ((asi < 0x80 && (env->pstate & PS_PRIV) == 0)
2055 || (cpu_has_hypervisor(env)
2056 && asi >= 0x30 && asi < 0x80
2057 && !(env->hpstate & HS_PRIV))) {
2058 helper_raise_exception(env, TT_PRIV_ACT);
2059 }
2060
2061 addr = asi_address_mask(env, asi, addr);
2062
2063 switch (asi) {
2064 #if !defined(CONFIG_USER_ONLY)
2065 case 0x24: /* Nucleus quad LDD 128 bit atomic */
2066 case 0x2c: /* Nucleus quad LDD 128 bit atomic LE */
2067 helper_check_align(env, addr, 0xf);
2068 if (rd == 0) {
2069 env->gregs[1] = cpu_ldq_nucleus(env, addr + 8);
2070 if (asi == 0x2c) {
2071 bswap64s(&env->gregs[1]);
2072 }
2073 } else if (rd < 8) {
2074 env->gregs[rd] = cpu_ldq_nucleus(env, addr);
2075 env->gregs[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
2076 if (asi == 0x2c) {
2077 bswap64s(&env->gregs[rd]);
2078 bswap64s(&env->gregs[rd + 1]);
2079 }
2080 } else {
2081 env->regwptr[rd] = cpu_ldq_nucleus(env, addr);
2082 env->regwptr[rd + 1] = cpu_ldq_nucleus(env, addr + 8);
2083 if (asi == 0x2c) {
2084 bswap64s(&env->regwptr[rd]);
2085 bswap64s(&env->regwptr[rd + 1]);
2086 }
2087 }
2088 break;
2089 #endif
2090 default:
2091 helper_check_align(env, addr, 0x3);
2092 if (rd == 0) {
2093 env->gregs[1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2094 } else if (rd < 8) {
2095 env->gregs[rd] = helper_ld_asi(env, addr, asi, 4, 0);
2096 env->gregs[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2097 } else {
2098 env->regwptr[rd] = helper_ld_asi(env, addr, asi, 4, 0);
2099 env->regwptr[rd + 1] = helper_ld_asi(env, addr + 4, asi, 4, 0);
2100 }
2101 break;
2102 }
2103 }
2104
2105 void helper_ldf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2106 int rd)
2107 {
2108 unsigned int i;
2109 target_ulong val;
2110
2111 helper_check_align(env, addr, 3);
2112 addr = asi_address_mask(env, asi, addr);
2113
2114 switch (asi) {
2115 case 0xf0: /* UA2007/JPS1 Block load primary */
2116 case 0xf1: /* UA2007/JPS1 Block load secondary */
2117 case 0xf8: /* UA2007/JPS1 Block load primary LE */
2118 case 0xf9: /* UA2007/JPS1 Block load secondary LE */
2119 if (rd & 7) {
2120 helper_raise_exception(env, TT_ILL_INSN);
2121 return;
2122 }
2123 helper_check_align(env, addr, 0x3f);
2124 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2125 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x8f, 8, 0);
2126 }
2127 return;
2128
2129 case 0x16: /* UA2007 Block load primary, user privilege */
2130 case 0x17: /* UA2007 Block load secondary, user privilege */
2131 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2132 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2133 case 0x70: /* JPS1 Block load primary, user privilege */
2134 case 0x71: /* JPS1 Block load secondary, user privilege */
2135 case 0x78: /* JPS1 Block load primary LE, user privilege */
2136 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2137 if (rd & 7) {
2138 helper_raise_exception(env, TT_ILL_INSN);
2139 return;
2140 }
2141 helper_check_align(env, addr, 0x3f);
2142 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2143 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi & 0x19, 8, 0);
2144 }
2145 return;
2146
2147 default:
2148 break;
2149 }
2150
2151 switch (size) {
2152 default:
2153 case 4:
2154 val = helper_ld_asi(env, addr, asi, size, 0);
2155 if (rd & 1) {
2156 env->fpr[rd / 2].l.lower = val;
2157 } else {
2158 env->fpr[rd / 2].l.upper = val;
2159 }
2160 break;
2161 case 8:
2162 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, size, 0);
2163 break;
2164 case 16:
2165 env->fpr[rd / 2].ll = helper_ld_asi(env, addr, asi, 8, 0);
2166 env->fpr[rd / 2 + 1].ll = helper_ld_asi(env, addr + 8, asi, 8, 0);
2167 break;
2168 }
2169 }
2170
2171 void helper_stf_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
2172 int rd)
2173 {
2174 unsigned int i;
2175 target_ulong val;
2176
2177 helper_check_align(env, addr, 3);
2178 addr = asi_address_mask(env, asi, addr);
2179
2180 switch (asi) {
2181 case 0xe0: /* UA2007/JPS1 Block commit store primary (cache flush) */
2182 case 0xe1: /* UA2007/JPS1 Block commit store secondary (cache flush) */
2183 case 0xf0: /* UA2007/JPS1 Block store primary */
2184 case 0xf1: /* UA2007/JPS1 Block store secondary */
2185 case 0xf8: /* UA2007/JPS1 Block store primary LE */
2186 case 0xf9: /* UA2007/JPS1 Block store secondary LE */
2187 if (rd & 7) {
2188 helper_raise_exception(env, TT_ILL_INSN);
2189 return;
2190 }
2191 helper_check_align(env, addr, 0x3f);
2192 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2193 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x8f, 8);
2194 }
2195
2196 return;
2197 case 0x16: /* UA2007 Block load primary, user privilege */
2198 case 0x17: /* UA2007 Block load secondary, user privilege */
2199 case 0x1e: /* UA2007 Block load primary LE, user privilege */
2200 case 0x1f: /* UA2007 Block load secondary LE, user privilege */
2201 case 0x70: /* JPS1 Block store primary, user privilege */
2202 case 0x71: /* JPS1 Block store secondary, user privilege */
2203 case 0x78: /* JPS1 Block load primary LE, user privilege */
2204 case 0x79: /* JPS1 Block load secondary LE, user privilege */
2205 if (rd & 7) {
2206 helper_raise_exception(env, TT_ILL_INSN);
2207 return;
2208 }
2209 helper_check_align(env, addr, 0x3f);
2210 for (i = 0; i < 8; i++, rd += 2, addr += 8) {
2211 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi & 0x19, 8);
2212 }
2213
2214 return;
2215 default:
2216 break;
2217 }
2218
2219 switch (size) {
2220 default:
2221 case 4:
2222 if (rd & 1) {
2223 val = env->fpr[rd / 2].l.lower;
2224 } else {
2225 val = env->fpr[rd / 2].l.upper;
2226 }
2227 helper_st_asi(env, addr, val, asi, size);
2228 break;
2229 case 8:
2230 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, size);
2231 break;
2232 case 16:
2233 helper_st_asi(env, addr, env->fpr[rd / 2].ll, asi, 8);
2234 helper_st_asi(env, addr + 8, env->fpr[rd / 2 + 1].ll, asi, 8);
2235 break;
2236 }
2237 }
2238
2239 target_ulong helper_casx_asi(CPUSPARCState *env, target_ulong addr,
2240 target_ulong val1, target_ulong val2,
2241 uint32_t asi)
2242 {
2243 target_ulong ret;
2244
2245 ret = helper_ld_asi(env, addr, asi, 8, 0);
2246 if (val2 == ret) {
2247 helper_st_asi(env, addr, val1, asi, 8);
2248 }
2249 return ret;
2250 }
2251 #endif /* TARGET_SPARC64 */
2252
2253 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2254 target_ulong helper_cas_asi(CPUSPARCState *env, target_ulong addr,
2255 target_ulong val1, target_ulong val2, uint32_t asi)
2256 {
2257 target_ulong ret;
2258
2259 val2 &= 0xffffffffUL;
2260 ret = helper_ld_asi(env, addr, asi, 4, 0);
2261 ret &= 0xffffffffUL;
2262 if (val2 == ret) {
2263 helper_st_asi(env, addr, val1 & 0xffffffffUL, asi, 4);
2264 }
2265 return ret;
2266 }
2267 #endif /* !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) */
2268
2269 void helper_ldqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2270 {
2271 /* XXX add 128 bit load */
2272 CPU_QuadU u;
2273
2274 helper_check_align(env, addr, 7);
2275 #if !defined(CONFIG_USER_ONLY)
2276 switch (mem_idx) {
2277 case MMU_USER_IDX:
2278 u.ll.upper = cpu_ldq_user(env, addr);
2279 u.ll.lower = cpu_ldq_user(env, addr + 8);
2280 QT0 = u.q;
2281 break;
2282 case MMU_KERNEL_IDX:
2283 u.ll.upper = cpu_ldq_kernel(env, addr);
2284 u.ll.lower = cpu_ldq_kernel(env, addr + 8);
2285 QT0 = u.q;
2286 break;
2287 #ifdef TARGET_SPARC64
2288 case MMU_HYPV_IDX:
2289 u.ll.upper = cpu_ldq_hypv(env, addr);
2290 u.ll.lower = cpu_ldq_hypv(env, addr + 8);
2291 QT0 = u.q;
2292 break;
2293 #endif
2294 default:
2295 DPRINTF_MMU("helper_ldqf: need to check MMU idx %d\n", mem_idx);
2296 break;
2297 }
2298 #else
2299 u.ll.upper = ldq_raw(address_mask(env, addr));
2300 u.ll.lower = ldq_raw(address_mask(env, addr + 8));
2301 QT0 = u.q;
2302 #endif
2303 }
2304
2305 void helper_stqf(CPUSPARCState *env, target_ulong addr, int mem_idx)
2306 {
2307 /* XXX add 128 bit store */
2308 CPU_QuadU u;
2309
2310 helper_check_align(env, addr, 7);
2311 #if !defined(CONFIG_USER_ONLY)
2312 switch (mem_idx) {
2313 case MMU_USER_IDX:
2314 u.q = QT0;
2315 cpu_stq_user(env, addr, u.ll.upper);
2316 cpu_stq_user(env, addr + 8, u.ll.lower);
2317 break;
2318 case MMU_KERNEL_IDX:
2319 u.q = QT0;
2320 cpu_stq_kernel(env, addr, u.ll.upper);
2321 cpu_stq_kernel(env, addr + 8, u.ll.lower);
2322 break;
2323 #ifdef TARGET_SPARC64
2324 case MMU_HYPV_IDX:
2325 u.q = QT0;
2326 cpu_stq_hypv(env, addr, u.ll.upper);
2327 cpu_stq_hypv(env, addr + 8, u.ll.lower);
2328 break;
2329 #endif
2330 default:
2331 DPRINTF_MMU("helper_stqf: need to check MMU idx %d\n", mem_idx);
2332 break;
2333 }
2334 #else
2335 u.q = QT0;
2336 stq_raw(address_mask(env, addr), u.ll.upper);
2337 stq_raw(address_mask(env, addr + 8), u.ll.lower);
2338 #endif
2339 }
2340
2341 #if !defined(CONFIG_USER_ONLY)
2342 #ifndef TARGET_SPARC64
2343 void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2344 bool is_write, bool is_exec, int is_asi,
2345 unsigned size)
2346 {
2347 SPARCCPU *cpu = SPARC_CPU(cs);
2348 CPUSPARCState *env = &cpu->env;
2349 int fault_type;
2350
2351 #ifdef DEBUG_UNASSIGNED
2352 if (is_asi) {
2353 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2354 " asi 0x%02x from " TARGET_FMT_lx "\n",
2355 is_exec ? "exec" : is_write ? "write" : "read", size,
2356 size == 1 ? "" : "s", addr, is_asi, env->pc);
2357 } else {
2358 printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx
2359 " from " TARGET_FMT_lx "\n",
2360 is_exec ? "exec" : is_write ? "write" : "read", size,
2361 size == 1 ? "" : "s", addr, env->pc);
2362 }
2363 #endif
2364 /* Don't overwrite translation and access faults */
2365 fault_type = (env->mmuregs[3] & 0x1c) >> 2;
2366 if ((fault_type > 4) || (fault_type == 0)) {
2367 env->mmuregs[3] = 0; /* Fault status register */
2368 if (is_asi) {
2369 env->mmuregs[3] |= 1 << 16;
2370 }
2371 if (env->psrs) {
2372 env->mmuregs[3] |= 1 << 5;
2373 }
2374 if (is_exec) {
2375 env->mmuregs[3] |= 1 << 6;
2376 }
2377 if (is_write) {
2378 env->mmuregs[3] |= 1 << 7;
2379 }
2380 env->mmuregs[3] |= (5 << 2) | 2;
2381 /* SuperSPARC will never place instruction fault addresses in the FAR */
2382 if (!is_exec) {
2383 env->mmuregs[4] = addr; /* Fault address register */
2384 }
2385 }
2386 /* overflow (same type fault was not read before another fault) */
2387 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) {
2388 env->mmuregs[3] |= 1;
2389 }
2390
2391 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) {
2392 if (is_exec) {
2393 helper_raise_exception(env, TT_CODE_ACCESS);
2394 } else {
2395 helper_raise_exception(env, TT_DATA_ACCESS);
2396 }
2397 }
2398
2399 /* flush neverland mappings created during no-fault mode,
2400 so the sequential MMU faults report proper fault types */
2401 if (env->mmuregs[0] & MMU_NF) {
2402 tlb_flush(cs, 1);
2403 }
2404 }
2405 #else
2406 void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2407 bool is_write, bool is_exec, int is_asi,
2408 unsigned size)
2409 {
2410 SPARCCPU *cpu = SPARC_CPU(cs);
2411 CPUSPARCState *env = &cpu->env;
2412
2413 #ifdef DEBUG_UNASSIGNED
2414 printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx
2415 "\n", addr, env->pc);
2416 #endif
2417
2418 if (is_exec) {
2419 helper_raise_exception(env, TT_CODE_ACCESS);
2420 } else {
2421 helper_raise_exception(env, TT_DATA_ACCESS);
2422 }
2423 }
2424 #endif
2425 #endif
2426
2427 #if !defined(CONFIG_USER_ONLY)
2428 static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env,
2429 target_ulong addr, int is_write,
2430 int is_user, uintptr_t retaddr)
2431 {
2432 SPARCCPU *cpu = sparc_env_get_cpu(env);
2433 #ifdef DEBUG_UNALIGNED
2434 printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx
2435 "\n", addr, env->pc);
2436 #endif
2437 if (retaddr) {
2438 cpu_restore_state(CPU(cpu), retaddr);
2439 }
2440 helper_raise_exception(env, TT_UNALIGNED);
2441 }
2442
2443 /* try to fill the TLB and return an exception if error. If retaddr is
2444 NULL, it means that the function was called in C code (i.e. not
2445 from generated code or from helper.c) */
2446 /* XXX: fix it to restore all registers */
2447 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2448 uintptr_t retaddr)
2449 {
2450 int ret;
2451
2452 ret = sparc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2453 if (ret) {
2454 if (retaddr) {
2455 cpu_restore_state(cs, retaddr);
2456 }
2457 cpu_loop_exit(cs);
2458 }
2459 }
2460 #endif