target-sparc: Clean up ENV_GET_CPU() usage
[qemu.git] / target-sparc / mmu_helper.c
1 /*
2 * Sparc MMU helpers
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "cpu.h"
21 #include "trace.h"
22 #include "exec/address-spaces.h"
23
24 /* Sparc MMU emulation */
25
26 #if defined(CONFIG_USER_ONLY)
27
28 int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
29 int mmu_idx)
30 {
31 if (rw & 2) {
32 env1->exception_index = TT_TFAULT;
33 } else {
34 env1->exception_index = TT_DFAULT;
35 }
36 return 1;
37 }
38
39 #else
40
41 #ifndef TARGET_SPARC64
42 /*
43 * Sparc V8 Reference MMU (SRMMU)
44 */
45 static const int access_table[8][8] = {
46 { 0, 0, 0, 0, 8, 0, 12, 12 },
47 { 0, 0, 0, 0, 8, 0, 0, 0 },
48 { 8, 8, 0, 0, 0, 8, 12, 12 },
49 { 8, 8, 0, 0, 0, 8, 0, 0 },
50 { 8, 0, 8, 0, 8, 8, 12, 12 },
51 { 8, 0, 8, 0, 8, 0, 8, 0 },
52 { 8, 8, 8, 0, 8, 8, 12, 12 },
53 { 8, 8, 8, 0, 8, 8, 8, 0 }
54 };
55
56 static const int perm_table[2][8] = {
57 {
58 PAGE_READ,
59 PAGE_READ | PAGE_WRITE,
60 PAGE_READ | PAGE_EXEC,
61 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
62 PAGE_EXEC,
63 PAGE_READ | PAGE_WRITE,
64 PAGE_READ | PAGE_EXEC,
65 PAGE_READ | PAGE_WRITE | PAGE_EXEC
66 },
67 {
68 PAGE_READ,
69 PAGE_READ | PAGE_WRITE,
70 PAGE_READ | PAGE_EXEC,
71 PAGE_READ | PAGE_WRITE | PAGE_EXEC,
72 PAGE_EXEC,
73 PAGE_READ,
74 0,
75 0,
76 }
77 };
78
79 static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
80 int *prot, int *access_index,
81 target_ulong address, int rw, int mmu_idx,
82 target_ulong *page_size)
83 {
84 int access_perms = 0;
85 hwaddr pde_ptr;
86 uint32_t pde;
87 int error_code = 0, is_dirty, is_user;
88 unsigned long page_offset;
89 CPUState *cs = CPU(sparc_env_get_cpu(env));
90
91 is_user = mmu_idx == MMU_USER_IDX;
92
93 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
94 *page_size = TARGET_PAGE_SIZE;
95 /* Boot mode: instruction fetches are taken from PROM */
96 if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) {
97 *physical = env->prom_addr | (address & 0x7ffffULL);
98 *prot = PAGE_READ | PAGE_EXEC;
99 return 0;
100 }
101 *physical = address;
102 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
103 return 0;
104 }
105
106 *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user ? 0 : 1);
107 *physical = 0xffffffffffff0000ULL;
108
109 /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
110 /* Context base + context number */
111 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
112 pde = ldl_phys(cs->as, pde_ptr);
113
114 /* Ctx pde */
115 switch (pde & PTE_ENTRYTYPE_MASK) {
116 default:
117 case 0: /* Invalid */
118 return 1 << 2;
119 case 2: /* L0 PTE, maybe should not happen? */
120 case 3: /* Reserved */
121 return 4 << 2;
122 case 1: /* L0 PDE */
123 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
124 pde = ldl_phys(cs->as, pde_ptr);
125
126 switch (pde & PTE_ENTRYTYPE_MASK) {
127 default:
128 case 0: /* Invalid */
129 return (1 << 8) | (1 << 2);
130 case 3: /* Reserved */
131 return (1 << 8) | (4 << 2);
132 case 1: /* L1 PDE */
133 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
134 pde = ldl_phys(cs->as, pde_ptr);
135
136 switch (pde & PTE_ENTRYTYPE_MASK) {
137 default:
138 case 0: /* Invalid */
139 return (2 << 8) | (1 << 2);
140 case 3: /* Reserved */
141 return (2 << 8) | (4 << 2);
142 case 1: /* L2 PDE */
143 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
144 pde = ldl_phys(cs->as, pde_ptr);
145
146 switch (pde & PTE_ENTRYTYPE_MASK) {
147 default:
148 case 0: /* Invalid */
149 return (3 << 8) | (1 << 2);
150 case 1: /* PDE, should not happen */
151 case 3: /* Reserved */
152 return (3 << 8) | (4 << 2);
153 case 2: /* L3 PTE */
154 page_offset = 0;
155 }
156 *page_size = TARGET_PAGE_SIZE;
157 break;
158 case 2: /* L2 PTE */
159 page_offset = address & 0x3f000;
160 *page_size = 0x40000;
161 }
162 break;
163 case 2: /* L1 PTE */
164 page_offset = address & 0xfff000;
165 *page_size = 0x1000000;
166 }
167 }
168
169 /* check access */
170 access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
171 error_code = access_table[*access_index][access_perms];
172 if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) {
173 return error_code;
174 }
175
176 /* update page modified and dirty bits */
177 is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
178 if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
179 pde |= PG_ACCESSED_MASK;
180 if (is_dirty) {
181 pde |= PG_MODIFIED_MASK;
182 }
183 stl_phys_notdirty(cs->as, pde_ptr, pde);
184 }
185
186 /* the page can be put in the TLB */
187 *prot = perm_table[is_user][access_perms];
188 if (!(pde & PG_MODIFIED_MASK)) {
189 /* only set write access if already dirty... otherwise wait
190 for dirty access */
191 *prot &= ~PAGE_WRITE;
192 }
193
194 /* Even if large ptes, we map only one 4KB page in the cache to
195 avoid filling it too fast */
196 *physical = ((hwaddr)(pde & PTE_ADDR_MASK) << 4) + page_offset;
197 return error_code;
198 }
199
200 /* Perform address translation */
201 int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw,
202 int mmu_idx)
203 {
204 hwaddr paddr;
205 target_ulong vaddr;
206 target_ulong page_size;
207 int error_code = 0, prot, access_index;
208
209 address &= TARGET_PAGE_MASK;
210 error_code = get_physical_address(env, &paddr, &prot, &access_index,
211 address, rw, mmu_idx, &page_size);
212 vaddr = address;
213 if (error_code == 0) {
214 #ifdef DEBUG_MMU
215 printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
216 TARGET_FMT_lx "\n", address, paddr, vaddr);
217 #endif
218 tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
219 return 0;
220 }
221
222 if (env->mmuregs[3]) { /* Fault status register */
223 env->mmuregs[3] = 1; /* overflow (not read before another fault) */
224 }
225 env->mmuregs[3] |= (access_index << 5) | error_code | 2;
226 env->mmuregs[4] = address; /* Fault address register */
227
228 if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
229 /* No fault mode: if a mapping is available, just override
230 permissions. If no mapping is available, redirect accesses to
231 neverland. Fake/overridden mappings will be flushed when
232 switching to normal mode. */
233 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
234 tlb_set_page(env, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
235 return 0;
236 } else {
237 if (rw & 2) {
238 env->exception_index = TT_TFAULT;
239 } else {
240 env->exception_index = TT_DFAULT;
241 }
242 return 1;
243 }
244 }
245
246 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev)
247 {
248 CPUState *cs = CPU(sparc_env_get_cpu(env));
249 hwaddr pde_ptr;
250 uint32_t pde;
251
252 /* Context base + context number */
253 pde_ptr = (hwaddr)(env->mmuregs[1] << 4) +
254 (env->mmuregs[2] << 2);
255 pde = ldl_phys(cs->as, pde_ptr);
256
257 switch (pde & PTE_ENTRYTYPE_MASK) {
258 default:
259 case 0: /* Invalid */
260 case 2: /* PTE, maybe should not happen? */
261 case 3: /* Reserved */
262 return 0;
263 case 1: /* L1 PDE */
264 if (mmulev == 3) {
265 return pde;
266 }
267 pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
268 pde = ldl_phys(cs->as, pde_ptr);
269
270 switch (pde & PTE_ENTRYTYPE_MASK) {
271 default:
272 case 0: /* Invalid */
273 case 3: /* Reserved */
274 return 0;
275 case 2: /* L1 PTE */
276 return pde;
277 case 1: /* L2 PDE */
278 if (mmulev == 2) {
279 return pde;
280 }
281 pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
282 pde = ldl_phys(cs->as, pde_ptr);
283
284 switch (pde & PTE_ENTRYTYPE_MASK) {
285 default:
286 case 0: /* Invalid */
287 case 3: /* Reserved */
288 return 0;
289 case 2: /* L2 PTE */
290 return pde;
291 case 1: /* L3 PDE */
292 if (mmulev == 1) {
293 return pde;
294 }
295 pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
296 pde = ldl_phys(cs->as, pde_ptr);
297
298 switch (pde & PTE_ENTRYTYPE_MASK) {
299 default:
300 case 0: /* Invalid */
301 case 1: /* PDE, should not happen */
302 case 3: /* Reserved */
303 return 0;
304 case 2: /* L3 PTE */
305 return pde;
306 }
307 }
308 }
309 }
310 return 0;
311 }
312
313 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
314 {
315 CPUState *cs = CPU(sparc_env_get_cpu(env));
316 target_ulong va, va1, va2;
317 unsigned int n, m, o;
318 hwaddr pde_ptr, pa;
319 uint32_t pde;
320
321 pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2);
322 pde = ldl_phys(cs->as, pde_ptr);
323 (*cpu_fprintf)(f, "Root ptr: " TARGET_FMT_plx ", ctx: %d\n",
324 (hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]);
325 for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) {
326 pde = mmu_probe(env, va, 2);
327 if (pde) {
328 pa = cpu_get_phys_page_debug(cs, va);
329 (*cpu_fprintf)(f, "VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx
330 " PDE: " TARGET_FMT_lx "\n", va, pa, pde);
331 for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) {
332 pde = mmu_probe(env, va1, 1);
333 if (pde) {
334 pa = cpu_get_phys_page_debug(cs, va1);
335 (*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: "
336 TARGET_FMT_plx " PDE: " TARGET_FMT_lx "\n",
337 va1, pa, pde);
338 for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) {
339 pde = mmu_probe(env, va2, 0);
340 if (pde) {
341 pa = cpu_get_phys_page_debug(cs, va2);
342 (*cpu_fprintf)(f, " VA: " TARGET_FMT_lx ", PA: "
343 TARGET_FMT_plx " PTE: "
344 TARGET_FMT_lx "\n",
345 va2, pa, pde);
346 }
347 }
348 }
349 }
350 }
351 }
352 }
353
354 /* Gdb expects all registers windows to be flushed in ram. This function handles
355 * reads (and only reads) in stack frames as if windows were flushed. We assume
356 * that the sparc ABI is followed.
357 */
358 int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr address,
359 uint8_t *buf, int len, bool is_write)
360 {
361 SPARCCPU *cpu = SPARC_CPU(cs);
362 CPUSPARCState *env = &cpu->env;
363 target_ulong addr = address;
364 int i;
365 int len1;
366 int cwp = env->cwp;
367
368 if (!is_write) {
369 for (i = 0; i < env->nwindows; i++) {
370 int off;
371 target_ulong fp = env->regbase[cwp * 16 + 22];
372
373 /* Assume fp == 0 means end of frame. */
374 if (fp == 0) {
375 break;
376 }
377
378 cwp = cpu_cwp_inc(env, cwp + 1);
379
380 /* Invalid window ? */
381 if (env->wim & (1 << cwp)) {
382 break;
383 }
384
385 /* According to the ABI, the stack is growing downward. */
386 if (addr + len < fp) {
387 break;
388 }
389
390 /* Not in this frame. */
391 if (addr > fp + 64) {
392 continue;
393 }
394
395 /* Handle access before this window. */
396 if (addr < fp) {
397 len1 = fp - addr;
398 if (cpu_memory_rw_debug(cs, addr, buf, len1, is_write) != 0) {
399 return -1;
400 }
401 addr += len1;
402 len -= len1;
403 buf += len1;
404 }
405
406 /* Access byte per byte to registers. Not very efficient but speed
407 * is not critical.
408 */
409 off = addr - fp;
410 len1 = 64 - off;
411
412 if (len1 > len) {
413 len1 = len;
414 }
415
416 for (; len1; len1--) {
417 int reg = cwp * 16 + 8 + (off >> 2);
418 union {
419 uint32_t v;
420 uint8_t c[4];
421 } u;
422 u.v = cpu_to_be32(env->regbase[reg]);
423 *buf++ = u.c[off & 3];
424 addr++;
425 len--;
426 off++;
427 }
428
429 if (len == 0) {
430 return 0;
431 }
432 }
433 }
434 return cpu_memory_rw_debug(cs, addr, buf, len, is_write);
435 }
436
437 #else /* !TARGET_SPARC64 */
438
439 /* 41 bit physical address space */
440 static inline hwaddr ultrasparc_truncate_physical(uint64_t x)
441 {
442 return x & 0x1ffffffffffULL;
443 }
444
445 /*
446 * UltraSparc IIi I/DMMUs
447 */
448
449 /* Returns true if TTE tag is valid and matches virtual address value
450 in context requires virtual address mask value calculated from TTE
451 entry size */
452 static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
453 uint64_t address, uint64_t context,
454 hwaddr *physical)
455 {
456 uint64_t mask;
457
458 switch (TTE_PGSIZE(tlb->tte)) {
459 default:
460 case 0x0: /* 8k */
461 mask = 0xffffffffffffe000ULL;
462 break;
463 case 0x1: /* 64k */
464 mask = 0xffffffffffff0000ULL;
465 break;
466 case 0x2: /* 512k */
467 mask = 0xfffffffffff80000ULL;
468 break;
469 case 0x3: /* 4M */
470 mask = 0xffffffffffc00000ULL;
471 break;
472 }
473
474 /* valid, context match, virtual address match? */
475 if (TTE_IS_VALID(tlb->tte) &&
476 (TTE_IS_GLOBAL(tlb->tte) || tlb_compare_context(tlb, context))
477 && compare_masked(address, tlb->tag, mask)) {
478 /* decode physical address */
479 *physical = ((tlb->tte & mask) | (address & ~mask)) & 0x1ffffffe000ULL;
480 return 1;
481 }
482
483 return 0;
484 }
485
486 static int get_physical_address_data(CPUSPARCState *env,
487 hwaddr *physical, int *prot,
488 target_ulong address, int rw, int mmu_idx)
489 {
490 unsigned int i;
491 uint64_t context;
492 uint64_t sfsr = 0;
493
494 int is_user = (mmu_idx == MMU_USER_IDX ||
495 mmu_idx == MMU_USER_SECONDARY_IDX);
496
497 if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */
498 *physical = ultrasparc_truncate_physical(address);
499 *prot = PAGE_READ | PAGE_WRITE;
500 return 0;
501 }
502
503 switch (mmu_idx) {
504 case MMU_USER_IDX:
505 case MMU_KERNEL_IDX:
506 context = env->dmmu.mmu_primary_context & 0x1fff;
507 sfsr |= SFSR_CT_PRIMARY;
508 break;
509 case MMU_USER_SECONDARY_IDX:
510 case MMU_KERNEL_SECONDARY_IDX:
511 context = env->dmmu.mmu_secondary_context & 0x1fff;
512 sfsr |= SFSR_CT_SECONDARY;
513 break;
514 case MMU_NUCLEUS_IDX:
515 sfsr |= SFSR_CT_NUCLEUS;
516 /* FALLTHRU */
517 default:
518 context = 0;
519 break;
520 }
521
522 if (rw == 1) {
523 sfsr |= SFSR_WRITE_BIT;
524 } else if (rw == 4) {
525 sfsr |= SFSR_NF_BIT;
526 }
527
528 for (i = 0; i < 64; i++) {
529 /* ctx match, vaddr match, valid? */
530 if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) {
531 int do_fault = 0;
532
533 /* access ok? */
534 /* multiple bits in SFSR.FT may be set on TT_DFAULT */
535 if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) {
536 do_fault = 1;
537 sfsr |= SFSR_FT_PRIV_BIT; /* privilege violation */
538 trace_mmu_helper_dfault(address, context, mmu_idx, env->tl);
539 }
540 if (rw == 4) {
541 if (TTE_IS_SIDEEFFECT(env->dtlb[i].tte)) {
542 do_fault = 1;
543 sfsr |= SFSR_FT_NF_E_BIT;
544 }
545 } else {
546 if (TTE_IS_NFO(env->dtlb[i].tte)) {
547 do_fault = 1;
548 sfsr |= SFSR_FT_NFO_BIT;
549 }
550 }
551
552 if (do_fault) {
553 /* faults above are reported with TT_DFAULT. */
554 env->exception_index = TT_DFAULT;
555 } else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) {
556 do_fault = 1;
557 env->exception_index = TT_DPROT;
558
559 trace_mmu_helper_dprot(address, context, mmu_idx, env->tl);
560 }
561
562 if (!do_fault) {
563 *prot = PAGE_READ;
564 if (TTE_IS_W_OK(env->dtlb[i].tte)) {
565 *prot |= PAGE_WRITE;
566 }
567
568 TTE_SET_USED(env->dtlb[i].tte);
569
570 return 0;
571 }
572
573 if (env->dmmu.sfsr & SFSR_VALID_BIT) { /* Fault status register */
574 sfsr |= SFSR_OW_BIT; /* overflow (not read before
575 another fault) */
576 }
577
578 if (env->pstate & PS_PRIV) {
579 sfsr |= SFSR_PR_BIT;
580 }
581
582 /* FIXME: ASI field in SFSR must be set */
583 env->dmmu.sfsr = sfsr | SFSR_VALID_BIT;
584
585 env->dmmu.sfar = address; /* Fault address register */
586
587 env->dmmu.tag_access = (address & ~0x1fffULL) | context;
588
589 return 1;
590 }
591 }
592
593 trace_mmu_helper_dmiss(address, context);
594
595 /*
596 * On MMU misses:
597 * - UltraSPARC IIi: SFSR and SFAR unmodified
598 * - JPS1: SFAR updated and some fields of SFSR updated
599 */
600 env->dmmu.tag_access = (address & ~0x1fffULL) | context;
601 env->exception_index = TT_DMISS;
602 return 1;
603 }
604
605 static int get_physical_address_code(CPUSPARCState *env,
606 hwaddr *physical, int *prot,
607 target_ulong address, int mmu_idx)
608 {
609 unsigned int i;
610 uint64_t context;
611
612 int is_user = (mmu_idx == MMU_USER_IDX ||
613 mmu_idx == MMU_USER_SECONDARY_IDX);
614
615 if ((env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0) {
616 /* IMMU disabled */
617 *physical = ultrasparc_truncate_physical(address);
618 *prot = PAGE_EXEC;
619 return 0;
620 }
621
622 if (env->tl == 0) {
623 /* PRIMARY context */
624 context = env->dmmu.mmu_primary_context & 0x1fff;
625 } else {
626 /* NUCLEUS context */
627 context = 0;
628 }
629
630 for (i = 0; i < 64; i++) {
631 /* ctx match, vaddr match, valid? */
632 if (ultrasparc_tag_match(&env->itlb[i],
633 address, context, physical)) {
634 /* access ok? */
635 if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) {
636 /* Fault status register */
637 if (env->immu.sfsr & SFSR_VALID_BIT) {
638 env->immu.sfsr = SFSR_OW_BIT; /* overflow (not read before
639 another fault) */
640 } else {
641 env->immu.sfsr = 0;
642 }
643 if (env->pstate & PS_PRIV) {
644 env->immu.sfsr |= SFSR_PR_BIT;
645 }
646 if (env->tl > 0) {
647 env->immu.sfsr |= SFSR_CT_NUCLEUS;
648 }
649
650 /* FIXME: ASI field in SFSR must be set */
651 env->immu.sfsr |= SFSR_FT_PRIV_BIT | SFSR_VALID_BIT;
652 env->exception_index = TT_TFAULT;
653
654 env->immu.tag_access = (address & ~0x1fffULL) | context;
655
656 trace_mmu_helper_tfault(address, context);
657
658 return 1;
659 }
660 *prot = PAGE_EXEC;
661 TTE_SET_USED(env->itlb[i].tte);
662 return 0;
663 }
664 }
665
666 trace_mmu_helper_tmiss(address, context);
667
668 /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
669 env->immu.tag_access = (address & ~0x1fffULL) | context;
670 env->exception_index = TT_TMISS;
671 return 1;
672 }
673
674 static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
675 int *prot, int *access_index,
676 target_ulong address, int rw, int mmu_idx,
677 target_ulong *page_size)
678 {
679 /* ??? We treat everything as a small page, then explicitly flush
680 everything when an entry is evicted. */
681 *page_size = TARGET_PAGE_SIZE;
682
683 /* safety net to catch wrong softmmu index use from dynamic code */
684 if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) {
685 if (rw == 2) {
686 trace_mmu_helper_get_phys_addr_code(env->tl, mmu_idx,
687 env->dmmu.mmu_primary_context,
688 env->dmmu.mmu_secondary_context,
689 address);
690 } else {
691 trace_mmu_helper_get_phys_addr_data(env->tl, mmu_idx,
692 env->dmmu.mmu_primary_context,
693 env->dmmu.mmu_secondary_context,
694 address);
695 }
696 }
697
698 if (rw == 2) {
699 return get_physical_address_code(env, physical, prot, address,
700 mmu_idx);
701 } else {
702 return get_physical_address_data(env, physical, prot, address, rw,
703 mmu_idx);
704 }
705 }
706
707 /* Perform address translation */
708 int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw,
709 int mmu_idx)
710 {
711 target_ulong vaddr;
712 hwaddr paddr;
713 target_ulong page_size;
714 int error_code = 0, prot, access_index;
715
716 address &= TARGET_PAGE_MASK;
717 error_code = get_physical_address(env, &paddr, &prot, &access_index,
718 address, rw, mmu_idx, &page_size);
719 if (error_code == 0) {
720 vaddr = address;
721
722 trace_mmu_helper_mmu_fault(address, paddr, mmu_idx, env->tl,
723 env->dmmu.mmu_primary_context,
724 env->dmmu.mmu_secondary_context);
725
726 tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
727 return 0;
728 }
729 /* XXX */
730 return 1;
731 }
732
733 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
734 {
735 unsigned int i;
736 const char *mask;
737
738 (*cpu_fprintf)(f, "MMU contexts: Primary: %" PRId64 ", Secondary: %"
739 PRId64 "\n",
740 env->dmmu.mmu_primary_context,
741 env->dmmu.mmu_secondary_context);
742 if ((env->lsu & DMMU_E) == 0) {
743 (*cpu_fprintf)(f, "DMMU disabled\n");
744 } else {
745 (*cpu_fprintf)(f, "DMMU dump\n");
746 for (i = 0; i < 64; i++) {
747 switch (TTE_PGSIZE(env->dtlb[i].tte)) {
748 default:
749 case 0x0:
750 mask = " 8k";
751 break;
752 case 0x1:
753 mask = " 64k";
754 break;
755 case 0x2:
756 mask = "512k";
757 break;
758 case 0x3:
759 mask = " 4M";
760 break;
761 }
762 if (TTE_IS_VALID(env->dtlb[i].tte)) {
763 (*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %llx"
764 ", %s, %s, %s, %s, ctx %" PRId64 " %s\n",
765 i,
766 env->dtlb[i].tag & (uint64_t)~0x1fffULL,
767 TTE_PA(env->dtlb[i].tte),
768 mask,
769 TTE_IS_PRIV(env->dtlb[i].tte) ? "priv" : "user",
770 TTE_IS_W_OK(env->dtlb[i].tte) ? "RW" : "RO",
771 TTE_IS_LOCKED(env->dtlb[i].tte) ?
772 "locked" : "unlocked",
773 env->dtlb[i].tag & (uint64_t)0x1fffULL,
774 TTE_IS_GLOBAL(env->dtlb[i].tte) ?
775 "global" : "local");
776 }
777 }
778 }
779 if ((env->lsu & IMMU_E) == 0) {
780 (*cpu_fprintf)(f, "IMMU disabled\n");
781 } else {
782 (*cpu_fprintf)(f, "IMMU dump\n");
783 for (i = 0; i < 64; i++) {
784 switch (TTE_PGSIZE(env->itlb[i].tte)) {
785 default:
786 case 0x0:
787 mask = " 8k";
788 break;
789 case 0x1:
790 mask = " 64k";
791 break;
792 case 0x2:
793 mask = "512k";
794 break;
795 case 0x3:
796 mask = " 4M";
797 break;
798 }
799 if (TTE_IS_VALID(env->itlb[i].tte)) {
800 (*cpu_fprintf)(f, "[%02u] VA: %" PRIx64 ", PA: %llx"
801 ", %s, %s, %s, ctx %" PRId64 " %s\n",
802 i,
803 env->itlb[i].tag & (uint64_t)~0x1fffULL,
804 TTE_PA(env->itlb[i].tte),
805 mask,
806 TTE_IS_PRIV(env->itlb[i].tte) ? "priv" : "user",
807 TTE_IS_LOCKED(env->itlb[i].tte) ?
808 "locked" : "unlocked",
809 env->itlb[i].tag & (uint64_t)0x1fffULL,
810 TTE_IS_GLOBAL(env->itlb[i].tte) ?
811 "global" : "local");
812 }
813 }
814 }
815 }
816
817 #endif /* TARGET_SPARC64 */
818
819 static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys,
820 target_ulong addr, int rw, int mmu_idx)
821 {
822 target_ulong page_size;
823 int prot, access_index;
824
825 return get_physical_address(env, phys, &prot, &access_index, addr, rw,
826 mmu_idx, &page_size);
827 }
828
829 #if defined(TARGET_SPARC64)
830 hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
831 int mmu_idx)
832 {
833 hwaddr phys_addr;
834
835 if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 4, mmu_idx) != 0) {
836 return -1;
837 }
838 return phys_addr;
839 }
840 #endif
841
842 hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
843 {
844 SPARCCPU *cpu = SPARC_CPU(cs);
845 CPUSPARCState *env = &cpu->env;
846 hwaddr phys_addr;
847 int mmu_idx = cpu_mmu_index(env);
848 MemoryRegionSection section;
849
850 if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) != 0) {
851 if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 0, mmu_idx) != 0) {
852 return -1;
853 }
854 }
855 section = memory_region_find(get_system_memory(), phys_addr, 1);
856 memory_region_unref(section.mr);
857 if (!int128_nz(section.size)) {
858 return -1;
859 }
860 return phys_addr;
861 }
862 #endif