scsi: esp: check buffer length before reading scsi command
[qemu.git] / target-tilegx / cpu.h
1 /*
2 * TILE-Gx virtual CPU header
3 *
4 * Copyright (c) 2015 Chen Gang
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #ifndef CPU_TILEGX_H
20 #define CPU_TILEGX_H
21
22 #include "qemu-common.h"
23
24 #define TARGET_LONG_BITS 64
25
26 #define CPUArchState struct CPUTLGState
27
28 #include "exec/cpu-defs.h"
29
30
31 /* TILE-Gx common register alias */
32 #define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */
33 #define TILEGX_R_ERR 1 /* 1 register, for syscall errno flag */
34 #define TILEGX_R_NR 10 /* 10 register, for syscall number */
35 #define TILEGX_R_BP 52 /* 52 register, optional frame pointer */
36 #define TILEGX_R_TP 53 /* TP register, thread local storage data */
37 #define TILEGX_R_SP 54 /* SP register, stack pointer */
38 #define TILEGX_R_LR 55 /* LR register, may save pc, but it is not pc */
39 #define TILEGX_R_COUNT 56 /* Only 56 registers are really useful */
40 #define TILEGX_R_SN 56 /* SN register, obsoleted, it likes zero register */
41 #define TILEGX_R_IDN0 57 /* IDN0 register, cause IDN_ACCESS exception */
42 #define TILEGX_R_IDN1 58 /* IDN1 register, cause IDN_ACCESS exception */
43 #define TILEGX_R_UDN0 59 /* UDN0 register, cause UDN_ACCESS exception */
44 #define TILEGX_R_UDN1 60 /* UDN1 register, cause UDN_ACCESS exception */
45 #define TILEGX_R_UDN2 61 /* UDN2 register, cause UDN_ACCESS exception */
46 #define TILEGX_R_UDN3 62 /* UDN3 register, cause UDN_ACCESS exception */
47 #define TILEGX_R_ZERO 63 /* Zero register, always zero */
48 #define TILEGX_R_NOREG 255 /* Invalid register value */
49
50 /* TILE-Gx special registers used by outside */
51 enum {
52 TILEGX_SPR_CMPEXCH = 0,
53 TILEGX_SPR_CRITICAL_SEC = 1,
54 TILEGX_SPR_SIM_CONTROL = 2,
55 TILEGX_SPR_EX_CONTEXT_0_0 = 3,
56 TILEGX_SPR_EX_CONTEXT_0_1 = 4,
57 TILEGX_SPR_COUNT
58 };
59
60 /* Exception numbers */
61 typedef enum {
62 TILEGX_EXCP_NONE = 0,
63 TILEGX_EXCP_SYSCALL = 1,
64 TILEGX_EXCP_SIGNAL = 2,
65 TILEGX_EXCP_OPCODE_UNKNOWN = 0x101,
66 TILEGX_EXCP_OPCODE_UNIMPLEMENTED = 0x102,
67 TILEGX_EXCP_OPCODE_CMPEXCH = 0x103,
68 TILEGX_EXCP_OPCODE_CMPEXCH4 = 0x104,
69 TILEGX_EXCP_OPCODE_EXCH = 0x105,
70 TILEGX_EXCP_OPCODE_EXCH4 = 0x106,
71 TILEGX_EXCP_OPCODE_FETCHADD = 0x107,
72 TILEGX_EXCP_OPCODE_FETCHADD4 = 0x108,
73 TILEGX_EXCP_OPCODE_FETCHADDGEZ = 0x109,
74 TILEGX_EXCP_OPCODE_FETCHADDGEZ4 = 0x10a,
75 TILEGX_EXCP_OPCODE_FETCHAND = 0x10b,
76 TILEGX_EXCP_OPCODE_FETCHAND4 = 0x10c,
77 TILEGX_EXCP_OPCODE_FETCHOR = 0x10d,
78 TILEGX_EXCP_OPCODE_FETCHOR4 = 0x10e,
79 TILEGX_EXCP_REG_IDN_ACCESS = 0x181,
80 TILEGX_EXCP_REG_UDN_ACCESS = 0x182,
81 TILEGX_EXCP_UNALIGNMENT = 0x201,
82 TILEGX_EXCP_DBUG_BREAK = 0x301
83 } TileExcp;
84
85 typedef struct CPUTLGState {
86 uint64_t regs[TILEGX_R_COUNT]; /* Common used registers by outside */
87 uint64_t spregs[TILEGX_SPR_COUNT]; /* Special used registers by outside */
88 uint64_t pc; /* Current pc */
89
90 #if defined(CONFIG_USER_ONLY)
91 uint64_t excaddr; /* exception address */
92 uint64_t atomic_srca; /* Arguments to atomic "exceptions" */
93 uint64_t atomic_srcb;
94 uint32_t atomic_dstr;
95 uint32_t signo; /* Signal number */
96 uint32_t sigcode; /* Signal code */
97 #endif
98
99 CPU_COMMON
100 } CPUTLGState;
101
102 #include "qom/cpu.h"
103
104 #define TYPE_TILEGX_CPU "tilegx-cpu"
105
106 #define TILEGX_CPU_CLASS(klass) \
107 OBJECT_CLASS_CHECK(TileGXCPUClass, (klass), TYPE_TILEGX_CPU)
108 #define TILEGX_CPU(obj) \
109 OBJECT_CHECK(TileGXCPU, (obj), TYPE_TILEGX_CPU)
110 #define TILEGX_CPU_GET_CLASS(obj) \
111 OBJECT_GET_CLASS(TileGXCPUClass, (obj), TYPE_TILEGX_CPU)
112
113 /**
114 * TileGXCPUClass:
115 * @parent_realize: The parent class' realize handler.
116 * @parent_reset: The parent class' reset handler.
117 *
118 * A Tile-Gx CPU model.
119 */
120 typedef struct TileGXCPUClass {
121 /*< private >*/
122 CPUClass parent_class;
123 /*< public >*/
124
125 DeviceRealize parent_realize;
126 void (*parent_reset)(CPUState *cpu);
127 } TileGXCPUClass;
128
129 /**
130 * TileGXCPU:
131 * @env: #CPUTLGState
132 *
133 * A Tile-GX CPU.
134 */
135 typedef struct TileGXCPU {
136 /*< private >*/
137 CPUState parent_obj;
138 /*< public >*/
139
140 CPUTLGState env;
141 } TileGXCPU;
142
143 static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env)
144 {
145 return container_of(env, TileGXCPU, env);
146 }
147
148 #define ENV_GET_CPU(e) CPU(tilegx_env_get_cpu(e))
149
150 #define ENV_OFFSET offsetof(TileGXCPU, env)
151
152 /* TILE-Gx memory attributes */
153 #define TARGET_PAGE_BITS 16 /* TILE-Gx uses 64KB page size */
154 #define TARGET_PHYS_ADDR_SPACE_BITS 42
155 #define TARGET_VIRT_ADDR_SPACE_BITS 64
156 #define MMU_USER_IDX 0 /* Current memory operation is in user mode */
157
158 #include "exec/cpu-all.h"
159
160 void tilegx_tcg_init(void);
161 int cpu_tilegx_exec(CPUState *s);
162 int cpu_tilegx_signal_handler(int host_signum, void *pinfo, void *puc);
163
164 TileGXCPU *cpu_tilegx_init(const char *cpu_model);
165
166 #define cpu_init(cpu_model) CPU(cpu_tilegx_init(cpu_model))
167
168 #define cpu_exec cpu_tilegx_exec
169 #define cpu_signal_handler cpu_tilegx_signal_handler
170
171 static inline void cpu_get_tb_cpu_state(CPUTLGState *env, target_ulong *pc,
172 target_ulong *cs_base, uint32_t *flags)
173 {
174 *pc = env->pc;
175 *cs_base = 0;
176 *flags = 0;
177 }
178
179 #endif