scsi: pvscsi: check command descriptor ring buffer size (CVE-2016-4952)
[qemu.git] / target-tricore / cpu.h
1 /*
2 * TriCore emulation for qemu: main CPU struct.
3 *
4 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #if !defined(__TRICORE_CPU_H__)
20 #define __TRICORE_CPU_H__
21
22 #include "tricore-defs.h"
23 #include "qemu-common.h"
24 #include "cpu-qom.h"
25 #include "exec/cpu-defs.h"
26 #include "fpu/softfloat.h"
27
28 #define CPUArchState struct CPUTriCoreState
29
30 struct CPUTriCoreState;
31
32 struct tricore_boot_info;
33
34 #define NB_MMU_MODES 3
35
36 typedef struct tricore_def_t tricore_def_t;
37
38 typedef struct CPUTriCoreState CPUTriCoreState;
39 struct CPUTriCoreState {
40 /* GPR Register */
41 uint32_t gpr_a[16];
42 uint32_t gpr_d[16];
43 /* CSFR Register */
44 uint32_t PCXI;
45 /* Frequently accessed PSW_USB bits are stored separately for efficiency.
46 This contains all the other bits. Use psw_{read,write} to access
47 the whole PSW. */
48 uint32_t PSW;
49
50 /* PSW flag cache for faster execution
51 */
52 uint32_t PSW_USB_C;
53 uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */
54 uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */
55 uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */
56 uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
57
58 uint32_t PC;
59 uint32_t SYSCON;
60 uint32_t CPU_ID;
61 uint32_t BIV;
62 uint32_t BTV;
63 uint32_t ISP;
64 uint32_t ICR;
65 uint32_t FCX;
66 uint32_t LCX;
67 uint32_t COMPAT;
68
69 /* Mem Protection Register */
70 uint32_t DPR0_0L;
71 uint32_t DPR0_0U;
72 uint32_t DPR0_1L;
73 uint32_t DPR0_1U;
74 uint32_t DPR0_2L;
75 uint32_t DPR0_2U;
76 uint32_t DPR0_3L;
77 uint32_t DPR0_3U;
78
79 uint32_t DPR1_0L;
80 uint32_t DPR1_0U;
81 uint32_t DPR1_1L;
82 uint32_t DPR1_1U;
83 uint32_t DPR1_2L;
84 uint32_t DPR1_2U;
85 uint32_t DPR1_3L;
86 uint32_t DPR1_3U;
87
88 uint32_t DPR2_0L;
89 uint32_t DPR2_0U;
90 uint32_t DPR2_1L;
91 uint32_t DPR2_1U;
92 uint32_t DPR2_2L;
93 uint32_t DPR2_2U;
94 uint32_t DPR2_3L;
95 uint32_t DPR2_3U;
96
97 uint32_t DPR3_0L;
98 uint32_t DPR3_0U;
99 uint32_t DPR3_1L;
100 uint32_t DPR3_1U;
101 uint32_t DPR3_2L;
102 uint32_t DPR3_2U;
103 uint32_t DPR3_3L;
104 uint32_t DPR3_3U;
105
106 uint32_t CPR0_0L;
107 uint32_t CPR0_0U;
108 uint32_t CPR0_1L;
109 uint32_t CPR0_1U;
110 uint32_t CPR0_2L;
111 uint32_t CPR0_2U;
112 uint32_t CPR0_3L;
113 uint32_t CPR0_3U;
114
115 uint32_t CPR1_0L;
116 uint32_t CPR1_0U;
117 uint32_t CPR1_1L;
118 uint32_t CPR1_1U;
119 uint32_t CPR1_2L;
120 uint32_t CPR1_2U;
121 uint32_t CPR1_3L;
122 uint32_t CPR1_3U;
123
124 uint32_t CPR2_0L;
125 uint32_t CPR2_0U;
126 uint32_t CPR2_1L;
127 uint32_t CPR2_1U;
128 uint32_t CPR2_2L;
129 uint32_t CPR2_2U;
130 uint32_t CPR2_3L;
131 uint32_t CPR2_3U;
132
133 uint32_t CPR3_0L;
134 uint32_t CPR3_0U;
135 uint32_t CPR3_1L;
136 uint32_t CPR3_1U;
137 uint32_t CPR3_2L;
138 uint32_t CPR3_2U;
139 uint32_t CPR3_3L;
140 uint32_t CPR3_3U;
141
142 uint32_t DPM0;
143 uint32_t DPM1;
144 uint32_t DPM2;
145 uint32_t DPM3;
146
147 uint32_t CPM0;
148 uint32_t CPM1;
149 uint32_t CPM2;
150 uint32_t CPM3;
151
152 /* Memory Management Registers */
153 uint32_t MMU_CON;
154 uint32_t MMU_ASI;
155 uint32_t MMU_TVA;
156 uint32_t MMU_TPA;
157 uint32_t MMU_TPX;
158 uint32_t MMU_TFA;
159 /* {1.3.1 only */
160 uint32_t BMACON;
161 uint32_t SMACON;
162 uint32_t DIEAR;
163 uint32_t DIETR;
164 uint32_t CCDIER;
165 uint32_t MIECON;
166 uint32_t PIEAR;
167 uint32_t PIETR;
168 uint32_t CCPIER;
169 /*} */
170 /* Debug Registers */
171 uint32_t DBGSR;
172 uint32_t EXEVT;
173 uint32_t CREVT;
174 uint32_t SWEVT;
175 uint32_t TR0EVT;
176 uint32_t TR1EVT;
177 uint32_t DMS;
178 uint32_t DCX;
179 uint32_t DBGTCR;
180 uint32_t CCTRL;
181 uint32_t CCNT;
182 uint32_t ICNT;
183 uint32_t M1CNT;
184 uint32_t M2CNT;
185 uint32_t M3CNT;
186 /* Floating Point Registers */
187 float_status fp_status;
188 /* QEMU */
189 int error_code;
190 uint32_t hflags; /* CPU State */
191
192 CPU_COMMON
193
194 /* Internal CPU feature flags. */
195 uint64_t features;
196
197 const tricore_def_t *cpu_model;
198 void *irq[8];
199 struct QEMUTimer *timer; /* Internal timer */
200 };
201
202 /**
203 * TriCoreCPU:
204 * @env: #CPUTriCoreState
205 *
206 * A TriCore CPU.
207 */
208 struct TriCoreCPU {
209 /*< private >*/
210 CPUState parent_obj;
211 /*< public >*/
212
213 CPUTriCoreState env;
214 };
215
216 static inline TriCoreCPU *tricore_env_get_cpu(CPUTriCoreState *env)
217 {
218 return TRICORE_CPU(container_of(env, TriCoreCPU, env));
219 }
220
221 #define ENV_GET_CPU(e) CPU(tricore_env_get_cpu(e))
222
223 #define ENV_OFFSET offsetof(TriCoreCPU, env)
224
225 hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
226 void tricore_cpu_dump_state(CPUState *cpu, FILE *f,
227 fprintf_function cpu_fprintf, int flags);
228
229
230 #define MASK_PCXI_PCPN 0xff000000
231 #define MASK_PCXI_PIE 0x00800000
232 #define MASK_PCXI_UL 0x00400000
233 #define MASK_PCXI_PCXS 0x000f0000
234 #define MASK_PCXI_PCXO 0x0000ffff
235
236 #define MASK_PSW_USB 0xff000000
237 #define MASK_USB_C 0x80000000
238 #define MASK_USB_V 0x40000000
239 #define MASK_USB_SV 0x20000000
240 #define MASK_USB_AV 0x10000000
241 #define MASK_USB_SAV 0x08000000
242 #define MASK_PSW_PRS 0x00003000
243 #define MASK_PSW_IO 0x00000c00
244 #define MASK_PSW_IS 0x00000200
245 #define MASK_PSW_GW 0x00000100
246 #define MASK_PSW_CDE 0x00000080
247 #define MASK_PSW_CDC 0x0000007f
248 #define MASK_PSW_FPU_RM 0x3000000
249
250 #define MASK_SYSCON_PRO_TEN 0x2
251 #define MASK_SYSCON_FCD_SF 0x1
252
253 #define MASK_CPUID_MOD 0xffff0000
254 #define MASK_CPUID_MOD_32B 0x0000ff00
255 #define MASK_CPUID_REV 0x000000ff
256
257 #define MASK_ICR_PIPN 0x00ff0000
258 #define MASK_ICR_IE 0x00000100
259 #define MASK_ICR_CCPN 0x000000ff
260
261 #define MASK_FCX_FCXS 0x000f0000
262 #define MASK_FCX_FCXO 0x0000ffff
263
264 #define MASK_LCX_LCXS 0x000f0000
265 #define MASK_LCX_LCX0 0x0000ffff
266
267 #define MASK_DBGSR_DE 0x1
268 #define MASK_DBGSR_HALT 0x6
269 #define MASK_DBGSR_SUSP 0x10
270 #define MASK_DBGSR_PREVSUSP 0x20
271 #define MASK_DBGSR_PEVT 0x40
272 #define MASK_DBGSR_EVTSRC 0x1f00
273
274 #define TRICORE_HFLAG_KUU 0x3
275 #define TRICORE_HFLAG_UM0 0x00002 /* user mode-0 flag */
276 #define TRICORE_HFLAG_UM1 0x00001 /* user mode-1 flag */
277 #define TRICORE_HFLAG_SM 0x00000 /* kernel mode flag */
278
279 enum tricore_features {
280 TRICORE_FEATURE_13,
281 TRICORE_FEATURE_131,
282 TRICORE_FEATURE_16,
283 TRICORE_FEATURE_161,
284 };
285
286 static inline int tricore_feature(CPUTriCoreState *env, int feature)
287 {
288 return (env->features & (1ULL << feature)) != 0;
289 }
290
291 /* TriCore Traps Classes*/
292 enum {
293 TRAPC_NONE = -1,
294 TRAPC_MMU = 0,
295 TRAPC_PROT = 1,
296 TRAPC_INSN_ERR = 2,
297 TRAPC_CTX_MNG = 3,
298 TRAPC_SYSBUS = 4,
299 TRAPC_ASSERT = 5,
300 TRAPC_SYSCALL = 6,
301 TRAPC_NMI = 7,
302 TRAPC_IRQ = 8
303 };
304
305 /* Class 0 TIN */
306 enum {
307 TIN0_VAF = 0,
308 TIN0_VAP = 1,
309 };
310
311 /* Class 1 TIN */
312 enum {
313 TIN1_PRIV = 1,
314 TIN1_MPR = 2,
315 TIN1_MPW = 3,
316 TIN1_MPX = 4,
317 TIN1_MPP = 5,
318 TIN1_MPN = 6,
319 TIN1_GRWP = 7,
320 };
321
322 /* Class 2 TIN */
323 enum {
324 TIN2_IOPC = 1,
325 TIN2_UOPC = 2,
326 TIN2_OPD = 3,
327 TIN2_ALN = 4,
328 TIN2_MEM = 5,
329 };
330
331 /* Class 3 TIN */
332 enum {
333 TIN3_FCD = 1,
334 TIN3_CDO = 2,
335 TIN3_CDU = 3,
336 TIN3_FCU = 4,
337 TIN3_CSU = 5,
338 TIN3_CTYP = 6,
339 TIN3_NEST = 7,
340 };
341
342 /* Class 4 TIN */
343 enum {
344 TIN4_PSE = 1,
345 TIN4_DSE = 2,
346 TIN4_DAE = 3,
347 TIN4_CAE = 4,
348 TIN4_PIE = 5,
349 TIN4_DIE = 6,
350 };
351
352 /* Class 5 TIN */
353 enum {
354 TIN5_OVF = 1,
355 TIN5_SOVF = 1,
356 };
357
358 /* Class 6 TIN
359 *
360 * Is always TIN6_SYS
361 */
362
363 /* Class 7 TIN */
364 enum {
365 TIN7_NMI = 0,
366 };
367
368 uint32_t psw_read(CPUTriCoreState *env);
369 void psw_write(CPUTriCoreState *env, uint32_t val);
370
371 void fpu_set_state(CPUTriCoreState *env);
372
373 #define MMU_USER_IDX 2
374
375 void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf);
376
377 #define cpu_exec cpu_tricore_exec
378 #define cpu_signal_handler cpu_tricore_signal_handler
379 #define cpu_list tricore_cpu_list
380
381 static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
382 {
383 return 0;
384 }
385
386
387
388 #include "exec/cpu-all.h"
389
390 enum {
391 /* 1 bit to define user level / supervisor access */
392 ACCESS_USER = 0x00,
393 ACCESS_SUPER = 0x01,
394 /* 1 bit to indicate direction */
395 ACCESS_STORE = 0x02,
396 /* Type of instruction that generated the access */
397 ACCESS_CODE = 0x10, /* Code fetch access */
398 ACCESS_INT = 0x20, /* Integer load/store access */
399 ACCESS_FLOAT = 0x30, /* floating point load/store access */
400 };
401
402 void cpu_state_reset(CPUTriCoreState *s);
403 int cpu_tricore_exec(CPUState *cpu);
404 void tricore_tcg_init(void);
405 int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc);
406
407 static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc,
408 target_ulong *cs_base, uint32_t *flags)
409 {
410 *pc = env->PC;
411 *cs_base = 0;
412 *flags = 0;
413 }
414
415 TriCoreCPU *cpu_tricore_init(const char *cpu_model);
416
417 #define cpu_init(cpu_model) CPU(cpu_tricore_init(cpu_model))
418
419
420 /* helpers.c */
421 int cpu_tricore_handle_mmu_fault(CPUState *cpu, target_ulong address,
422 int rw, int mmu_idx);
423 #define cpu_handle_mmu_fault cpu_tricore_handle_mmu_fault
424
425 #endif /*__TRICORE_CPU_H__ */