seccomp: whitelist syscalls fallocate(), fadvise64(), inotify_init1() and inotify_add...
[qemu.git] / target-tricore / cpu.h
1 /*
2 * TriCore emulation for qemu: main CPU struct.
3 *
4 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #if !defined(__TRICORE_CPU_H__)
20 #define __TRICORE_CPU_H__
21
22 #include "tricore-defs.h"
23 #include "config.h"
24 #include "qemu-common.h"
25 #include "exec/cpu-defs.h"
26 #include "fpu/softfloat.h"
27
28 #define ELF_MACHINE EM_TRICORE
29
30 #define CPUArchState struct CPUTriCoreState
31
32 struct CPUTriCoreState;
33
34 struct tricore_boot_info;
35
36 #define NB_MMU_MODES 3
37
38 typedef struct tricore_def_t tricore_def_t;
39
40 typedef struct CPUTriCoreState CPUTriCoreState;
41 struct CPUTriCoreState {
42 /* GPR Register */
43 uint32_t gpr_a[16];
44 uint32_t gpr_d[16];
45 /* CSFR Register */
46 uint32_t PCXI;
47 /* Frequently accessed PSW_USB bits are stored separately for efficiency.
48 This contains all the other bits. Use psw_{read,write} to access
49 the whole PSW. */
50 uint32_t PSW;
51
52 /* PSW flag cache for faster execution
53 */
54 uint32_t PSW_USB_C;
55 uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */
56 uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */
57 uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */
58 uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */
59
60 uint32_t PC;
61 uint32_t SYSCON;
62 uint32_t CPU_ID;
63 uint32_t BIV;
64 uint32_t BTV;
65 uint32_t ISP;
66 uint32_t ICR;
67 uint32_t FCX;
68 uint32_t LCX;
69 uint32_t COMPAT;
70
71 /* Mem Protection Register */
72 uint32_t DPR0_0L;
73 uint32_t DPR0_0U;
74 uint32_t DPR0_1L;
75 uint32_t DPR0_1U;
76 uint32_t DPR0_2L;
77 uint32_t DPR0_2U;
78 uint32_t DPR0_3L;
79 uint32_t DPR0_3U;
80
81 uint32_t DPR1_0L;
82 uint32_t DPR1_0U;
83 uint32_t DPR1_1L;
84 uint32_t DPR1_1U;
85 uint32_t DPR1_2L;
86 uint32_t DPR1_2U;
87 uint32_t DPR1_3L;
88 uint32_t DPR1_3U;
89
90 uint32_t DPR2_0L;
91 uint32_t DPR2_0U;
92 uint32_t DPR2_1L;
93 uint32_t DPR2_1U;
94 uint32_t DPR2_2L;
95 uint32_t DPR2_2U;
96 uint32_t DPR2_3L;
97 uint32_t DPR2_3U;
98
99 uint32_t DPR3_0L;
100 uint32_t DPR3_0U;
101 uint32_t DPR3_1L;
102 uint32_t DPR3_1U;
103 uint32_t DPR3_2L;
104 uint32_t DPR3_2U;
105 uint32_t DPR3_3L;
106 uint32_t DPR3_3U;
107
108 uint32_t CPR0_0L;
109 uint32_t CPR0_0U;
110 uint32_t CPR0_1L;
111 uint32_t CPR0_1U;
112 uint32_t CPR0_2L;
113 uint32_t CPR0_2U;
114 uint32_t CPR0_3L;
115 uint32_t CPR0_3U;
116
117 uint32_t CPR1_0L;
118 uint32_t CPR1_0U;
119 uint32_t CPR1_1L;
120 uint32_t CPR1_1U;
121 uint32_t CPR1_2L;
122 uint32_t CPR1_2U;
123 uint32_t CPR1_3L;
124 uint32_t CPR1_3U;
125
126 uint32_t CPR2_0L;
127 uint32_t CPR2_0U;
128 uint32_t CPR2_1L;
129 uint32_t CPR2_1U;
130 uint32_t CPR2_2L;
131 uint32_t CPR2_2U;
132 uint32_t CPR2_3L;
133 uint32_t CPR2_3U;
134
135 uint32_t CPR3_0L;
136 uint32_t CPR3_0U;
137 uint32_t CPR3_1L;
138 uint32_t CPR3_1U;
139 uint32_t CPR3_2L;
140 uint32_t CPR3_2U;
141 uint32_t CPR3_3L;
142 uint32_t CPR3_3U;
143
144 uint32_t DPM0;
145 uint32_t DPM1;
146 uint32_t DPM2;
147 uint32_t DPM3;
148
149 uint32_t CPM0;
150 uint32_t CPM1;
151 uint32_t CPM2;
152 uint32_t CPM3;
153
154 /* Memory Management Registers */
155 uint32_t MMU_CON;
156 uint32_t MMU_ASI;
157 uint32_t MMU_TVA;
158 uint32_t MMU_TPA;
159 uint32_t MMU_TPX;
160 uint32_t MMU_TFA;
161 /* {1.3.1 only */
162 uint32_t BMACON;
163 uint32_t SMACON;
164 uint32_t DIEAR;
165 uint32_t DIETR;
166 uint32_t CCDIER;
167 uint32_t MIECON;
168 uint32_t PIEAR;
169 uint32_t PIETR;
170 uint32_t CCPIER;
171 /*} */
172 /* Debug Registers */
173 uint32_t DBGSR;
174 uint32_t EXEVT;
175 uint32_t CREVT;
176 uint32_t SWEVT;
177 uint32_t TR0EVT;
178 uint32_t TR1EVT;
179 uint32_t DMS;
180 uint32_t DCX;
181 uint32_t DBGTCR;
182 uint32_t CCTRL;
183 uint32_t CCNT;
184 uint32_t ICNT;
185 uint32_t M1CNT;
186 uint32_t M2CNT;
187 uint32_t M3CNT;
188 /* Floating Point Registers */
189 /* XXX: */
190
191 /* QEMU */
192 int error_code;
193 uint32_t hflags; /* CPU State */
194
195 CPU_COMMON
196
197 /* Internal CPU feature flags. */
198 uint64_t features;
199
200 const tricore_def_t *cpu_model;
201 void *irq[8];
202 struct QEMUTimer *timer; /* Internal timer */
203 };
204
205 #define MASK_PCXI_PCPN 0xff000000
206 #define MASK_PCXI_PIE 0x00800000
207 #define MASK_PCXI_UL 0x00400000
208 #define MASK_PCXI_PCXS 0x000f0000
209 #define MASK_PCXI_PCXO 0x0000ffff
210
211 #define MASK_PSW_USB 0xff000000
212 #define MASK_USB_C 0x80000000
213 #define MASK_USB_V 0x40000000
214 #define MASK_USB_SV 0x20000000
215 #define MASK_USB_AV 0x10000000
216 #define MASK_USB_SAV 0x08000000
217 #define MASK_PSW_PRS 0x00003000
218 #define MASK_PSW_IO 0x00000c00
219 #define MASK_PSW_IS 0x00000200
220 #define MASK_PSW_GW 0x00000100
221 #define MASK_PSW_CDE 0x00000080
222 #define MASK_PSW_CDC 0x0000007f
223
224 #define MASK_SYSCON_PRO_TEN 0x2
225 #define MASK_SYSCON_FCD_SF 0x1
226
227 #define MASK_CPUID_MOD 0xffff0000
228 #define MASK_CPUID_MOD_32B 0x0000ff00
229 #define MASK_CPUID_REV 0x000000ff
230
231 #define MASK_ICR_PIPN 0x00ff0000
232 #define MASK_ICR_IE 0x00000100
233 #define MASK_ICR_CCPN 0x000000ff
234
235 #define MASK_FCX_FCXS 0x000f0000
236 #define MASK_FCX_FCXO 0x0000ffff
237
238 #define MASK_LCX_LCXS 0x000f0000
239 #define MASK_LCX_LCX0 0x0000ffff
240
241 #define TRICORE_HFLAG_UM0 0x00002 /* user mode-0 flag */
242 #define TRICORE_HFLAG_UM1 0x00001 /* user mode-1 flag */
243 #define TRICORE_HFLAG_SM 0x00000 /* kernel mode flag */
244
245 enum tricore_features {
246 TRICORE_FEATURE_13,
247 TRICORE_FEATURE_131,
248 TRICORE_FEATURE_16,
249 };
250
251 static inline int tricore_feature(CPUTriCoreState *env, int feature)
252 {
253 return (env->features & (1ULL << feature)) != 0;
254 }
255
256 /* TriCore Traps Classes*/
257 enum {
258 TRAPC_NONE = -1,
259 TRAPC_MMU = 0,
260 TRAPC_PROT = 1,
261 TRAPC_INSN_ERR = 2,
262 TRAPC_CTX_MNG = 3,
263 TRAPC_SYSBUS = 4,
264 TRAPC_ASSERT = 5,
265 TRAPC_SYSCALL = 6,
266 TRAPC_NMI = 7,
267 };
268
269 /* Class 0 TIN */
270 enum {
271 TIN0_VAF = 0,
272 TIN0_VAP = 1,
273 };
274
275 /* Class 1 TIN */
276 enum {
277 TIN1_PRIV = 1,
278 TIN1_MPR = 2,
279 TIN1_MPW = 3,
280 TIN1_MPX = 4,
281 TIN1_MPP = 5,
282 TIN1_MPN = 6,
283 TIN1_GRWP = 7,
284 };
285
286 /* Class 2 TIN */
287 enum {
288 TIN2_IOPC = 1,
289 TIN2_UOPC = 2,
290 TIN2_OPD = 3,
291 TIN2_ALN = 4,
292 TIN2_MEM = 5,
293 };
294
295 /* Class 3 TIN */
296 enum {
297 TIN3_FCD = 1,
298 TIN3_CDO = 2,
299 TIN3_CDU = 3,
300 TIN3_FCU = 4,
301 TIN3_CSU = 5,
302 TIN3_CTYP = 6,
303 TIN3_NEST = 7,
304 };
305
306 /* Class 4 TIN */
307 enum {
308 TIN4_PSE = 1,
309 TIN4_DSE = 2,
310 TIN4_DAE = 3,
311 TIN4_CAE = 4,
312 TIN4_PIE = 5,
313 TIN4_DIE = 6,
314 };
315
316 /* Class 5 TIN */
317 enum {
318 TIN5_OVF = 1,
319 TIN5_SOVF = 1,
320 };
321
322 /* Class 6 TIN
323 *
324 * Is always TIN6_SYS
325 */
326
327 /* Class 7 TIN */
328 enum {
329 TIN7_NMI = 0,
330 };
331
332 uint32_t psw_read(CPUTriCoreState *env);
333 void psw_write(CPUTriCoreState *env, uint32_t val);
334
335 #include "cpu-qom.h"
336 #define MMU_USER_IDX 2
337
338 void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf);
339
340 #define cpu_exec cpu_tricore_exec
341 #define cpu_signal_handler cpu_tricore_signal_handler
342 #define cpu_list tricore_cpu_list
343
344 static inline int cpu_mmu_index(CPUTriCoreState *env)
345 {
346 return 0;
347 }
348
349
350
351 #include "exec/cpu-all.h"
352
353 enum {
354 /* 1 bit to define user level / supervisor access */
355 ACCESS_USER = 0x00,
356 ACCESS_SUPER = 0x01,
357 /* 1 bit to indicate direction */
358 ACCESS_STORE = 0x02,
359 /* Type of instruction that generated the access */
360 ACCESS_CODE = 0x10, /* Code fetch access */
361 ACCESS_INT = 0x20, /* Integer load/store access */
362 ACCESS_FLOAT = 0x30, /* floating point load/store access */
363 };
364
365 void cpu_state_reset(CPUTriCoreState *s);
366 int cpu_tricore_exec(CPUTriCoreState *s);
367 void tricore_tcg_init(void);
368 int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc);
369
370 static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc,
371 target_ulong *cs_base, int *flags)
372 {
373 *pc = env->PC;
374 *cs_base = 0;
375 *flags = 0;
376 }
377
378 TriCoreCPU *cpu_tricore_init(const char *cpu_model);
379
380 static inline CPUTriCoreState *cpu_init(const char *cpu_model)
381 {
382 TriCoreCPU *cpu = cpu_tricore_init(cpu_model);
383 if (cpu == NULL) {
384 return NULL;
385 }
386 return &cpu->env;
387
388 }
389
390
391 /* helpers.c */
392 int cpu_tricore_handle_mmu_fault(CPUState *cpu, target_ulong address,
393 int rw, int mmu_idx);
394 #define cpu_handle_mmu_fault cpu_tricore_handle_mmu_fault
395
396 #include "exec/exec-all.h"
397
398 static inline void cpu_pc_from_tb(CPUTriCoreState *env, TranslationBlock *tb)
399 {
400 env->PC = tb->pc;
401 }
402
403 #endif /*__TRICORE_CPU_H__ */