cpu: Move halted and interrupt_request fields to CPUState
[qemu.git] / target-unicore32 / cpu.h
1 /*
2 * UniCore32 virtual CPU header
3 *
4 * Copyright (C) 2010-2012 Guan Xuetao
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or (at your option) any
9 * later version. See the COPYING file in the top-level directory.
10 */
11 #ifndef QEMU_UNICORE32_CPU_H
12 #define QEMU_UNICORE32_CPU_H
13
14 #define TARGET_LONG_BITS 32
15 #define TARGET_PAGE_BITS 12
16
17 #define TARGET_PHYS_ADDR_SPACE_BITS 32
18 #define TARGET_VIRT_ADDR_SPACE_BITS 32
19
20 #define ELF_MACHINE EM_UNICORE32
21
22 #define CPUArchState struct CPUUniCore32State
23
24 #include "config.h"
25 #include "qemu-common.h"
26 #include "exec/cpu-defs.h"
27 #include "fpu/softfloat.h"
28
29 #define NB_MMU_MODES 2
30
31 typedef struct CPUUniCore32State {
32 /* Regs for current mode. */
33 uint32_t regs[32];
34 /* Frequently accessed ASR bits are stored separately for efficiently.
35 This contains all the other bits. Use asr_{read,write} to access
36 the whole ASR. */
37 uint32_t uncached_asr;
38 uint32_t bsr;
39
40 /* Banked registers. */
41 uint32_t banked_bsr[6];
42 uint32_t banked_r29[6];
43 uint32_t banked_r30[6];
44
45 /* asr flag cache for faster execution */
46 uint32_t CF; /* 0 or 1 */
47 uint32_t VF; /* V is the bit 31. All other bits are undefined */
48 uint32_t NF; /* N is bit 31. All other bits are undefined. */
49 uint32_t ZF; /* Z set if zero. */
50
51 /* System control coprocessor (cp0) */
52 struct {
53 uint32_t c0_cpuid;
54 uint32_t c0_cachetype;
55 uint32_t c1_sys; /* System control register. */
56 uint32_t c2_base; /* MMU translation table base. */
57 uint32_t c3_faultstatus; /* Fault status registers. */
58 uint32_t c4_faultaddr; /* Fault address registers. */
59 uint32_t c5_cacheop; /* Cache operation registers. */
60 uint32_t c6_tlbop; /* TLB operation registers. */
61 } cp0;
62
63 /* UniCore-F64 coprocessor state. */
64 struct {
65 float64 regs[16];
66 uint32_t xregs[32];
67 float_status fp_status;
68 } ucf64;
69
70 CPU_COMMON
71
72 /* Internal CPU feature flags. */
73 uint32_t features;
74
75 } CPUUniCore32State;
76
77 #define ASR_M (0x1f)
78 #define ASR_MODE_USER (0x10)
79 #define ASR_MODE_INTR (0x12)
80 #define ASR_MODE_PRIV (0x13)
81 #define ASR_MODE_TRAP (0x17)
82 #define ASR_MODE_EXTN (0x1b)
83 #define ASR_MODE_SUSR (0x1f)
84 #define ASR_I (1 << 7)
85 #define ASR_V (1 << 28)
86 #define ASR_C (1 << 29)
87 #define ASR_Z (1 << 30)
88 #define ASR_N (1 << 31)
89 #define ASR_NZCV (ASR_N | ASR_Z | ASR_C | ASR_V)
90 #define ASR_RESERVED (~(ASR_M | ASR_I | ASR_NZCV))
91
92 #define UC32_EXCP_PRIV (1)
93 #define UC32_EXCP_ITRAP (2)
94 #define UC32_EXCP_DTRAP (3)
95 #define UC32_EXCP_INTR (4)
96
97 /* Return the current ASR value. */
98 target_ulong cpu_asr_read(CPUUniCore32State *env1);
99 /* Set the ASR. Note that some bits of mask must be all-set or all-clear. */
100 void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask);
101
102 /* UniCore-F64 system registers. */
103 #define UC32_UCF64_FPSCR (31)
104 #define UCF64_FPSCR_MASK (0x27ffffff)
105 #define UCF64_FPSCR_RND_MASK (0x7)
106 #define UCF64_FPSCR_RND(r) (((r) >> 0) & UCF64_FPSCR_RND_MASK)
107 #define UCF64_FPSCR_TRAPEN_MASK (0x7f)
108 #define UCF64_FPSCR_TRAPEN(r) (((r) >> 10) & UCF64_FPSCR_TRAPEN_MASK)
109 #define UCF64_FPSCR_FLAG_MASK (0x3ff)
110 #define UCF64_FPSCR_FLAG(r) (((r) >> 17) & UCF64_FPSCR_FLAG_MASK)
111 #define UCF64_FPSCR_FLAG_ZERO (1 << 17)
112 #define UCF64_FPSCR_FLAG_INFINITY (1 << 18)
113 #define UCF64_FPSCR_FLAG_INVALID (1 << 19)
114 #define UCF64_FPSCR_FLAG_UNDERFLOW (1 << 20)
115 #define UCF64_FPSCR_FLAG_OVERFLOW (1 << 21)
116 #define UCF64_FPSCR_FLAG_INEXACT (1 << 22)
117 #define UCF64_FPSCR_FLAG_HUGEINT (1 << 23)
118 #define UCF64_FPSCR_FLAG_DENORMAL (1 << 24)
119 #define UCF64_FPSCR_FLAG_UNIMP (1 << 25)
120 #define UCF64_FPSCR_FLAG_DIVZERO (1 << 26)
121
122 #define UC32_HWCAP_CMOV 4 /* 1 << 2 */
123 #define UC32_HWCAP_UCF64 8 /* 1 << 3 */
124
125 #define cpu_init uc32_cpu_init
126 #define cpu_exec uc32_cpu_exec
127 #define cpu_signal_handler uc32_cpu_signal_handler
128 #define cpu_handle_mmu_fault uc32_cpu_handle_mmu_fault
129
130 CPUUniCore32State *uc32_cpu_init(const char *cpu_model);
131 int uc32_cpu_exec(CPUUniCore32State *s);
132 int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
133 int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw,
134 int mmu_idx);
135
136 /* MMU modes definitions */
137 #define MMU_MODE0_SUFFIX _kernel
138 #define MMU_MODE1_SUFFIX _user
139 #define MMU_USER_IDX 1
140 static inline int cpu_mmu_index(CPUUniCore32State *env)
141 {
142 return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0;
143 }
144
145 static inline void cpu_clone_regs(CPUUniCore32State *env, target_ulong newsp)
146 {
147 if (newsp) {
148 env->regs[29] = newsp;
149 }
150 env->regs[0] = 0;
151 }
152
153 static inline void cpu_set_tls(CPUUniCore32State *env, target_ulong newtls)
154 {
155 env->regs[16] = newtls;
156 }
157
158 #include "exec/cpu-all.h"
159 #include "cpu-qom.h"
160 #include "exec/exec-all.h"
161
162 static inline void cpu_pc_from_tb(CPUUniCore32State *env, TranslationBlock *tb)
163 {
164 env->regs[31] = tb->pc;
165 }
166
167 static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc,
168 target_ulong *cs_base, int *flags)
169 {
170 *pc = env->regs[31];
171 *cs_base = 0;
172 *flags = 0;
173 if ((env->uncached_asr & ASR_M) != ASR_MODE_USER) {
174 *flags |= (1 << 6);
175 }
176 }
177
178 void uc32_translate_init(void);
179 void do_interrupt(CPUUniCore32State *);
180 void switch_mode(CPUUniCore32State *, int);
181
182 static inline bool cpu_has_work(CPUState *cpu)
183 {
184 return cpu->interrupt_request &
185 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
186 }
187
188 #endif /* QEMU_UNICORE32_CPU_H */