cputlb: Change tlb_flush() argument to CPUState
[qemu.git] / target-unicore32 / helper.c
1 /*
2 * Copyright (C) 2010-2012 Guan Xuetao
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Contributions from 2012-04-01 on are considered under GPL version 2,
9 * or (at your option) any later version.
10 */
11
12 #include "cpu.h"
13 #include "exec/gdbstub.h"
14 #include "helper.h"
15 #include "qemu/host-utils.h"
16 #ifndef CONFIG_USER_ONLY
17 #include "ui/console.h"
18 #endif
19
20 #undef DEBUG_UC32
21
22 #ifdef DEBUG_UC32
23 #define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
24 #else
25 #define DPRINTF(fmt, ...) do {} while (0)
26 #endif
27
28 CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
29 {
30 UniCore32CPU *cpu;
31
32 cpu = UNICORE32_CPU(cpu_generic_init(TYPE_UNICORE32_CPU, cpu_model));
33 if (cpu == NULL) {
34 return NULL;
35 }
36 return &cpu->env;
37 }
38
39 uint32_t HELPER(clo)(uint32_t x)
40 {
41 return clo32(x);
42 }
43
44 uint32_t HELPER(clz)(uint32_t x)
45 {
46 return clz32(x);
47 }
48
49 #ifndef CONFIG_USER_ONLY
50 void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
51 uint32_t cop)
52 {
53 UniCore32CPU *cpu = uc32_env_get_cpu(env);
54
55 /*
56 * movc pp.nn, rn, #imm9
57 * rn: UCOP_REG_D
58 * nn: UCOP_REG_N
59 * 1: sys control reg.
60 * 2: page table base reg.
61 * 3: data fault status reg.
62 * 4: insn fault status reg.
63 * 5: cache op. reg.
64 * 6: tlb op. reg.
65 * imm9: split UCOP_IMM10 with bit5 is 0
66 */
67 switch (creg) {
68 case 1:
69 if (cop != 0) {
70 goto unrecognized;
71 }
72 env->cp0.c1_sys = val;
73 break;
74 case 2:
75 if (cop != 0) {
76 goto unrecognized;
77 }
78 env->cp0.c2_base = val;
79 break;
80 case 3:
81 if (cop != 0) {
82 goto unrecognized;
83 }
84 env->cp0.c3_faultstatus = val;
85 break;
86 case 4:
87 if (cop != 0) {
88 goto unrecognized;
89 }
90 env->cp0.c4_faultaddr = val;
91 break;
92 case 5:
93 switch (cop) {
94 case 28:
95 DPRINTF("Invalidate Entire I&D cache\n");
96 return;
97 case 20:
98 DPRINTF("Invalidate Entire Icache\n");
99 return;
100 case 12:
101 DPRINTF("Invalidate Entire Dcache\n");
102 return;
103 case 10:
104 DPRINTF("Clean Entire Dcache\n");
105 return;
106 case 14:
107 DPRINTF("Flush Entire Dcache\n");
108 return;
109 case 13:
110 DPRINTF("Invalidate Dcache line\n");
111 return;
112 case 11:
113 DPRINTF("Clean Dcache line\n");
114 return;
115 case 15:
116 DPRINTF("Flush Dcache line\n");
117 return;
118 }
119 break;
120 case 6:
121 if ((cop <= 6) && (cop >= 2)) {
122 /* invalid all tlb */
123 tlb_flush(CPU(cpu), 1);
124 return;
125 }
126 break;
127 default:
128 goto unrecognized;
129 }
130 return;
131 unrecognized:
132 DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
133 creg, cop);
134 }
135
136 uint32_t helper_cp0_get(CPUUniCore32State *env, uint32_t creg, uint32_t cop)
137 {
138 /*
139 * movc rd, pp.nn, #imm9
140 * rd: UCOP_REG_D
141 * nn: UCOP_REG_N
142 * 0: cpuid and cachetype
143 * 1: sys control reg.
144 * 2: page table base reg.
145 * 3: data fault status reg.
146 * 4: insn fault status reg.
147 * imm9: split UCOP_IMM10 with bit5 is 0
148 */
149 switch (creg) {
150 case 0:
151 switch (cop) {
152 case 0:
153 return env->cp0.c0_cpuid;
154 case 1:
155 return env->cp0.c0_cachetype;
156 }
157 break;
158 case 1:
159 if (cop == 0) {
160 return env->cp0.c1_sys;
161 }
162 break;
163 case 2:
164 if (cop == 0) {
165 return env->cp0.c2_base;
166 }
167 break;
168 case 3:
169 if (cop == 0) {
170 return env->cp0.c3_faultstatus;
171 }
172 break;
173 case 4:
174 if (cop == 0) {
175 return env->cp0.c4_faultaddr;
176 }
177 break;
178 }
179 DPRINTF("Wrong register (%d) or wrong operation (%d) in cp0_set!\n",
180 creg, cop);
181 return 0;
182 }
183
184 #ifdef CONFIG_CURSES
185 /*
186 * FIXME:
187 * 1. curses windows will be blank when switching back
188 * 2. backspace is not handled yet
189 */
190 static void putc_on_screen(unsigned char ch)
191 {
192 static WINDOW *localwin;
193 static int init;
194
195 if (!init) {
196 /* Assume 80 * 30 screen to minimize the implementation */
197 localwin = newwin(30, 80, 0, 0);
198 scrollok(localwin, TRUE);
199 init = TRUE;
200 }
201
202 if (isprint(ch)) {
203 wprintw(localwin, "%c", ch);
204 } else {
205 switch (ch) {
206 case '\n':
207 wprintw(localwin, "%c", ch);
208 break;
209 case '\r':
210 /* If '\r' is put before '\n', the curses window will destroy the
211 * last print line. And meanwhile, '\n' implifies '\r' inside. */
212 break;
213 default: /* Not handled, so just print it hex code */
214 wprintw(localwin, "-- 0x%x --", ch);
215 }
216 }
217
218 wrefresh(localwin);
219 }
220 #else
221 #define putc_on_screen(c) do { } while (0)
222 #endif
223
224 void helper_cp1_putc(target_ulong x)
225 {
226 putc_on_screen((unsigned char)x); /* Output to screen */
227 DPRINTF("%c", x); /* Output to stdout */
228 }
229 #endif
230
231 #ifdef CONFIG_USER_ONLY
232 void switch_mode(CPUUniCore32State *env, int mode)
233 {
234 UniCore32CPU *cpu = uc32_env_get_cpu(env);
235
236 if (mode != ASR_MODE_USER) {
237 cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
238 }
239 }
240
241 void uc32_cpu_do_interrupt(CPUState *cs)
242 {
243 cpu_abort(cs, "NO interrupt in user mode\n");
244 }
245
246 int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
247 int access_type, int mmu_idx)
248 {
249 cpu_abort(cs, "NO mmu fault in user mode\n");
250 return 1;
251 }
252 #endif