target-unicore32: Clean up ENV_GET_CPU() usage
[qemu.git] / target-unicore32 / softmmu.c
1 /*
2 * Softmmu related functions
3 *
4 * Copyright (C) 2010-2012 Guan Xuetao
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or any later version.
9 * See the COPYING file in the top-level directory.
10 */
11 #ifdef CONFIG_USER_ONLY
12 #error This file only exist under softmmu circumstance
13 #endif
14
15 #include <cpu.h>
16
17 #undef DEBUG_UC32
18
19 #ifdef DEBUG_UC32
20 #define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
21 #else
22 #define DPRINTF(fmt, ...) do {} while (0)
23 #endif
24
25 #define SUPERPAGE_SIZE (1 << 22)
26 #define UC32_PAGETABLE_READ (1 << 8)
27 #define UC32_PAGETABLE_WRITE (1 << 7)
28 #define UC32_PAGETABLE_EXEC (1 << 6)
29 #define UC32_PAGETABLE_EXIST (1 << 2)
30 #define PAGETABLE_TYPE(x) ((x) & 3)
31
32
33 /* Map CPU modes onto saved register banks. */
34 static inline int bank_number(CPUUniCore32State *env, int mode)
35 {
36 switch (mode) {
37 case ASR_MODE_USER:
38 case ASR_MODE_SUSR:
39 return 0;
40 case ASR_MODE_PRIV:
41 return 1;
42 case ASR_MODE_TRAP:
43 return 2;
44 case ASR_MODE_EXTN:
45 return 3;
46 case ASR_MODE_INTR:
47 return 4;
48 }
49 cpu_abort(env, "Bad mode %x\n", mode);
50 return -1;
51 }
52
53 void switch_mode(CPUUniCore32State *env, int mode)
54 {
55 int old_mode;
56 int i;
57
58 old_mode = env->uncached_asr & ASR_M;
59 if (mode == old_mode) {
60 return;
61 }
62
63 i = bank_number(env, old_mode);
64 env->banked_r29[i] = env->regs[29];
65 env->banked_r30[i] = env->regs[30];
66 env->banked_bsr[i] = env->bsr;
67
68 i = bank_number(env, mode);
69 env->regs[29] = env->banked_r29[i];
70 env->regs[30] = env->banked_r30[i];
71 env->bsr = env->banked_bsr[i];
72 }
73
74 /* Handle a CPU exception. */
75 void uc32_cpu_do_interrupt(CPUState *cs)
76 {
77 UniCore32CPU *cpu = UNICORE32_CPU(cs);
78 CPUUniCore32State *env = &cpu->env;
79 uint32_t addr;
80 int new_mode;
81
82 switch (env->exception_index) {
83 case UC32_EXCP_PRIV:
84 new_mode = ASR_MODE_PRIV;
85 addr = 0x08;
86 break;
87 case UC32_EXCP_ITRAP:
88 DPRINTF("itrap happened at %x\n", env->regs[31]);
89 new_mode = ASR_MODE_TRAP;
90 addr = 0x0c;
91 break;
92 case UC32_EXCP_DTRAP:
93 DPRINTF("dtrap happened at %x\n", env->regs[31]);
94 new_mode = ASR_MODE_TRAP;
95 addr = 0x10;
96 break;
97 case UC32_EXCP_INTR:
98 new_mode = ASR_MODE_INTR;
99 addr = 0x18;
100 break;
101 default:
102 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
103 return;
104 }
105 /* High vectors. */
106 if (env->cp0.c1_sys & (1 << 13)) {
107 addr += 0xffff0000;
108 }
109
110 switch_mode(env, new_mode);
111 env->bsr = cpu_asr_read(env);
112 env->uncached_asr = (env->uncached_asr & ~ASR_M) | new_mode;
113 env->uncached_asr |= ASR_I;
114 /* The PC already points to the proper instruction. */
115 env->regs[30] = env->regs[31];
116 env->regs[31] = addr;
117 cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
118 }
119
120 static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
121 int access_type, int is_user, uint32_t *phys_ptr, int *prot,
122 target_ulong *page_size)
123 {
124 CPUState *cs = CPU(uc32_env_get_cpu(env));
125 int code;
126 uint32_t table;
127 uint32_t desc;
128 uint32_t phys_addr;
129
130 /* Pagetable walk. */
131 /* Lookup l1 descriptor. */
132 table = env->cp0.c2_base & 0xfffff000;
133 table |= (address >> 20) & 0xffc;
134 desc = ldl_phys(cs->as, table);
135 code = 0;
136 switch (PAGETABLE_TYPE(desc)) {
137 case 3:
138 /* Superpage */
139 if (!(desc & UC32_PAGETABLE_EXIST)) {
140 code = 0x0b; /* superpage miss */
141 goto do_fault;
142 }
143 phys_addr = (desc & 0xffc00000) | (address & 0x003fffff);
144 *page_size = SUPERPAGE_SIZE;
145 break;
146 case 0:
147 /* Lookup l2 entry. */
148 if (is_user) {
149 DPRINTF("PGD address %x, desc %x\n", table, desc);
150 }
151 if (!(desc & UC32_PAGETABLE_EXIST)) {
152 code = 0x05; /* second pagetable miss */
153 goto do_fault;
154 }
155 table = (desc & 0xfffff000) | ((address >> 10) & 0xffc);
156 desc = ldl_phys(cs->as, table);
157 /* 4k page. */
158 if (is_user) {
159 DPRINTF("PTE address %x, desc %x\n", table, desc);
160 }
161 if (!(desc & UC32_PAGETABLE_EXIST)) {
162 code = 0x08; /* page miss */
163 goto do_fault;
164 }
165 switch (PAGETABLE_TYPE(desc)) {
166 case 0:
167 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
168 *page_size = TARGET_PAGE_SIZE;
169 break;
170 default:
171 cpu_abort(env, "wrong page type!");
172 }
173 break;
174 default:
175 cpu_abort(env, "wrong page type!");
176 }
177
178 *phys_ptr = phys_addr;
179 *prot = 0;
180 /* Check access permissions. */
181 if (desc & UC32_PAGETABLE_READ) {
182 *prot |= PAGE_READ;
183 } else {
184 if (is_user && (access_type == 0)) {
185 code = 0x11; /* access unreadable area */
186 goto do_fault;
187 }
188 }
189
190 if (desc & UC32_PAGETABLE_WRITE) {
191 *prot |= PAGE_WRITE;
192 } else {
193 if (is_user && (access_type == 1)) {
194 code = 0x12; /* access unwritable area */
195 goto do_fault;
196 }
197 }
198
199 if (desc & UC32_PAGETABLE_EXEC) {
200 *prot |= PAGE_EXEC;
201 } else {
202 if (is_user && (access_type == 2)) {
203 code = 0x13; /* access unexecutable area */
204 goto do_fault;
205 }
206 }
207
208 do_fault:
209 return code;
210 }
211
212 int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
213 int access_type, int mmu_idx)
214 {
215 uint32_t phys_addr;
216 target_ulong page_size;
217 int prot;
218 int ret, is_user;
219
220 ret = 1;
221 is_user = mmu_idx == MMU_USER_IDX;
222
223 if ((env->cp0.c1_sys & 1) == 0) {
224 /* MMU disabled. */
225 phys_addr = address;
226 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
227 page_size = TARGET_PAGE_SIZE;
228 ret = 0;
229 } else {
230 if ((address & (1 << 31)) || (is_user)) {
231 ret = get_phys_addr_ucv2(env, address, access_type, is_user,
232 &phys_addr, &prot, &page_size);
233 if (is_user) {
234 DPRINTF("user space access: ret %x, address %x, "
235 "access_type %x, phys_addr %x, prot %x\n",
236 ret, address, access_type, phys_addr, prot);
237 }
238 } else {
239 /*IO memory */
240 phys_addr = address | (1 << 31);
241 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
242 page_size = TARGET_PAGE_SIZE;
243 ret = 0;
244 }
245 }
246
247 if (ret == 0) {
248 /* Map a single page. */
249 phys_addr &= TARGET_PAGE_MASK;
250 address &= TARGET_PAGE_MASK;
251 tlb_set_page(env, address, phys_addr, prot, mmu_idx, page_size);
252 return 0;
253 }
254
255 env->cp0.c3_faultstatus = ret;
256 env->cp0.c4_faultaddr = address;
257 if (access_type == 2) {
258 env->exception_index = UC32_EXCP_ITRAP;
259 } else {
260 env->exception_index = UC32_EXCP_DTRAP;
261 }
262 return ret;
263 }
264
265 hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
266 {
267 UniCore32CPU *cpu = UNICORE32_CPU(cs);
268
269 cpu_abort(&cpu->env, "%s not supported yet\n", __func__);
270 return addr;
271 }