target-xtensa: add missing window check for entry
[qemu.git] / target-xtensa / cpu.h
1 /*
2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #ifndef CPU_XTENSA_H
29 #define CPU_XTENSA_H
30
31 #define ALIGNED_ONLY
32 #define TARGET_LONG_BITS 32
33 #define ELF_MACHINE EM_XTENSA
34
35 #define CPUArchState struct CPUXtensaState
36
37 #include "config.h"
38 #include "qemu-common.h"
39 #include "exec/cpu-defs.h"
40 #include "fpu/softfloat.h"
41
42 #define TARGET_HAS_ICE 1
43
44 #define NB_MMU_MODES 4
45
46 #define TARGET_PHYS_ADDR_SPACE_BITS 32
47 #define TARGET_VIRT_ADDR_SPACE_BITS 32
48 #define TARGET_PAGE_BITS 12
49
50 enum {
51 /* Additional instructions */
52 XTENSA_OPTION_CODE_DENSITY,
53 XTENSA_OPTION_LOOP,
54 XTENSA_OPTION_EXTENDED_L32R,
55 XTENSA_OPTION_16_BIT_IMUL,
56 XTENSA_OPTION_32_BIT_IMUL,
57 XTENSA_OPTION_32_BIT_IMUL_HIGH,
58 XTENSA_OPTION_32_BIT_IDIV,
59 XTENSA_OPTION_MAC16,
60 XTENSA_OPTION_MISC_OP_NSA,
61 XTENSA_OPTION_MISC_OP_MINMAX,
62 XTENSA_OPTION_MISC_OP_SEXT,
63 XTENSA_OPTION_MISC_OP_CLAMPS,
64 XTENSA_OPTION_COPROCESSOR,
65 XTENSA_OPTION_BOOLEAN,
66 XTENSA_OPTION_FP_COPROCESSOR,
67 XTENSA_OPTION_MP_SYNCHRO,
68 XTENSA_OPTION_CONDITIONAL_STORE,
69 XTENSA_OPTION_ATOMCTL,
70
71 /* Interrupts and exceptions */
72 XTENSA_OPTION_EXCEPTION,
73 XTENSA_OPTION_RELOCATABLE_VECTOR,
74 XTENSA_OPTION_UNALIGNED_EXCEPTION,
75 XTENSA_OPTION_INTERRUPT,
76 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
77 XTENSA_OPTION_TIMER_INTERRUPT,
78
79 /* Local memory */
80 XTENSA_OPTION_ICACHE,
81 XTENSA_OPTION_ICACHE_TEST,
82 XTENSA_OPTION_ICACHE_INDEX_LOCK,
83 XTENSA_OPTION_DCACHE,
84 XTENSA_OPTION_DCACHE_TEST,
85 XTENSA_OPTION_DCACHE_INDEX_LOCK,
86 XTENSA_OPTION_IRAM,
87 XTENSA_OPTION_IROM,
88 XTENSA_OPTION_DRAM,
89 XTENSA_OPTION_DROM,
90 XTENSA_OPTION_XLMI,
91 XTENSA_OPTION_HW_ALIGNMENT,
92 XTENSA_OPTION_MEMORY_ECC_PARITY,
93
94 /* Memory protection and translation */
95 XTENSA_OPTION_REGION_PROTECTION,
96 XTENSA_OPTION_REGION_TRANSLATION,
97 XTENSA_OPTION_MMU,
98 XTENSA_OPTION_CACHEATTR,
99
100 /* Other */
101 XTENSA_OPTION_WINDOWED_REGISTER,
102 XTENSA_OPTION_PROCESSOR_INTERFACE,
103 XTENSA_OPTION_MISC_SR,
104 XTENSA_OPTION_THREAD_POINTER,
105 XTENSA_OPTION_PROCESSOR_ID,
106 XTENSA_OPTION_DEBUG,
107 XTENSA_OPTION_TRACE_PORT,
108 };
109
110 enum {
111 THREADPTR = 231,
112 FCR = 232,
113 FSR = 233,
114 };
115
116 enum {
117 LBEG = 0,
118 LEND = 1,
119 LCOUNT = 2,
120 SAR = 3,
121 BR = 4,
122 LITBASE = 5,
123 SCOMPARE1 = 12,
124 ACCLO = 16,
125 ACCHI = 17,
126 MR = 32,
127 WINDOW_BASE = 72,
128 WINDOW_START = 73,
129 PTEVADDR = 83,
130 RASID = 90,
131 ITLBCFG = 91,
132 DTLBCFG = 92,
133 IBREAKENABLE = 96,
134 CACHEATTR = 98,
135 ATOMCTL = 99,
136 IBREAKA = 128,
137 DBREAKA = 144,
138 DBREAKC = 160,
139 CONFIGID0 = 176,
140 EPC1 = 177,
141 DEPC = 192,
142 EPS2 = 194,
143 CONFIGID1 = 208,
144 EXCSAVE1 = 209,
145 CPENABLE = 224,
146 INTSET = 226,
147 INTCLEAR = 227,
148 INTENABLE = 228,
149 PS = 230,
150 VECBASE = 231,
151 EXCCAUSE = 232,
152 DEBUGCAUSE = 233,
153 CCOUNT = 234,
154 PRID = 235,
155 ICOUNT = 236,
156 ICOUNTLEVEL = 237,
157 EXCVADDR = 238,
158 CCOMPARE = 240,
159 MISC = 244,
160 };
161
162 #define PS_INTLEVEL 0xf
163 #define PS_INTLEVEL_SHIFT 0
164
165 #define PS_EXCM 0x10
166 #define PS_UM 0x20
167
168 #define PS_RING 0xc0
169 #define PS_RING_SHIFT 6
170
171 #define PS_OWB 0xf00
172 #define PS_OWB_SHIFT 8
173
174 #define PS_CALLINC 0x30000
175 #define PS_CALLINC_SHIFT 16
176 #define PS_CALLINC_LEN 2
177
178 #define PS_WOE 0x40000
179
180 #define DEBUGCAUSE_IC 0x1
181 #define DEBUGCAUSE_IB 0x2
182 #define DEBUGCAUSE_DB 0x4
183 #define DEBUGCAUSE_BI 0x8
184 #define DEBUGCAUSE_BN 0x10
185 #define DEBUGCAUSE_DI 0x20
186 #define DEBUGCAUSE_DBNUM 0xf00
187 #define DEBUGCAUSE_DBNUM_SHIFT 8
188
189 #define DBREAKC_SB 0x80000000
190 #define DBREAKC_LB 0x40000000
191 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
192 #define DBREAKC_MASK 0x3f
193
194 #define MAX_NAREG 64
195 #define MAX_NINTERRUPT 32
196 #define MAX_NLEVEL 6
197 #define MAX_NNMI 1
198 #define MAX_NCCOMPARE 3
199 #define MAX_TLB_WAY_SIZE 8
200 #define MAX_NDBREAK 2
201
202 #define REGION_PAGE_MASK 0xe0000000
203
204 #define PAGE_CACHE_MASK 0x700
205 #define PAGE_CACHE_SHIFT 8
206 #define PAGE_CACHE_INVALID 0x000
207 #define PAGE_CACHE_BYPASS 0x100
208 #define PAGE_CACHE_WT 0x200
209 #define PAGE_CACHE_WB 0x400
210 #define PAGE_CACHE_ISOLATE 0x600
211
212 enum {
213 /* Static vectors */
214 EXC_RESET,
215 EXC_MEMORY_ERROR,
216
217 /* Dynamic vectors */
218 EXC_WINDOW_OVERFLOW4,
219 EXC_WINDOW_UNDERFLOW4,
220 EXC_WINDOW_OVERFLOW8,
221 EXC_WINDOW_UNDERFLOW8,
222 EXC_WINDOW_OVERFLOW12,
223 EXC_WINDOW_UNDERFLOW12,
224 EXC_IRQ,
225 EXC_KERNEL,
226 EXC_USER,
227 EXC_DOUBLE,
228 EXC_DEBUG,
229 EXC_MAX
230 };
231
232 enum {
233 ILLEGAL_INSTRUCTION_CAUSE = 0,
234 SYSCALL_CAUSE,
235 INSTRUCTION_FETCH_ERROR_CAUSE,
236 LOAD_STORE_ERROR_CAUSE,
237 LEVEL1_INTERRUPT_CAUSE,
238 ALLOCA_CAUSE,
239 INTEGER_DIVIDE_BY_ZERO_CAUSE,
240 PRIVILEGED_CAUSE = 8,
241 LOAD_STORE_ALIGNMENT_CAUSE,
242
243 INSTR_PIF_DATA_ERROR_CAUSE = 12,
244 LOAD_STORE_PIF_DATA_ERROR_CAUSE,
245 INSTR_PIF_ADDR_ERROR_CAUSE,
246 LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
247
248 INST_TLB_MISS_CAUSE,
249 INST_TLB_MULTI_HIT_CAUSE,
250 INST_FETCH_PRIVILEGE_CAUSE,
251 INST_FETCH_PROHIBITED_CAUSE = 20,
252 LOAD_STORE_TLB_MISS_CAUSE = 24,
253 LOAD_STORE_TLB_MULTI_HIT_CAUSE,
254 LOAD_STORE_PRIVILEGE_CAUSE,
255 LOAD_PROHIBITED_CAUSE = 28,
256 STORE_PROHIBITED_CAUSE,
257
258 COPROCESSOR0_DISABLED = 32,
259 };
260
261 typedef enum {
262 INTTYPE_LEVEL,
263 INTTYPE_EDGE,
264 INTTYPE_NMI,
265 INTTYPE_SOFTWARE,
266 INTTYPE_TIMER,
267 INTTYPE_DEBUG,
268 INTTYPE_WRITE_ERR,
269 INTTYPE_PROFILING,
270 INTTYPE_MAX
271 } interrupt_type;
272
273 typedef struct xtensa_tlb_entry {
274 uint32_t vaddr;
275 uint32_t paddr;
276 uint8_t asid;
277 uint8_t attr;
278 bool variable;
279 } xtensa_tlb_entry;
280
281 typedef struct xtensa_tlb {
282 unsigned nways;
283 const unsigned way_size[10];
284 bool varway56;
285 unsigned nrefillentries;
286 } xtensa_tlb;
287
288 typedef struct XtensaGdbReg {
289 int targno;
290 int type;
291 int group;
292 } XtensaGdbReg;
293
294 typedef struct XtensaGdbRegmap {
295 int num_regs;
296 int num_core_regs;
297 /* PC + a + ar + sr + ur */
298 XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
299 } XtensaGdbRegmap;
300
301 typedef struct XtensaConfig {
302 const char *name;
303 uint64_t options;
304 XtensaGdbRegmap gdb_regmap;
305 unsigned nareg;
306 int excm_level;
307 int ndepc;
308 uint32_t vecbase;
309 uint32_t exception_vector[EXC_MAX];
310 unsigned ninterrupt;
311 unsigned nlevel;
312 uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
313 uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
314 uint32_t inttype_mask[INTTYPE_MAX];
315 struct {
316 uint32_t level;
317 interrupt_type inttype;
318 } interrupt[MAX_NINTERRUPT];
319 unsigned nccompare;
320 uint32_t timerint[MAX_NCCOMPARE];
321 unsigned nextint;
322 unsigned extint[MAX_NINTERRUPT];
323
324 unsigned debug_level;
325 unsigned nibreak;
326 unsigned ndbreak;
327
328 uint32_t configid[2];
329
330 uint32_t clock_freq_khz;
331
332 xtensa_tlb itlb;
333 xtensa_tlb dtlb;
334 } XtensaConfig;
335
336 typedef struct XtensaConfigList {
337 const XtensaConfig *config;
338 struct XtensaConfigList *next;
339 } XtensaConfigList;
340
341 typedef struct CPUXtensaState {
342 const XtensaConfig *config;
343 uint32_t regs[16];
344 uint32_t pc;
345 uint32_t sregs[256];
346 uint32_t uregs[256];
347 uint32_t phys_regs[MAX_NAREG];
348 float32 fregs[16];
349 float_status fp_status;
350
351 xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
352 xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
353 unsigned autorefill_idx;
354
355 int pending_irq_level; /* level of last raised IRQ */
356 void **irq_inputs;
357 QEMUTimer *ccompare_timer;
358 uint32_t wake_ccount;
359 int64_t halt_clock;
360
361 int exception_taken;
362
363 /* Watchpoints for DBREAK registers */
364 struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
365
366 CPU_COMMON
367 } CPUXtensaState;
368
369 #include "cpu-qom.h"
370
371 #define cpu_exec cpu_xtensa_exec
372 #define cpu_gen_code cpu_xtensa_gen_code
373 #define cpu_signal_handler cpu_xtensa_signal_handler
374 #define cpu_list xtensa_cpu_list
375
376 #ifdef TARGET_WORDS_BIGENDIAN
377 #define XTENSA_DEFAULT_CPU_MODEL "fsf"
378 #else
379 #define XTENSA_DEFAULT_CPU_MODEL "dc232b"
380 #endif
381
382 XtensaCPU *cpu_xtensa_init(const char *cpu_model);
383
384 static inline CPUXtensaState *cpu_init(const char *cpu_model)
385 {
386 XtensaCPU *cpu = cpu_xtensa_init(cpu_model);
387 if (cpu == NULL) {
388 return NULL;
389 }
390 return &cpu->env;
391 }
392
393 void xtensa_translate_init(void);
394 void xtensa_breakpoint_handler(CPUState *cs);
395 int cpu_xtensa_exec(CPUXtensaState *s);
396 void xtensa_register_core(XtensaConfigList *node);
397 void check_interrupts(CPUXtensaState *s);
398 void xtensa_irq_init(CPUXtensaState *env);
399 void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
400 void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
401 void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
402 void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
403 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
404 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
405 void xtensa_sync_window_from_phys(CPUXtensaState *env);
406 void xtensa_sync_phys_from_window(CPUXtensaState *env);
407 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
408 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
409 uint32_t *vpn, uint32_t wi, uint32_t *ei);
410 int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
411 uint32_t *pwi, uint32_t *pei, uint8_t *pring);
412 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
413 xtensa_tlb_entry *entry, bool dtlb,
414 unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
415 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
416 unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
417 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
418 uint32_t vaddr, int is_write, int mmu_idx,
419 uint32_t *paddr, uint32_t *page_size, unsigned *access);
420 void reset_mmu(CPUXtensaState *env);
421 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
422 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
423
424
425 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
426 #define XTENSA_OPTION_ALL (~(uint64_t)0)
427
428 static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
429 uint64_t opt)
430 {
431 return (config->options & opt) != 0;
432 }
433
434 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
435 {
436 return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
437 }
438
439 static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
440 {
441 int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
442 if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
443 level = env->config->excm_level;
444 }
445 return level;
446 }
447
448 static inline int xtensa_get_ring(const CPUXtensaState *env)
449 {
450 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
451 return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
452 } else {
453 return 0;
454 }
455 }
456
457 static inline int xtensa_get_cring(const CPUXtensaState *env)
458 {
459 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
460 (env->sregs[PS] & PS_EXCM) == 0) {
461 return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
462 } else {
463 return 0;
464 }
465 }
466
467 static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
468 bool dtlb, unsigned wi, unsigned ei)
469 {
470 return dtlb ?
471 env->dtlb[wi] + ei :
472 env->itlb[wi] + ei;
473 }
474
475 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
476 {
477 return env->sregs[WINDOW_START] |
478 (env->sregs[WINDOW_START] << env->config->nareg / 4);
479 }
480
481 /* MMU modes definitions */
482 #define MMU_MODE0_SUFFIX _ring0
483 #define MMU_MODE1_SUFFIX _ring1
484 #define MMU_MODE2_SUFFIX _ring2
485 #define MMU_MODE3_SUFFIX _ring3
486
487 static inline int cpu_mmu_index(CPUXtensaState *env)
488 {
489 return xtensa_get_cring(env);
490 }
491
492 #define XTENSA_TBFLAG_RING_MASK 0x3
493 #define XTENSA_TBFLAG_EXCM 0x4
494 #define XTENSA_TBFLAG_LITBASE 0x8
495 #define XTENSA_TBFLAG_DEBUG 0x10
496 #define XTENSA_TBFLAG_ICOUNT 0x20
497 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
498 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6
499 #define XTENSA_TBFLAG_EXCEPTION 0x4000
500
501 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
502 target_ulong *cs_base, int *flags)
503 {
504 CPUState *cs = CPU(xtensa_env_get_cpu(env));
505
506 *pc = env->pc;
507 *cs_base = 0;
508 *flags = 0;
509 *flags |= xtensa_get_ring(env);
510 if (env->sregs[PS] & PS_EXCM) {
511 *flags |= XTENSA_TBFLAG_EXCM;
512 }
513 if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
514 (env->sregs[LITBASE] & 1)) {
515 *flags |= XTENSA_TBFLAG_LITBASE;
516 }
517 if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
518 if (xtensa_get_cintlevel(env) < env->config->debug_level) {
519 *flags |= XTENSA_TBFLAG_DEBUG;
520 }
521 if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
522 *flags |= XTENSA_TBFLAG_ICOUNT;
523 }
524 }
525 if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
526 *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
527 }
528 if (cs->singlestep_enabled && env->exception_taken) {
529 *flags |= XTENSA_TBFLAG_EXCEPTION;
530 }
531 }
532
533 #include "exec/cpu-all.h"
534 #include "exec/exec-all.h"
535
536 #endif