cpu: Move watchpoint fields from CPU_COMMON to CPUState
[qemu.git] / target-xtensa / cpu.h
1 /*
2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #ifndef CPU_XTENSA_H
29 #define CPU_XTENSA_H
30
31 #define TARGET_LONG_BITS 32
32 #define ELF_MACHINE EM_XTENSA
33
34 #define CPUArchState struct CPUXtensaState
35
36 #include "config.h"
37 #include "qemu-common.h"
38 #include "exec/cpu-defs.h"
39 #include "fpu/softfloat.h"
40
41 #define TARGET_HAS_ICE 1
42
43 #define NB_MMU_MODES 4
44
45 #define TARGET_PHYS_ADDR_SPACE_BITS 32
46 #define TARGET_VIRT_ADDR_SPACE_BITS 32
47 #define TARGET_PAGE_BITS 12
48
49 enum {
50 /* Additional instructions */
51 XTENSA_OPTION_CODE_DENSITY,
52 XTENSA_OPTION_LOOP,
53 XTENSA_OPTION_EXTENDED_L32R,
54 XTENSA_OPTION_16_BIT_IMUL,
55 XTENSA_OPTION_32_BIT_IMUL,
56 XTENSA_OPTION_32_BIT_IMUL_HIGH,
57 XTENSA_OPTION_32_BIT_IDIV,
58 XTENSA_OPTION_MAC16,
59 XTENSA_OPTION_MISC_OP_NSA,
60 XTENSA_OPTION_MISC_OP_MINMAX,
61 XTENSA_OPTION_MISC_OP_SEXT,
62 XTENSA_OPTION_MISC_OP_CLAMPS,
63 XTENSA_OPTION_COPROCESSOR,
64 XTENSA_OPTION_BOOLEAN,
65 XTENSA_OPTION_FP_COPROCESSOR,
66 XTENSA_OPTION_MP_SYNCHRO,
67 XTENSA_OPTION_CONDITIONAL_STORE,
68 XTENSA_OPTION_ATOMCTL,
69
70 /* Interrupts and exceptions */
71 XTENSA_OPTION_EXCEPTION,
72 XTENSA_OPTION_RELOCATABLE_VECTOR,
73 XTENSA_OPTION_UNALIGNED_EXCEPTION,
74 XTENSA_OPTION_INTERRUPT,
75 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
76 XTENSA_OPTION_TIMER_INTERRUPT,
77
78 /* Local memory */
79 XTENSA_OPTION_ICACHE,
80 XTENSA_OPTION_ICACHE_TEST,
81 XTENSA_OPTION_ICACHE_INDEX_LOCK,
82 XTENSA_OPTION_DCACHE,
83 XTENSA_OPTION_DCACHE_TEST,
84 XTENSA_OPTION_DCACHE_INDEX_LOCK,
85 XTENSA_OPTION_IRAM,
86 XTENSA_OPTION_IROM,
87 XTENSA_OPTION_DRAM,
88 XTENSA_OPTION_DROM,
89 XTENSA_OPTION_XLMI,
90 XTENSA_OPTION_HW_ALIGNMENT,
91 XTENSA_OPTION_MEMORY_ECC_PARITY,
92
93 /* Memory protection and translation */
94 XTENSA_OPTION_REGION_PROTECTION,
95 XTENSA_OPTION_REGION_TRANSLATION,
96 XTENSA_OPTION_MMU,
97 XTENSA_OPTION_CACHEATTR,
98
99 /* Other */
100 XTENSA_OPTION_WINDOWED_REGISTER,
101 XTENSA_OPTION_PROCESSOR_INTERFACE,
102 XTENSA_OPTION_MISC_SR,
103 XTENSA_OPTION_THREAD_POINTER,
104 XTENSA_OPTION_PROCESSOR_ID,
105 XTENSA_OPTION_DEBUG,
106 XTENSA_OPTION_TRACE_PORT,
107 };
108
109 enum {
110 THREADPTR = 231,
111 FCR = 232,
112 FSR = 233,
113 };
114
115 enum {
116 LBEG = 0,
117 LEND = 1,
118 LCOUNT = 2,
119 SAR = 3,
120 BR = 4,
121 LITBASE = 5,
122 SCOMPARE1 = 12,
123 ACCLO = 16,
124 ACCHI = 17,
125 MR = 32,
126 WINDOW_BASE = 72,
127 WINDOW_START = 73,
128 PTEVADDR = 83,
129 RASID = 90,
130 ITLBCFG = 91,
131 DTLBCFG = 92,
132 IBREAKENABLE = 96,
133 CACHEATTR = 98,
134 ATOMCTL = 99,
135 IBREAKA = 128,
136 DBREAKA = 144,
137 DBREAKC = 160,
138 CONFIGID0 = 176,
139 EPC1 = 177,
140 DEPC = 192,
141 EPS2 = 194,
142 CONFIGID1 = 208,
143 EXCSAVE1 = 209,
144 CPENABLE = 224,
145 INTSET = 226,
146 INTCLEAR = 227,
147 INTENABLE = 228,
148 PS = 230,
149 VECBASE = 231,
150 EXCCAUSE = 232,
151 DEBUGCAUSE = 233,
152 CCOUNT = 234,
153 PRID = 235,
154 ICOUNT = 236,
155 ICOUNTLEVEL = 237,
156 EXCVADDR = 238,
157 CCOMPARE = 240,
158 MISC = 244,
159 };
160
161 #define PS_INTLEVEL 0xf
162 #define PS_INTLEVEL_SHIFT 0
163
164 #define PS_EXCM 0x10
165 #define PS_UM 0x20
166
167 #define PS_RING 0xc0
168 #define PS_RING_SHIFT 6
169
170 #define PS_OWB 0xf00
171 #define PS_OWB_SHIFT 8
172
173 #define PS_CALLINC 0x30000
174 #define PS_CALLINC_SHIFT 16
175 #define PS_CALLINC_LEN 2
176
177 #define PS_WOE 0x40000
178
179 #define DEBUGCAUSE_IC 0x1
180 #define DEBUGCAUSE_IB 0x2
181 #define DEBUGCAUSE_DB 0x4
182 #define DEBUGCAUSE_BI 0x8
183 #define DEBUGCAUSE_BN 0x10
184 #define DEBUGCAUSE_DI 0x20
185 #define DEBUGCAUSE_DBNUM 0xf00
186 #define DEBUGCAUSE_DBNUM_SHIFT 8
187
188 #define DBREAKC_SB 0x80000000
189 #define DBREAKC_LB 0x40000000
190 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
191 #define DBREAKC_MASK 0x3f
192
193 #define MAX_NAREG 64
194 #define MAX_NINTERRUPT 32
195 #define MAX_NLEVEL 6
196 #define MAX_NNMI 1
197 #define MAX_NCCOMPARE 3
198 #define MAX_TLB_WAY_SIZE 8
199 #define MAX_NDBREAK 2
200
201 #define REGION_PAGE_MASK 0xe0000000
202
203 #define PAGE_CACHE_MASK 0x700
204 #define PAGE_CACHE_SHIFT 8
205 #define PAGE_CACHE_INVALID 0x000
206 #define PAGE_CACHE_BYPASS 0x100
207 #define PAGE_CACHE_WT 0x200
208 #define PAGE_CACHE_WB 0x400
209 #define PAGE_CACHE_ISOLATE 0x600
210
211 enum {
212 /* Static vectors */
213 EXC_RESET,
214 EXC_MEMORY_ERROR,
215
216 /* Dynamic vectors */
217 EXC_WINDOW_OVERFLOW4,
218 EXC_WINDOW_UNDERFLOW4,
219 EXC_WINDOW_OVERFLOW8,
220 EXC_WINDOW_UNDERFLOW8,
221 EXC_WINDOW_OVERFLOW12,
222 EXC_WINDOW_UNDERFLOW12,
223 EXC_IRQ,
224 EXC_KERNEL,
225 EXC_USER,
226 EXC_DOUBLE,
227 EXC_DEBUG,
228 EXC_MAX
229 };
230
231 enum {
232 ILLEGAL_INSTRUCTION_CAUSE = 0,
233 SYSCALL_CAUSE,
234 INSTRUCTION_FETCH_ERROR_CAUSE,
235 LOAD_STORE_ERROR_CAUSE,
236 LEVEL1_INTERRUPT_CAUSE,
237 ALLOCA_CAUSE,
238 INTEGER_DIVIDE_BY_ZERO_CAUSE,
239 PRIVILEGED_CAUSE = 8,
240 LOAD_STORE_ALIGNMENT_CAUSE,
241
242 INSTR_PIF_DATA_ERROR_CAUSE = 12,
243 LOAD_STORE_PIF_DATA_ERROR_CAUSE,
244 INSTR_PIF_ADDR_ERROR_CAUSE,
245 LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
246
247 INST_TLB_MISS_CAUSE,
248 INST_TLB_MULTI_HIT_CAUSE,
249 INST_FETCH_PRIVILEGE_CAUSE,
250 INST_FETCH_PROHIBITED_CAUSE = 20,
251 LOAD_STORE_TLB_MISS_CAUSE = 24,
252 LOAD_STORE_TLB_MULTI_HIT_CAUSE,
253 LOAD_STORE_PRIVILEGE_CAUSE,
254 LOAD_PROHIBITED_CAUSE = 28,
255 STORE_PROHIBITED_CAUSE,
256
257 COPROCESSOR0_DISABLED = 32,
258 };
259
260 typedef enum {
261 INTTYPE_LEVEL,
262 INTTYPE_EDGE,
263 INTTYPE_NMI,
264 INTTYPE_SOFTWARE,
265 INTTYPE_TIMER,
266 INTTYPE_DEBUG,
267 INTTYPE_WRITE_ERR,
268 INTTYPE_MAX
269 } interrupt_type;
270
271 typedef struct xtensa_tlb_entry {
272 uint32_t vaddr;
273 uint32_t paddr;
274 uint8_t asid;
275 uint8_t attr;
276 bool variable;
277 } xtensa_tlb_entry;
278
279 typedef struct xtensa_tlb {
280 unsigned nways;
281 const unsigned way_size[10];
282 bool varway56;
283 unsigned nrefillentries;
284 } xtensa_tlb;
285
286 typedef struct XtensaGdbReg {
287 int targno;
288 int type;
289 int group;
290 } XtensaGdbReg;
291
292 typedef struct XtensaGdbRegmap {
293 int num_regs;
294 int num_core_regs;
295 /* PC + a + ar + sr + ur */
296 XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
297 } XtensaGdbRegmap;
298
299 typedef struct XtensaConfig {
300 const char *name;
301 uint64_t options;
302 XtensaGdbRegmap gdb_regmap;
303 unsigned nareg;
304 int excm_level;
305 int ndepc;
306 uint32_t vecbase;
307 uint32_t exception_vector[EXC_MAX];
308 unsigned ninterrupt;
309 unsigned nlevel;
310 uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
311 uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
312 uint32_t inttype_mask[INTTYPE_MAX];
313 struct {
314 uint32_t level;
315 interrupt_type inttype;
316 } interrupt[MAX_NINTERRUPT];
317 unsigned nccompare;
318 uint32_t timerint[MAX_NCCOMPARE];
319 unsigned nextint;
320 unsigned extint[MAX_NINTERRUPT];
321
322 unsigned debug_level;
323 unsigned nibreak;
324 unsigned ndbreak;
325
326 uint32_t configid[2];
327
328 uint32_t clock_freq_khz;
329
330 xtensa_tlb itlb;
331 xtensa_tlb dtlb;
332 } XtensaConfig;
333
334 typedef struct XtensaConfigList {
335 const XtensaConfig *config;
336 struct XtensaConfigList *next;
337 } XtensaConfigList;
338
339 typedef struct CPUXtensaState {
340 const XtensaConfig *config;
341 uint32_t regs[16];
342 uint32_t pc;
343 uint32_t sregs[256];
344 uint32_t uregs[256];
345 uint32_t phys_regs[MAX_NAREG];
346 float32 fregs[16];
347 float_status fp_status;
348
349 xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
350 xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
351 unsigned autorefill_idx;
352
353 int pending_irq_level; /* level of last raised IRQ */
354 void **irq_inputs;
355 QEMUTimer *ccompare_timer;
356 uint32_t wake_ccount;
357 int64_t halt_clock;
358
359 int exception_taken;
360
361 /* Watchpoints for DBREAK registers */
362 struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
363
364 CPU_COMMON
365 } CPUXtensaState;
366
367 #include "cpu-qom.h"
368
369 #define cpu_exec cpu_xtensa_exec
370 #define cpu_gen_code cpu_xtensa_gen_code
371 #define cpu_signal_handler cpu_xtensa_signal_handler
372 #define cpu_list xtensa_cpu_list
373
374 #ifdef TARGET_WORDS_BIGENDIAN
375 #define XTENSA_DEFAULT_CPU_MODEL "fsf"
376 #else
377 #define XTENSA_DEFAULT_CPU_MODEL "dc232b"
378 #endif
379
380 XtensaCPU *cpu_xtensa_init(const char *cpu_model);
381
382 static inline CPUXtensaState *cpu_init(const char *cpu_model)
383 {
384 XtensaCPU *cpu = cpu_xtensa_init(cpu_model);
385 if (cpu == NULL) {
386 return NULL;
387 }
388 return &cpu->env;
389 }
390
391 void xtensa_translate_init(void);
392 void xtensa_breakpoint_handler(CPUXtensaState *env);
393 int cpu_xtensa_exec(CPUXtensaState *s);
394 void xtensa_register_core(XtensaConfigList *node);
395 void check_interrupts(CPUXtensaState *s);
396 void xtensa_irq_init(CPUXtensaState *env);
397 void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
398 void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
399 void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
400 void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
401 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
402 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
403 void xtensa_sync_window_from_phys(CPUXtensaState *env);
404 void xtensa_sync_phys_from_window(CPUXtensaState *env);
405 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
406 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
407 uint32_t *vpn, uint32_t wi, uint32_t *ei);
408 int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
409 uint32_t *pwi, uint32_t *pei, uint8_t *pring);
410 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
411 xtensa_tlb_entry *entry, bool dtlb,
412 unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
413 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
414 unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
415 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
416 uint32_t vaddr, int is_write, int mmu_idx,
417 uint32_t *paddr, uint32_t *page_size, unsigned *access);
418 void reset_mmu(CPUXtensaState *env);
419 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
420 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
421
422
423 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
424 #define XTENSA_OPTION_ALL (~(uint64_t)0)
425
426 static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
427 uint64_t opt)
428 {
429 return (config->options & opt) != 0;
430 }
431
432 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
433 {
434 return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
435 }
436
437 static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
438 {
439 int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
440 if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
441 level = env->config->excm_level;
442 }
443 return level;
444 }
445
446 static inline int xtensa_get_ring(const CPUXtensaState *env)
447 {
448 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
449 return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
450 } else {
451 return 0;
452 }
453 }
454
455 static inline int xtensa_get_cring(const CPUXtensaState *env)
456 {
457 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
458 (env->sregs[PS] & PS_EXCM) == 0) {
459 return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
460 } else {
461 return 0;
462 }
463 }
464
465 static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
466 bool dtlb, unsigned wi, unsigned ei)
467 {
468 return dtlb ?
469 env->dtlb[wi] + ei :
470 env->itlb[wi] + ei;
471 }
472
473 /* MMU modes definitions */
474 #define MMU_MODE0_SUFFIX _ring0
475 #define MMU_MODE1_SUFFIX _ring1
476 #define MMU_MODE2_SUFFIX _ring2
477 #define MMU_MODE3_SUFFIX _ring3
478
479 static inline int cpu_mmu_index(CPUXtensaState *env)
480 {
481 return xtensa_get_cring(env);
482 }
483
484 #define XTENSA_TBFLAG_RING_MASK 0x3
485 #define XTENSA_TBFLAG_EXCM 0x4
486 #define XTENSA_TBFLAG_LITBASE 0x8
487 #define XTENSA_TBFLAG_DEBUG 0x10
488 #define XTENSA_TBFLAG_ICOUNT 0x20
489 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
490 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6
491 #define XTENSA_TBFLAG_EXCEPTION 0x4000
492
493 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
494 target_ulong *cs_base, int *flags)
495 {
496 CPUState *cs = CPU(xtensa_env_get_cpu(env));
497
498 *pc = env->pc;
499 *cs_base = 0;
500 *flags = 0;
501 *flags |= xtensa_get_ring(env);
502 if (env->sregs[PS] & PS_EXCM) {
503 *flags |= XTENSA_TBFLAG_EXCM;
504 }
505 if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
506 (env->sregs[LITBASE] & 1)) {
507 *flags |= XTENSA_TBFLAG_LITBASE;
508 }
509 if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
510 if (xtensa_get_cintlevel(env) < env->config->debug_level) {
511 *flags |= XTENSA_TBFLAG_DEBUG;
512 }
513 if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
514 *flags |= XTENSA_TBFLAG_ICOUNT;
515 }
516 }
517 if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
518 *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
519 }
520 if (cs->singlestep_enabled && env->exception_taken) {
521 *flags |= XTENSA_TBFLAG_EXCEPTION;
522 }
523 }
524
525 #include "exec/cpu-all.h"
526 #include "exec/exec-all.h"
527
528 #endif