qemu-img: Omit error_report() after img_open()
[qemu.git] / target-xtensa / op_helper.c
1 /*
2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include "cpu.h"
29 #include "exec/helper-proto.h"
30 #include "qemu/host-utils.h"
31 #include "exec/cpu_ldst.h"
32 #include "exec/address-spaces.h"
33 #include "qemu/timer.h"
34
35 void xtensa_cpu_do_unaligned_access(CPUState *cs,
36 vaddr addr, int is_write, int is_user, uintptr_t retaddr)
37 {
38 XtensaCPU *cpu = XTENSA_CPU(cs);
39 CPUXtensaState *env = &cpu->env;
40
41 if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
42 !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
43 cpu_restore_state(CPU(cpu), retaddr);
44 HELPER(exception_cause_vaddr)(env,
45 env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
46 }
47 }
48
49 void tlb_fill(CPUState *cs,
50 target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr)
51 {
52 XtensaCPU *cpu = XTENSA_CPU(cs);
53 CPUXtensaState *env = &cpu->env;
54 uint32_t paddr;
55 uint32_t page_size;
56 unsigned access;
57 int ret = xtensa_get_physical_addr(env, true, vaddr, is_write, mmu_idx,
58 &paddr, &page_size, &access);
59
60 qemu_log("%s(%08x, %d, %d) -> %08x, ret = %d\n", __func__,
61 vaddr, is_write, mmu_idx, paddr, ret);
62
63 if (ret == 0) {
64 tlb_set_page(cs,
65 vaddr & TARGET_PAGE_MASK,
66 paddr & TARGET_PAGE_MASK,
67 access, mmu_idx, page_size);
68 } else {
69 cpu_restore_state(cs, retaddr);
70 HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
71 }
72 }
73
74 static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
75 {
76 uint32_t paddr;
77 uint32_t page_size;
78 unsigned access;
79 int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
80 &paddr, &page_size, &access);
81 if (ret == 0) {
82 tb_invalidate_phys_addr(&address_space_memory, paddr);
83 }
84 }
85
86 void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
87 {
88 CPUState *cs = CPU(xtensa_env_get_cpu(env));
89
90 cs->exception_index = excp;
91 if (excp == EXCP_DEBUG) {
92 env->exception_taken = 0;
93 }
94 cpu_loop_exit(cs);
95 }
96
97 void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
98 {
99 uint32_t vector;
100
101 env->pc = pc;
102 if (env->sregs[PS] & PS_EXCM) {
103 if (env->config->ndepc) {
104 env->sregs[DEPC] = pc;
105 } else {
106 env->sregs[EPC1] = pc;
107 }
108 vector = EXC_DOUBLE;
109 } else {
110 env->sregs[EPC1] = pc;
111 vector = (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
112 }
113
114 env->sregs[EXCCAUSE] = cause;
115 env->sregs[PS] |= PS_EXCM;
116
117 HELPER(exception)(env, vector);
118 }
119
120 void HELPER(exception_cause_vaddr)(CPUXtensaState *env,
121 uint32_t pc, uint32_t cause, uint32_t vaddr)
122 {
123 env->sregs[EXCVADDR] = vaddr;
124 HELPER(exception_cause)(env, pc, cause);
125 }
126
127 void debug_exception_env(CPUXtensaState *env, uint32_t cause)
128 {
129 if (xtensa_get_cintlevel(env) < env->config->debug_level) {
130 HELPER(debug_exception)(env, env->pc, cause);
131 }
132 }
133
134 void HELPER(debug_exception)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
135 {
136 unsigned level = env->config->debug_level;
137
138 env->pc = pc;
139 env->sregs[DEBUGCAUSE] = cause;
140 env->sregs[EPC1 + level - 1] = pc;
141 env->sregs[EPS2 + level - 2] = env->sregs[PS];
142 env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) | PS_EXCM |
143 (level << PS_INTLEVEL_SHIFT);
144 HELPER(exception)(env, EXC_DEBUG);
145 }
146
147 uint32_t HELPER(nsa)(uint32_t v)
148 {
149 if (v & 0x80000000) {
150 v = ~v;
151 }
152 return v ? clz32(v) - 1 : 31;
153 }
154
155 uint32_t HELPER(nsau)(uint32_t v)
156 {
157 return v ? clz32(v) : 32;
158 }
159
160 static void copy_window_from_phys(CPUXtensaState *env,
161 uint32_t window, uint32_t phys, uint32_t n)
162 {
163 assert(phys < env->config->nareg);
164 if (phys + n <= env->config->nareg) {
165 memcpy(env->regs + window, env->phys_regs + phys,
166 n * sizeof(uint32_t));
167 } else {
168 uint32_t n1 = env->config->nareg - phys;
169 memcpy(env->regs + window, env->phys_regs + phys,
170 n1 * sizeof(uint32_t));
171 memcpy(env->regs + window + n1, env->phys_regs,
172 (n - n1) * sizeof(uint32_t));
173 }
174 }
175
176 static void copy_phys_from_window(CPUXtensaState *env,
177 uint32_t phys, uint32_t window, uint32_t n)
178 {
179 assert(phys < env->config->nareg);
180 if (phys + n <= env->config->nareg) {
181 memcpy(env->phys_regs + phys, env->regs + window,
182 n * sizeof(uint32_t));
183 } else {
184 uint32_t n1 = env->config->nareg - phys;
185 memcpy(env->phys_regs + phys, env->regs + window,
186 n1 * sizeof(uint32_t));
187 memcpy(env->phys_regs, env->regs + window + n1,
188 (n - n1) * sizeof(uint32_t));
189 }
190 }
191
192
193 static inline unsigned windowbase_bound(unsigned a, const CPUXtensaState *env)
194 {
195 return a & (env->config->nareg / 4 - 1);
196 }
197
198 static inline unsigned windowstart_bit(unsigned a, const CPUXtensaState *env)
199 {
200 return 1 << windowbase_bound(a, env);
201 }
202
203 void xtensa_sync_window_from_phys(CPUXtensaState *env)
204 {
205 copy_window_from_phys(env, 0, env->sregs[WINDOW_BASE] * 4, 16);
206 }
207
208 void xtensa_sync_phys_from_window(CPUXtensaState *env)
209 {
210 copy_phys_from_window(env, env->sregs[WINDOW_BASE] * 4, 0, 16);
211 }
212
213 static void rotate_window_abs(CPUXtensaState *env, uint32_t position)
214 {
215 xtensa_sync_phys_from_window(env);
216 env->sregs[WINDOW_BASE] = windowbase_bound(position, env);
217 xtensa_sync_window_from_phys(env);
218 }
219
220 static void rotate_window(CPUXtensaState *env, uint32_t delta)
221 {
222 rotate_window_abs(env, env->sregs[WINDOW_BASE] + delta);
223 }
224
225 void HELPER(wsr_windowbase)(CPUXtensaState *env, uint32_t v)
226 {
227 rotate_window_abs(env, v);
228 }
229
230 void HELPER(entry)(CPUXtensaState *env, uint32_t pc, uint32_t s, uint32_t imm)
231 {
232 int callinc = (env->sregs[PS] & PS_CALLINC) >> PS_CALLINC_SHIFT;
233 if (s > 3 || ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
234 qemu_log("Illegal entry instruction(pc = %08x), PS = %08x\n",
235 pc, env->sregs[PS]);
236 HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
237 } else {
238 env->regs[(callinc << 2) | (s & 3)] = env->regs[s] - (imm << 3);
239 rotate_window(env, callinc);
240 env->sregs[WINDOW_START] |=
241 windowstart_bit(env->sregs[WINDOW_BASE], env);
242 }
243 }
244
245 void HELPER(window_check)(CPUXtensaState *env, uint32_t pc, uint32_t w)
246 {
247 uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
248 uint32_t windowstart = env->sregs[WINDOW_START];
249 uint32_t m, n;
250
251 if ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) {
252 return;
253 }
254
255 for (n = 1; ; ++n) {
256 if (n > w) {
257 return;
258 }
259 if (windowstart & windowstart_bit(windowbase + n, env)) {
260 break;
261 }
262 }
263
264 m = windowbase_bound(windowbase + n, env);
265 rotate_window(env, n);
266 env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
267 (windowbase << PS_OWB_SHIFT) | PS_EXCM;
268 env->sregs[EPC1] = env->pc = pc;
269
270 if (windowstart & windowstart_bit(m + 1, env)) {
271 HELPER(exception)(env, EXC_WINDOW_OVERFLOW4);
272 } else if (windowstart & windowstart_bit(m + 2, env)) {
273 HELPER(exception)(env, EXC_WINDOW_OVERFLOW8);
274 } else {
275 HELPER(exception)(env, EXC_WINDOW_OVERFLOW12);
276 }
277 }
278
279 uint32_t HELPER(retw)(CPUXtensaState *env, uint32_t pc)
280 {
281 int n = (env->regs[0] >> 30) & 0x3;
282 int m = 0;
283 uint32_t windowbase = windowbase_bound(env->sregs[WINDOW_BASE], env);
284 uint32_t windowstart = env->sregs[WINDOW_START];
285 uint32_t ret_pc = 0;
286
287 if (windowstart & windowstart_bit(windowbase - 1, env)) {
288 m = 1;
289 } else if (windowstart & windowstart_bit(windowbase - 2, env)) {
290 m = 2;
291 } else if (windowstart & windowstart_bit(windowbase - 3, env)) {
292 m = 3;
293 }
294
295 if (n == 0 || (m != 0 && m != n) ||
296 ((env->sregs[PS] & (PS_WOE | PS_EXCM)) ^ PS_WOE) != 0) {
297 qemu_log("Illegal retw instruction(pc = %08x), "
298 "PS = %08x, m = %d, n = %d\n",
299 pc, env->sregs[PS], m, n);
300 HELPER(exception_cause)(env, pc, ILLEGAL_INSTRUCTION_CAUSE);
301 } else {
302 int owb = windowbase;
303
304 ret_pc = (pc & 0xc0000000) | (env->regs[0] & 0x3fffffff);
305
306 rotate_window(env, -n);
307 if (windowstart & windowstart_bit(env->sregs[WINDOW_BASE], env)) {
308 env->sregs[WINDOW_START] &= ~windowstart_bit(owb, env);
309 } else {
310 /* window underflow */
311 env->sregs[PS] = (env->sregs[PS] & ~PS_OWB) |
312 (windowbase << PS_OWB_SHIFT) | PS_EXCM;
313 env->sregs[EPC1] = env->pc = pc;
314
315 if (n == 1) {
316 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW4);
317 } else if (n == 2) {
318 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW8);
319 } else if (n == 3) {
320 HELPER(exception)(env, EXC_WINDOW_UNDERFLOW12);
321 }
322 }
323 }
324 return ret_pc;
325 }
326
327 void HELPER(rotw)(CPUXtensaState *env, uint32_t imm4)
328 {
329 rotate_window(env, imm4);
330 }
331
332 void HELPER(restore_owb)(CPUXtensaState *env)
333 {
334 rotate_window_abs(env, (env->sregs[PS] & PS_OWB) >> PS_OWB_SHIFT);
335 }
336
337 void HELPER(movsp)(CPUXtensaState *env, uint32_t pc)
338 {
339 if ((env->sregs[WINDOW_START] &
340 (windowstart_bit(env->sregs[WINDOW_BASE] - 3, env) |
341 windowstart_bit(env->sregs[WINDOW_BASE] - 2, env) |
342 windowstart_bit(env->sregs[WINDOW_BASE] - 1, env))) == 0) {
343 HELPER(exception_cause)(env, pc, ALLOCA_CAUSE);
344 }
345 }
346
347 void HELPER(wsr_lbeg)(CPUXtensaState *env, uint32_t v)
348 {
349 if (env->sregs[LBEG] != v) {
350 tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
351 env->sregs[LBEG] = v;
352 }
353 }
354
355 void HELPER(wsr_lend)(CPUXtensaState *env, uint32_t v)
356 {
357 if (env->sregs[LEND] != v) {
358 tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
359 env->sregs[LEND] = v;
360 tb_invalidate_virtual_addr(env, env->sregs[LEND] - 1);
361 }
362 }
363
364 void HELPER(dump_state)(CPUXtensaState *env)
365 {
366 XtensaCPU *cpu = xtensa_env_get_cpu(env);
367
368 cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
369 }
370
371 void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
372 {
373 CPUState *cpu;
374
375 env->pc = pc;
376 env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
377 (intlevel << PS_INTLEVEL_SHIFT);
378 check_interrupts(env);
379 if (env->pending_irq_level) {
380 cpu_loop_exit(CPU(xtensa_env_get_cpu(env)));
381 return;
382 }
383
384 cpu = CPU(xtensa_env_get_cpu(env));
385 env->halt_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
386 cpu->halted = 1;
387 if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
388 xtensa_rearm_ccompare_timer(env);
389 }
390 HELPER(exception)(env, EXCP_HLT);
391 }
392
393 void HELPER(timer_irq)(CPUXtensaState *env, uint32_t id, uint32_t active)
394 {
395 xtensa_timer_irq(env, id, active);
396 }
397
398 void HELPER(advance_ccount)(CPUXtensaState *env, uint32_t d)
399 {
400 xtensa_advance_ccount(env, d);
401 }
402
403 void HELPER(check_interrupts)(CPUXtensaState *env)
404 {
405 check_interrupts(env);
406 }
407
408 void HELPER(itlb_hit_test)(CPUXtensaState *env, uint32_t vaddr)
409 {
410 get_page_addr_code(env, vaddr);
411 }
412
413 /*!
414 * Check vaddr accessibility/cache attributes and raise an exception if
415 * specified by the ATOMCTL SR.
416 *
417 * Note: local memory exclusion is not implemented
418 */
419 void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
420 {
421 uint32_t paddr, page_size, access;
422 uint32_t atomctl = env->sregs[ATOMCTL];
423 int rc = xtensa_get_physical_addr(env, true, vaddr, 1,
424 xtensa_get_cring(env), &paddr, &page_size, &access);
425
426 /*
427 * s32c1i never causes LOAD_PROHIBITED_CAUSE exceptions,
428 * see opcode description in the ISA
429 */
430 if (rc == 0 &&
431 (access & (PAGE_READ | PAGE_WRITE)) != (PAGE_READ | PAGE_WRITE)) {
432 rc = STORE_PROHIBITED_CAUSE;
433 }
434
435 if (rc) {
436 HELPER(exception_cause_vaddr)(env, pc, rc, vaddr);
437 }
438
439 /*
440 * When data cache is not configured use ATOMCTL bypass field.
441 * See ISA, 4.3.12.4 The Atomic Operation Control Register (ATOMCTL)
442 * under the Conditional Store Option.
443 */
444 if (!xtensa_option_enabled(env->config, XTENSA_OPTION_DCACHE)) {
445 access = PAGE_CACHE_BYPASS;
446 }
447
448 switch (access & PAGE_CACHE_MASK) {
449 case PAGE_CACHE_WB:
450 atomctl >>= 2;
451 /* fall through */
452 case PAGE_CACHE_WT:
453 atomctl >>= 2;
454 /* fall through */
455 case PAGE_CACHE_BYPASS:
456 if ((atomctl & 0x3) == 0) {
457 HELPER(exception_cause_vaddr)(env, pc,
458 LOAD_STORE_ERROR_CAUSE, vaddr);
459 }
460 break;
461
462 case PAGE_CACHE_ISOLATE:
463 HELPER(exception_cause_vaddr)(env, pc,
464 LOAD_STORE_ERROR_CAUSE, vaddr);
465 break;
466
467 default:
468 break;
469 }
470 }
471
472 void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
473 {
474 XtensaCPU *cpu = xtensa_env_get_cpu(env);
475
476 v = (v & 0xffffff00) | 0x1;
477 if (v != env->sregs[RASID]) {
478 env->sregs[RASID] = v;
479 tlb_flush(CPU(cpu), 1);
480 }
481 }
482
483 static uint32_t get_page_size(const CPUXtensaState *env, bool dtlb, uint32_t way)
484 {
485 uint32_t tlbcfg = env->sregs[dtlb ? DTLBCFG : ITLBCFG];
486
487 switch (way) {
488 case 4:
489 return (tlbcfg >> 16) & 0x3;
490
491 case 5:
492 return (tlbcfg >> 20) & 0x1;
493
494 case 6:
495 return (tlbcfg >> 24) & 0x1;
496
497 default:
498 return 0;
499 }
500 }
501
502 /*!
503 * Get bit mask for the virtual address bits translated by the TLB way
504 */
505 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
506 {
507 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
508 bool varway56 = dtlb ?
509 env->config->dtlb.varway56 :
510 env->config->itlb.varway56;
511
512 switch (way) {
513 case 4:
514 return 0xfff00000 << get_page_size(env, dtlb, way) * 2;
515
516 case 5:
517 if (varway56) {
518 return 0xf8000000 << get_page_size(env, dtlb, way);
519 } else {
520 return 0xf8000000;
521 }
522
523 case 6:
524 if (varway56) {
525 return 0xf0000000 << (1 - get_page_size(env, dtlb, way));
526 } else {
527 return 0xf0000000;
528 }
529
530 default:
531 return 0xfffff000;
532 }
533 } else {
534 return REGION_PAGE_MASK;
535 }
536 }
537
538 /*!
539 * Get bit mask for the 'VPN without index' field.
540 * See ISA, 4.6.5.6, data format for RxTLB0
541 */
542 static uint32_t get_vpn_mask(const CPUXtensaState *env, bool dtlb, uint32_t way)
543 {
544 if (way < 4) {
545 bool is32 = (dtlb ?
546 env->config->dtlb.nrefillentries :
547 env->config->itlb.nrefillentries) == 32;
548 return is32 ? 0xffff8000 : 0xffffc000;
549 } else if (way == 4) {
550 return xtensa_tlb_get_addr_mask(env, dtlb, way) << 2;
551 } else if (way <= 6) {
552 uint32_t mask = xtensa_tlb_get_addr_mask(env, dtlb, way);
553 bool varway56 = dtlb ?
554 env->config->dtlb.varway56 :
555 env->config->itlb.varway56;
556
557 if (varway56) {
558 return mask << (way == 5 ? 2 : 3);
559 } else {
560 return mask << 1;
561 }
562 } else {
563 return 0xfffff000;
564 }
565 }
566
567 /*!
568 * Split virtual address into VPN (with index) and entry index
569 * for the given TLB way
570 */
571 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
572 uint32_t *vpn, uint32_t wi, uint32_t *ei)
573 {
574 bool varway56 = dtlb ?
575 env->config->dtlb.varway56 :
576 env->config->itlb.varway56;
577
578 if (!dtlb) {
579 wi &= 7;
580 }
581
582 if (wi < 4) {
583 bool is32 = (dtlb ?
584 env->config->dtlb.nrefillentries :
585 env->config->itlb.nrefillentries) == 32;
586 *ei = (v >> 12) & (is32 ? 0x7 : 0x3);
587 } else {
588 switch (wi) {
589 case 4:
590 {
591 uint32_t eibase = 20 + get_page_size(env, dtlb, wi) * 2;
592 *ei = (v >> eibase) & 0x3;
593 }
594 break;
595
596 case 5:
597 if (varway56) {
598 uint32_t eibase = 27 + get_page_size(env, dtlb, wi);
599 *ei = (v >> eibase) & 0x3;
600 } else {
601 *ei = (v >> 27) & 0x1;
602 }
603 break;
604
605 case 6:
606 if (varway56) {
607 uint32_t eibase = 29 - get_page_size(env, dtlb, wi);
608 *ei = (v >> eibase) & 0x7;
609 } else {
610 *ei = (v >> 28) & 0x1;
611 }
612 break;
613
614 default:
615 *ei = 0;
616 break;
617 }
618 }
619 *vpn = v & xtensa_tlb_get_addr_mask(env, dtlb, wi);
620 }
621
622 /*!
623 * Split TLB address into TLB way, entry index and VPN (with index).
624 * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format
625 */
626 static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb,
627 uint32_t *vpn, uint32_t *wi, uint32_t *ei)
628 {
629 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
630 *wi = v & (dtlb ? 0xf : 0x7);
631 split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei);
632 } else {
633 *vpn = v & REGION_PAGE_MASK;
634 *wi = 0;
635 *ei = (v >> 29) & 0x7;
636 }
637 }
638
639 static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env,
640 uint32_t v, bool dtlb, uint32_t *pwi)
641 {
642 uint32_t vpn;
643 uint32_t wi;
644 uint32_t ei;
645
646 split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
647 if (pwi) {
648 *pwi = wi;
649 }
650 return xtensa_tlb_get_entry(env, dtlb, wi, ei);
651 }
652
653 uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
654 {
655 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
656 uint32_t wi;
657 const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
658 return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid;
659 } else {
660 return v & REGION_PAGE_MASK;
661 }
662 }
663
664 uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
665 {
666 const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL);
667 return entry->paddr | entry->attr;
668 }
669
670 void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
671 {
672 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
673 uint32_t wi;
674 xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
675 if (entry->variable && entry->asid) {
676 tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr);
677 entry->asid = 0;
678 }
679 }
680 }
681
682 uint32_t HELPER(ptlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
683 {
684 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
685 uint32_t wi;
686 uint32_t ei;
687 uint8_t ring;
688 int res = xtensa_tlb_lookup(env, v, dtlb, &wi, &ei, &ring);
689
690 switch (res) {
691 case 0:
692 if (ring >= xtensa_get_ring(env)) {
693 return (v & 0xfffff000) | wi | (dtlb ? 0x10 : 0x8);
694 }
695 break;
696
697 case INST_TLB_MULTI_HIT_CAUSE:
698 case LOAD_STORE_TLB_MULTI_HIT_CAUSE:
699 HELPER(exception_cause_vaddr)(env, env->pc, res, v);
700 break;
701 }
702 return 0;
703 } else {
704 return (v & REGION_PAGE_MASK) | 0x1;
705 }
706 }
707
708 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
709 xtensa_tlb_entry *entry, bool dtlb,
710 unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
711 {
712 entry->vaddr = vpn;
713 entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi);
714 entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff;
715 entry->attr = pte & 0xf;
716 }
717
718 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
719 unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
720 {
721 XtensaCPU *cpu = xtensa_env_get_cpu(env);
722 CPUState *cs = CPU(cpu);
723 xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
724
725 if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
726 if (entry->variable) {
727 if (entry->asid) {
728 tlb_flush_page(cs, entry->vaddr);
729 }
730 xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
731 tlb_flush_page(cs, entry->vaddr);
732 } else {
733 qemu_log("%s %d, %d, %d trying to set immutable entry\n",
734 __func__, dtlb, wi, ei);
735 }
736 } else {
737 tlb_flush_page(cs, entry->vaddr);
738 if (xtensa_option_enabled(env->config,
739 XTENSA_OPTION_REGION_TRANSLATION)) {
740 entry->paddr = pte & REGION_PAGE_MASK;
741 }
742 entry->attr = pte & 0xf;
743 }
744 }
745
746 void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb)
747 {
748 uint32_t vpn;
749 uint32_t wi;
750 uint32_t ei;
751 split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei);
752 xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p);
753 }
754
755
756 void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v)
757 {
758 uint32_t change = v ^ env->sregs[IBREAKENABLE];
759 unsigned i;
760
761 for (i = 0; i < env->config->nibreak; ++i) {
762 if (change & (1 << i)) {
763 tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
764 }
765 }
766 env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1);
767 }
768
769 void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
770 {
771 if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) {
772 tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]);
773 tb_invalidate_virtual_addr(env, v);
774 }
775 env->sregs[IBREAKA + i] = v;
776 }
777
778 static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
779 uint32_t dbreakc)
780 {
781 CPUState *cs = CPU(xtensa_env_get_cpu(env));
782 int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
783 uint32_t mask = dbreakc | ~DBREAKC_MASK;
784
785 if (env->cpu_watchpoint[i]) {
786 cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
787 }
788 if (dbreakc & DBREAKC_SB) {
789 flags |= BP_MEM_WRITE;
790 }
791 if (dbreakc & DBREAKC_LB) {
792 flags |= BP_MEM_READ;
793 }
794 /* contiguous mask after inversion is one less than some power of 2 */
795 if ((~mask + 1) & ~mask) {
796 qemu_log("DBREAKC mask is not contiguous: 0x%08x\n", dbreakc);
797 /* cut mask after the first zero bit */
798 mask = 0xffffffff << (32 - clo32(mask));
799 }
800 if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1,
801 flags, &env->cpu_watchpoint[i])) {
802 env->cpu_watchpoint[i] = NULL;
803 qemu_log("Failed to set data breakpoint at 0x%08x/%d\n",
804 dbreaka & mask, ~mask + 1);
805 }
806 }
807
808 void HELPER(wsr_dbreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
809 {
810 uint32_t dbreakc = env->sregs[DBREAKC + i];
811
812 if ((dbreakc & DBREAKC_SB_LB) &&
813 env->sregs[DBREAKA + i] != v) {
814 set_dbreak(env, i, v, dbreakc);
815 }
816 env->sregs[DBREAKA + i] = v;
817 }
818
819 void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v)
820 {
821 if ((env->sregs[DBREAKC + i] ^ v) & (DBREAKC_SB_LB | DBREAKC_MASK)) {
822 if (v & DBREAKC_SB_LB) {
823 set_dbreak(env, i, env->sregs[DBREAKA + i], v);
824 } else {
825 if (env->cpu_watchpoint[i]) {
826 CPUState *cs = CPU(xtensa_env_get_cpu(env));
827
828 cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
829 env->cpu_watchpoint[i] = NULL;
830 }
831 }
832 }
833 env->sregs[DBREAKC + i] = v;
834 }
835
836 void HELPER(wur_fcr)(CPUXtensaState *env, uint32_t v)
837 {
838 static const int rounding_mode[] = {
839 float_round_nearest_even,
840 float_round_to_zero,
841 float_round_up,
842 float_round_down,
843 };
844
845 env->uregs[FCR] = v & 0xfffff07f;
846 set_float_rounding_mode(rounding_mode[v & 3], &env->fp_status);
847 }
848
849 float32 HELPER(abs_s)(float32 v)
850 {
851 return float32_abs(v);
852 }
853
854 float32 HELPER(neg_s)(float32 v)
855 {
856 return float32_chs(v);
857 }
858
859 float32 HELPER(add_s)(CPUXtensaState *env, float32 a, float32 b)
860 {
861 return float32_add(a, b, &env->fp_status);
862 }
863
864 float32 HELPER(sub_s)(CPUXtensaState *env, float32 a, float32 b)
865 {
866 return float32_sub(a, b, &env->fp_status);
867 }
868
869 float32 HELPER(mul_s)(CPUXtensaState *env, float32 a, float32 b)
870 {
871 return float32_mul(a, b, &env->fp_status);
872 }
873
874 float32 HELPER(madd_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
875 {
876 return float32_muladd(b, c, a, 0,
877 &env->fp_status);
878 }
879
880 float32 HELPER(msub_s)(CPUXtensaState *env, float32 a, float32 b, float32 c)
881 {
882 return float32_muladd(b, c, a, float_muladd_negate_product,
883 &env->fp_status);
884 }
885
886 uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale)
887 {
888 float_status fp_status = {0};
889
890 set_float_rounding_mode(rounding_mode, &fp_status);
891 return float32_to_int32(
892 float32_scalbn(v, scale, &fp_status), &fp_status);
893 }
894
895 uint32_t HELPER(ftoui)(float32 v, uint32_t rounding_mode, uint32_t scale)
896 {
897 float_status fp_status = {0};
898 float32 res;
899
900 set_float_rounding_mode(rounding_mode, &fp_status);
901
902 res = float32_scalbn(v, scale, &fp_status);
903
904 if (float32_is_neg(v) && !float32_is_any_nan(v)) {
905 return float32_to_int32(res, &fp_status);
906 } else {
907 return float32_to_uint32(res, &fp_status);
908 }
909 }
910
911 float32 HELPER(itof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
912 {
913 return float32_scalbn(int32_to_float32(v, &env->fp_status),
914 (int32_t)scale, &env->fp_status);
915 }
916
917 float32 HELPER(uitof)(CPUXtensaState *env, uint32_t v, uint32_t scale)
918 {
919 return float32_scalbn(uint32_to_float32(v, &env->fp_status),
920 (int32_t)scale, &env->fp_status);
921 }
922
923 static inline void set_br(CPUXtensaState *env, bool v, uint32_t br)
924 {
925 if (v) {
926 env->sregs[BR] |= br;
927 } else {
928 env->sregs[BR] &= ~br;
929 }
930 }
931
932 void HELPER(un_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
933 {
934 set_br(env, float32_unordered_quiet(a, b, &env->fp_status), br);
935 }
936
937 void HELPER(oeq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
938 {
939 set_br(env, float32_eq_quiet(a, b, &env->fp_status), br);
940 }
941
942 void HELPER(ueq_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
943 {
944 int v = float32_compare_quiet(a, b, &env->fp_status);
945 set_br(env, v == float_relation_equal || v == float_relation_unordered, br);
946 }
947
948 void HELPER(olt_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
949 {
950 set_br(env, float32_lt_quiet(a, b, &env->fp_status), br);
951 }
952
953 void HELPER(ult_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
954 {
955 int v = float32_compare_quiet(a, b, &env->fp_status);
956 set_br(env, v == float_relation_less || v == float_relation_unordered, br);
957 }
958
959 void HELPER(ole_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
960 {
961 set_br(env, float32_le_quiet(a, b, &env->fp_status), br);
962 }
963
964 void HELPER(ule_s)(CPUXtensaState *env, uint32_t br, float32 a, float32 b)
965 {
966 int v = float32_compare_quiet(a, b, &env->fp_status);
967 set_br(env, v != float_relation_greater, br);
968 }