Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
[qemu.git] / target-xtensa / overlay_tool.h
1 /*
2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
29 a1, a2, a3, a4, a5, a6) \
30 { .targno = (no), .type = (typ), .group = (grp) },
31
32 #ifndef XCHAL_HAVE_DIV32
33 #define XCHAL_HAVE_DIV32 0
34 #endif
35
36 #ifndef XCHAL_UNALIGNED_LOAD_HW
37 #define XCHAL_UNALIGNED_LOAD_HW 0
38 #endif
39
40 #ifndef XCHAL_HAVE_VECBASE
41 #define XCHAL_HAVE_VECBASE 0
42 #define XCHAL_VECBASE_RESET_VADDR 0
43 #endif
44
45 #ifndef XCHAL_HW_MIN_VERSION
46 #define XCHAL_HW_MIN_VERSION 0
47 #endif
48
49 #define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)
50
51 #define XTENSA_OPTIONS ( \
52 XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \
53 XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \
54 XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \
55 XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \
56 XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \
57 XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \
58 XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \
59 XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \
60 XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \
61 XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \
62 XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \
63 XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \
64 XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
65 XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
66 XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
67 XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
68 XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
69 XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \
70 XTENSA_OPTION_ATOMCTL) | \
71 /* Interrupts and exceptions */ \
72 XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
73 XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
74 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
75 XTENSA_OPTION_UNALIGNED_EXCEPTION) | \
76 XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \
77 XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
78 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \
79 XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \
80 /* Local memory, TODO */ \
81 XCHAL_OPTION(XCHAL_ICACHE_WAYS, XTENSA_OPTION_ICACHE) | \
82 XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
83 XTENSA_OPTION_ICACHE_INDEX_LOCK) | \
84 XCHAL_OPTION(XCHAL_DCACHE_WAYS, XTENSA_OPTION_DCACHE) | \
85 XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
86 XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
87 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
88 /* Memory protection and translation */ \
89 XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
90 XTENSA_OPTION_REGION_PROTECTION) | \
91 XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
92 XTENSA_OPTION_REGION_TRANSLATION) | \
93 XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \
94 XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \
95 /* Other, TODO */ \
96 XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \
97 XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\
98 XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \
99 XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \
100 XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID))
101
102 #ifndef XCHAL_WINDOW_OF4_VECOFS
103 #define XCHAL_WINDOW_OF4_VECOFS 0x00000000
104 #define XCHAL_WINDOW_UF4_VECOFS 0x00000040
105 #define XCHAL_WINDOW_OF8_VECOFS 0x00000080
106 #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
107 #define XCHAL_WINDOW_OF12_VECOFS 0x00000100
108 #define XCHAL_WINDOW_UF12_VECOFS 0x00000140
109 #endif
110
111 #define EXCEPTION_VECTORS { \
112 [EXC_RESET] = XCHAL_RESET_VECTOR_VADDR, \
113 [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
114 XCHAL_WINDOW_VECTORS_VADDR, \
115 [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
116 XCHAL_WINDOW_VECTORS_VADDR, \
117 [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
118 XCHAL_WINDOW_VECTORS_VADDR, \
119 [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
120 XCHAL_WINDOW_VECTORS_VADDR, \
121 [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
122 XCHAL_WINDOW_VECTORS_VADDR, \
123 [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
124 XCHAL_WINDOW_VECTORS_VADDR, \
125 [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
126 [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
127 [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
128 [EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \
129 }
130
131 #define INTERRUPT_VECTORS { \
132 0, \
133 0, \
134 XCHAL_INTLEVEL2_VECTOR_VADDR, \
135 XCHAL_INTLEVEL3_VECTOR_VADDR, \
136 XCHAL_INTLEVEL4_VECTOR_VADDR, \
137 XCHAL_INTLEVEL5_VECTOR_VADDR, \
138 XCHAL_INTLEVEL6_VECTOR_VADDR, \
139 XCHAL_INTLEVEL7_VECTOR_VADDR, \
140 }
141
142 #define LEVEL_MASKS { \
143 [1] = XCHAL_INTLEVEL1_MASK, \
144 [2] = XCHAL_INTLEVEL2_MASK, \
145 [3] = XCHAL_INTLEVEL3_MASK, \
146 [4] = XCHAL_INTLEVEL4_MASK, \
147 [5] = XCHAL_INTLEVEL5_MASK, \
148 [6] = XCHAL_INTLEVEL6_MASK, \
149 [7] = XCHAL_INTLEVEL7_MASK, \
150 }
151
152 #define INTTYPE_MASKS { \
153 [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
154 [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
155 [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
156 }
157
158 #define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
159 #define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
160 #define XTHAL_INTTYPE_NMI INTTYPE_NMI
161 #define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
162 #define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
163 #define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
164 #define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
165 #define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
166
167
168 #define INTERRUPT(i) { \
169 .level = XCHAL_INT ## i ## _LEVEL, \
170 .inttype = XCHAL_INT ## i ## _TYPE, \
171 }
172
173 #define INTERRUPTS { \
174 [0] = INTERRUPT(0), \
175 [1] = INTERRUPT(1), \
176 [2] = INTERRUPT(2), \
177 [3] = INTERRUPT(3), \
178 [4] = INTERRUPT(4), \
179 [5] = INTERRUPT(5), \
180 [6] = INTERRUPT(6), \
181 [7] = INTERRUPT(7), \
182 [8] = INTERRUPT(8), \
183 [9] = INTERRUPT(9), \
184 [10] = INTERRUPT(10), \
185 [11] = INTERRUPT(11), \
186 [12] = INTERRUPT(12), \
187 [13] = INTERRUPT(13), \
188 [14] = INTERRUPT(14), \
189 [15] = INTERRUPT(15), \
190 [16] = INTERRUPT(16), \
191 [17] = INTERRUPT(17), \
192 [18] = INTERRUPT(18), \
193 [19] = INTERRUPT(19), \
194 [20] = INTERRUPT(20), \
195 [21] = INTERRUPT(21), \
196 [22] = INTERRUPT(22), \
197 [23] = INTERRUPT(23), \
198 [24] = INTERRUPT(24), \
199 [25] = INTERRUPT(25), \
200 [26] = INTERRUPT(26), \
201 [27] = INTERRUPT(27), \
202 [28] = INTERRUPT(28), \
203 [29] = INTERRUPT(29), \
204 [30] = INTERRUPT(30), \
205 [31] = INTERRUPT(31), \
206 }
207
208 #define TIMERINTS { \
209 [0] = XCHAL_TIMER0_INTERRUPT, \
210 [1] = XCHAL_TIMER1_INTERRUPT, \
211 [2] = XCHAL_TIMER2_INTERRUPT, \
212 }
213
214 #define EXTINTS { \
215 [0] = XCHAL_EXTINT0_NUM, \
216 [1] = XCHAL_EXTINT1_NUM, \
217 [2] = XCHAL_EXTINT2_NUM, \
218 [3] = XCHAL_EXTINT3_NUM, \
219 [4] = XCHAL_EXTINT4_NUM, \
220 [5] = XCHAL_EXTINT5_NUM, \
221 [6] = XCHAL_EXTINT6_NUM, \
222 [7] = XCHAL_EXTINT7_NUM, \
223 [8] = XCHAL_EXTINT8_NUM, \
224 [9] = XCHAL_EXTINT9_NUM, \
225 [10] = XCHAL_EXTINT10_NUM, \
226 [11] = XCHAL_EXTINT11_NUM, \
227 [12] = XCHAL_EXTINT12_NUM, \
228 [13] = XCHAL_EXTINT13_NUM, \
229 [14] = XCHAL_EXTINT14_NUM, \
230 [15] = XCHAL_EXTINT15_NUM, \
231 [16] = XCHAL_EXTINT16_NUM, \
232 [17] = XCHAL_EXTINT17_NUM, \
233 [18] = XCHAL_EXTINT18_NUM, \
234 [19] = XCHAL_EXTINT19_NUM, \
235 [20] = XCHAL_EXTINT20_NUM, \
236 [21] = XCHAL_EXTINT21_NUM, \
237 [22] = XCHAL_EXTINT22_NUM, \
238 [23] = XCHAL_EXTINT23_NUM, \
239 [24] = XCHAL_EXTINT24_NUM, \
240 [25] = XCHAL_EXTINT25_NUM, \
241 [26] = XCHAL_EXTINT26_NUM, \
242 [27] = XCHAL_EXTINT27_NUM, \
243 [28] = XCHAL_EXTINT28_NUM, \
244 [29] = XCHAL_EXTINT29_NUM, \
245 [30] = XCHAL_EXTINT30_NUM, \
246 [31] = XCHAL_EXTINT31_NUM, \
247 }
248
249 #define EXCEPTIONS_SECTION \
250 .excm_level = XCHAL_EXCM_LEVEL, \
251 .vecbase = XCHAL_VECBASE_RESET_VADDR, \
252 .exception_vector = EXCEPTION_VECTORS
253
254 #define INTERRUPTS_SECTION \
255 .ninterrupt = XCHAL_NUM_INTERRUPTS, \
256 .nlevel = XCHAL_NUM_INTLEVELS, \
257 .interrupt_vector = INTERRUPT_VECTORS, \
258 .level_mask = LEVEL_MASKS, \
259 .inttype_mask = INTTYPE_MASKS, \
260 .interrupt = INTERRUPTS, \
261 .nccompare = XCHAL_NUM_TIMERS, \
262 .timerint = TIMERINTS, \
263 .nextint = XCHAL_NUM_EXTINTERRUPTS, \
264 .extint = EXTINTS
265
266 #if XCHAL_HAVE_PTP_MMU
267
268 #define TLB_TEMPLATE(ways, refill_way_size, way56) { \
269 .nways = ways, \
270 .way_size = { \
271 (refill_way_size), (refill_way_size), \
272 (refill_way_size), (refill_way_size), \
273 4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \
274 }, \
275 .varway56 = (way56), \
276 .nrefillentries = (refill_way_size) * 4, \
277 }
278
279 #define ITLB(varway56) \
280 TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)
281
282 #define DTLB(varway56) \
283 TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
284
285 #define TLB_SECTION \
286 .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
287 .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
288
289 #elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR
290
291 #define TLB_TEMPLATE { \
292 .nways = 1, \
293 .way_size = { \
294 8, \
295 } \
296 }
297
298 #define TLB_SECTION \
299 .itlb = TLB_TEMPLATE, \
300 .dtlb = TLB_TEMPLATE
301
302 #endif
303
304 #if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
305 #define REGISTER_CORE(core) \
306 static void __attribute__((constructor)) register_core(void) \
307 { \
308 static XtensaConfigList node = { \
309 .config = &core, \
310 }; \
311 xtensa_register_core(&node); \
312 }
313 #else
314 #define REGISTER_CORE(core)
315 #endif
316
317 #define DEBUG_SECTION \
318 .debug_level = XCHAL_DEBUGLEVEL, \
319 .nibreak = XCHAL_NUM_IBREAK, \
320 .ndbreak = XCHAL_NUM_DBREAK
321
322 #define CONFIG_SECTION \
323 .configid = { \
324 XCHAL_HW_CONFIGID0, \
325 XCHAL_HW_CONFIGID1, \
326 }
327
328 #define DEFAULT_SECTIONS \
329 .options = XTENSA_OPTIONS, \
330 .nareg = XCHAL_NUM_AREGS, \
331 .ndepc = (XCHAL_XEA_VERSION >= 2), \
332 EXCEPTIONS_SECTION, \
333 INTERRUPTS_SECTION, \
334 TLB_SECTION, \
335 DEBUG_SECTION, \
336 CONFIG_SECTION
337
338
339 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
340 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0
341 #endif
342 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
343 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0
344 #endif
345 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
346 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0
347 #endif
348 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
349 #define XCHAL_INTLEVEL5_VECTOR_VADDR 0
350 #endif
351 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
352 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0
353 #endif
354 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
355 #define XCHAL_INTLEVEL7_VECTOR_VADDR 0
356 #endif
357
358
359 #if XCHAL_NUM_INTERRUPTS <= 0
360 #define XCHAL_INT0_LEVEL 0
361 #define XCHAL_INT0_TYPE 0
362 #endif
363 #if XCHAL_NUM_INTERRUPTS <= 1
364 #define XCHAL_INT1_LEVEL 0
365 #define XCHAL_INT1_TYPE 0
366 #endif
367 #if XCHAL_NUM_INTERRUPTS <= 2
368 #define XCHAL_INT2_LEVEL 0
369 #define XCHAL_INT2_TYPE 0
370 #endif
371 #if XCHAL_NUM_INTERRUPTS <= 3
372 #define XCHAL_INT3_LEVEL 0
373 #define XCHAL_INT3_TYPE 0
374 #endif
375 #if XCHAL_NUM_INTERRUPTS <= 4
376 #define XCHAL_INT4_LEVEL 0
377 #define XCHAL_INT4_TYPE 0
378 #endif
379 #if XCHAL_NUM_INTERRUPTS <= 5
380 #define XCHAL_INT5_LEVEL 0
381 #define XCHAL_INT5_TYPE 0
382 #endif
383 #if XCHAL_NUM_INTERRUPTS <= 6
384 #define XCHAL_INT6_LEVEL 0
385 #define XCHAL_INT6_TYPE 0
386 #endif
387 #if XCHAL_NUM_INTERRUPTS <= 7
388 #define XCHAL_INT7_LEVEL 0
389 #define XCHAL_INT7_TYPE 0
390 #endif
391 #if XCHAL_NUM_INTERRUPTS <= 8
392 #define XCHAL_INT8_LEVEL 0
393 #define XCHAL_INT8_TYPE 0
394 #endif
395 #if XCHAL_NUM_INTERRUPTS <= 9
396 #define XCHAL_INT9_LEVEL 0
397 #define XCHAL_INT9_TYPE 0
398 #endif
399 #if XCHAL_NUM_INTERRUPTS <= 10
400 #define XCHAL_INT10_LEVEL 0
401 #define XCHAL_INT10_TYPE 0
402 #endif
403 #if XCHAL_NUM_INTERRUPTS <= 11
404 #define XCHAL_INT11_LEVEL 0
405 #define XCHAL_INT11_TYPE 0
406 #endif
407 #if XCHAL_NUM_INTERRUPTS <= 12
408 #define XCHAL_INT12_LEVEL 0
409 #define XCHAL_INT12_TYPE 0
410 #endif
411 #if XCHAL_NUM_INTERRUPTS <= 13
412 #define XCHAL_INT13_LEVEL 0
413 #define XCHAL_INT13_TYPE 0
414 #endif
415 #if XCHAL_NUM_INTERRUPTS <= 14
416 #define XCHAL_INT14_LEVEL 0
417 #define XCHAL_INT14_TYPE 0
418 #endif
419 #if XCHAL_NUM_INTERRUPTS <= 15
420 #define XCHAL_INT15_LEVEL 0
421 #define XCHAL_INT15_TYPE 0
422 #endif
423 #if XCHAL_NUM_INTERRUPTS <= 16
424 #define XCHAL_INT16_LEVEL 0
425 #define XCHAL_INT16_TYPE 0
426 #endif
427 #if XCHAL_NUM_INTERRUPTS <= 17
428 #define XCHAL_INT17_LEVEL 0
429 #define XCHAL_INT17_TYPE 0
430 #endif
431 #if XCHAL_NUM_INTERRUPTS <= 18
432 #define XCHAL_INT18_LEVEL 0
433 #define XCHAL_INT18_TYPE 0
434 #endif
435 #if XCHAL_NUM_INTERRUPTS <= 19
436 #define XCHAL_INT19_LEVEL 0
437 #define XCHAL_INT19_TYPE 0
438 #endif
439 #if XCHAL_NUM_INTERRUPTS <= 20
440 #define XCHAL_INT20_LEVEL 0
441 #define XCHAL_INT20_TYPE 0
442 #endif
443 #if XCHAL_NUM_INTERRUPTS <= 21
444 #define XCHAL_INT21_LEVEL 0
445 #define XCHAL_INT21_TYPE 0
446 #endif
447 #if XCHAL_NUM_INTERRUPTS <= 22
448 #define XCHAL_INT22_LEVEL 0
449 #define XCHAL_INT22_TYPE 0
450 #endif
451 #if XCHAL_NUM_INTERRUPTS <= 23
452 #define XCHAL_INT23_LEVEL 0
453 #define XCHAL_INT23_TYPE 0
454 #endif
455 #if XCHAL_NUM_INTERRUPTS <= 24
456 #define XCHAL_INT24_LEVEL 0
457 #define XCHAL_INT24_TYPE 0
458 #endif
459 #if XCHAL_NUM_INTERRUPTS <= 25
460 #define XCHAL_INT25_LEVEL 0
461 #define XCHAL_INT25_TYPE 0
462 #endif
463 #if XCHAL_NUM_INTERRUPTS <= 26
464 #define XCHAL_INT26_LEVEL 0
465 #define XCHAL_INT26_TYPE 0
466 #endif
467 #if XCHAL_NUM_INTERRUPTS <= 27
468 #define XCHAL_INT27_LEVEL 0
469 #define XCHAL_INT27_TYPE 0
470 #endif
471 #if XCHAL_NUM_INTERRUPTS <= 28
472 #define XCHAL_INT28_LEVEL 0
473 #define XCHAL_INT28_TYPE 0
474 #endif
475 #if XCHAL_NUM_INTERRUPTS <= 29
476 #define XCHAL_INT29_LEVEL 0
477 #define XCHAL_INT29_TYPE 0
478 #endif
479 #if XCHAL_NUM_INTERRUPTS <= 30
480 #define XCHAL_INT30_LEVEL 0
481 #define XCHAL_INT30_TYPE 0
482 #endif
483 #if XCHAL_NUM_INTERRUPTS <= 31
484 #define XCHAL_INT31_LEVEL 0
485 #define XCHAL_INT31_TYPE 0
486 #endif
487
488
489 #if XCHAL_NUM_EXTINTERRUPTS <= 0
490 #define XCHAL_EXTINT0_NUM 0
491 #endif
492 #if XCHAL_NUM_EXTINTERRUPTS <= 1
493 #define XCHAL_EXTINT1_NUM 0
494 #endif
495 #if XCHAL_NUM_EXTINTERRUPTS <= 2
496 #define XCHAL_EXTINT2_NUM 0
497 #endif
498 #if XCHAL_NUM_EXTINTERRUPTS <= 3
499 #define XCHAL_EXTINT3_NUM 0
500 #endif
501 #if XCHAL_NUM_EXTINTERRUPTS <= 4
502 #define XCHAL_EXTINT4_NUM 0
503 #endif
504 #if XCHAL_NUM_EXTINTERRUPTS <= 5
505 #define XCHAL_EXTINT5_NUM 0
506 #endif
507 #if XCHAL_NUM_EXTINTERRUPTS <= 6
508 #define XCHAL_EXTINT6_NUM 0
509 #endif
510 #if XCHAL_NUM_EXTINTERRUPTS <= 7
511 #define XCHAL_EXTINT7_NUM 0
512 #endif
513 #if XCHAL_NUM_EXTINTERRUPTS <= 8
514 #define XCHAL_EXTINT8_NUM 0
515 #endif
516 #if XCHAL_NUM_EXTINTERRUPTS <= 9
517 #define XCHAL_EXTINT9_NUM 0
518 #endif
519 #if XCHAL_NUM_EXTINTERRUPTS <= 10
520 #define XCHAL_EXTINT10_NUM 0
521 #endif
522 #if XCHAL_NUM_EXTINTERRUPTS <= 11
523 #define XCHAL_EXTINT11_NUM 0
524 #endif
525 #if XCHAL_NUM_EXTINTERRUPTS <= 12
526 #define XCHAL_EXTINT12_NUM 0
527 #endif
528 #if XCHAL_NUM_EXTINTERRUPTS <= 13
529 #define XCHAL_EXTINT13_NUM 0
530 #endif
531 #if XCHAL_NUM_EXTINTERRUPTS <= 14
532 #define XCHAL_EXTINT14_NUM 0
533 #endif
534 #if XCHAL_NUM_EXTINTERRUPTS <= 15
535 #define XCHAL_EXTINT15_NUM 0
536 #endif
537 #if XCHAL_NUM_EXTINTERRUPTS <= 16
538 #define XCHAL_EXTINT16_NUM 0
539 #endif
540 #if XCHAL_NUM_EXTINTERRUPTS <= 17
541 #define XCHAL_EXTINT17_NUM 0
542 #endif
543 #if XCHAL_NUM_EXTINTERRUPTS <= 18
544 #define XCHAL_EXTINT18_NUM 0
545 #endif
546 #if XCHAL_NUM_EXTINTERRUPTS <= 19
547 #define XCHAL_EXTINT19_NUM 0
548 #endif
549 #if XCHAL_NUM_EXTINTERRUPTS <= 20
550 #define XCHAL_EXTINT20_NUM 0
551 #endif
552 #if XCHAL_NUM_EXTINTERRUPTS <= 21
553 #define XCHAL_EXTINT21_NUM 0
554 #endif
555 #if XCHAL_NUM_EXTINTERRUPTS <= 22
556 #define XCHAL_EXTINT22_NUM 0
557 #endif
558 #if XCHAL_NUM_EXTINTERRUPTS <= 23
559 #define XCHAL_EXTINT23_NUM 0
560 #endif
561 #if XCHAL_NUM_EXTINTERRUPTS <= 24
562 #define XCHAL_EXTINT24_NUM 0
563 #endif
564 #if XCHAL_NUM_EXTINTERRUPTS <= 25
565 #define XCHAL_EXTINT25_NUM 0
566 #endif
567 #if XCHAL_NUM_EXTINTERRUPTS <= 26
568 #define XCHAL_EXTINT26_NUM 0
569 #endif
570 #if XCHAL_NUM_EXTINTERRUPTS <= 27
571 #define XCHAL_EXTINT27_NUM 0
572 #endif
573 #if XCHAL_NUM_EXTINTERRUPTS <= 28
574 #define XCHAL_EXTINT28_NUM 0
575 #endif
576 #if XCHAL_NUM_EXTINTERRUPTS <= 29
577 #define XCHAL_EXTINT29_NUM 0
578 #endif
579 #if XCHAL_NUM_EXTINTERRUPTS <= 30
580 #define XCHAL_EXTINT30_NUM 0
581 #endif
582 #if XCHAL_NUM_EXTINTERRUPTS <= 31
583 #define XCHAL_EXTINT31_NUM 0
584 #endif
585
586
587 #define XTHAL_TIMER_UNCONFIGURED 0