scsi: pvscsi: check command descriptor ring buffer size (CVE-2016-4952)
[qemu.git] / target-xtensa / overlay_tool.h
1 /*
2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
29 a1, a2, a3, a4, a5, a6) \
30 { .targno = (no), .type = (typ), .group = (grp), .size = (sz) },
31 #define XTREG_END { .targno = -1 },
32
33 #ifndef XCHAL_HAVE_DEPBITS
34 #define XCHAL_HAVE_DEPBITS 0
35 #endif
36
37 #ifndef XCHAL_HAVE_DIV32
38 #define XCHAL_HAVE_DIV32 0
39 #endif
40
41 #ifndef XCHAL_UNALIGNED_LOAD_HW
42 #define XCHAL_UNALIGNED_LOAD_HW 0
43 #endif
44
45 #ifndef XCHAL_HAVE_VECBASE
46 #define XCHAL_HAVE_VECBASE 0
47 #define XCHAL_VECBASE_RESET_VADDR 0
48 #endif
49
50 #ifndef XCHAL_HW_MIN_VERSION
51 #define XCHAL_HW_MIN_VERSION 0
52 #endif
53
54 #define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)
55
56 #define XTENSA_OPTIONS ( \
57 XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \
58 XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \
59 XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \
60 XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \
61 XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \
62 XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \
63 XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \
64 XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \
65 XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \
66 XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \
67 XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \
68 XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \
69 XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
70 XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
71 XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
72 XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
73 XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
74 XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \
75 XTENSA_OPTION_ATOMCTL) | \
76 XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \
77 /* Interrupts and exceptions */ \
78 XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
79 XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
80 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
81 XTENSA_OPTION_UNALIGNED_EXCEPTION) | \
82 XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \
83 XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
84 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \
85 XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \
86 /* Local memory, TODO */ \
87 XCHAL_OPTION(XCHAL_ICACHE_WAYS, XTENSA_OPTION_ICACHE) | \
88 XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
89 XTENSA_OPTION_ICACHE_INDEX_LOCK) | \
90 XCHAL_OPTION(XCHAL_DCACHE_WAYS, XTENSA_OPTION_DCACHE) | \
91 XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
92 XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
93 XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
94 /* Memory protection and translation */ \
95 XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
96 XTENSA_OPTION_REGION_PROTECTION) | \
97 XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
98 XTENSA_OPTION_REGION_TRANSLATION) | \
99 XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \
100 XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \
101 /* Other, TODO */ \
102 XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \
103 XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\
104 XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \
105 XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \
106 XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID))
107
108 #ifndef XCHAL_WINDOW_OF4_VECOFS
109 #define XCHAL_WINDOW_OF4_VECOFS 0x00000000
110 #define XCHAL_WINDOW_UF4_VECOFS 0x00000040
111 #define XCHAL_WINDOW_OF8_VECOFS 0x00000080
112 #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
113 #define XCHAL_WINDOW_OF12_VECOFS 0x00000100
114 #define XCHAL_WINDOW_UF12_VECOFS 0x00000140
115 #endif
116
117 #if XCHAL_HAVE_WINDOWED
118 #define WINDOW_VECTORS \
119 [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
120 XCHAL_WINDOW_VECTORS_VADDR, \
121 [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
122 XCHAL_WINDOW_VECTORS_VADDR, \
123 [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
124 XCHAL_WINDOW_VECTORS_VADDR, \
125 [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
126 XCHAL_WINDOW_VECTORS_VADDR, \
127 [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
128 XCHAL_WINDOW_VECTORS_VADDR, \
129 [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
130 XCHAL_WINDOW_VECTORS_VADDR,
131 #else
132 #define WINDOW_VECTORS
133 #endif
134
135 #define EXCEPTION_VECTORS { \
136 [EXC_RESET] = XCHAL_RESET_VECTOR_VADDR, \
137 WINDOW_VECTORS \
138 [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
139 [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
140 [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
141 [EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \
142 }
143
144 #define INTERRUPT_VECTORS { \
145 0, \
146 0, \
147 XCHAL_INTLEVEL2_VECTOR_VADDR, \
148 XCHAL_INTLEVEL3_VECTOR_VADDR, \
149 XCHAL_INTLEVEL4_VECTOR_VADDR, \
150 XCHAL_INTLEVEL5_VECTOR_VADDR, \
151 XCHAL_INTLEVEL6_VECTOR_VADDR, \
152 XCHAL_INTLEVEL7_VECTOR_VADDR, \
153 }
154
155 #define LEVEL_MASKS { \
156 [1] = XCHAL_INTLEVEL1_MASK, \
157 [2] = XCHAL_INTLEVEL2_MASK, \
158 [3] = XCHAL_INTLEVEL3_MASK, \
159 [4] = XCHAL_INTLEVEL4_MASK, \
160 [5] = XCHAL_INTLEVEL5_MASK, \
161 [6] = XCHAL_INTLEVEL6_MASK, \
162 [7] = XCHAL_INTLEVEL7_MASK, \
163 }
164
165 #define INTTYPE_MASKS { \
166 [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
167 [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
168 [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
169 }
170
171 #define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
172 #define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
173 #define XTHAL_INTTYPE_NMI INTTYPE_NMI
174 #define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
175 #define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
176 #define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
177 #define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
178 #define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
179 #define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING
180
181
182 #define INTERRUPT(i) { \
183 .level = XCHAL_INT ## i ## _LEVEL, \
184 .inttype = XCHAL_INT ## i ## _TYPE, \
185 }
186
187 #define INTERRUPTS { \
188 [0] = INTERRUPT(0), \
189 [1] = INTERRUPT(1), \
190 [2] = INTERRUPT(2), \
191 [3] = INTERRUPT(3), \
192 [4] = INTERRUPT(4), \
193 [5] = INTERRUPT(5), \
194 [6] = INTERRUPT(6), \
195 [7] = INTERRUPT(7), \
196 [8] = INTERRUPT(8), \
197 [9] = INTERRUPT(9), \
198 [10] = INTERRUPT(10), \
199 [11] = INTERRUPT(11), \
200 [12] = INTERRUPT(12), \
201 [13] = INTERRUPT(13), \
202 [14] = INTERRUPT(14), \
203 [15] = INTERRUPT(15), \
204 [16] = INTERRUPT(16), \
205 [17] = INTERRUPT(17), \
206 [18] = INTERRUPT(18), \
207 [19] = INTERRUPT(19), \
208 [20] = INTERRUPT(20), \
209 [21] = INTERRUPT(21), \
210 [22] = INTERRUPT(22), \
211 [23] = INTERRUPT(23), \
212 [24] = INTERRUPT(24), \
213 [25] = INTERRUPT(25), \
214 [26] = INTERRUPT(26), \
215 [27] = INTERRUPT(27), \
216 [28] = INTERRUPT(28), \
217 [29] = INTERRUPT(29), \
218 [30] = INTERRUPT(30), \
219 [31] = INTERRUPT(31), \
220 }
221
222 #define TIMERINTS { \
223 [0] = XCHAL_TIMER0_INTERRUPT, \
224 [1] = XCHAL_TIMER1_INTERRUPT, \
225 [2] = XCHAL_TIMER2_INTERRUPT, \
226 }
227
228 #define EXTINTS { \
229 [0] = XCHAL_EXTINT0_NUM, \
230 [1] = XCHAL_EXTINT1_NUM, \
231 [2] = XCHAL_EXTINT2_NUM, \
232 [3] = XCHAL_EXTINT3_NUM, \
233 [4] = XCHAL_EXTINT4_NUM, \
234 [5] = XCHAL_EXTINT5_NUM, \
235 [6] = XCHAL_EXTINT6_NUM, \
236 [7] = XCHAL_EXTINT7_NUM, \
237 [8] = XCHAL_EXTINT8_NUM, \
238 [9] = XCHAL_EXTINT9_NUM, \
239 [10] = XCHAL_EXTINT10_NUM, \
240 [11] = XCHAL_EXTINT11_NUM, \
241 [12] = XCHAL_EXTINT12_NUM, \
242 [13] = XCHAL_EXTINT13_NUM, \
243 [14] = XCHAL_EXTINT14_NUM, \
244 [15] = XCHAL_EXTINT15_NUM, \
245 [16] = XCHAL_EXTINT16_NUM, \
246 [17] = XCHAL_EXTINT17_NUM, \
247 [18] = XCHAL_EXTINT18_NUM, \
248 [19] = XCHAL_EXTINT19_NUM, \
249 [20] = XCHAL_EXTINT20_NUM, \
250 [21] = XCHAL_EXTINT21_NUM, \
251 [22] = XCHAL_EXTINT22_NUM, \
252 [23] = XCHAL_EXTINT23_NUM, \
253 [24] = XCHAL_EXTINT24_NUM, \
254 [25] = XCHAL_EXTINT25_NUM, \
255 [26] = XCHAL_EXTINT26_NUM, \
256 [27] = XCHAL_EXTINT27_NUM, \
257 [28] = XCHAL_EXTINT28_NUM, \
258 [29] = XCHAL_EXTINT29_NUM, \
259 [30] = XCHAL_EXTINT30_NUM, \
260 [31] = XCHAL_EXTINT31_NUM, \
261 }
262
263 #define EXCEPTIONS_SECTION \
264 .excm_level = XCHAL_EXCM_LEVEL, \
265 .vecbase = XCHAL_VECBASE_RESET_VADDR, \
266 .exception_vector = EXCEPTION_VECTORS
267
268 #define INTERRUPTS_SECTION \
269 .ninterrupt = XCHAL_NUM_INTERRUPTS, \
270 .nlevel = XCHAL_NUM_INTLEVELS, \
271 .interrupt_vector = INTERRUPT_VECTORS, \
272 .level_mask = LEVEL_MASKS, \
273 .inttype_mask = INTTYPE_MASKS, \
274 .interrupt = INTERRUPTS, \
275 .nccompare = XCHAL_NUM_TIMERS, \
276 .timerint = TIMERINTS, \
277 .nextint = XCHAL_NUM_EXTINTERRUPTS, \
278 .extint = EXTINTS
279
280 #if XCHAL_HAVE_PTP_MMU
281
282 #define TLB_TEMPLATE(ways, refill_way_size, way56) { \
283 .nways = ways, \
284 .way_size = { \
285 (refill_way_size), (refill_way_size), \
286 (refill_way_size), (refill_way_size), \
287 4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \
288 }, \
289 .varway56 = (way56), \
290 .nrefillentries = (refill_way_size) * 4, \
291 }
292
293 #define ITLB(varway56) \
294 TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)
295
296 #define DTLB(varway56) \
297 TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
298
299 #define TLB_SECTION \
300 .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
301 .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
302
303 #elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR
304
305 #define TLB_TEMPLATE { \
306 .nways = 1, \
307 .way_size = { \
308 8, \
309 } \
310 }
311
312 #define TLB_SECTION \
313 .itlb = TLB_TEMPLATE, \
314 .dtlb = TLB_TEMPLATE
315
316 #endif
317
318 #if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
319 #define REGISTER_CORE(core) \
320 static void __attribute__((constructor)) register_core(void) \
321 { \
322 static XtensaConfigList node = { \
323 .config = &core, \
324 }; \
325 xtensa_finalize_config(&core); \
326 xtensa_register_core(&node); \
327 }
328 #else
329 #define REGISTER_CORE(core)
330 #endif
331
332 #define DEBUG_SECTION \
333 .debug_level = XCHAL_DEBUGLEVEL, \
334 .nibreak = XCHAL_NUM_IBREAK, \
335 .ndbreak = XCHAL_NUM_DBREAK
336
337 #define CONFIG_SECTION \
338 .configid = { \
339 XCHAL_HW_CONFIGID0, \
340 XCHAL_HW_CONFIGID1, \
341 }
342
343 #define DEFAULT_SECTIONS \
344 .options = XTENSA_OPTIONS, \
345 .nareg = XCHAL_NUM_AREGS, \
346 .ndepc = (XCHAL_XEA_VERSION >= 2), \
347 EXCEPTIONS_SECTION, \
348 INTERRUPTS_SECTION, \
349 TLB_SECTION, \
350 DEBUG_SECTION, \
351 CONFIG_SECTION
352
353
354 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
355 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0
356 #endif
357 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
358 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0
359 #endif
360 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
361 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0
362 #endif
363 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
364 #define XCHAL_INTLEVEL5_VECTOR_VADDR 0
365 #endif
366 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
367 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0
368 #endif
369 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
370 #define XCHAL_INTLEVEL7_VECTOR_VADDR 0
371 #endif
372
373
374 #if XCHAL_NUM_INTERRUPTS <= 0
375 #define XCHAL_INT0_LEVEL 0
376 #define XCHAL_INT0_TYPE 0
377 #endif
378 #if XCHAL_NUM_INTERRUPTS <= 1
379 #define XCHAL_INT1_LEVEL 0
380 #define XCHAL_INT1_TYPE 0
381 #endif
382 #if XCHAL_NUM_INTERRUPTS <= 2
383 #define XCHAL_INT2_LEVEL 0
384 #define XCHAL_INT2_TYPE 0
385 #endif
386 #if XCHAL_NUM_INTERRUPTS <= 3
387 #define XCHAL_INT3_LEVEL 0
388 #define XCHAL_INT3_TYPE 0
389 #endif
390 #if XCHAL_NUM_INTERRUPTS <= 4
391 #define XCHAL_INT4_LEVEL 0
392 #define XCHAL_INT4_TYPE 0
393 #endif
394 #if XCHAL_NUM_INTERRUPTS <= 5
395 #define XCHAL_INT5_LEVEL 0
396 #define XCHAL_INT5_TYPE 0
397 #endif
398 #if XCHAL_NUM_INTERRUPTS <= 6
399 #define XCHAL_INT6_LEVEL 0
400 #define XCHAL_INT6_TYPE 0
401 #endif
402 #if XCHAL_NUM_INTERRUPTS <= 7
403 #define XCHAL_INT7_LEVEL 0
404 #define XCHAL_INT7_TYPE 0
405 #endif
406 #if XCHAL_NUM_INTERRUPTS <= 8
407 #define XCHAL_INT8_LEVEL 0
408 #define XCHAL_INT8_TYPE 0
409 #endif
410 #if XCHAL_NUM_INTERRUPTS <= 9
411 #define XCHAL_INT9_LEVEL 0
412 #define XCHAL_INT9_TYPE 0
413 #endif
414 #if XCHAL_NUM_INTERRUPTS <= 10
415 #define XCHAL_INT10_LEVEL 0
416 #define XCHAL_INT10_TYPE 0
417 #endif
418 #if XCHAL_NUM_INTERRUPTS <= 11
419 #define XCHAL_INT11_LEVEL 0
420 #define XCHAL_INT11_TYPE 0
421 #endif
422 #if XCHAL_NUM_INTERRUPTS <= 12
423 #define XCHAL_INT12_LEVEL 0
424 #define XCHAL_INT12_TYPE 0
425 #endif
426 #if XCHAL_NUM_INTERRUPTS <= 13
427 #define XCHAL_INT13_LEVEL 0
428 #define XCHAL_INT13_TYPE 0
429 #endif
430 #if XCHAL_NUM_INTERRUPTS <= 14
431 #define XCHAL_INT14_LEVEL 0
432 #define XCHAL_INT14_TYPE 0
433 #endif
434 #if XCHAL_NUM_INTERRUPTS <= 15
435 #define XCHAL_INT15_LEVEL 0
436 #define XCHAL_INT15_TYPE 0
437 #endif
438 #if XCHAL_NUM_INTERRUPTS <= 16
439 #define XCHAL_INT16_LEVEL 0
440 #define XCHAL_INT16_TYPE 0
441 #endif
442 #if XCHAL_NUM_INTERRUPTS <= 17
443 #define XCHAL_INT17_LEVEL 0
444 #define XCHAL_INT17_TYPE 0
445 #endif
446 #if XCHAL_NUM_INTERRUPTS <= 18
447 #define XCHAL_INT18_LEVEL 0
448 #define XCHAL_INT18_TYPE 0
449 #endif
450 #if XCHAL_NUM_INTERRUPTS <= 19
451 #define XCHAL_INT19_LEVEL 0
452 #define XCHAL_INT19_TYPE 0
453 #endif
454 #if XCHAL_NUM_INTERRUPTS <= 20
455 #define XCHAL_INT20_LEVEL 0
456 #define XCHAL_INT20_TYPE 0
457 #endif
458 #if XCHAL_NUM_INTERRUPTS <= 21
459 #define XCHAL_INT21_LEVEL 0
460 #define XCHAL_INT21_TYPE 0
461 #endif
462 #if XCHAL_NUM_INTERRUPTS <= 22
463 #define XCHAL_INT22_LEVEL 0
464 #define XCHAL_INT22_TYPE 0
465 #endif
466 #if XCHAL_NUM_INTERRUPTS <= 23
467 #define XCHAL_INT23_LEVEL 0
468 #define XCHAL_INT23_TYPE 0
469 #endif
470 #if XCHAL_NUM_INTERRUPTS <= 24
471 #define XCHAL_INT24_LEVEL 0
472 #define XCHAL_INT24_TYPE 0
473 #endif
474 #if XCHAL_NUM_INTERRUPTS <= 25
475 #define XCHAL_INT25_LEVEL 0
476 #define XCHAL_INT25_TYPE 0
477 #endif
478 #if XCHAL_NUM_INTERRUPTS <= 26
479 #define XCHAL_INT26_LEVEL 0
480 #define XCHAL_INT26_TYPE 0
481 #endif
482 #if XCHAL_NUM_INTERRUPTS <= 27
483 #define XCHAL_INT27_LEVEL 0
484 #define XCHAL_INT27_TYPE 0
485 #endif
486 #if XCHAL_NUM_INTERRUPTS <= 28
487 #define XCHAL_INT28_LEVEL 0
488 #define XCHAL_INT28_TYPE 0
489 #endif
490 #if XCHAL_NUM_INTERRUPTS <= 29
491 #define XCHAL_INT29_LEVEL 0
492 #define XCHAL_INT29_TYPE 0
493 #endif
494 #if XCHAL_NUM_INTERRUPTS <= 30
495 #define XCHAL_INT30_LEVEL 0
496 #define XCHAL_INT30_TYPE 0
497 #endif
498 #if XCHAL_NUM_INTERRUPTS <= 31
499 #define XCHAL_INT31_LEVEL 0
500 #define XCHAL_INT31_TYPE 0
501 #endif
502
503
504 #if XCHAL_NUM_EXTINTERRUPTS <= 0
505 #define XCHAL_EXTINT0_NUM 0
506 #endif
507 #if XCHAL_NUM_EXTINTERRUPTS <= 1
508 #define XCHAL_EXTINT1_NUM 0
509 #endif
510 #if XCHAL_NUM_EXTINTERRUPTS <= 2
511 #define XCHAL_EXTINT2_NUM 0
512 #endif
513 #if XCHAL_NUM_EXTINTERRUPTS <= 3
514 #define XCHAL_EXTINT3_NUM 0
515 #endif
516 #if XCHAL_NUM_EXTINTERRUPTS <= 4
517 #define XCHAL_EXTINT4_NUM 0
518 #endif
519 #if XCHAL_NUM_EXTINTERRUPTS <= 5
520 #define XCHAL_EXTINT5_NUM 0
521 #endif
522 #if XCHAL_NUM_EXTINTERRUPTS <= 6
523 #define XCHAL_EXTINT6_NUM 0
524 #endif
525 #if XCHAL_NUM_EXTINTERRUPTS <= 7
526 #define XCHAL_EXTINT7_NUM 0
527 #endif
528 #if XCHAL_NUM_EXTINTERRUPTS <= 8
529 #define XCHAL_EXTINT8_NUM 0
530 #endif
531 #if XCHAL_NUM_EXTINTERRUPTS <= 9
532 #define XCHAL_EXTINT9_NUM 0
533 #endif
534 #if XCHAL_NUM_EXTINTERRUPTS <= 10
535 #define XCHAL_EXTINT10_NUM 0
536 #endif
537 #if XCHAL_NUM_EXTINTERRUPTS <= 11
538 #define XCHAL_EXTINT11_NUM 0
539 #endif
540 #if XCHAL_NUM_EXTINTERRUPTS <= 12
541 #define XCHAL_EXTINT12_NUM 0
542 #endif
543 #if XCHAL_NUM_EXTINTERRUPTS <= 13
544 #define XCHAL_EXTINT13_NUM 0
545 #endif
546 #if XCHAL_NUM_EXTINTERRUPTS <= 14
547 #define XCHAL_EXTINT14_NUM 0
548 #endif
549 #if XCHAL_NUM_EXTINTERRUPTS <= 15
550 #define XCHAL_EXTINT15_NUM 0
551 #endif
552 #if XCHAL_NUM_EXTINTERRUPTS <= 16
553 #define XCHAL_EXTINT16_NUM 0
554 #endif
555 #if XCHAL_NUM_EXTINTERRUPTS <= 17
556 #define XCHAL_EXTINT17_NUM 0
557 #endif
558 #if XCHAL_NUM_EXTINTERRUPTS <= 18
559 #define XCHAL_EXTINT18_NUM 0
560 #endif
561 #if XCHAL_NUM_EXTINTERRUPTS <= 19
562 #define XCHAL_EXTINT19_NUM 0
563 #endif
564 #if XCHAL_NUM_EXTINTERRUPTS <= 20
565 #define XCHAL_EXTINT20_NUM 0
566 #endif
567 #if XCHAL_NUM_EXTINTERRUPTS <= 21
568 #define XCHAL_EXTINT21_NUM 0
569 #endif
570 #if XCHAL_NUM_EXTINTERRUPTS <= 22
571 #define XCHAL_EXTINT22_NUM 0
572 #endif
573 #if XCHAL_NUM_EXTINTERRUPTS <= 23
574 #define XCHAL_EXTINT23_NUM 0
575 #endif
576 #if XCHAL_NUM_EXTINTERRUPTS <= 24
577 #define XCHAL_EXTINT24_NUM 0
578 #endif
579 #if XCHAL_NUM_EXTINTERRUPTS <= 25
580 #define XCHAL_EXTINT25_NUM 0
581 #endif
582 #if XCHAL_NUM_EXTINTERRUPTS <= 26
583 #define XCHAL_EXTINT26_NUM 0
584 #endif
585 #if XCHAL_NUM_EXTINTERRUPTS <= 27
586 #define XCHAL_EXTINT27_NUM 0
587 #endif
588 #if XCHAL_NUM_EXTINTERRUPTS <= 28
589 #define XCHAL_EXTINT28_NUM 0
590 #endif
591 #if XCHAL_NUM_EXTINTERRUPTS <= 29
592 #define XCHAL_EXTINT29_NUM 0
593 #endif
594 #if XCHAL_NUM_EXTINTERRUPTS <= 30
595 #define XCHAL_EXTINT30_NUM 0
596 #endif
597 #if XCHAL_NUM_EXTINTERRUPTS <= 31
598 #define XCHAL_EXTINT31_NUM 0
599 #endif
600
601
602 #define XTHAL_TIMER_UNCONFIGURED 0