scsi: pvscsi: check command descriptor ring buffer size (CVE-2016-4952)
[qemu.git] / target-xtensa / translate.c
1 /*
2 * Xtensa ISA:
3 * http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
4 *
5 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include "qemu/osdep.h"
32
33 #include "cpu.h"
34 #include "exec/exec-all.h"
35 #include "disas/disas.h"
36 #include "tcg-op.h"
37 #include "qemu/log.h"
38 #include "sysemu/sysemu.h"
39 #include "exec/exec-all.h"
40 #include "exec/cpu_ldst.h"
41 #include "exec/semihost.h"
42
43 #include "exec/helper-proto.h"
44 #include "exec/helper-gen.h"
45
46 #include "trace-tcg.h"
47 #include "exec/log.h"
48
49
50 typedef struct DisasContext {
51 const XtensaConfig *config;
52 TranslationBlock *tb;
53 uint32_t pc;
54 uint32_t next_pc;
55 int cring;
56 int ring;
57 uint32_t lbeg;
58 uint32_t lend;
59 TCGv_i32 litbase;
60 int is_jmp;
61 int singlestep_enabled;
62
63 bool sar_5bit;
64 bool sar_m32_5bit;
65 bool sar_m32_allocated;
66 TCGv_i32 sar_m32;
67
68 uint32_t ccount_delta;
69 unsigned window;
70
71 bool debug;
72 bool icount;
73 TCGv_i32 next_icount;
74
75 unsigned cpenable;
76 } DisasContext;
77
78 static TCGv_env cpu_env;
79 static TCGv_i32 cpu_pc;
80 static TCGv_i32 cpu_R[16];
81 static TCGv_i32 cpu_FR[16];
82 static TCGv_i32 cpu_SR[256];
83 static TCGv_i32 cpu_UR[256];
84
85 #include "exec/gen-icount.h"
86
87 typedef struct XtensaReg {
88 const char *name;
89 uint64_t opt_bits;
90 enum {
91 SR_R = 1,
92 SR_W = 2,
93 SR_X = 4,
94 SR_RW = 3,
95 SR_RWX = 7,
96 } access;
97 } XtensaReg;
98
99 #define XTENSA_REG_ACCESS(regname, opt, acc) { \
100 .name = (regname), \
101 .opt_bits = XTENSA_OPTION_BIT(opt), \
102 .access = (acc), \
103 }
104
105 #define XTENSA_REG(regname, opt) XTENSA_REG_ACCESS(regname, opt, SR_RWX)
106
107 #define XTENSA_REG_BITS_ACCESS(regname, opt, acc) { \
108 .name = (regname), \
109 .opt_bits = (opt), \
110 .access = (acc), \
111 }
112
113 #define XTENSA_REG_BITS(regname, opt) \
114 XTENSA_REG_BITS_ACCESS(regname, opt, SR_RWX)
115
116 static const XtensaReg sregnames[256] = {
117 [LBEG] = XTENSA_REG("LBEG", XTENSA_OPTION_LOOP),
118 [LEND] = XTENSA_REG("LEND", XTENSA_OPTION_LOOP),
119 [LCOUNT] = XTENSA_REG("LCOUNT", XTENSA_OPTION_LOOP),
120 [SAR] = XTENSA_REG_BITS("SAR", XTENSA_OPTION_ALL),
121 [BR] = XTENSA_REG("BR", XTENSA_OPTION_BOOLEAN),
122 [LITBASE] = XTENSA_REG("LITBASE", XTENSA_OPTION_EXTENDED_L32R),
123 [SCOMPARE1] = XTENSA_REG("SCOMPARE1", XTENSA_OPTION_CONDITIONAL_STORE),
124 [ACCLO] = XTENSA_REG("ACCLO", XTENSA_OPTION_MAC16),
125 [ACCHI] = XTENSA_REG("ACCHI", XTENSA_OPTION_MAC16),
126 [MR] = XTENSA_REG("MR0", XTENSA_OPTION_MAC16),
127 [MR + 1] = XTENSA_REG("MR1", XTENSA_OPTION_MAC16),
128 [MR + 2] = XTENSA_REG("MR2", XTENSA_OPTION_MAC16),
129 [MR + 3] = XTENSA_REG("MR3", XTENSA_OPTION_MAC16),
130 [WINDOW_BASE] = XTENSA_REG("WINDOW_BASE", XTENSA_OPTION_WINDOWED_REGISTER),
131 [WINDOW_START] = XTENSA_REG("WINDOW_START",
132 XTENSA_OPTION_WINDOWED_REGISTER),
133 [PTEVADDR] = XTENSA_REG("PTEVADDR", XTENSA_OPTION_MMU),
134 [RASID] = XTENSA_REG("RASID", XTENSA_OPTION_MMU),
135 [ITLBCFG] = XTENSA_REG("ITLBCFG", XTENSA_OPTION_MMU),
136 [DTLBCFG] = XTENSA_REG("DTLBCFG", XTENSA_OPTION_MMU),
137 [IBREAKENABLE] = XTENSA_REG("IBREAKENABLE", XTENSA_OPTION_DEBUG),
138 [CACHEATTR] = XTENSA_REG("CACHEATTR", XTENSA_OPTION_CACHEATTR),
139 [ATOMCTL] = XTENSA_REG("ATOMCTL", XTENSA_OPTION_ATOMCTL),
140 [IBREAKA] = XTENSA_REG("IBREAKA0", XTENSA_OPTION_DEBUG),
141 [IBREAKA + 1] = XTENSA_REG("IBREAKA1", XTENSA_OPTION_DEBUG),
142 [DBREAKA] = XTENSA_REG("DBREAKA0", XTENSA_OPTION_DEBUG),
143 [DBREAKA + 1] = XTENSA_REG("DBREAKA1", XTENSA_OPTION_DEBUG),
144 [DBREAKC] = XTENSA_REG("DBREAKC0", XTENSA_OPTION_DEBUG),
145 [DBREAKC + 1] = XTENSA_REG("DBREAKC1", XTENSA_OPTION_DEBUG),
146 [CONFIGID0] = XTENSA_REG_BITS_ACCESS("CONFIGID0", XTENSA_OPTION_ALL, SR_R),
147 [EPC1] = XTENSA_REG("EPC1", XTENSA_OPTION_EXCEPTION),
148 [EPC1 + 1] = XTENSA_REG("EPC2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
149 [EPC1 + 2] = XTENSA_REG("EPC3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
150 [EPC1 + 3] = XTENSA_REG("EPC4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
151 [EPC1 + 4] = XTENSA_REG("EPC5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
152 [EPC1 + 5] = XTENSA_REG("EPC6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
153 [EPC1 + 6] = XTENSA_REG("EPC7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
154 [DEPC] = XTENSA_REG("DEPC", XTENSA_OPTION_EXCEPTION),
155 [EPS2] = XTENSA_REG("EPS2", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
156 [EPS2 + 1] = XTENSA_REG("EPS3", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
157 [EPS2 + 2] = XTENSA_REG("EPS4", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
158 [EPS2 + 3] = XTENSA_REG("EPS5", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
159 [EPS2 + 4] = XTENSA_REG("EPS6", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
160 [EPS2 + 5] = XTENSA_REG("EPS7", XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
161 [CONFIGID1] = XTENSA_REG_BITS_ACCESS("CONFIGID1", XTENSA_OPTION_ALL, SR_R),
162 [EXCSAVE1] = XTENSA_REG("EXCSAVE1", XTENSA_OPTION_EXCEPTION),
163 [EXCSAVE1 + 1] = XTENSA_REG("EXCSAVE2",
164 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
165 [EXCSAVE1 + 2] = XTENSA_REG("EXCSAVE3",
166 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
167 [EXCSAVE1 + 3] = XTENSA_REG("EXCSAVE4",
168 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
169 [EXCSAVE1 + 4] = XTENSA_REG("EXCSAVE5",
170 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
171 [EXCSAVE1 + 5] = XTENSA_REG("EXCSAVE6",
172 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
173 [EXCSAVE1 + 6] = XTENSA_REG("EXCSAVE7",
174 XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT),
175 [CPENABLE] = XTENSA_REG("CPENABLE", XTENSA_OPTION_COPROCESSOR),
176 [INTSET] = XTENSA_REG_ACCESS("INTSET", XTENSA_OPTION_INTERRUPT, SR_RW),
177 [INTCLEAR] = XTENSA_REG_ACCESS("INTCLEAR", XTENSA_OPTION_INTERRUPT, SR_W),
178 [INTENABLE] = XTENSA_REG("INTENABLE", XTENSA_OPTION_INTERRUPT),
179 [PS] = XTENSA_REG_BITS("PS", XTENSA_OPTION_ALL),
180 [VECBASE] = XTENSA_REG("VECBASE", XTENSA_OPTION_RELOCATABLE_VECTOR),
181 [EXCCAUSE] = XTENSA_REG("EXCCAUSE", XTENSA_OPTION_EXCEPTION),
182 [DEBUGCAUSE] = XTENSA_REG_ACCESS("DEBUGCAUSE", XTENSA_OPTION_DEBUG, SR_R),
183 [CCOUNT] = XTENSA_REG("CCOUNT", XTENSA_OPTION_TIMER_INTERRUPT),
184 [PRID] = XTENSA_REG_ACCESS("PRID", XTENSA_OPTION_PROCESSOR_ID, SR_R),
185 [ICOUNT] = XTENSA_REG("ICOUNT", XTENSA_OPTION_DEBUG),
186 [ICOUNTLEVEL] = XTENSA_REG("ICOUNTLEVEL", XTENSA_OPTION_DEBUG),
187 [EXCVADDR] = XTENSA_REG("EXCVADDR", XTENSA_OPTION_EXCEPTION),
188 [CCOMPARE] = XTENSA_REG("CCOMPARE0", XTENSA_OPTION_TIMER_INTERRUPT),
189 [CCOMPARE + 1] = XTENSA_REG("CCOMPARE1",
190 XTENSA_OPTION_TIMER_INTERRUPT),
191 [CCOMPARE + 2] = XTENSA_REG("CCOMPARE2",
192 XTENSA_OPTION_TIMER_INTERRUPT),
193 [MISC] = XTENSA_REG("MISC0", XTENSA_OPTION_MISC_SR),
194 [MISC + 1] = XTENSA_REG("MISC1", XTENSA_OPTION_MISC_SR),
195 [MISC + 2] = XTENSA_REG("MISC2", XTENSA_OPTION_MISC_SR),
196 [MISC + 3] = XTENSA_REG("MISC3", XTENSA_OPTION_MISC_SR),
197 };
198
199 static const XtensaReg uregnames[256] = {
200 [THREADPTR] = XTENSA_REG("THREADPTR", XTENSA_OPTION_THREAD_POINTER),
201 [FCR] = XTENSA_REG("FCR", XTENSA_OPTION_FP_COPROCESSOR),
202 [FSR] = XTENSA_REG("FSR", XTENSA_OPTION_FP_COPROCESSOR),
203 };
204
205 void xtensa_translate_init(void)
206 {
207 static const char * const regnames[] = {
208 "ar0", "ar1", "ar2", "ar3",
209 "ar4", "ar5", "ar6", "ar7",
210 "ar8", "ar9", "ar10", "ar11",
211 "ar12", "ar13", "ar14", "ar15",
212 };
213 static const char * const fregnames[] = {
214 "f0", "f1", "f2", "f3",
215 "f4", "f5", "f6", "f7",
216 "f8", "f9", "f10", "f11",
217 "f12", "f13", "f14", "f15",
218 };
219 int i;
220
221 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
222 cpu_pc = tcg_global_mem_new_i32(cpu_env,
223 offsetof(CPUXtensaState, pc), "pc");
224
225 for (i = 0; i < 16; i++) {
226 cpu_R[i] = tcg_global_mem_new_i32(cpu_env,
227 offsetof(CPUXtensaState, regs[i]),
228 regnames[i]);
229 }
230
231 for (i = 0; i < 16; i++) {
232 cpu_FR[i] = tcg_global_mem_new_i32(cpu_env,
233 offsetof(CPUXtensaState, fregs[i].f32[FP_F32_LOW]),
234 fregnames[i]);
235 }
236
237 for (i = 0; i < 256; ++i) {
238 if (sregnames[i].name) {
239 cpu_SR[i] = tcg_global_mem_new_i32(cpu_env,
240 offsetof(CPUXtensaState, sregs[i]),
241 sregnames[i].name);
242 }
243 }
244
245 for (i = 0; i < 256; ++i) {
246 if (uregnames[i].name) {
247 cpu_UR[i] = tcg_global_mem_new_i32(cpu_env,
248 offsetof(CPUXtensaState, uregs[i]),
249 uregnames[i].name);
250 }
251 }
252 }
253
254 static inline bool option_bits_enabled(DisasContext *dc, uint64_t opt)
255 {
256 return xtensa_option_bits_enabled(dc->config, opt);
257 }
258
259 static inline bool option_enabled(DisasContext *dc, int opt)
260 {
261 return xtensa_option_enabled(dc->config, opt);
262 }
263
264 static void init_litbase(DisasContext *dc)
265 {
266 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
267 dc->litbase = tcg_temp_local_new_i32();
268 tcg_gen_andi_i32(dc->litbase, cpu_SR[LITBASE], 0xfffff000);
269 }
270 }
271
272 static void reset_litbase(DisasContext *dc)
273 {
274 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
275 tcg_temp_free(dc->litbase);
276 }
277 }
278
279 static void init_sar_tracker(DisasContext *dc)
280 {
281 dc->sar_5bit = false;
282 dc->sar_m32_5bit = false;
283 dc->sar_m32_allocated = false;
284 }
285
286 static void reset_sar_tracker(DisasContext *dc)
287 {
288 if (dc->sar_m32_allocated) {
289 tcg_temp_free(dc->sar_m32);
290 }
291 }
292
293 static void gen_right_shift_sar(DisasContext *dc, TCGv_i32 sa)
294 {
295 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f);
296 if (dc->sar_m32_5bit) {
297 tcg_gen_discard_i32(dc->sar_m32);
298 }
299 dc->sar_5bit = true;
300 dc->sar_m32_5bit = false;
301 }
302
303 static void gen_left_shift_sar(DisasContext *dc, TCGv_i32 sa)
304 {
305 TCGv_i32 tmp = tcg_const_i32(32);
306 if (!dc->sar_m32_allocated) {
307 dc->sar_m32 = tcg_temp_local_new_i32();
308 dc->sar_m32_allocated = true;
309 }
310 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f);
311 tcg_gen_sub_i32(cpu_SR[SAR], tmp, dc->sar_m32);
312 dc->sar_5bit = false;
313 dc->sar_m32_5bit = true;
314 tcg_temp_free(tmp);
315 }
316
317 static void gen_advance_ccount(DisasContext *dc)
318 {
319 if (dc->ccount_delta > 0) {
320 TCGv_i32 tmp = tcg_const_i32(dc->ccount_delta);
321 gen_helper_advance_ccount(cpu_env, tmp);
322 tcg_temp_free(tmp);
323 }
324 dc->ccount_delta = 0;
325 }
326
327 static void gen_exception(DisasContext *dc, int excp)
328 {
329 TCGv_i32 tmp = tcg_const_i32(excp);
330 gen_advance_ccount(dc);
331 gen_helper_exception(cpu_env, tmp);
332 tcg_temp_free(tmp);
333 }
334
335 static void gen_exception_cause(DisasContext *dc, uint32_t cause)
336 {
337 TCGv_i32 tpc = tcg_const_i32(dc->pc);
338 TCGv_i32 tcause = tcg_const_i32(cause);
339 gen_advance_ccount(dc);
340 gen_helper_exception_cause(cpu_env, tpc, tcause);
341 tcg_temp_free(tpc);
342 tcg_temp_free(tcause);
343 if (cause == ILLEGAL_INSTRUCTION_CAUSE ||
344 cause == SYSCALL_CAUSE) {
345 dc->is_jmp = DISAS_UPDATE;
346 }
347 }
348
349 static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
350 TCGv_i32 vaddr)
351 {
352 TCGv_i32 tpc = tcg_const_i32(dc->pc);
353 TCGv_i32 tcause = tcg_const_i32(cause);
354 gen_advance_ccount(dc);
355 gen_helper_exception_cause_vaddr(cpu_env, tpc, tcause, vaddr);
356 tcg_temp_free(tpc);
357 tcg_temp_free(tcause);
358 }
359
360 static void gen_debug_exception(DisasContext *dc, uint32_t cause)
361 {
362 TCGv_i32 tpc = tcg_const_i32(dc->pc);
363 TCGv_i32 tcause = tcg_const_i32(cause);
364 gen_advance_ccount(dc);
365 gen_helper_debug_exception(cpu_env, tpc, tcause);
366 tcg_temp_free(tpc);
367 tcg_temp_free(tcause);
368 if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) {
369 dc->is_jmp = DISAS_UPDATE;
370 }
371 }
372
373 static bool gen_check_privilege(DisasContext *dc)
374 {
375 if (dc->cring) {
376 gen_exception_cause(dc, PRIVILEGED_CAUSE);
377 dc->is_jmp = DISAS_UPDATE;
378 return false;
379 }
380 return true;
381 }
382
383 static bool gen_check_cpenable(DisasContext *dc, unsigned cp)
384 {
385 if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) &&
386 !(dc->cpenable & (1 << cp))) {
387 gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp);
388 dc->is_jmp = DISAS_UPDATE;
389 return false;
390 }
391 return true;
392 }
393
394 static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
395 {
396 tcg_gen_mov_i32(cpu_pc, dest);
397 gen_advance_ccount(dc);
398 if (dc->icount) {
399 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
400 }
401 if (dc->singlestep_enabled) {
402 gen_exception(dc, EXCP_DEBUG);
403 } else {
404 if (slot >= 0) {
405 tcg_gen_goto_tb(slot);
406 tcg_gen_exit_tb((uintptr_t)dc->tb + slot);
407 } else {
408 tcg_gen_exit_tb(0);
409 }
410 }
411 dc->is_jmp = DISAS_UPDATE;
412 }
413
414 static void gen_jump(DisasContext *dc, TCGv dest)
415 {
416 gen_jump_slot(dc, dest, -1);
417 }
418
419 static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
420 {
421 TCGv_i32 tmp = tcg_const_i32(dest);
422 #ifndef CONFIG_USER_ONLY
423 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
424 slot = -1;
425 }
426 #endif
427 gen_jump_slot(dc, tmp, slot);
428 tcg_temp_free(tmp);
429 }
430
431 static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest,
432 int slot)
433 {
434 TCGv_i32 tcallinc = tcg_const_i32(callinc);
435
436 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS],
437 tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN);
438 tcg_temp_free(tcallinc);
439 tcg_gen_movi_i32(cpu_R[callinc << 2],
440 (callinc << 30) | (dc->next_pc & 0x3fffffff));
441 gen_jump_slot(dc, dest, slot);
442 }
443
444 static void gen_callw(DisasContext *dc, int callinc, TCGv_i32 dest)
445 {
446 gen_callw_slot(dc, callinc, dest, -1);
447 }
448
449 static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot)
450 {
451 TCGv_i32 tmp = tcg_const_i32(dest);
452 #ifndef CONFIG_USER_ONLY
453 if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
454 slot = -1;
455 }
456 #endif
457 gen_callw_slot(dc, callinc, tmp, slot);
458 tcg_temp_free(tmp);
459 }
460
461 static bool gen_check_loop_end(DisasContext *dc, int slot)
462 {
463 if (option_enabled(dc, XTENSA_OPTION_LOOP) &&
464 !(dc->tb->flags & XTENSA_TBFLAG_EXCM) &&
465 dc->next_pc == dc->lend) {
466 TCGLabel *label = gen_new_label();
467
468 gen_advance_ccount(dc);
469 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label);
470 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1);
471 gen_jumpi(dc, dc->lbeg, slot);
472 gen_set_label(label);
473 gen_jumpi(dc, dc->next_pc, -1);
474 return true;
475 }
476 return false;
477 }
478
479 static void gen_jumpi_check_loop_end(DisasContext *dc, int slot)
480 {
481 if (!gen_check_loop_end(dc, slot)) {
482 gen_jumpi(dc, dc->next_pc, slot);
483 }
484 }
485
486 static void gen_brcond(DisasContext *dc, TCGCond cond,
487 TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
488 {
489 TCGLabel *label = gen_new_label();
490
491 gen_advance_ccount(dc);
492 tcg_gen_brcond_i32(cond, t0, t1, label);
493 gen_jumpi_check_loop_end(dc, 0);
494 gen_set_label(label);
495 gen_jumpi(dc, dc->pc + offset, 1);
496 }
497
498 static void gen_brcondi(DisasContext *dc, TCGCond cond,
499 TCGv_i32 t0, uint32_t t1, uint32_t offset)
500 {
501 TCGv_i32 tmp = tcg_const_i32(t1);
502 gen_brcond(dc, cond, t0, tmp, offset);
503 tcg_temp_free(tmp);
504 }
505
506 static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access)
507 {
508 if (!xtensa_option_bits_enabled(dc->config, sregnames[sr].opt_bits)) {
509 if (sregnames[sr].name) {
510 qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not configured\n", sregnames[sr].name);
511 } else {
512 qemu_log_mask(LOG_UNIMP, "SR %d is not implemented\n", sr);
513 }
514 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
515 return false;
516 } else if (!(sregnames[sr].access & access)) {
517 static const char * const access_text[] = {
518 [SR_R] = "rsr",
519 [SR_W] = "wsr",
520 [SR_X] = "xsr",
521 };
522 assert(access < ARRAY_SIZE(access_text) && access_text[access]);
523 qemu_log_mask(LOG_GUEST_ERROR, "SR %s is not available for %s\n", sregnames[sr].name,
524 access_text[access]);
525 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
526 return false;
527 }
528 return true;
529 }
530
531 static void gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr)
532 {
533 gen_advance_ccount(dc);
534 tcg_gen_mov_i32(d, cpu_SR[sr]);
535 }
536
537 static void gen_rsr_ptevaddr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
538 {
539 tcg_gen_shri_i32(d, cpu_SR[EXCVADDR], 10);
540 tcg_gen_or_i32(d, d, cpu_SR[sr]);
541 tcg_gen_andi_i32(d, d, 0xfffffffc);
542 }
543
544 static void gen_rsr(DisasContext *dc, TCGv_i32 d, uint32_t sr)
545 {
546 static void (* const rsr_handler[256])(DisasContext *dc,
547 TCGv_i32 d, uint32_t sr) = {
548 [CCOUNT] = gen_rsr_ccount,
549 [PTEVADDR] = gen_rsr_ptevaddr,
550 };
551
552 if (rsr_handler[sr]) {
553 rsr_handler[sr](dc, d, sr);
554 } else {
555 tcg_gen_mov_i32(d, cpu_SR[sr]);
556 }
557 }
558
559 static void gen_wsr_lbeg(DisasContext *dc, uint32_t sr, TCGv_i32 s)
560 {
561 gen_helper_wsr_lbeg(cpu_env, s);
562 gen_jumpi_check_loop_end(dc, 0);
563 }
564
565 static void gen_wsr_lend(DisasContext *dc, uint32_t sr, TCGv_i32 s)
566 {
567 gen_helper_wsr_lend(cpu_env, s);
568 gen_jumpi_check_loop_end(dc, 0);
569 }
570
571 static void gen_wsr_sar(DisasContext *dc, uint32_t sr, TCGv_i32 s)
572 {
573 tcg_gen_andi_i32(cpu_SR[sr], s, 0x3f);
574 if (dc->sar_m32_5bit) {
575 tcg_gen_discard_i32(dc->sar_m32);
576 }
577 dc->sar_5bit = false;
578 dc->sar_m32_5bit = false;
579 }
580
581 static void gen_wsr_br(DisasContext *dc, uint32_t sr, TCGv_i32 s)
582 {
583 tcg_gen_andi_i32(cpu_SR[sr], s, 0xffff);
584 }
585
586 static void gen_wsr_litbase(DisasContext *dc, uint32_t sr, TCGv_i32 s)
587 {
588 tcg_gen_andi_i32(cpu_SR[sr], s, 0xfffff001);
589 /* This can change tb->flags, so exit tb */
590 gen_jumpi_check_loop_end(dc, -1);
591 }
592
593 static void gen_wsr_acchi(DisasContext *dc, uint32_t sr, TCGv_i32 s)
594 {
595 tcg_gen_ext8s_i32(cpu_SR[sr], s);
596 }
597
598 static void gen_wsr_windowbase(DisasContext *dc, uint32_t sr, TCGv_i32 v)
599 {
600 gen_helper_wsr_windowbase(cpu_env, v);
601 /* This can change tb->flags, so exit tb */
602 gen_jumpi_check_loop_end(dc, -1);
603 }
604
605 static void gen_wsr_windowstart(DisasContext *dc, uint32_t sr, TCGv_i32 v)
606 {
607 tcg_gen_andi_i32(cpu_SR[sr], v, (1 << dc->config->nareg / 4) - 1);
608 /* This can change tb->flags, so exit tb */
609 gen_jumpi_check_loop_end(dc, -1);
610 }
611
612 static void gen_wsr_ptevaddr(DisasContext *dc, uint32_t sr, TCGv_i32 v)
613 {
614 tcg_gen_andi_i32(cpu_SR[sr], v, 0xffc00000);
615 }
616
617 static void gen_wsr_rasid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
618 {
619 gen_helper_wsr_rasid(cpu_env, v);
620 /* This can change tb->flags, so exit tb */
621 gen_jumpi_check_loop_end(dc, -1);
622 }
623
624 static void gen_wsr_tlbcfg(DisasContext *dc, uint32_t sr, TCGv_i32 v)
625 {
626 tcg_gen_andi_i32(cpu_SR[sr], v, 0x01130000);
627 }
628
629 static void gen_wsr_ibreakenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
630 {
631 gen_helper_wsr_ibreakenable(cpu_env, v);
632 gen_jumpi_check_loop_end(dc, 0);
633 }
634
635 static void gen_wsr_atomctl(DisasContext *dc, uint32_t sr, TCGv_i32 v)
636 {
637 tcg_gen_andi_i32(cpu_SR[sr], v, 0x3f);
638 }
639
640 static void gen_wsr_ibreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
641 {
642 unsigned id = sr - IBREAKA;
643
644 if (id < dc->config->nibreak) {
645 TCGv_i32 tmp = tcg_const_i32(id);
646 gen_helper_wsr_ibreaka(cpu_env, tmp, v);
647 tcg_temp_free(tmp);
648 gen_jumpi_check_loop_end(dc, 0);
649 }
650 }
651
652 static void gen_wsr_dbreaka(DisasContext *dc, uint32_t sr, TCGv_i32 v)
653 {
654 unsigned id = sr - DBREAKA;
655
656 if (id < dc->config->ndbreak) {
657 TCGv_i32 tmp = tcg_const_i32(id);
658 gen_helper_wsr_dbreaka(cpu_env, tmp, v);
659 tcg_temp_free(tmp);
660 }
661 }
662
663 static void gen_wsr_dbreakc(DisasContext *dc, uint32_t sr, TCGv_i32 v)
664 {
665 unsigned id = sr - DBREAKC;
666
667 if (id < dc->config->ndbreak) {
668 TCGv_i32 tmp = tcg_const_i32(id);
669 gen_helper_wsr_dbreakc(cpu_env, tmp, v);
670 tcg_temp_free(tmp);
671 }
672 }
673
674 static void gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
675 {
676 tcg_gen_andi_i32(cpu_SR[sr], v, 0xff);
677 /* This can change tb->flags, so exit tb */
678 gen_jumpi_check_loop_end(dc, -1);
679 }
680
681 static void gen_wsr_intset(DisasContext *dc, uint32_t sr, TCGv_i32 v)
682 {
683 tcg_gen_andi_i32(cpu_SR[sr], v,
684 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
685 gen_helper_check_interrupts(cpu_env);
686 gen_jumpi_check_loop_end(dc, 0);
687 }
688
689 static void gen_wsr_intclear(DisasContext *dc, uint32_t sr, TCGv_i32 v)
690 {
691 TCGv_i32 tmp = tcg_temp_new_i32();
692
693 tcg_gen_andi_i32(tmp, v,
694 dc->config->inttype_mask[INTTYPE_EDGE] |
695 dc->config->inttype_mask[INTTYPE_NMI] |
696 dc->config->inttype_mask[INTTYPE_SOFTWARE]);
697 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp);
698 tcg_temp_free(tmp);
699 gen_helper_check_interrupts(cpu_env);
700 }
701
702 static void gen_wsr_intenable(DisasContext *dc, uint32_t sr, TCGv_i32 v)
703 {
704 tcg_gen_mov_i32(cpu_SR[sr], v);
705 gen_helper_check_interrupts(cpu_env);
706 gen_jumpi_check_loop_end(dc, 0);
707 }
708
709 static void gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v)
710 {
711 uint32_t mask = PS_WOE | PS_CALLINC | PS_OWB |
712 PS_UM | PS_EXCM | PS_INTLEVEL;
713
714 if (option_enabled(dc, XTENSA_OPTION_MMU)) {
715 mask |= PS_RING;
716 }
717 tcg_gen_andi_i32(cpu_SR[sr], v, mask);
718 gen_helper_check_interrupts(cpu_env);
719 /* This can change mmu index and tb->flags, so exit tb */
720 gen_jumpi_check_loop_end(dc, -1);
721 }
722
723 static void gen_wsr_icount(DisasContext *dc, uint32_t sr, TCGv_i32 v)
724 {
725 if (dc->icount) {
726 tcg_gen_mov_i32(dc->next_icount, v);
727 } else {
728 tcg_gen_mov_i32(cpu_SR[sr], v);
729 }
730 }
731
732 static void gen_wsr_icountlevel(DisasContext *dc, uint32_t sr, TCGv_i32 v)
733 {
734 tcg_gen_andi_i32(cpu_SR[sr], v, 0xf);
735 /* This can change tb->flags, so exit tb */
736 gen_jumpi_check_loop_end(dc, -1);
737 }
738
739 static void gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v)
740 {
741 uint32_t id = sr - CCOMPARE;
742 if (id < dc->config->nccompare) {
743 uint32_t int_bit = 1 << dc->config->timerint[id];
744 gen_advance_ccount(dc);
745 tcg_gen_mov_i32(cpu_SR[sr], v);
746 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit);
747 gen_helper_check_interrupts(cpu_env);
748 }
749 }
750
751 static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
752 {
753 static void (* const wsr_handler[256])(DisasContext *dc,
754 uint32_t sr, TCGv_i32 v) = {
755 [LBEG] = gen_wsr_lbeg,
756 [LEND] = gen_wsr_lend,
757 [SAR] = gen_wsr_sar,
758 [BR] = gen_wsr_br,
759 [LITBASE] = gen_wsr_litbase,
760 [ACCHI] = gen_wsr_acchi,
761 [WINDOW_BASE] = gen_wsr_windowbase,
762 [WINDOW_START] = gen_wsr_windowstart,
763 [PTEVADDR] = gen_wsr_ptevaddr,
764 [RASID] = gen_wsr_rasid,
765 [ITLBCFG] = gen_wsr_tlbcfg,
766 [DTLBCFG] = gen_wsr_tlbcfg,
767 [IBREAKENABLE] = gen_wsr_ibreakenable,
768 [ATOMCTL] = gen_wsr_atomctl,
769 [IBREAKA] = gen_wsr_ibreaka,
770 [IBREAKA + 1] = gen_wsr_ibreaka,
771 [DBREAKA] = gen_wsr_dbreaka,
772 [DBREAKA + 1] = gen_wsr_dbreaka,
773 [DBREAKC] = gen_wsr_dbreakc,
774 [DBREAKC + 1] = gen_wsr_dbreakc,
775 [CPENABLE] = gen_wsr_cpenable,
776 [INTSET] = gen_wsr_intset,
777 [INTCLEAR] = gen_wsr_intclear,
778 [INTENABLE] = gen_wsr_intenable,
779 [PS] = gen_wsr_ps,
780 [ICOUNT] = gen_wsr_icount,
781 [ICOUNTLEVEL] = gen_wsr_icountlevel,
782 [CCOMPARE] = gen_wsr_ccompare,
783 [CCOMPARE + 1] = gen_wsr_ccompare,
784 [CCOMPARE + 2] = gen_wsr_ccompare,
785 };
786
787 if (wsr_handler[sr]) {
788 wsr_handler[sr](dc, sr, s);
789 } else {
790 tcg_gen_mov_i32(cpu_SR[sr], s);
791 }
792 }
793
794 static void gen_wur(uint32_t ur, TCGv_i32 s)
795 {
796 switch (ur) {
797 case FCR:
798 gen_helper_wur_fcr(cpu_env, s);
799 break;
800
801 case FSR:
802 tcg_gen_andi_i32(cpu_UR[ur], s, 0xffffff80);
803 break;
804
805 default:
806 tcg_gen_mov_i32(cpu_UR[ur], s);
807 break;
808 }
809 }
810
811 static void gen_load_store_alignment(DisasContext *dc, int shift,
812 TCGv_i32 addr, bool no_hw_alignment)
813 {
814 if (!option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
815 tcg_gen_andi_i32(addr, addr, ~0 << shift);
816 } else if (option_enabled(dc, XTENSA_OPTION_HW_ALIGNMENT) &&
817 no_hw_alignment) {
818 TCGLabel *label = gen_new_label();
819 TCGv_i32 tmp = tcg_temp_new_i32();
820 tcg_gen_andi_i32(tmp, addr, ~(~0 << shift));
821 tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, label);
822 gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
823 gen_set_label(label);
824 tcg_temp_free(tmp);
825 }
826 }
827
828 static void gen_waiti(DisasContext *dc, uint32_t imm4)
829 {
830 TCGv_i32 pc = tcg_const_i32(dc->next_pc);
831 TCGv_i32 intlevel = tcg_const_i32(imm4);
832 gen_advance_ccount(dc);
833 gen_helper_waiti(cpu_env, pc, intlevel);
834 tcg_temp_free(pc);
835 tcg_temp_free(intlevel);
836 }
837
838 static bool gen_window_check1(DisasContext *dc, unsigned r1)
839 {
840 if (r1 / 4 > dc->window) {
841 TCGv_i32 pc = tcg_const_i32(dc->pc);
842 TCGv_i32 w = tcg_const_i32(r1 / 4);
843
844 gen_advance_ccount(dc);
845 gen_helper_window_check(cpu_env, pc, w);
846 dc->is_jmp = DISAS_UPDATE;
847 return false;
848 }
849 return true;
850 }
851
852 static bool gen_window_check2(DisasContext *dc, unsigned r1, unsigned r2)
853 {
854 return gen_window_check1(dc, r1 > r2 ? r1 : r2);
855 }
856
857 static bool gen_window_check3(DisasContext *dc, unsigned r1, unsigned r2,
858 unsigned r3)
859 {
860 return gen_window_check2(dc, r1, r2 > r3 ? r2 : r3);
861 }
862
863 static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
864 {
865 TCGv_i32 m = tcg_temp_new_i32();
866
867 if (hi) {
868 (is_unsigned ? tcg_gen_shri_i32 : tcg_gen_sari_i32)(m, v, 16);
869 } else {
870 (is_unsigned ? tcg_gen_ext16u_i32 : tcg_gen_ext16s_i32)(m, v);
871 }
872 return m;
873 }
874
875 static inline unsigned xtensa_op0_insn_len(unsigned op0)
876 {
877 return op0 >= 8 ? 2 : 3;
878 }
879
880 static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
881 {
882 #define HAS_OPTION_BITS(opt) do { \
883 if (!option_bits_enabled(dc, opt)) { \
884 qemu_log_mask(LOG_GUEST_ERROR, "Option is not enabled %s:%d\n", \
885 __FILE__, __LINE__); \
886 goto invalid_opcode; \
887 } \
888 } while (0)
889
890 #define HAS_OPTION(opt) HAS_OPTION_BITS(XTENSA_OPTION_BIT(opt))
891
892 #define TBD() qemu_log_mask(LOG_UNIMP, "TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
893 #define RESERVED() do { \
894 qemu_log_mask(LOG_GUEST_ERROR, "RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
895 dc->pc, b0, b1, b2, __FILE__, __LINE__); \
896 goto invalid_opcode; \
897 } while (0)
898
899
900 #ifdef TARGET_WORDS_BIGENDIAN
901 #define OP0 (((b0) & 0xf0) >> 4)
902 #define OP1 (((b2) & 0xf0) >> 4)
903 #define OP2 ((b2) & 0xf)
904 #define RRR_R ((b1) & 0xf)
905 #define RRR_S (((b1) & 0xf0) >> 4)
906 #define RRR_T ((b0) & 0xf)
907 #else
908 #define OP0 (((b0) & 0xf))
909 #define OP1 (((b2) & 0xf))
910 #define OP2 (((b2) & 0xf0) >> 4)
911 #define RRR_R (((b1) & 0xf0) >> 4)
912 #define RRR_S (((b1) & 0xf))
913 #define RRR_T (((b0) & 0xf0) >> 4)
914 #endif
915 #define RRR_X ((RRR_R & 0x4) >> 2)
916 #define RRR_Y ((RRR_T & 0x4) >> 2)
917 #define RRR_W (RRR_R & 0x3)
918
919 #define RRRN_R RRR_R
920 #define RRRN_S RRR_S
921 #define RRRN_T RRR_T
922
923 #define RRI4_R RRR_R
924 #define RRI4_S RRR_S
925 #define RRI4_T RRR_T
926 #ifdef TARGET_WORDS_BIGENDIAN
927 #define RRI4_IMM4 ((b2) & 0xf)
928 #else
929 #define RRI4_IMM4 (((b2) & 0xf0) >> 4)
930 #endif
931
932 #define RRI8_R RRR_R
933 #define RRI8_S RRR_S
934 #define RRI8_T RRR_T
935 #define RRI8_IMM8 (b2)
936 #define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
937
938 #ifdef TARGET_WORDS_BIGENDIAN
939 #define RI16_IMM16 (((b1) << 8) | (b2))
940 #else
941 #define RI16_IMM16 (((b2) << 8) | (b1))
942 #endif
943
944 #ifdef TARGET_WORDS_BIGENDIAN
945 #define CALL_N (((b0) & 0xc) >> 2)
946 #define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
947 #else
948 #define CALL_N (((b0) & 0x30) >> 4)
949 #define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
950 #endif
951 #define CALL_OFFSET_SE \
952 (((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
953
954 #define CALLX_N CALL_N
955 #ifdef TARGET_WORDS_BIGENDIAN
956 #define CALLX_M ((b0) & 0x3)
957 #else
958 #define CALLX_M (((b0) & 0xc0) >> 6)
959 #endif
960 #define CALLX_S RRR_S
961
962 #define BRI12_M CALLX_M
963 #define BRI12_S RRR_S
964 #ifdef TARGET_WORDS_BIGENDIAN
965 #define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
966 #else
967 #define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
968 #endif
969 #define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
970
971 #define BRI8_M BRI12_M
972 #define BRI8_R RRI8_R
973 #define BRI8_S RRI8_S
974 #define BRI8_IMM8 RRI8_IMM8
975 #define BRI8_IMM8_SE RRI8_IMM8_SE
976
977 #define RSR_SR (b1)
978
979 uint8_t b0 = cpu_ldub_code(env, dc->pc);
980 uint8_t b1 = cpu_ldub_code(env, dc->pc + 1);
981 uint8_t b2 = 0;
982 unsigned len = xtensa_op0_insn_len(OP0);
983
984 static const uint32_t B4CONST[] = {
985 0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
986 };
987
988 static const uint32_t B4CONSTU[] = {
989 32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
990 };
991
992 switch (len) {
993 case 2:
994 HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
995 break;
996
997 case 3:
998 b2 = cpu_ldub_code(env, dc->pc + 2);
999 break;
1000
1001 default:
1002 RESERVED();
1003 }
1004 dc->next_pc = dc->pc + len;
1005
1006 switch (OP0) {
1007 case 0: /*QRST*/
1008 switch (OP1) {
1009 case 0: /*RST0*/
1010 switch (OP2) {
1011 case 0: /*ST0*/
1012 if ((RRR_R & 0xc) == 0x8) {
1013 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1014 }
1015
1016 switch (RRR_R) {
1017 case 0: /*SNM0*/
1018 switch (CALLX_M) {
1019 case 0: /*ILL*/
1020 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1021 break;
1022
1023 case 1: /*reserved*/
1024 RESERVED();
1025 break;
1026
1027 case 2: /*JR*/
1028 switch (CALLX_N) {
1029 case 0: /*RET*/
1030 case 2: /*JX*/
1031 if (gen_window_check1(dc, CALLX_S)) {
1032 gen_jump(dc, cpu_R[CALLX_S]);
1033 }
1034 break;
1035
1036 case 1: /*RETWw*/
1037 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1038 {
1039 TCGv_i32 tmp = tcg_const_i32(dc->pc);
1040 gen_advance_ccount(dc);
1041 gen_helper_retw(tmp, cpu_env, tmp);
1042 gen_jump(dc, tmp);
1043 tcg_temp_free(tmp);
1044 }
1045 break;
1046
1047 case 3: /*reserved*/
1048 RESERVED();
1049 break;
1050 }
1051 break;
1052
1053 case 3: /*CALLX*/
1054 if (!gen_window_check2(dc, CALLX_S, CALLX_N << 2)) {
1055 break;
1056 }
1057 switch (CALLX_N) {
1058 case 0: /*CALLX0*/
1059 {
1060 TCGv_i32 tmp = tcg_temp_new_i32();
1061 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1062 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
1063 gen_jump(dc, tmp);
1064 tcg_temp_free(tmp);
1065 }
1066 break;
1067
1068 case 1: /*CALLX4w*/
1069 case 2: /*CALLX8w*/
1070 case 3: /*CALLX12w*/
1071 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1072 {
1073 TCGv_i32 tmp = tcg_temp_new_i32();
1074
1075 tcg_gen_mov_i32(tmp, cpu_R[CALLX_S]);
1076 gen_callw(dc, CALLX_N, tmp);
1077 tcg_temp_free(tmp);
1078 }
1079 break;
1080 }
1081 break;
1082 }
1083 break;
1084
1085 case 1: /*MOVSPw*/
1086 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1087 if (gen_window_check2(dc, RRR_T, RRR_S)) {
1088 TCGv_i32 pc = tcg_const_i32(dc->pc);
1089 gen_advance_ccount(dc);
1090 gen_helper_movsp(cpu_env, pc);
1091 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_R[RRR_S]);
1092 tcg_temp_free(pc);
1093 }
1094 break;
1095
1096 case 2: /*SYNC*/
1097 switch (RRR_T) {
1098 case 0: /*ISYNC*/
1099 break;
1100
1101 case 1: /*RSYNC*/
1102 break;
1103
1104 case 2: /*ESYNC*/
1105 break;
1106
1107 case 3: /*DSYNC*/
1108 break;
1109
1110 case 8: /*EXCW*/
1111 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1112 break;
1113
1114 case 12: /*MEMW*/
1115 break;
1116
1117 case 13: /*EXTW*/
1118 break;
1119
1120 case 15: /*NOP*/
1121 break;
1122
1123 default: /*reserved*/
1124 RESERVED();
1125 break;
1126 }
1127 break;
1128
1129 case 3: /*RFEIx*/
1130 switch (RRR_T) {
1131 case 0: /*RFETx*/
1132 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1133 switch (RRR_S) {
1134 case 0: /*RFEx*/
1135 if (gen_check_privilege(dc)) {
1136 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1137 gen_helper_check_interrupts(cpu_env);
1138 gen_jump(dc, cpu_SR[EPC1]);
1139 }
1140 break;
1141
1142 case 1: /*RFUEx*/
1143 RESERVED();
1144 break;
1145
1146 case 2: /*RFDEx*/
1147 if (gen_check_privilege(dc)) {
1148 gen_jump(dc, cpu_SR[
1149 dc->config->ndepc ? DEPC : EPC1]);
1150 }
1151 break;
1152
1153 case 4: /*RFWOw*/
1154 case 5: /*RFWUw*/
1155 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1156 if (gen_check_privilege(dc)) {
1157 TCGv_i32 tmp = tcg_const_i32(1);
1158
1159 tcg_gen_andi_i32(
1160 cpu_SR[PS], cpu_SR[PS], ~PS_EXCM);
1161 tcg_gen_shl_i32(tmp, tmp, cpu_SR[WINDOW_BASE]);
1162
1163 if (RRR_S == 4) {
1164 tcg_gen_andc_i32(cpu_SR[WINDOW_START],
1165 cpu_SR[WINDOW_START], tmp);
1166 } else {
1167 tcg_gen_or_i32(cpu_SR[WINDOW_START],
1168 cpu_SR[WINDOW_START], tmp);
1169 }
1170
1171 gen_helper_restore_owb(cpu_env);
1172 gen_helper_check_interrupts(cpu_env);
1173 gen_jump(dc, cpu_SR[EPC1]);
1174
1175 tcg_temp_free(tmp);
1176 }
1177 break;
1178
1179 default: /*reserved*/
1180 RESERVED();
1181 break;
1182 }
1183 break;
1184
1185 case 1: /*RFIx*/
1186 HAS_OPTION(XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT);
1187 if (RRR_S >= 2 && RRR_S <= dc->config->nlevel) {
1188 if (gen_check_privilege(dc)) {
1189 tcg_gen_mov_i32(cpu_SR[PS],
1190 cpu_SR[EPS2 + RRR_S - 2]);
1191 gen_helper_check_interrupts(cpu_env);
1192 gen_jump(dc, cpu_SR[EPC1 + RRR_S - 1]);
1193 }
1194 } else {
1195 qemu_log_mask(LOG_GUEST_ERROR, "RFI %d is illegal\n", RRR_S);
1196 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1197 }
1198 break;
1199
1200 case 2: /*RFME*/
1201 TBD();
1202 break;
1203
1204 default: /*reserved*/
1205 RESERVED();
1206 break;
1207
1208 }
1209 break;
1210
1211 case 4: /*BREAKx*/
1212 HAS_OPTION(XTENSA_OPTION_DEBUG);
1213 if (dc->debug) {
1214 gen_debug_exception(dc, DEBUGCAUSE_BI);
1215 }
1216 break;
1217
1218 case 5: /*SYSCALLx*/
1219 HAS_OPTION(XTENSA_OPTION_EXCEPTION);
1220 switch (RRR_S) {
1221 case 0: /*SYSCALLx*/
1222 gen_exception_cause(dc, SYSCALL_CAUSE);
1223 break;
1224
1225 case 1: /*SIMCALL*/
1226 if (semihosting_enabled()) {
1227 if (gen_check_privilege(dc)) {
1228 gen_helper_simcall(cpu_env);
1229 }
1230 } else {
1231 qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
1232 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
1233 }
1234 break;
1235
1236 default:
1237 RESERVED();
1238 break;
1239 }
1240 break;
1241
1242 case 6: /*RSILx*/
1243 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1244 if (gen_check_privilege(dc) &&
1245 gen_window_check1(dc, RRR_T)) {
1246 tcg_gen_mov_i32(cpu_R[RRR_T], cpu_SR[PS]);
1247 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL);
1248 tcg_gen_ori_i32(cpu_SR[PS], cpu_SR[PS], RRR_S);
1249 gen_helper_check_interrupts(cpu_env);
1250 gen_jumpi_check_loop_end(dc, 0);
1251 }
1252 break;
1253
1254 case 7: /*WAITIx*/
1255 HAS_OPTION(XTENSA_OPTION_INTERRUPT);
1256 if (gen_check_privilege(dc)) {
1257 gen_waiti(dc, RRR_S);
1258 }
1259 break;
1260
1261 case 8: /*ANY4p*/
1262 case 9: /*ALL4p*/
1263 case 10: /*ANY8p*/
1264 case 11: /*ALL8p*/
1265 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1266 {
1267 const unsigned shift = (RRR_R & 2) ? 8 : 4;
1268 TCGv_i32 mask = tcg_const_i32(
1269 ((1 << shift) - 1) << RRR_S);
1270 TCGv_i32 tmp = tcg_temp_new_i32();
1271
1272 tcg_gen_and_i32(tmp, cpu_SR[BR], mask);
1273 if (RRR_R & 1) { /*ALL*/
1274 tcg_gen_addi_i32(tmp, tmp, 1 << RRR_S);
1275 } else { /*ANY*/
1276 tcg_gen_add_i32(tmp, tmp, mask);
1277 }
1278 tcg_gen_shri_i32(tmp, tmp, RRR_S + shift);
1279 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR],
1280 tmp, RRR_T, 1);
1281 tcg_temp_free(mask);
1282 tcg_temp_free(tmp);
1283 }
1284 break;
1285
1286 default: /*reserved*/
1287 RESERVED();
1288 break;
1289
1290 }
1291 break;
1292
1293 case 1: /*AND*/
1294 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1295 tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1296 }
1297 break;
1298
1299 case 2: /*OR*/
1300 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1301 tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1302 }
1303 break;
1304
1305 case 3: /*XOR*/
1306 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1307 tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1308 }
1309 break;
1310
1311 case 4: /*ST1*/
1312 switch (RRR_R) {
1313 case 0: /*SSR*/
1314 if (gen_window_check1(dc, RRR_S)) {
1315 gen_right_shift_sar(dc, cpu_R[RRR_S]);
1316 }
1317 break;
1318
1319 case 1: /*SSL*/
1320 if (gen_window_check1(dc, RRR_S)) {
1321 gen_left_shift_sar(dc, cpu_R[RRR_S]);
1322 }
1323 break;
1324
1325 case 2: /*SSA8L*/
1326 if (gen_window_check1(dc, RRR_S)) {
1327 TCGv_i32 tmp = tcg_temp_new_i32();
1328 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1329 gen_right_shift_sar(dc, tmp);
1330 tcg_temp_free(tmp);
1331 }
1332 break;
1333
1334 case 3: /*SSA8B*/
1335 if (gen_window_check1(dc, RRR_S)) {
1336 TCGv_i32 tmp = tcg_temp_new_i32();
1337 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], 3);
1338 gen_left_shift_sar(dc, tmp);
1339 tcg_temp_free(tmp);
1340 }
1341 break;
1342
1343 case 4: /*SSAI*/
1344 {
1345 TCGv_i32 tmp = tcg_const_i32(
1346 RRR_S | ((RRR_T & 1) << 4));
1347 gen_right_shift_sar(dc, tmp);
1348 tcg_temp_free(tmp);
1349 }
1350 break;
1351
1352 case 6: /*RER*/
1353 TBD();
1354 break;
1355
1356 case 7: /*WER*/
1357 TBD();
1358 break;
1359
1360 case 8: /*ROTWw*/
1361 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1362 if (gen_check_privilege(dc)) {
1363 TCGv_i32 tmp = tcg_const_i32(
1364 RRR_T | ((RRR_T & 8) ? 0xfffffff0 : 0));
1365 gen_helper_rotw(cpu_env, tmp);
1366 tcg_temp_free(tmp);
1367 /* This can change tb->flags, so exit tb */
1368 gen_jumpi_check_loop_end(dc, -1);
1369 }
1370 break;
1371
1372 case 14: /*NSAu*/
1373 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1374 if (gen_window_check2(dc, RRR_S, RRR_T)) {
1375 gen_helper_nsa(cpu_R[RRR_T], cpu_R[RRR_S]);
1376 }
1377 break;
1378
1379 case 15: /*NSAUu*/
1380 HAS_OPTION(XTENSA_OPTION_MISC_OP_NSA);
1381 if (gen_window_check2(dc, RRR_S, RRR_T)) {
1382 gen_helper_nsau(cpu_R[RRR_T], cpu_R[RRR_S]);
1383 }
1384 break;
1385
1386 default: /*reserved*/
1387 RESERVED();
1388 break;
1389 }
1390 break;
1391
1392 case 5: /*TLB*/
1393 HAS_OPTION_BITS(
1394 XTENSA_OPTION_BIT(XTENSA_OPTION_MMU) |
1395 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_PROTECTION) |
1396 XTENSA_OPTION_BIT(XTENSA_OPTION_REGION_TRANSLATION));
1397 if (gen_check_privilege(dc) &&
1398 gen_window_check2(dc, RRR_S, RRR_T)) {
1399 TCGv_i32 dtlb = tcg_const_i32((RRR_R & 8) != 0);
1400
1401 switch (RRR_R & 7) {
1402 case 3: /*RITLB0*/ /*RDTLB0*/
1403 gen_helper_rtlb0(cpu_R[RRR_T],
1404 cpu_env, cpu_R[RRR_S], dtlb);
1405 break;
1406
1407 case 4: /*IITLB*/ /*IDTLB*/
1408 gen_helper_itlb(cpu_env, cpu_R[RRR_S], dtlb);
1409 /* This could change memory mapping, so exit tb */
1410 gen_jumpi_check_loop_end(dc, -1);
1411 break;
1412
1413 case 5: /*PITLB*/ /*PDTLB*/
1414 tcg_gen_movi_i32(cpu_pc, dc->pc);
1415 gen_helper_ptlb(cpu_R[RRR_T],
1416 cpu_env, cpu_R[RRR_S], dtlb);
1417 break;
1418
1419 case 6: /*WITLB*/ /*WDTLB*/
1420 gen_helper_wtlb(
1421 cpu_env, cpu_R[RRR_T], cpu_R[RRR_S], dtlb);
1422 /* This could change memory mapping, so exit tb */
1423 gen_jumpi_check_loop_end(dc, -1);
1424 break;
1425
1426 case 7: /*RITLB1*/ /*RDTLB1*/
1427 gen_helper_rtlb1(cpu_R[RRR_T],
1428 cpu_env, cpu_R[RRR_S], dtlb);
1429 break;
1430
1431 default:
1432 tcg_temp_free(dtlb);
1433 RESERVED();
1434 break;
1435 }
1436 tcg_temp_free(dtlb);
1437 }
1438 break;
1439
1440 case 6: /*RT0*/
1441 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1442 break;
1443 }
1444 switch (RRR_S) {
1445 case 0: /*NEG*/
1446 tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
1447 break;
1448
1449 case 1: /*ABS*/
1450 {
1451 TCGv_i32 zero = tcg_const_i32(0);
1452 TCGv_i32 neg = tcg_temp_new_i32();
1453
1454 tcg_gen_neg_i32(neg, cpu_R[RRR_T]);
1455 tcg_gen_movcond_i32(TCG_COND_GE, cpu_R[RRR_R],
1456 cpu_R[RRR_T], zero, cpu_R[RRR_T], neg);
1457 tcg_temp_free(neg);
1458 tcg_temp_free(zero);
1459 }
1460 break;
1461
1462 default: /*reserved*/
1463 RESERVED();
1464 break;
1465 }
1466 break;
1467
1468 case 7: /*reserved*/
1469 RESERVED();
1470 break;
1471
1472 case 8: /*ADD*/
1473 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1474 tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1475 }
1476 break;
1477
1478 case 9: /*ADD**/
1479 case 10:
1480 case 11:
1481 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1482 TCGv_i32 tmp = tcg_temp_new_i32();
1483 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
1484 tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1485 tcg_temp_free(tmp);
1486 }
1487 break;
1488
1489 case 12: /*SUB*/
1490 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1491 tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1492 }
1493 break;
1494
1495 case 13: /*SUB**/
1496 case 14:
1497 case 15:
1498 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1499 TCGv_i32 tmp = tcg_temp_new_i32();
1500 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
1501 tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
1502 tcg_temp_free(tmp);
1503 }
1504 break;
1505 }
1506 break;
1507
1508 case 1: /*RST1*/
1509 switch (OP2) {
1510 case 0: /*SLLI*/
1511 case 1:
1512 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1513 tcg_gen_shli_i32(cpu_R[RRR_R], cpu_R[RRR_S],
1514 32 - (RRR_T | ((OP2 & 1) << 4)));
1515 }
1516 break;
1517
1518 case 2: /*SRAI*/
1519 case 3:
1520 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1521 tcg_gen_sari_i32(cpu_R[RRR_R], cpu_R[RRR_T],
1522 RRR_S | ((OP2 & 1) << 4));
1523 }
1524 break;
1525
1526 case 4: /*SRLI*/
1527 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1528 tcg_gen_shri_i32(cpu_R[RRR_R], cpu_R[RRR_T], RRR_S);
1529 }
1530 break;
1531
1532 case 6: /*XSR*/
1533 if (gen_check_sr(dc, RSR_SR, SR_X) &&
1534 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1535 gen_window_check1(dc, RRR_T)) {
1536 TCGv_i32 tmp = tcg_temp_new_i32();
1537
1538 tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
1539 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1540 gen_wsr(dc, RSR_SR, tmp);
1541 tcg_temp_free(tmp);
1542 }
1543 break;
1544
1545 /*
1546 * Note: 64 bit ops are used here solely because SAR values
1547 * have range 0..63
1548 */
1549 #define gen_shift_reg(cmd, reg) do { \
1550 TCGv_i64 tmp = tcg_temp_new_i64(); \
1551 tcg_gen_extu_i32_i64(tmp, reg); \
1552 tcg_gen_##cmd##_i64(v, v, tmp); \
1553 tcg_gen_extrl_i64_i32(cpu_R[RRR_R], v); \
1554 tcg_temp_free_i64(v); \
1555 tcg_temp_free_i64(tmp); \
1556 } while (0)
1557
1558 #define gen_shift(cmd) gen_shift_reg(cmd, cpu_SR[SAR])
1559
1560 case 8: /*SRC*/
1561 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1562 TCGv_i64 v = tcg_temp_new_i64();
1563 tcg_gen_concat_i32_i64(v, cpu_R[RRR_T], cpu_R[RRR_S]);
1564 gen_shift(shr);
1565 }
1566 break;
1567
1568 case 9: /*SRL*/
1569 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1570 break;
1571 }
1572 if (dc->sar_5bit) {
1573 tcg_gen_shr_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1574 } else {
1575 TCGv_i64 v = tcg_temp_new_i64();
1576 tcg_gen_extu_i32_i64(v, cpu_R[RRR_T]);
1577 gen_shift(shr);
1578 }
1579 break;
1580
1581 case 10: /*SLL*/
1582 if (!gen_window_check2(dc, RRR_R, RRR_S)) {
1583 break;
1584 }
1585 if (dc->sar_m32_5bit) {
1586 tcg_gen_shl_i32(cpu_R[RRR_R], cpu_R[RRR_S], dc->sar_m32);
1587 } else {
1588 TCGv_i64 v = tcg_temp_new_i64();
1589 TCGv_i32 s = tcg_const_i32(32);
1590 tcg_gen_sub_i32(s, s, cpu_SR[SAR]);
1591 tcg_gen_andi_i32(s, s, 0x3f);
1592 tcg_gen_extu_i32_i64(v, cpu_R[RRR_S]);
1593 gen_shift_reg(shl, s);
1594 tcg_temp_free(s);
1595 }
1596 break;
1597
1598 case 11: /*SRA*/
1599 if (!gen_window_check2(dc, RRR_R, RRR_T)) {
1600 break;
1601 }
1602 if (dc->sar_5bit) {
1603 tcg_gen_sar_i32(cpu_R[RRR_R], cpu_R[RRR_T], cpu_SR[SAR]);
1604 } else {
1605 TCGv_i64 v = tcg_temp_new_i64();
1606 tcg_gen_ext_i32_i64(v, cpu_R[RRR_T]);
1607 gen_shift(sar);
1608 }
1609 break;
1610 #undef gen_shift
1611 #undef gen_shift_reg
1612
1613 case 12: /*MUL16U*/
1614 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1615 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1616 TCGv_i32 v1 = tcg_temp_new_i32();
1617 TCGv_i32 v2 = tcg_temp_new_i32();
1618 tcg_gen_ext16u_i32(v1, cpu_R[RRR_S]);
1619 tcg_gen_ext16u_i32(v2, cpu_R[RRR_T]);
1620 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1621 tcg_temp_free(v2);
1622 tcg_temp_free(v1);
1623 }
1624 break;
1625
1626 case 13: /*MUL16S*/
1627 HAS_OPTION(XTENSA_OPTION_16_BIT_IMUL);
1628 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1629 TCGv_i32 v1 = tcg_temp_new_i32();
1630 TCGv_i32 v2 = tcg_temp_new_i32();
1631 tcg_gen_ext16s_i32(v1, cpu_R[RRR_S]);
1632 tcg_gen_ext16s_i32(v2, cpu_R[RRR_T]);
1633 tcg_gen_mul_i32(cpu_R[RRR_R], v1, v2);
1634 tcg_temp_free(v2);
1635 tcg_temp_free(v1);
1636 }
1637 break;
1638
1639 default: /*reserved*/
1640 RESERVED();
1641 break;
1642 }
1643 break;
1644
1645 case 2: /*RST2*/
1646 if (OP2 >= 8 && !gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1647 break;
1648 }
1649
1650 if (OP2 >= 12) {
1651 HAS_OPTION(XTENSA_OPTION_32_BIT_IDIV);
1652 TCGLabel *label = gen_new_label();
1653 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0, label);
1654 gen_exception_cause(dc, INTEGER_DIVIDE_BY_ZERO_CAUSE);
1655 gen_set_label(label);
1656 }
1657
1658 switch (OP2) {
1659 #define BOOLEAN_LOGIC(fn, r, s, t) \
1660 do { \
1661 HAS_OPTION(XTENSA_OPTION_BOOLEAN); \
1662 TCGv_i32 tmp1 = tcg_temp_new_i32(); \
1663 TCGv_i32 tmp2 = tcg_temp_new_i32(); \
1664 \
1665 tcg_gen_shri_i32(tmp1, cpu_SR[BR], s); \
1666 tcg_gen_shri_i32(tmp2, cpu_SR[BR], t); \
1667 tcg_gen_##fn##_i32(tmp1, tmp1, tmp2); \
1668 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], tmp1, r, 1); \
1669 tcg_temp_free(tmp1); \
1670 tcg_temp_free(tmp2); \
1671 } while (0)
1672
1673 case 0: /*ANDBp*/
1674 BOOLEAN_LOGIC(and, RRR_R, RRR_S, RRR_T);
1675 break;
1676
1677 case 1: /*ANDBCp*/
1678 BOOLEAN_LOGIC(andc, RRR_R, RRR_S, RRR_T);
1679 break;
1680
1681 case 2: /*ORBp*/
1682 BOOLEAN_LOGIC(or, RRR_R, RRR_S, RRR_T);
1683 break;
1684
1685 case 3: /*ORBCp*/
1686 BOOLEAN_LOGIC(orc, RRR_R, RRR_S, RRR_T);
1687 break;
1688
1689 case 4: /*XORBp*/
1690 BOOLEAN_LOGIC(xor, RRR_R, RRR_S, RRR_T);
1691 break;
1692
1693 #undef BOOLEAN_LOGIC
1694
1695 case 8: /*MULLi*/
1696 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL);
1697 tcg_gen_mul_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1698 break;
1699
1700 case 10: /*MULUHi*/
1701 case 11: /*MULSHi*/
1702 HAS_OPTION(XTENSA_OPTION_32_BIT_IMUL_HIGH);
1703 {
1704 TCGv lo = tcg_temp_new();
1705
1706 if (OP2 == 10) {
1707 tcg_gen_mulu2_i32(lo, cpu_R[RRR_R],
1708 cpu_R[RRR_S], cpu_R[RRR_T]);
1709 } else {
1710 tcg_gen_muls2_i32(lo, cpu_R[RRR_R],
1711 cpu_R[RRR_S], cpu_R[RRR_T]);
1712 }
1713 tcg_temp_free(lo);
1714 }
1715 break;
1716
1717 case 12: /*QUOUi*/
1718 tcg_gen_divu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1719 break;
1720
1721 case 13: /*QUOSi*/
1722 case 15: /*REMSi*/
1723 {
1724 TCGLabel *label1 = gen_new_label();
1725 TCGLabel *label2 = gen_new_label();
1726
1727 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_S], 0x80000000,
1728 label1);
1729 tcg_gen_brcondi_i32(TCG_COND_NE, cpu_R[RRR_T], 0xffffffff,
1730 label1);
1731 tcg_gen_movi_i32(cpu_R[RRR_R],
1732 OP2 == 13 ? 0x80000000 : 0);
1733 tcg_gen_br(label2);
1734 gen_set_label(label1);
1735 if (OP2 == 13) {
1736 tcg_gen_div_i32(cpu_R[RRR_R],
1737 cpu_R[RRR_S], cpu_R[RRR_T]);
1738 } else {
1739 tcg_gen_rem_i32(cpu_R[RRR_R],
1740 cpu_R[RRR_S], cpu_R[RRR_T]);
1741 }
1742 gen_set_label(label2);
1743 }
1744 break;
1745
1746 case 14: /*REMUi*/
1747 tcg_gen_remu_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
1748 break;
1749
1750 default: /*reserved*/
1751 RESERVED();
1752 break;
1753 }
1754 break;
1755
1756 case 3: /*RST3*/
1757 switch (OP2) {
1758 case 0: /*RSR*/
1759 if (gen_check_sr(dc, RSR_SR, SR_R) &&
1760 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1761 gen_window_check1(dc, RRR_T)) {
1762 gen_rsr(dc, cpu_R[RRR_T], RSR_SR);
1763 }
1764 break;
1765
1766 case 1: /*WSR*/
1767 if (gen_check_sr(dc, RSR_SR, SR_W) &&
1768 (RSR_SR < 64 || gen_check_privilege(dc)) &&
1769 gen_window_check1(dc, RRR_T)) {
1770 gen_wsr(dc, RSR_SR, cpu_R[RRR_T]);
1771 }
1772 break;
1773
1774 case 2: /*SEXTu*/
1775 HAS_OPTION(XTENSA_OPTION_MISC_OP_SEXT);
1776 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1777 int shift = 24 - RRR_T;
1778
1779 if (shift == 24) {
1780 tcg_gen_ext8s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1781 } else if (shift == 16) {
1782 tcg_gen_ext16s_i32(cpu_R[RRR_R], cpu_R[RRR_S]);
1783 } else {
1784 TCGv_i32 tmp = tcg_temp_new_i32();
1785 tcg_gen_shli_i32(tmp, cpu_R[RRR_S], shift);
1786 tcg_gen_sari_i32(cpu_R[RRR_R], tmp, shift);
1787 tcg_temp_free(tmp);
1788 }
1789 }
1790 break;
1791
1792 case 3: /*CLAMPSu*/
1793 HAS_OPTION(XTENSA_OPTION_MISC_OP_CLAMPS);
1794 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1795 TCGv_i32 tmp1 = tcg_temp_new_i32();
1796 TCGv_i32 tmp2 = tcg_temp_new_i32();
1797 TCGv_i32 zero = tcg_const_i32(0);
1798
1799 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 24 - RRR_T);
1800 tcg_gen_xor_i32(tmp2, tmp1, cpu_R[RRR_S]);
1801 tcg_gen_andi_i32(tmp2, tmp2, 0xffffffff << (RRR_T + 7));
1802
1803 tcg_gen_sari_i32(tmp1, cpu_R[RRR_S], 31);
1804 tcg_gen_xori_i32(tmp1, tmp1, 0xffffffff >> (25 - RRR_T));
1805
1806 tcg_gen_movcond_i32(TCG_COND_EQ, cpu_R[RRR_R], tmp2, zero,
1807 cpu_R[RRR_S], tmp1);
1808 tcg_temp_free(tmp1);
1809 tcg_temp_free(tmp2);
1810 tcg_temp_free(zero);
1811 }
1812 break;
1813
1814 case 4: /*MINu*/
1815 case 5: /*MAXu*/
1816 case 6: /*MINUu*/
1817 case 7: /*MAXUu*/
1818 HAS_OPTION(XTENSA_OPTION_MISC_OP_MINMAX);
1819 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1820 static const TCGCond cond[] = {
1821 TCG_COND_LE,
1822 TCG_COND_GE,
1823 TCG_COND_LEU,
1824 TCG_COND_GEU
1825 };
1826 tcg_gen_movcond_i32(cond[OP2 - 4], cpu_R[RRR_R],
1827 cpu_R[RRR_S], cpu_R[RRR_T],
1828 cpu_R[RRR_S], cpu_R[RRR_T]);
1829 }
1830 break;
1831
1832 case 8: /*MOVEQZ*/
1833 case 9: /*MOVNEZ*/
1834 case 10: /*MOVLTZ*/
1835 case 11: /*MOVGEZ*/
1836 if (gen_window_check3(dc, RRR_R, RRR_S, RRR_T)) {
1837 static const TCGCond cond[] = {
1838 TCG_COND_EQ,
1839 TCG_COND_NE,
1840 TCG_COND_LT,
1841 TCG_COND_GE,
1842 };
1843 TCGv_i32 zero = tcg_const_i32(0);
1844
1845 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_R[RRR_R],
1846 cpu_R[RRR_T], zero, cpu_R[RRR_S], cpu_R[RRR_R]);
1847 tcg_temp_free(zero);
1848 }
1849 break;
1850
1851 case 12: /*MOVFp*/
1852 case 13: /*MOVTp*/
1853 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
1854 if (gen_window_check2(dc, RRR_R, RRR_S)) {
1855 TCGv_i32 zero = tcg_const_i32(0);
1856 TCGv_i32 tmp = tcg_temp_new_i32();
1857
1858 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
1859 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
1860 cpu_R[RRR_R], tmp, zero,
1861 cpu_R[RRR_S], cpu_R[RRR_R]);
1862
1863 tcg_temp_free(tmp);
1864 tcg_temp_free(zero);
1865 }
1866 break;
1867
1868 case 14: /*RUR*/
1869 if (gen_window_check1(dc, RRR_R)) {
1870 int st = (RRR_S << 4) + RRR_T;
1871 if (uregnames[st].name) {
1872 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]);
1873 } else {
1874 qemu_log_mask(LOG_UNIMP, "RUR %d not implemented, ", st);
1875 TBD();
1876 }
1877 }
1878 break;
1879
1880 case 15: /*WUR*/
1881 if (gen_window_check1(dc, RRR_T)) {
1882 if (uregnames[RSR_SR].name) {
1883 gen_wur(RSR_SR, cpu_R[RRR_T]);
1884 } else {
1885 qemu_log_mask(LOG_UNIMP, "WUR %d not implemented, ", RSR_SR);
1886 TBD();
1887 }
1888 }
1889 break;
1890
1891 }
1892 break;
1893
1894 case 4: /*EXTUI*/
1895 case 5:
1896 if (gen_window_check2(dc, RRR_R, RRR_T)) {
1897 int shiftimm = RRR_S | ((OP1 & 1) << 4);
1898 int maskimm = (1 << (OP2 + 1)) - 1;
1899
1900 TCGv_i32 tmp = tcg_temp_new_i32();
1901 tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
1902 tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
1903 tcg_temp_free(tmp);
1904 }
1905 break;
1906
1907 case 6: /*CUST0*/
1908 RESERVED();
1909 break;
1910
1911 case 7: /*CUST1*/
1912 RESERVED();
1913 break;
1914
1915 case 8: /*LSCXp*/
1916 switch (OP2) {
1917 case 0: /*LSXf*/
1918 case 1: /*LSXUf*/
1919 case 4: /*SSXf*/
1920 case 5: /*SSXUf*/
1921 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
1922 if (gen_window_check2(dc, RRR_S, RRR_T) &&
1923 gen_check_cpenable(dc, 0)) {
1924 TCGv_i32 addr = tcg_temp_new_i32();
1925 tcg_gen_add_i32(addr, cpu_R[RRR_S], cpu_R[RRR_T]);
1926 gen_load_store_alignment(dc, 2, addr, false);
1927 if (OP2 & 0x4) {
1928 tcg_gen_qemu_st32(cpu_FR[RRR_R], addr, dc->cring);
1929 } else {
1930 tcg_gen_qemu_ld32u(cpu_FR[RRR_R], addr, dc->cring);
1931 }
1932 if (OP2 & 0x1) {
1933 tcg_gen_mov_i32(cpu_R[RRR_S], addr);
1934 }
1935 tcg_temp_free(addr);
1936 }
1937 break;
1938
1939 default: /*reserved*/
1940 RESERVED();
1941 break;
1942 }
1943 break;
1944
1945 case 9: /*LSC4*/
1946 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
1947 break;
1948 }
1949 switch (OP2) {
1950 case 0: /*L32E*/
1951 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1952 if (gen_check_privilege(dc) &&
1953 gen_window_check2(dc, RRR_S, RRR_T)) {
1954 TCGv_i32 addr = tcg_temp_new_i32();
1955 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1956 (0xffffffc0 | (RRR_R << 2)));
1957 tcg_gen_qemu_ld32u(cpu_R[RRR_T], addr, dc->ring);
1958 tcg_temp_free(addr);
1959 }
1960 break;
1961
1962 case 4: /*S32E*/
1963 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
1964 if (gen_check_privilege(dc) &&
1965 gen_window_check2(dc, RRR_S, RRR_T)) {
1966 TCGv_i32 addr = tcg_temp_new_i32();
1967 tcg_gen_addi_i32(addr, cpu_R[RRR_S],
1968 (0xffffffc0 | (RRR_R << 2)));
1969 tcg_gen_qemu_st32(cpu_R[RRR_T], addr, dc->ring);
1970 tcg_temp_free(addr);
1971 }
1972 break;
1973
1974 case 5: /*S32N*/
1975 if (gen_window_check2(dc, RRI4_S, RRI4_T)) {
1976 TCGv_i32 addr = tcg_temp_new_i32();
1977
1978 tcg_gen_addi_i32(addr, cpu_R[RRI4_S], RRI4_IMM4 << 2);
1979 gen_load_store_alignment(dc, 2, addr, false);
1980 tcg_gen_qemu_st32(cpu_R[RRI4_T], addr, dc->cring);
1981 tcg_temp_free(addr);
1982 }
1983 break;
1984
1985 default:
1986 RESERVED();
1987 break;
1988 }
1989 break;
1990
1991 case 10: /*FP0*/
1992 /*DEPBITS*/
1993 if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
1994 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
1995 break;
1996 }
1997 tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
1998 OP2, RRR_R + 1);
1999 break;
2000 }
2001
2002 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2003 switch (OP2) {
2004 case 0: /*ADD.Sf*/
2005 if (gen_check_cpenable(dc, 0)) {
2006 gen_helper_add_s(cpu_FR[RRR_R], cpu_env,
2007 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2008 }
2009 break;
2010
2011 case 1: /*SUB.Sf*/
2012 if (gen_check_cpenable(dc, 0)) {
2013 gen_helper_sub_s(cpu_FR[RRR_R], cpu_env,
2014 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2015 }
2016 break;
2017
2018 case 2: /*MUL.Sf*/
2019 if (gen_check_cpenable(dc, 0)) {
2020 gen_helper_mul_s(cpu_FR[RRR_R], cpu_env,
2021 cpu_FR[RRR_S], cpu_FR[RRR_T]);
2022 }
2023 break;
2024
2025 case 4: /*MADD.Sf*/
2026 if (gen_check_cpenable(dc, 0)) {
2027 gen_helper_madd_s(cpu_FR[RRR_R], cpu_env,
2028 cpu_FR[RRR_R], cpu_FR[RRR_S],
2029 cpu_FR[RRR_T]);
2030 }
2031 break;
2032
2033 case 5: /*MSUB.Sf*/
2034 if (gen_check_cpenable(dc, 0)) {
2035 gen_helper_msub_s(cpu_FR[RRR_R], cpu_env,
2036 cpu_FR[RRR_R], cpu_FR[RRR_S],
2037 cpu_FR[RRR_T]);
2038 }
2039 break;
2040
2041 case 8: /*ROUND.Sf*/
2042 case 9: /*TRUNC.Sf*/
2043 case 10: /*FLOOR.Sf*/
2044 case 11: /*CEIL.Sf*/
2045 case 14: /*UTRUNC.Sf*/
2046 if (gen_window_check1(dc, RRR_R) &&
2047 gen_check_cpenable(dc, 0)) {
2048 static const unsigned rounding_mode_const[] = {
2049 float_round_nearest_even,
2050 float_round_to_zero,
2051 float_round_down,
2052 float_round_up,
2053 [6] = float_round_to_zero,
2054 };
2055 TCGv_i32 rounding_mode = tcg_const_i32(
2056 rounding_mode_const[OP2 & 7]);
2057 TCGv_i32 scale = tcg_const_i32(RRR_T);
2058
2059 if (OP2 == 14) {
2060 gen_helper_ftoui(cpu_R[RRR_R], cpu_FR[RRR_S],
2061 rounding_mode, scale);
2062 } else {
2063 gen_helper_ftoi(cpu_R[RRR_R], cpu_FR[RRR_S],
2064 rounding_mode, scale);
2065 }
2066
2067 tcg_temp_free(rounding_mode);
2068 tcg_temp_free(scale);
2069 }
2070 break;
2071
2072 case 12: /*FLOAT.Sf*/
2073 case 13: /*UFLOAT.Sf*/
2074 if (gen_window_check1(dc, RRR_S) &&
2075 gen_check_cpenable(dc, 0)) {
2076 TCGv_i32 scale = tcg_const_i32(-RRR_T);
2077
2078 if (OP2 == 13) {
2079 gen_helper_uitof(cpu_FR[RRR_R], cpu_env,
2080 cpu_R[RRR_S], scale);
2081 } else {
2082 gen_helper_itof(cpu_FR[RRR_R], cpu_env,
2083 cpu_R[RRR_S], scale);
2084 }
2085 tcg_temp_free(scale);
2086 }
2087 break;
2088
2089 case 15: /*FP1OP*/
2090 switch (RRR_T) {
2091 case 0: /*MOV.Sf*/
2092 if (gen_check_cpenable(dc, 0)) {
2093 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2094 }
2095 break;
2096
2097 case 1: /*ABS.Sf*/
2098 if (gen_check_cpenable(dc, 0)) {
2099 gen_helper_abs_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2100 }
2101 break;
2102
2103 case 4: /*RFRf*/
2104 if (gen_window_check1(dc, RRR_R) &&
2105 gen_check_cpenable(dc, 0)) {
2106 tcg_gen_mov_i32(cpu_R[RRR_R], cpu_FR[RRR_S]);
2107 }
2108 break;
2109
2110 case 5: /*WFRf*/
2111 if (gen_window_check1(dc, RRR_S) &&
2112 gen_check_cpenable(dc, 0)) {
2113 tcg_gen_mov_i32(cpu_FR[RRR_R], cpu_R[RRR_S]);
2114 }
2115 break;
2116
2117 case 6: /*NEG.Sf*/
2118 if (gen_check_cpenable(dc, 0)) {
2119 gen_helper_neg_s(cpu_FR[RRR_R], cpu_FR[RRR_S]);
2120 }
2121 break;
2122
2123 default: /*reserved*/
2124 RESERVED();
2125 break;
2126 }
2127 break;
2128
2129 default: /*reserved*/
2130 RESERVED();
2131 break;
2132 }
2133 break;
2134
2135 case 11: /*FP1*/
2136 /*DEPBITS*/
2137 if (option_enabled(dc, XTENSA_OPTION_DEPBITS)) {
2138 if (!gen_window_check2(dc, RRR_S, RRR_T)) {
2139 break;
2140 }
2141 tcg_gen_deposit_i32(cpu_R[RRR_T], cpu_R[RRR_T], cpu_R[RRR_S],
2142 OP2 + 16, RRR_R + 1);
2143 break;
2144 }
2145
2146 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2147
2148 #define gen_compare(rel, br, a, b) \
2149 do { \
2150 if (gen_check_cpenable(dc, 0)) { \
2151 TCGv_i32 bit = tcg_const_i32(1 << br); \
2152 \
2153 gen_helper_##rel(cpu_env, bit, cpu_FR[a], cpu_FR[b]); \
2154 tcg_temp_free(bit); \
2155 } \
2156 } while (0)
2157
2158 switch (OP2) {
2159 case 1: /*UN.Sf*/
2160 gen_compare(un_s, RRR_R, RRR_S, RRR_T);
2161 break;
2162
2163 case 2: /*OEQ.Sf*/
2164 gen_compare(oeq_s, RRR_R, RRR_S, RRR_T);
2165 break;
2166
2167 case 3: /*UEQ.Sf*/
2168 gen_compare(ueq_s, RRR_R, RRR_S, RRR_T);
2169 break;
2170
2171 case 4: /*OLT.Sf*/
2172 gen_compare(olt_s, RRR_R, RRR_S, RRR_T);
2173 break;
2174
2175 case 5: /*ULT.Sf*/
2176 gen_compare(ult_s, RRR_R, RRR_S, RRR_T);
2177 break;
2178
2179 case 6: /*OLE.Sf*/
2180 gen_compare(ole_s, RRR_R, RRR_S, RRR_T);
2181 break;
2182
2183 case 7: /*ULE.Sf*/
2184 gen_compare(ule_s, RRR_R, RRR_S, RRR_T);
2185 break;
2186
2187 #undef gen_compare
2188
2189 case 8: /*MOVEQZ.Sf*/
2190 case 9: /*MOVNEZ.Sf*/
2191 case 10: /*MOVLTZ.Sf*/
2192 case 11: /*MOVGEZ.Sf*/
2193 if (gen_window_check1(dc, RRR_T) &&
2194 gen_check_cpenable(dc, 0)) {
2195 static const TCGCond cond[] = {
2196 TCG_COND_EQ,
2197 TCG_COND_NE,
2198 TCG_COND_LT,
2199 TCG_COND_GE,
2200 };
2201 TCGv_i32 zero = tcg_const_i32(0);
2202
2203 tcg_gen_movcond_i32(cond[OP2 - 8], cpu_FR[RRR_R],
2204 cpu_R[RRR_T], zero, cpu_FR[RRR_S], cpu_FR[RRR_R]);
2205 tcg_temp_free(zero);
2206 }
2207 break;
2208
2209 case 12: /*MOVF.Sf*/
2210 case 13: /*MOVT.Sf*/
2211 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2212 if (gen_check_cpenable(dc, 0)) {
2213 TCGv_i32 zero = tcg_const_i32(0);
2214 TCGv_i32 tmp = tcg_temp_new_i32();
2215
2216 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRR_T);
2217 tcg_gen_movcond_i32(OP2 & 1 ? TCG_COND_NE : TCG_COND_EQ,
2218 cpu_FR[RRR_R], tmp, zero,
2219 cpu_FR[RRR_S], cpu_FR[RRR_R]);
2220
2221 tcg_temp_free(tmp);
2222 tcg_temp_free(zero);
2223 }
2224 break;
2225
2226 default: /*reserved*/
2227 RESERVED();
2228 break;
2229 }
2230 break;
2231
2232 default: /*reserved*/
2233 RESERVED();
2234 break;
2235 }
2236 break;
2237
2238 case 1: /*L32R*/
2239 if (gen_window_check1(dc, RRR_T)) {
2240 TCGv_i32 tmp = tcg_const_i32(
2241 ((dc->tb->flags & XTENSA_TBFLAG_LITBASE) ?
2242 0 : ((dc->pc + 3) & ~3)) +
2243 (0xfffc0000 | (RI16_IMM16 << 2)));
2244
2245 if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) {
2246 tcg_gen_add_i32(tmp, tmp, dc->litbase);
2247 }
2248 tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, dc->cring);
2249 tcg_temp_free(tmp);
2250 }
2251 break;
2252
2253 case 2: /*LSAI*/
2254 #define gen_load_store(type, shift) do { \
2255 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2256 TCGv_i32 addr = tcg_temp_new_i32(); \
2257 \
2258 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << shift); \
2259 if (shift) { \
2260 gen_load_store_alignment(dc, shift, addr, false); \
2261 } \
2262 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2263 tcg_temp_free(addr); \
2264 } \
2265 } while (0)
2266
2267 switch (RRI8_R) {
2268 case 0: /*L8UI*/
2269 gen_load_store(ld8u, 0);
2270 break;
2271
2272 case 1: /*L16UI*/
2273 gen_load_store(ld16u, 1);
2274 break;
2275
2276 case 2: /*L32I*/
2277 gen_load_store(ld32u, 2);
2278 break;
2279
2280 case 4: /*S8I*/
2281 gen_load_store(st8, 0);
2282 break;
2283
2284 case 5: /*S16I*/
2285 gen_load_store(st16, 1);
2286 break;
2287
2288 case 6: /*S32I*/
2289 gen_load_store(st32, 2);
2290 break;
2291
2292 #define gen_dcache_hit_test(w, shift) do { \
2293 if (gen_window_check1(dc, RRI##w##_S)) { \
2294 TCGv_i32 addr = tcg_temp_new_i32(); \
2295 TCGv_i32 res = tcg_temp_new_i32(); \
2296 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2297 RRI##w##_IMM##w << shift); \
2298 tcg_gen_qemu_ld8u(res, addr, dc->cring); \
2299 tcg_temp_free(addr); \
2300 tcg_temp_free(res); \
2301 } \
2302 } while (0)
2303
2304 #define gen_dcache_hit_test4() gen_dcache_hit_test(4, 4)
2305 #define gen_dcache_hit_test8() gen_dcache_hit_test(8, 2)
2306
2307 case 7: /*CACHEc*/
2308 if (RRI8_T < 8) {
2309 HAS_OPTION(XTENSA_OPTION_DCACHE);
2310 }
2311
2312 switch (RRI8_T) {
2313 case 0: /*DPFRc*/
2314 gen_window_check1(dc, RRI8_S);
2315 break;
2316
2317 case 1: /*DPFWc*/
2318 gen_window_check1(dc, RRI8_S);
2319 break;
2320
2321 case 2: /*DPFROc*/
2322 gen_window_check1(dc, RRI8_S);
2323 break;
2324
2325 case 3: /*DPFWOc*/
2326 gen_window_check1(dc, RRI8_S);
2327 break;
2328
2329 case 4: /*DHWBc*/
2330 gen_dcache_hit_test8();
2331 break;
2332
2333 case 5: /*DHWBIc*/
2334 gen_dcache_hit_test8();
2335 break;
2336
2337 case 6: /*DHIc*/
2338 if (gen_check_privilege(dc)) {
2339 gen_dcache_hit_test8();
2340 }
2341 break;
2342
2343 case 7: /*DIIc*/
2344 if (gen_check_privilege(dc)) {
2345 gen_window_check1(dc, RRI8_S);
2346 }
2347 break;
2348
2349 case 8: /*DCEc*/
2350 switch (OP1) {
2351 case 0: /*DPFLl*/
2352 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2353 if (gen_check_privilege(dc)) {
2354 gen_dcache_hit_test4();
2355 }
2356 break;
2357
2358 case 2: /*DHUl*/
2359 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2360 if (gen_check_privilege(dc)) {
2361 gen_dcache_hit_test4();
2362 }
2363 break;
2364
2365 case 3: /*DIUl*/
2366 HAS_OPTION(XTENSA_OPTION_DCACHE_INDEX_LOCK);
2367 if (gen_check_privilege(dc)) {
2368 gen_window_check1(dc, RRI4_S);
2369 }
2370 break;
2371
2372 case 4: /*DIWBc*/
2373 HAS_OPTION(XTENSA_OPTION_DCACHE);
2374 if (gen_check_privilege(dc)) {
2375 gen_window_check1(dc, RRI4_S);
2376 }
2377 break;
2378
2379 case 5: /*DIWBIc*/
2380 HAS_OPTION(XTENSA_OPTION_DCACHE);
2381 if (gen_check_privilege(dc)) {
2382 gen_window_check1(dc, RRI4_S);
2383 }
2384 break;
2385
2386 default: /*reserved*/
2387 RESERVED();
2388 break;
2389
2390 }
2391 break;
2392
2393 #undef gen_dcache_hit_test
2394 #undef gen_dcache_hit_test4
2395 #undef gen_dcache_hit_test8
2396
2397 #define gen_icache_hit_test(w, shift) do { \
2398 if (gen_window_check1(dc, RRI##w##_S)) { \
2399 TCGv_i32 addr = tcg_temp_new_i32(); \
2400 tcg_gen_movi_i32(cpu_pc, dc->pc); \
2401 tcg_gen_addi_i32(addr, cpu_R[RRI##w##_S], \
2402 RRI##w##_IMM##w << shift); \
2403 gen_helper_itlb_hit_test(cpu_env, addr); \
2404 tcg_temp_free(addr); \
2405 }\
2406 } while (0)
2407
2408 #define gen_icache_hit_test4() gen_icache_hit_test(4, 4)
2409 #define gen_icache_hit_test8() gen_icache_hit_test(8, 2)
2410
2411 case 12: /*IPFc*/
2412 HAS_OPTION(XTENSA_OPTION_ICACHE);
2413 gen_window_check1(dc, RRI8_S);
2414 break;
2415
2416 case 13: /*ICEc*/
2417 switch (OP1) {
2418 case 0: /*IPFLl*/
2419 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2420 if (gen_check_privilege(dc)) {
2421 gen_icache_hit_test4();
2422 }
2423 break;
2424
2425 case 2: /*IHUl*/
2426 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2427 if (gen_check_privilege(dc)) {
2428 gen_icache_hit_test4();
2429 }
2430 break;
2431
2432 case 3: /*IIUl*/
2433 HAS_OPTION(XTENSA_OPTION_ICACHE_INDEX_LOCK);
2434 if (gen_check_privilege(dc)) {
2435 gen_window_check1(dc, RRI4_S);
2436 }
2437 break;
2438
2439 default: /*reserved*/
2440 RESERVED();
2441 break;
2442 }
2443 break;
2444
2445 case 14: /*IHIc*/
2446 HAS_OPTION(XTENSA_OPTION_ICACHE);
2447 gen_icache_hit_test8();
2448 break;
2449
2450 case 15: /*IIIc*/
2451 HAS_OPTION(XTENSA_OPTION_ICACHE);
2452 if (gen_check_privilege(dc)) {
2453 gen_window_check1(dc, RRI8_S);
2454 }
2455 break;
2456
2457 default: /*reserved*/
2458 RESERVED();
2459 break;
2460 }
2461 break;
2462
2463 #undef gen_icache_hit_test
2464 #undef gen_icache_hit_test4
2465 #undef gen_icache_hit_test8
2466
2467 case 9: /*L16SI*/
2468 gen_load_store(ld16s, 1);
2469 break;
2470 #undef gen_load_store
2471
2472 case 10: /*MOVI*/
2473 if (gen_window_check1(dc, RRI8_T)) {
2474 tcg_gen_movi_i32(cpu_R[RRI8_T],
2475 RRI8_IMM8 | (RRI8_S << 8) |
2476 ((RRI8_S & 0x8) ? 0xfffff000 : 0));
2477 }
2478 break;
2479
2480 #define gen_load_store_no_hw_align(type) do { \
2481 if (gen_window_check2(dc, RRI8_S, RRI8_T)) { \
2482 TCGv_i32 addr = tcg_temp_local_new_i32(); \
2483 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2); \
2484 gen_load_store_alignment(dc, 2, addr, true); \
2485 tcg_gen_qemu_##type(cpu_R[RRI8_T], addr, dc->cring); \
2486 tcg_temp_free(addr); \
2487 } \
2488 } while (0)
2489
2490 case 11: /*L32AIy*/
2491 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2492 gen_load_store_no_hw_align(ld32u); /*TODO acquire?*/
2493 break;
2494
2495 case 12: /*ADDI*/
2496 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2497 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S], RRI8_IMM8_SE);
2498 }
2499 break;
2500
2501 case 13: /*ADDMI*/
2502 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2503 tcg_gen_addi_i32(cpu_R[RRI8_T], cpu_R[RRI8_S],
2504 RRI8_IMM8_SE << 8);
2505 }
2506 break;
2507
2508 case 14: /*S32C1Iy*/
2509 HAS_OPTION(XTENSA_OPTION_CONDITIONAL_STORE);
2510 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2511 TCGLabel *label = gen_new_label();
2512 TCGv_i32 tmp = tcg_temp_local_new_i32();
2513 TCGv_i32 addr = tcg_temp_local_new_i32();
2514 TCGv_i32 tpc;
2515
2516 tcg_gen_mov_i32(tmp, cpu_R[RRI8_T]);
2517 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2518 gen_load_store_alignment(dc, 2, addr, true);
2519
2520 gen_advance_ccount(dc);
2521 tpc = tcg_const_i32(dc->pc);
2522 gen_helper_check_atomctl(cpu_env, tpc, addr);
2523 tcg_gen_qemu_ld32u(cpu_R[RRI8_T], addr, dc->cring);
2524 tcg_gen_brcond_i32(TCG_COND_NE, cpu_R[RRI8_T],
2525 cpu_SR[SCOMPARE1], label);
2526
2527 tcg_gen_qemu_st32(tmp, addr, dc->cring);
2528
2529 gen_set_label(label);
2530 tcg_temp_free(tpc);
2531 tcg_temp_free(addr);
2532 tcg_temp_free(tmp);
2533 }
2534 break;
2535
2536 case 15: /*S32RIy*/
2537 HAS_OPTION(XTENSA_OPTION_MP_SYNCHRO);
2538 gen_load_store_no_hw_align(st32); /*TODO release?*/
2539 break;
2540 #undef gen_load_store_no_hw_align
2541
2542 default: /*reserved*/
2543 RESERVED();
2544 break;
2545 }
2546 break;
2547
2548 case 3: /*LSCIp*/
2549 switch (RRI8_R) {
2550 case 0: /*LSIf*/
2551 case 4: /*SSIf*/
2552 case 8: /*LSIUf*/
2553 case 12: /*SSIUf*/
2554 HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
2555 if (gen_window_check1(dc, RRI8_S) &&
2556 gen_check_cpenable(dc, 0)) {
2557 TCGv_i32 addr = tcg_temp_new_i32();
2558 tcg_gen_addi_i32(addr, cpu_R[RRI8_S], RRI8_IMM8 << 2);
2559 gen_load_store_alignment(dc, 2, addr, false);
2560 if (RRI8_R & 0x4) {
2561 tcg_gen_qemu_st32(cpu_FR[RRI8_T], addr, dc->cring);
2562 } else {
2563 tcg_gen_qemu_ld32u(cpu_FR[RRI8_T], addr, dc->cring);
2564 }
2565 if (RRI8_R & 0x8) {
2566 tcg_gen_mov_i32(cpu_R[RRI8_S], addr);
2567 }
2568 tcg_temp_free(addr);
2569 }
2570 break;
2571
2572 default: /*reserved*/
2573 RESERVED();
2574 break;
2575 }
2576 break;
2577
2578 case 4: /*MAC16d*/
2579 HAS_OPTION(XTENSA_OPTION_MAC16);
2580 {
2581 enum {
2582 MAC16_UMUL = 0x0,
2583 MAC16_MUL = 0x4,
2584 MAC16_MULA = 0x8,
2585 MAC16_MULS = 0xc,
2586 MAC16_NONE = 0xf,
2587 } op = OP1 & 0xc;
2588 bool is_m1_sr = (OP2 & 0x3) == 2;
2589 bool is_m2_sr = (OP2 & 0xc) == 0;
2590 uint32_t ld_offset = 0;
2591
2592 if (OP2 > 9) {
2593 RESERVED();
2594 }
2595
2596 switch (OP2 & 2) {
2597 case 0: /*MACI?/MACC?*/
2598 is_m1_sr = true;
2599 ld_offset = (OP2 & 1) ? -4 : 4;
2600
2601 if (OP2 >= 8) { /*MACI/MACC*/
2602 if (OP1 == 0) { /*LDINC/LDDEC*/
2603 op = MAC16_NONE;
2604 } else {
2605 RESERVED();
2606 }
2607 } else if (op != MAC16_MULA) { /*MULA.*.*.LDINC/LDDEC*/
2608 RESERVED();
2609 }
2610 break;
2611
2612 case 2: /*MACD?/MACA?*/
2613 if (op == MAC16_UMUL && OP2 != 7) { /*UMUL only in MACAA*/
2614 RESERVED();
2615 }
2616 break;
2617 }
2618
2619 if (op != MAC16_NONE) {
2620 if (!is_m1_sr && !gen_window_check1(dc, RRR_S)) {
2621 break;
2622 }
2623 if (!is_m2_sr && !gen_window_check1(dc, RRR_T)) {
2624 break;
2625 }
2626 }
2627
2628 if (ld_offset && !gen_window_check1(dc, RRR_S)) {
2629 break;
2630 }
2631
2632 {
2633 TCGv_i32 vaddr = tcg_temp_new_i32();
2634 TCGv_i32 mem32 = tcg_temp_new_i32();
2635
2636 if (ld_offset) {
2637 tcg_gen_addi_i32(vaddr, cpu_R[RRR_S], ld_offset);
2638 gen_load_store_alignment(dc, 2, vaddr, false);
2639 tcg_gen_qemu_ld32u(mem32, vaddr, dc->cring);
2640 }
2641 if (op != MAC16_NONE) {
2642 TCGv_i32 m1 = gen_mac16_m(
2643 is_m1_sr ? cpu_SR[MR + RRR_X] : cpu_R[RRR_S],
2644 OP1 & 1, op == MAC16_UMUL);
2645 TCGv_i32 m2 = gen_mac16_m(
2646 is_m2_sr ? cpu_SR[MR + 2 + RRR_Y] : cpu_R[RRR_T],
2647 OP1 & 2, op == MAC16_UMUL);
2648
2649 if (op == MAC16_MUL || op == MAC16_UMUL) {
2650 tcg_gen_mul_i32(cpu_SR[ACCLO], m1, m2);
2651 if (op == MAC16_UMUL) {
2652 tcg_gen_movi_i32(cpu_SR[ACCHI], 0);
2653 } else {
2654 tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
2655 }
2656 } else {
2657 TCGv_i32 lo = tcg_temp_new_i32();
2658 TCGv_i32 hi = tcg_temp_new_i32();
2659
2660 tcg_gen_mul_i32(lo, m1, m2);
2661 tcg_gen_sari_i32(hi, lo, 31);
2662 if (op == MAC16_MULA) {
2663 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2664 cpu_SR[ACCLO], cpu_SR[ACCHI],
2665 lo, hi);
2666 } else {
2667 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
2668 cpu_SR[ACCLO], cpu_SR[ACCHI],
2669 lo, hi);
2670 }
2671 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
2672
2673 tcg_temp_free_i32(lo);
2674 tcg_temp_free_i32(hi);
2675 }
2676 tcg_temp_free(m1);
2677 tcg_temp_free(m2);
2678 }
2679 if (ld_offset) {
2680 tcg_gen_mov_i32(cpu_R[RRR_S], vaddr);
2681 tcg_gen_mov_i32(cpu_SR[MR + RRR_W], mem32);
2682 }
2683 tcg_temp_free(vaddr);
2684 tcg_temp_free(mem32);
2685 }
2686 }
2687 break;
2688
2689 case 5: /*CALLN*/
2690 switch (CALL_N) {
2691 case 0: /*CALL0*/
2692 tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
2693 gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2694 break;
2695
2696 case 1: /*CALL4w*/
2697 case 2: /*CALL8w*/
2698 case 3: /*CALL12w*/
2699 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2700 if (gen_window_check1(dc, CALL_N << 2)) {
2701 gen_callwi(dc, CALL_N,
2702 (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
2703 }
2704 break;
2705 }
2706 break;
2707
2708 case 6: /*SI*/
2709 switch (CALL_N) {
2710 case 0: /*J*/
2711 gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
2712 break;
2713
2714 case 1: /*BZ*/
2715 if (gen_window_check1(dc, BRI12_S)) {
2716 static const TCGCond cond[] = {
2717 TCG_COND_EQ, /*BEQZ*/
2718 TCG_COND_NE, /*BNEZ*/
2719 TCG_COND_LT, /*BLTZ*/
2720 TCG_COND_GE, /*BGEZ*/
2721 };
2722
2723 gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
2724 4 + BRI12_IMM12_SE);
2725 }
2726 break;
2727
2728 case 2: /*BI0*/
2729 if (gen_window_check1(dc, BRI8_S)) {
2730 static const TCGCond cond[] = {
2731 TCG_COND_EQ, /*BEQI*/
2732 TCG_COND_NE, /*BNEI*/
2733 TCG_COND_LT, /*BLTI*/
2734 TCG_COND_GE, /*BGEI*/
2735 };
2736
2737 gen_brcondi(dc, cond[BRI8_M & 3],
2738 cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
2739 }
2740 break;
2741
2742 case 3: /*BI1*/
2743 switch (BRI8_M) {
2744 case 0: /*ENTRYw*/
2745 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2746 {
2747 TCGv_i32 pc = tcg_const_i32(dc->pc);
2748 TCGv_i32 s = tcg_const_i32(BRI12_S);
2749 TCGv_i32 imm = tcg_const_i32(BRI12_IMM12);
2750 gen_advance_ccount(dc);
2751 gen_helper_entry(cpu_env, pc, s, imm);
2752 tcg_temp_free(imm);
2753 tcg_temp_free(s);
2754 tcg_temp_free(pc);
2755 /* This can change tb->flags, so exit tb */
2756 gen_jumpi_check_loop_end(dc, -1);
2757 }
2758 break;
2759
2760 case 1: /*B1*/
2761 switch (BRI8_R) {
2762 case 0: /*BFp*/
2763 case 1: /*BTp*/
2764 HAS_OPTION(XTENSA_OPTION_BOOLEAN);
2765 {
2766 TCGv_i32 tmp = tcg_temp_new_i32();
2767 tcg_gen_andi_i32(tmp, cpu_SR[BR], 1 << RRI8_S);
2768 gen_brcondi(dc,
2769 BRI8_R == 1 ? TCG_COND_NE : TCG_COND_EQ,
2770 tmp, 0, 4 + RRI8_IMM8_SE);
2771 tcg_temp_free(tmp);
2772 }
2773 break;
2774
2775 case 8: /*LOOP*/
2776 case 9: /*LOOPNEZ*/
2777 case 10: /*LOOPGTZ*/
2778 HAS_OPTION(XTENSA_OPTION_LOOP);
2779 if (gen_window_check1(dc, RRI8_S)) {
2780 uint32_t lend = dc->pc + RRI8_IMM8 + 4;
2781 TCGv_i32 tmp = tcg_const_i32(lend);
2782
2783 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[RRI8_S], 1);
2784 tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc);
2785 gen_helper_wsr_lend(cpu_env, tmp);
2786 tcg_temp_free(tmp);
2787
2788 if (BRI8_R > 8) {
2789 TCGLabel *label = gen_new_label();
2790 tcg_gen_brcondi_i32(
2791 BRI8_R == 9 ? TCG_COND_NE : TCG_COND_GT,
2792 cpu_R[RRI8_S], 0, label);
2793 gen_jumpi(dc, lend, 1);
2794 gen_set_label(label);
2795 }
2796
2797 gen_jumpi(dc, dc->next_pc, 0);
2798 }
2799 break;
2800
2801 default: /*reserved*/
2802 RESERVED();
2803 break;
2804
2805 }
2806 break;
2807
2808 case 2: /*BLTUI*/
2809 case 3: /*BGEUI*/
2810 if (gen_window_check1(dc, BRI8_S)) {
2811 gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
2812 cpu_R[BRI8_S], B4CONSTU[BRI8_R],
2813 4 + BRI8_IMM8_SE);
2814 }
2815 break;
2816 }
2817 break;
2818
2819 }
2820 break;
2821
2822 case 7: /*B*/
2823 {
2824 TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
2825
2826 switch (RRI8_R & 7) {
2827 case 0: /*BNONE*/ /*BANY*/
2828 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2829 TCGv_i32 tmp = tcg_temp_new_i32();
2830 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2831 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2832 tcg_temp_free(tmp);
2833 }
2834 break;
2835
2836 case 1: /*BEQ*/ /*BNE*/
2837 case 2: /*BLT*/ /*BGE*/
2838 case 3: /*BLTU*/ /*BGEU*/
2839 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2840 static const TCGCond cond[] = {
2841 [1] = TCG_COND_EQ,
2842 [2] = TCG_COND_LT,
2843 [3] = TCG_COND_LTU,
2844 [9] = TCG_COND_NE,
2845 [10] = TCG_COND_GE,
2846 [11] = TCG_COND_GEU,
2847 };
2848 gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
2849 4 + RRI8_IMM8_SE);
2850 }
2851 break;
2852
2853 case 4: /*BALL*/ /*BNALL*/
2854 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2855 TCGv_i32 tmp = tcg_temp_new_i32();
2856 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
2857 gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
2858 4 + RRI8_IMM8_SE);
2859 tcg_temp_free(tmp);
2860 }
2861 break;
2862
2863 case 5: /*BBC*/ /*BBS*/
2864 if (gen_window_check2(dc, RRI8_S, RRI8_T)) {
2865 #ifdef TARGET_WORDS_BIGENDIAN
2866 TCGv_i32 bit = tcg_const_i32(0x80000000);
2867 #else
2868 TCGv_i32 bit = tcg_const_i32(0x00000001);
2869 #endif
2870 TCGv_i32 tmp = tcg_temp_new_i32();
2871 tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
2872 #ifdef TARGET_WORDS_BIGENDIAN
2873 tcg_gen_shr_i32(bit, bit, tmp);
2874 #else
2875 tcg_gen_shl_i32(bit, bit, tmp);
2876 #endif
2877 tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
2878 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2879 tcg_temp_free(tmp);
2880 tcg_temp_free(bit);
2881 }
2882 break;
2883
2884 case 6: /*BBCI*/ /*BBSI*/
2885 case 7:
2886 if (gen_window_check1(dc, RRI8_S)) {
2887 TCGv_i32 tmp = tcg_temp_new_i32();
2888 tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
2889 #ifdef TARGET_WORDS_BIGENDIAN
2890 0x80000000 >> (((RRI8_R & 1) << 4) | RRI8_T));
2891 #else
2892 0x00000001 << (((RRI8_R & 1) << 4) | RRI8_T));
2893 #endif
2894 gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
2895 tcg_temp_free(tmp);
2896 }
2897 break;
2898
2899 }
2900 }
2901 break;
2902
2903 #define gen_narrow_load_store(type) do { \
2904 if (gen_window_check2(dc, RRRN_S, RRRN_T)) { \
2905 TCGv_i32 addr = tcg_temp_new_i32(); \
2906 tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
2907 gen_load_store_alignment(dc, 2, addr, false); \
2908 tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, dc->cring); \
2909 tcg_temp_free(addr); \
2910 } \
2911 } while (0)
2912
2913 case 8: /*L32I.Nn*/
2914 gen_narrow_load_store(ld32u);
2915 break;
2916
2917 case 9: /*S32I.Nn*/
2918 gen_narrow_load_store(st32);
2919 break;
2920 #undef gen_narrow_load_store
2921
2922 case 10: /*ADD.Nn*/
2923 if (gen_window_check3(dc, RRRN_R, RRRN_S, RRRN_T)) {
2924 tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
2925 }
2926 break;
2927
2928 case 11: /*ADDI.Nn*/
2929 if (gen_window_check2(dc, RRRN_R, RRRN_S)) {
2930 tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S],
2931 RRRN_T ? RRRN_T : -1);
2932 }
2933 break;
2934
2935 case 12: /*ST2n*/
2936 if (!gen_window_check1(dc, RRRN_S)) {
2937 break;
2938 }
2939 if (RRRN_T < 8) { /*MOVI.Nn*/
2940 tcg_gen_movi_i32(cpu_R[RRRN_S],
2941 RRRN_R | (RRRN_T << 4) |
2942 ((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
2943 } else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
2944 TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
2945
2946 gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
2947 4 + (RRRN_R | ((RRRN_T & 3) << 4)));
2948 }
2949 break;
2950
2951 case 13: /*ST3n*/
2952 switch (RRRN_R) {
2953 case 0: /*MOV.Nn*/
2954 if (gen_window_check2(dc, RRRN_S, RRRN_T)) {
2955 tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
2956 }
2957 break;
2958
2959 case 15: /*S3*/
2960 switch (RRRN_T) {
2961 case 0: /*RET.Nn*/
2962 gen_jump(dc, cpu_R[0]);
2963 break;
2964
2965 case 1: /*RETW.Nn*/
2966 HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
2967 {
2968 TCGv_i32 tmp = tcg_const_i32(dc->pc);
2969 gen_advance_ccount(dc);
2970 gen_helper_retw(tmp, cpu_env, tmp);
2971 gen_jump(dc, tmp);
2972 tcg_temp_free(tmp);
2973 }
2974 break;
2975
2976 case 2: /*BREAK.Nn*/
2977 HAS_OPTION(XTENSA_OPTION_DEBUG);
2978 if (dc->debug) {
2979 gen_debug_exception(dc, DEBUGCAUSE_BN);
2980 }
2981 break;
2982
2983 case 3: /*NOP.Nn*/
2984 break;
2985
2986 case 6: /*ILL.Nn*/
2987 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
2988 break;
2989
2990 default: /*reserved*/
2991 RESERVED();
2992 break;
2993 }
2994 break;
2995
2996 default: /*reserved*/
2997 RESERVED();
2998 break;
2999 }
3000 break;
3001
3002 default: /*reserved*/
3003 RESERVED();
3004 break;
3005 }
3006
3007 if (dc->is_jmp == DISAS_NEXT) {
3008 gen_check_loop_end(dc, 0);
3009 }
3010 dc->pc = dc->next_pc;
3011
3012 return;
3013
3014 invalid_opcode:
3015 qemu_log_mask(LOG_GUEST_ERROR, "INVALID(pc = %08x)\n", dc->pc);
3016 gen_exception_cause(dc, ILLEGAL_INSTRUCTION_CAUSE);
3017 #undef HAS_OPTION
3018 }
3019
3020 static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc)
3021 {
3022 uint8_t b0 = cpu_ldub_code(env, dc->pc);
3023 return xtensa_op0_insn_len(OP0);
3024 }
3025
3026 static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc)
3027 {
3028 unsigned i;
3029
3030 for (i = 0; i < dc->config->nibreak; ++i) {
3031 if ((env->sregs[IBREAKENABLE] & (1 << i)) &&
3032 env->sregs[IBREAKA + i] == dc->pc) {
3033 gen_debug_exception(dc, DEBUGCAUSE_IB);
3034 break;
3035 }
3036 }
3037 }
3038
3039 void gen_intermediate_code(CPUXtensaState *env, TranslationBlock *tb)
3040 {
3041 XtensaCPU *cpu = xtensa_env_get_cpu(env);
3042 CPUState *cs = CPU(cpu);
3043 DisasContext dc;
3044 int insn_count = 0;
3045 int max_insns = tb->cflags & CF_COUNT_MASK;
3046 uint32_t pc_start = tb->pc;
3047 uint32_t next_page_start =
3048 (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3049
3050 if (max_insns == 0) {
3051 max_insns = CF_COUNT_MASK;
3052 }
3053 if (max_insns > TCG_MAX_INSNS) {
3054 max_insns = TCG_MAX_INSNS;
3055 }
3056
3057 dc.config = env->config;
3058 dc.singlestep_enabled = cs->singlestep_enabled;
3059 dc.tb = tb;
3060 dc.pc = pc_start;
3061 dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK;
3062 dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring;
3063 dc.lbeg = env->sregs[LBEG];
3064 dc.lend = env->sregs[LEND];
3065 dc.is_jmp = DISAS_NEXT;
3066 dc.ccount_delta = 0;
3067 dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG;
3068 dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT;
3069 dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >>
3070 XTENSA_TBFLAG_CPENABLE_SHIFT;
3071 dc.window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >>
3072 XTENSA_TBFLAG_WINDOW_SHIFT);
3073
3074 init_litbase(&dc);
3075 init_sar_tracker(&dc);
3076 if (dc.icount) {
3077 dc.next_icount = tcg_temp_local_new_i32();
3078 }
3079
3080 gen_tb_start(tb);
3081
3082 if (tb->flags & XTENSA_TBFLAG_EXCEPTION) {
3083 tcg_gen_movi_i32(cpu_pc, dc.pc);
3084 gen_exception(&dc, EXCP_DEBUG);
3085 }
3086
3087 do {
3088 tcg_gen_insn_start(dc.pc);
3089 ++insn_count;
3090
3091 ++dc.ccount_delta;
3092
3093 if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) {
3094 tcg_gen_movi_i32(cpu_pc, dc.pc);
3095 gen_exception(&dc, EXCP_DEBUG);
3096 dc.is_jmp = DISAS_UPDATE;
3097 /* The address covered by the breakpoint must be included in
3098 [tb->pc, tb->pc + tb->size) in order to for it to be
3099 properly cleared -- thus we increment the PC here so that
3100 the logic setting tb->size below does the right thing. */
3101 dc.pc += 2;
3102 break;
3103 }
3104
3105 if (insn_count == max_insns && (tb->cflags & CF_LAST_IO)) {
3106 gen_io_start();
3107 }
3108
3109 if (dc.icount) {
3110 TCGLabel *label = gen_new_label();
3111
3112 tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1);
3113 tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label);
3114 tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]);
3115 if (dc.debug) {
3116 gen_debug_exception(&dc, DEBUGCAUSE_IC);
3117 }
3118 gen_set_label(label);
3119 }
3120
3121 if (dc.debug) {
3122 gen_ibreak_check(env, &dc);
3123 }
3124
3125 disas_xtensa_insn(env, &dc);
3126 if (dc.icount) {
3127 tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);
3128 }
3129 if (cs->singlestep_enabled) {
3130 tcg_gen_movi_i32(cpu_pc, dc.pc);
3131 gen_exception(&dc, EXCP_DEBUG);
3132 break;
3133 }
3134 } while (dc.is_jmp == DISAS_NEXT &&
3135 insn_count < max_insns &&
3136 dc.pc < next_page_start &&
3137 dc.pc + xtensa_insn_len(env, &dc) <= next_page_start &&
3138 !tcg_op_buf_full());
3139
3140 reset_litbase(&dc);
3141 reset_sar_tracker(&dc);
3142 if (dc.icount) {
3143 tcg_temp_free(dc.next_icount);
3144 }
3145
3146 if (tb->cflags & CF_LAST_IO) {
3147 gen_io_end();
3148 }
3149
3150 if (dc.is_jmp == DISAS_NEXT) {
3151 gen_jumpi(&dc, dc.pc, 0);
3152 }
3153 gen_tb_end(tb, insn_count);
3154
3155 #ifdef DEBUG_DISAS
3156 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3157 qemu_log("----------------\n");
3158 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3159 log_target_disas(cs, pc_start, dc.pc - pc_start, 0);
3160 qemu_log("\n");
3161 }
3162 #endif
3163 tb->size = dc.pc - pc_start;
3164 tb->icount = insn_count;
3165 }
3166
3167 void xtensa_cpu_dump_state(CPUState *cs, FILE *f,
3168 fprintf_function cpu_fprintf, int flags)
3169 {
3170 XtensaCPU *cpu = XTENSA_CPU(cs);
3171 CPUXtensaState *env = &cpu->env;
3172 int i, j;
3173
3174 cpu_fprintf(f, "PC=%08x\n\n", env->pc);
3175
3176 for (i = j = 0; i < 256; ++i) {
3177 if (xtensa_option_bits_enabled(env->config, sregnames[i].opt_bits)) {
3178 cpu_fprintf(f, "%12s=%08x%c", sregnames[i].name, env->sregs[i],
3179 (j++ % 4) == 3 ? '\n' : ' ');