virtio-scsi: suppress virtqueue kick during processing
[qemu.git] / target / arm / cpu.c
1 /*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/error-report.h"
23 #include "qapi/error.h"
24 #include "cpu.h"
25 #include "internals.h"
26 #include "qemu-common.h"
27 #include "exec/exec-all.h"
28 #include "hw/qdev-properties.h"
29 #if !defined(CONFIG_USER_ONLY)
30 #include "hw/loader.h"
31 #endif
32 #include "hw/arm/arm.h"
33 #include "sysemu/sysemu.h"
34 #include "sysemu/kvm.h"
35 #include "kvm_arm.h"
36
37 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
38 {
39 ARMCPU *cpu = ARM_CPU(cs);
40
41 cpu->env.regs[15] = value;
42 }
43
44 static bool arm_cpu_has_work(CPUState *cs)
45 {
46 ARMCPU *cpu = ARM_CPU(cs);
47
48 return !cpu->powered_off
49 && cs->interrupt_request &
50 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
51 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
52 | CPU_INTERRUPT_EXITTB);
53 }
54
55 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
56 void *opaque)
57 {
58 /* We currently only support registering a single hook function */
59 assert(!cpu->el_change_hook);
60 cpu->el_change_hook = hook;
61 cpu->el_change_hook_opaque = opaque;
62 }
63
64 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
65 {
66 /* Reset a single ARMCPRegInfo register */
67 ARMCPRegInfo *ri = value;
68 ARMCPU *cpu = opaque;
69
70 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
71 return;
72 }
73
74 if (ri->resetfn) {
75 ri->resetfn(&cpu->env, ri);
76 return;
77 }
78
79 /* A zero offset is never possible as it would be regs[0]
80 * so we use it to indicate that reset is being handled elsewhere.
81 * This is basically only used for fields in non-core coprocessors
82 * (like the pxa2xx ones).
83 */
84 if (!ri->fieldoffset) {
85 return;
86 }
87
88 if (cpreg_field_is_64bit(ri)) {
89 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
90 } else {
91 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
92 }
93 }
94
95 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
96 {
97 /* Purely an assertion check: we've already done reset once,
98 * so now check that running the reset for the cpreg doesn't
99 * change its value. This traps bugs where two different cpregs
100 * both try to reset the same state field but to different values.
101 */
102 ARMCPRegInfo *ri = value;
103 ARMCPU *cpu = opaque;
104 uint64_t oldvalue, newvalue;
105
106 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
107 return;
108 }
109
110 oldvalue = read_raw_cp_reg(&cpu->env, ri);
111 cp_reg_reset(key, value, opaque);
112 newvalue = read_raw_cp_reg(&cpu->env, ri);
113 assert(oldvalue == newvalue);
114 }
115
116 /* CPUClass::reset() */
117 static void arm_cpu_reset(CPUState *s)
118 {
119 ARMCPU *cpu = ARM_CPU(s);
120 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
121 CPUARMState *env = &cpu->env;
122
123 acc->parent_reset(s);
124
125 memset(env, 0, offsetof(CPUARMState, features));
126 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
127 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
128
129 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
130 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
131 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
132 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
133
134 cpu->powered_off = cpu->start_powered_off;
135 s->halted = cpu->start_powered_off;
136
137 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
138 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
139 }
140
141 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
142 /* 64 bit CPUs always start in 64 bit mode */
143 env->aarch64 = 1;
144 #if defined(CONFIG_USER_ONLY)
145 env->pstate = PSTATE_MODE_EL0t;
146 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
147 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
148 /* and to the FP/Neon instructions */
149 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
150 #else
151 /* Reset into the highest available EL */
152 if (arm_feature(env, ARM_FEATURE_EL3)) {
153 env->pstate = PSTATE_MODE_EL3h;
154 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
155 env->pstate = PSTATE_MODE_EL2h;
156 } else {
157 env->pstate = PSTATE_MODE_EL1h;
158 }
159 env->pc = cpu->rvbar;
160 #endif
161 } else {
162 #if defined(CONFIG_USER_ONLY)
163 /* Userspace expects access to cp10 and cp11 for FP/Neon */
164 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
165 #endif
166 }
167
168 #if defined(CONFIG_USER_ONLY)
169 env->uncached_cpsr = ARM_CPU_MODE_USR;
170 /* For user mode we must enable access to coprocessors */
171 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
172 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
173 env->cp15.c15_cpar = 3;
174 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
175 env->cp15.c15_cpar = 1;
176 }
177 #else
178 /* SVC mode with interrupts disabled. */
179 env->uncached_cpsr = ARM_CPU_MODE_SVC;
180 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
181 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
182 * clear at reset. Initial SP and PC are loaded from ROM.
183 */
184 if (IS_M(env)) {
185 uint32_t initial_msp; /* Loaded from 0x0 */
186 uint32_t initial_pc; /* Loaded from 0x4 */
187 uint8_t *rom;
188
189 env->daif &= ~PSTATE_I;
190 rom = rom_ptr(0);
191 if (rom) {
192 /* Address zero is covered by ROM which hasn't yet been
193 * copied into physical memory.
194 */
195 initial_msp = ldl_p(rom);
196 initial_pc = ldl_p(rom + 4);
197 } else {
198 /* Address zero not covered by a ROM blob, or the ROM blob
199 * is in non-modifiable memory and this is a second reset after
200 * it got copied into memory. In the latter case, rom_ptr
201 * will return a NULL pointer and we should use ldl_phys instead.
202 */
203 initial_msp = ldl_phys(s->as, 0);
204 initial_pc = ldl_phys(s->as, 4);
205 }
206
207 env->regs[13] = initial_msp & 0xFFFFFFFC;
208 env->regs[15] = initial_pc & ~1;
209 env->thumb = initial_pc & 1;
210 }
211
212 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
213 * executing as AArch32 then check if highvecs are enabled and
214 * adjust the PC accordingly.
215 */
216 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
217 env->regs[15] = 0xFFFF0000;
218 }
219
220 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
221 #endif
222 set_flush_to_zero(1, &env->vfp.standard_fp_status);
223 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
224 set_default_nan_mode(1, &env->vfp.standard_fp_status);
225 set_float_detect_tininess(float_tininess_before_rounding,
226 &env->vfp.fp_status);
227 set_float_detect_tininess(float_tininess_before_rounding,
228 &env->vfp.standard_fp_status);
229 tlb_flush(s, 1);
230
231 #ifndef CONFIG_USER_ONLY
232 if (kvm_enabled()) {
233 kvm_arm_reset_vcpu(cpu);
234 }
235 #endif
236
237 hw_breakpoint_update_all(cpu);
238 hw_watchpoint_update_all(cpu);
239 }
240
241 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
242 {
243 CPUClass *cc = CPU_GET_CLASS(cs);
244 CPUARMState *env = cs->env_ptr;
245 uint32_t cur_el = arm_current_el(env);
246 bool secure = arm_is_secure(env);
247 uint32_t target_el;
248 uint32_t excp_idx;
249 bool ret = false;
250
251 if (interrupt_request & CPU_INTERRUPT_FIQ) {
252 excp_idx = EXCP_FIQ;
253 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
254 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
255 cs->exception_index = excp_idx;
256 env->exception.target_el = target_el;
257 cc->do_interrupt(cs);
258 ret = true;
259 }
260 }
261 if (interrupt_request & CPU_INTERRUPT_HARD) {
262 excp_idx = EXCP_IRQ;
263 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
264 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
265 cs->exception_index = excp_idx;
266 env->exception.target_el = target_el;
267 cc->do_interrupt(cs);
268 ret = true;
269 }
270 }
271 if (interrupt_request & CPU_INTERRUPT_VIRQ) {
272 excp_idx = EXCP_VIRQ;
273 target_el = 1;
274 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
275 cs->exception_index = excp_idx;
276 env->exception.target_el = target_el;
277 cc->do_interrupt(cs);
278 ret = true;
279 }
280 }
281 if (interrupt_request & CPU_INTERRUPT_VFIQ) {
282 excp_idx = EXCP_VFIQ;
283 target_el = 1;
284 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
285 cs->exception_index = excp_idx;
286 env->exception.target_el = target_el;
287 cc->do_interrupt(cs);
288 ret = true;
289 }
290 }
291
292 return ret;
293 }
294
295 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
296 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
297 {
298 CPUClass *cc = CPU_GET_CLASS(cs);
299 ARMCPU *cpu = ARM_CPU(cs);
300 CPUARMState *env = &cpu->env;
301 bool ret = false;
302
303
304 if (interrupt_request & CPU_INTERRUPT_FIQ
305 && !(env->daif & PSTATE_F)) {
306 cs->exception_index = EXCP_FIQ;
307 cc->do_interrupt(cs);
308 ret = true;
309 }
310 /* ARMv7-M interrupt return works by loading a magic value
311 * into the PC. On real hardware the load causes the
312 * return to occur. The qemu implementation performs the
313 * jump normally, then does the exception return when the
314 * CPU tries to execute code at the magic address.
315 * This will cause the magic PC value to be pushed to
316 * the stack if an interrupt occurred at the wrong time.
317 * We avoid this by disabling interrupts when
318 * pc contains a magic address.
319 */
320 if (interrupt_request & CPU_INTERRUPT_HARD
321 && !(env->daif & PSTATE_I)
322 && (env->regs[15] < 0xfffffff0)) {
323 cs->exception_index = EXCP_IRQ;
324 cc->do_interrupt(cs);
325 ret = true;
326 }
327 return ret;
328 }
329 #endif
330
331 #ifndef CONFIG_USER_ONLY
332 static void arm_cpu_set_irq(void *opaque, int irq, int level)
333 {
334 ARMCPU *cpu = opaque;
335 CPUARMState *env = &cpu->env;
336 CPUState *cs = CPU(cpu);
337 static const int mask[] = {
338 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
339 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
340 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
341 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
342 };
343
344 switch (irq) {
345 case ARM_CPU_VIRQ:
346 case ARM_CPU_VFIQ:
347 assert(arm_feature(env, ARM_FEATURE_EL2));
348 /* fall through */
349 case ARM_CPU_IRQ:
350 case ARM_CPU_FIQ:
351 if (level) {
352 cpu_interrupt(cs, mask[irq]);
353 } else {
354 cpu_reset_interrupt(cs, mask[irq]);
355 }
356 break;
357 default:
358 g_assert_not_reached();
359 }
360 }
361
362 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
363 {
364 #ifdef CONFIG_KVM
365 ARMCPU *cpu = opaque;
366 CPUState *cs = CPU(cpu);
367 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
368
369 switch (irq) {
370 case ARM_CPU_IRQ:
371 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
372 break;
373 case ARM_CPU_FIQ:
374 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
375 break;
376 default:
377 g_assert_not_reached();
378 }
379 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
380 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
381 #endif
382 }
383
384 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
385 {
386 ARMCPU *cpu = ARM_CPU(cs);
387 CPUARMState *env = &cpu->env;
388
389 cpu_synchronize_state(cs);
390 return arm_cpu_data_is_big_endian(env);
391 }
392
393 #endif
394
395 static inline void set_feature(CPUARMState *env, int feature)
396 {
397 env->features |= 1ULL << feature;
398 }
399
400 static inline void unset_feature(CPUARMState *env, int feature)
401 {
402 env->features &= ~(1ULL << feature);
403 }
404
405 static int
406 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
407 {
408 return print_insn_arm(pc | 1, info);
409 }
410
411 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
412 {
413 ARMCPU *ac = ARM_CPU(cpu);
414 CPUARMState *env = &ac->env;
415
416 if (is_a64(env)) {
417 /* We might not be compiled with the A64 disassembler
418 * because it needs a C++ compiler. Leave print_insn
419 * unset in this case to use the caller default behaviour.
420 */
421 #if defined(CONFIG_ARM_A64_DIS)
422 info->print_insn = print_insn_arm_a64;
423 #endif
424 } else if (env->thumb) {
425 info->print_insn = print_insn_thumb1;
426 } else {
427 info->print_insn = print_insn_arm;
428 }
429 if (bswap_code(arm_sctlr_b(env))) {
430 #ifdef TARGET_WORDS_BIGENDIAN
431 info->endian = BFD_ENDIAN_LITTLE;
432 #else
433 info->endian = BFD_ENDIAN_BIG;
434 #endif
435 }
436 }
437
438 static void arm_cpu_initfn(Object *obj)
439 {
440 CPUState *cs = CPU(obj);
441 ARMCPU *cpu = ARM_CPU(obj);
442 static bool inited;
443
444 cs->env_ptr = &cpu->env;
445 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
446 g_free, g_free);
447
448 #ifndef CONFIG_USER_ONLY
449 /* Our inbound IRQ and FIQ lines */
450 if (kvm_enabled()) {
451 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
452 * the same interface as non-KVM CPUs.
453 */
454 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
455 } else {
456 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
457 }
458
459 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
460 arm_gt_ptimer_cb, cpu);
461 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
462 arm_gt_vtimer_cb, cpu);
463 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
464 arm_gt_htimer_cb, cpu);
465 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
466 arm_gt_stimer_cb, cpu);
467 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
468 ARRAY_SIZE(cpu->gt_timer_outputs));
469 #endif
470
471 /* DTB consumers generally don't in fact care what the 'compatible'
472 * string is, so always provide some string and trust that a hypothetical
473 * picky DTB consumer will also provide a helpful error message.
474 */
475 cpu->dtb_compatible = "qemu,unknown";
476 cpu->psci_version = 1; /* By default assume PSCI v0.1 */
477 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
478
479 if (tcg_enabled()) {
480 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
481 if (!inited) {
482 inited = true;
483 arm_translate_init();
484 }
485 }
486 }
487
488 static Property arm_cpu_reset_cbar_property =
489 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
490
491 static Property arm_cpu_reset_hivecs_property =
492 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
493
494 static Property arm_cpu_rvbar_property =
495 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
496
497 static Property arm_cpu_has_el3_property =
498 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
499
500 /* use property name "pmu" to match other archs and virt tools */
501 static Property arm_cpu_has_pmu_property =
502 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
503
504 static Property arm_cpu_has_mpu_property =
505 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
506
507 static Property arm_cpu_pmsav7_dregion_property =
508 DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16);
509
510 static void arm_cpu_post_init(Object *obj)
511 {
512 ARMCPU *cpu = ARM_CPU(obj);
513
514 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
515 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
516 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
517 &error_abort);
518 }
519
520 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
521 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
522 &error_abort);
523 }
524
525 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
526 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
527 &error_abort);
528 }
529
530 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
531 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
532 * prevent "has_el3" from existing on CPUs which cannot support EL3.
533 */
534 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
535 &error_abort);
536
537 #ifndef CONFIG_USER_ONLY
538 object_property_add_link(obj, "secure-memory",
539 TYPE_MEMORY_REGION,
540 (Object **)&cpu->secure_memory,
541 qdev_prop_allow_set_link_before_realize,
542 OBJ_PROP_LINK_UNREF_ON_RELEASE,
543 &error_abort);
544 #endif
545 }
546
547 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
548 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
549 &error_abort);
550 }
551
552 if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
553 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
554 &error_abort);
555 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
556 qdev_property_add_static(DEVICE(obj),
557 &arm_cpu_pmsav7_dregion_property,
558 &error_abort);
559 }
560 }
561
562 }
563
564 static void arm_cpu_finalizefn(Object *obj)
565 {
566 ARMCPU *cpu = ARM_CPU(obj);
567 g_hash_table_destroy(cpu->cp_regs);
568 }
569
570 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
571 {
572 CPUState *cs = CPU(dev);
573 ARMCPU *cpu = ARM_CPU(dev);
574 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
575 CPUARMState *env = &cpu->env;
576 int pagebits;
577 Error *local_err = NULL;
578
579 cpu_exec_realizefn(cs, &local_err);
580 if (local_err != NULL) {
581 error_propagate(errp, local_err);
582 return;
583 }
584
585 /* Some features automatically imply others: */
586 if (arm_feature(env, ARM_FEATURE_V8)) {
587 set_feature(env, ARM_FEATURE_V7);
588 set_feature(env, ARM_FEATURE_ARM_DIV);
589 set_feature(env, ARM_FEATURE_LPAE);
590 }
591 if (arm_feature(env, ARM_FEATURE_V7)) {
592 set_feature(env, ARM_FEATURE_VAPA);
593 set_feature(env, ARM_FEATURE_THUMB2);
594 set_feature(env, ARM_FEATURE_MPIDR);
595 if (!arm_feature(env, ARM_FEATURE_M)) {
596 set_feature(env, ARM_FEATURE_V6K);
597 } else {
598 set_feature(env, ARM_FEATURE_V6);
599 }
600
601 /* Always define VBAR for V7 CPUs even if it doesn't exist in
602 * non-EL3 configs. This is needed by some legacy boards.
603 */
604 set_feature(env, ARM_FEATURE_VBAR);
605 }
606 if (arm_feature(env, ARM_FEATURE_V6K)) {
607 set_feature(env, ARM_FEATURE_V6);
608 set_feature(env, ARM_FEATURE_MVFR);
609 }
610 if (arm_feature(env, ARM_FEATURE_V6)) {
611 set_feature(env, ARM_FEATURE_V5);
612 if (!arm_feature(env, ARM_FEATURE_M)) {
613 set_feature(env, ARM_FEATURE_AUXCR);
614 }
615 }
616 if (arm_feature(env, ARM_FEATURE_V5)) {
617 set_feature(env, ARM_FEATURE_V4T);
618 }
619 if (arm_feature(env, ARM_FEATURE_M)) {
620 set_feature(env, ARM_FEATURE_THUMB_DIV);
621 }
622 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
623 set_feature(env, ARM_FEATURE_THUMB_DIV);
624 }
625 if (arm_feature(env, ARM_FEATURE_VFP4)) {
626 set_feature(env, ARM_FEATURE_VFP3);
627 set_feature(env, ARM_FEATURE_VFP_FP16);
628 }
629 if (arm_feature(env, ARM_FEATURE_VFP3)) {
630 set_feature(env, ARM_FEATURE_VFP);
631 }
632 if (arm_feature(env, ARM_FEATURE_LPAE)) {
633 set_feature(env, ARM_FEATURE_V7MP);
634 set_feature(env, ARM_FEATURE_PXN);
635 }
636 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
637 set_feature(env, ARM_FEATURE_CBAR);
638 }
639 if (arm_feature(env, ARM_FEATURE_THUMB2) &&
640 !arm_feature(env, ARM_FEATURE_M)) {
641 set_feature(env, ARM_FEATURE_THUMB_DSP);
642 }
643
644 if (arm_feature(env, ARM_FEATURE_V7) &&
645 !arm_feature(env, ARM_FEATURE_M) &&
646 !arm_feature(env, ARM_FEATURE_MPU)) {
647 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
648 * can use 4K pages.
649 */
650 pagebits = 12;
651 } else {
652 /* For CPUs which might have tiny 1K pages, or which have an
653 * MPU and might have small region sizes, stick with 1K pages.
654 */
655 pagebits = 10;
656 }
657 if (!set_preferred_target_page_bits(pagebits)) {
658 /* This can only ever happen for hotplugging a CPU, or if
659 * the board code incorrectly creates a CPU which it has
660 * promised via minimum_page_size that it will not.
661 */
662 error_setg(errp, "This CPU requires a smaller page size than the "
663 "system is using");
664 return;
665 }
666
667 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
668 * We don't support setting cluster ID ([16..23]) (known as Aff2
669 * in later ARM ARM versions), or any of the higher affinity level fields,
670 * so these bits always RAZ.
671 */
672 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
673 uint32_t Aff1 = cs->cpu_index / ARM_DEFAULT_CPUS_PER_CLUSTER;
674 uint32_t Aff0 = cs->cpu_index % ARM_DEFAULT_CPUS_PER_CLUSTER;
675 cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0;
676 }
677
678 if (cpu->reset_hivecs) {
679 cpu->reset_sctlr |= (1 << 13);
680 }
681
682 if (!cpu->has_el3) {
683 /* If the has_el3 CPU property is disabled then we need to disable the
684 * feature.
685 */
686 unset_feature(env, ARM_FEATURE_EL3);
687
688 /* Disable the security extension feature bits in the processor feature
689 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
690 */
691 cpu->id_pfr1 &= ~0xf0;
692 cpu->id_aa64pfr0 &= ~0xf000;
693 }
694
695 if (!cpu->has_pmu || !kvm_enabled()) {
696 cpu->has_pmu = false;
697 unset_feature(env, ARM_FEATURE_PMU);
698 }
699
700 if (!arm_feature(env, ARM_FEATURE_EL2)) {
701 /* Disable the hypervisor feature bits in the processor feature
702 * registers if we don't have EL2. These are id_pfr1[15:12] and
703 * id_aa64pfr0_el1[11:8].
704 */
705 cpu->id_aa64pfr0 &= ~0xf00;
706 cpu->id_pfr1 &= ~0xf000;
707 }
708
709 if (!cpu->has_mpu) {
710 unset_feature(env, ARM_FEATURE_MPU);
711 }
712
713 if (arm_feature(env, ARM_FEATURE_MPU) &&
714 arm_feature(env, ARM_FEATURE_V7)) {
715 uint32_t nr = cpu->pmsav7_dregion;
716
717 if (nr > 0xff) {
718 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
719 return;
720 }
721
722 if (nr) {
723 env->pmsav7.drbar = g_new0(uint32_t, nr);
724 env->pmsav7.drsr = g_new0(uint32_t, nr);
725 env->pmsav7.dracr = g_new0(uint32_t, nr);
726 }
727 }
728
729 if (arm_feature(env, ARM_FEATURE_EL3)) {
730 set_feature(env, ARM_FEATURE_VBAR);
731 }
732
733 register_cp_regs_for_features(cpu);
734 arm_cpu_register_gdb_regs_for_features(cpu);
735
736 init_cpreg_list(cpu);
737
738 #ifndef CONFIG_USER_ONLY
739 if (cpu->has_el3) {
740 cs->num_ases = 2;
741 } else {
742 cs->num_ases = 1;
743 }
744
745 if (cpu->has_el3) {
746 AddressSpace *as;
747
748 if (!cpu->secure_memory) {
749 cpu->secure_memory = cs->memory;
750 }
751 as = address_space_init_shareable(cpu->secure_memory,
752 "cpu-secure-memory");
753 cpu_address_space_init(cs, as, ARMASIdx_S);
754 }
755 cpu_address_space_init(cs,
756 address_space_init_shareable(cs->memory,
757 "cpu-memory"),
758 ARMASIdx_NS);
759 #endif
760
761 qemu_init_vcpu(cs);
762 cpu_reset(cs);
763
764 acc->parent_realize(dev, errp);
765 }
766
767 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
768 {
769 ObjectClass *oc;
770 char *typename;
771 char **cpuname;
772
773 if (!cpu_model) {
774 return NULL;
775 }
776
777 cpuname = g_strsplit(cpu_model, ",", 1);
778 typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
779 oc = object_class_by_name(typename);
780 g_strfreev(cpuname);
781 g_free(typename);
782 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
783 object_class_is_abstract(oc)) {
784 return NULL;
785 }
786 return oc;
787 }
788
789 /* CPU models. These are not needed for the AArch64 linux-user build. */
790 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
791
792 static void arm926_initfn(Object *obj)
793 {
794 ARMCPU *cpu = ARM_CPU(obj);
795
796 cpu->dtb_compatible = "arm,arm926";
797 set_feature(&cpu->env, ARM_FEATURE_V5);
798 set_feature(&cpu->env, ARM_FEATURE_VFP);
799 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
800 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
801 cpu->midr = 0x41069265;
802 cpu->reset_fpsid = 0x41011090;
803 cpu->ctr = 0x1dd20d2;
804 cpu->reset_sctlr = 0x00090078;
805 }
806
807 static void arm946_initfn(Object *obj)
808 {
809 ARMCPU *cpu = ARM_CPU(obj);
810
811 cpu->dtb_compatible = "arm,arm946";
812 set_feature(&cpu->env, ARM_FEATURE_V5);
813 set_feature(&cpu->env, ARM_FEATURE_MPU);
814 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
815 cpu->midr = 0x41059461;
816 cpu->ctr = 0x0f004006;
817 cpu->reset_sctlr = 0x00000078;
818 }
819
820 static void arm1026_initfn(Object *obj)
821 {
822 ARMCPU *cpu = ARM_CPU(obj);
823
824 cpu->dtb_compatible = "arm,arm1026";
825 set_feature(&cpu->env, ARM_FEATURE_V5);
826 set_feature(&cpu->env, ARM_FEATURE_VFP);
827 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
828 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
829 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
830 cpu->midr = 0x4106a262;
831 cpu->reset_fpsid = 0x410110a0;
832 cpu->ctr = 0x1dd20d2;
833 cpu->reset_sctlr = 0x00090078;
834 cpu->reset_auxcr = 1;
835 {
836 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
837 ARMCPRegInfo ifar = {
838 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
839 .access = PL1_RW,
840 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
841 .resetvalue = 0
842 };
843 define_one_arm_cp_reg(cpu, &ifar);
844 }
845 }
846
847 static void arm1136_r2_initfn(Object *obj)
848 {
849 ARMCPU *cpu = ARM_CPU(obj);
850 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
851 * older core than plain "arm1136". In particular this does not
852 * have the v6K features.
853 * These ID register values are correct for 1136 but may be wrong
854 * for 1136_r2 (in particular r0p2 does not actually implement most
855 * of the ID registers).
856 */
857
858 cpu->dtb_compatible = "arm,arm1136";
859 set_feature(&cpu->env, ARM_FEATURE_V6);
860 set_feature(&cpu->env, ARM_FEATURE_VFP);
861 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
862 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
863 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
864 cpu->midr = 0x4107b362;
865 cpu->reset_fpsid = 0x410120b4;
866 cpu->mvfr0 = 0x11111111;
867 cpu->mvfr1 = 0x00000000;
868 cpu->ctr = 0x1dd20d2;
869 cpu->reset_sctlr = 0x00050078;
870 cpu->id_pfr0 = 0x111;
871 cpu->id_pfr1 = 0x1;
872 cpu->id_dfr0 = 0x2;
873 cpu->id_afr0 = 0x3;
874 cpu->id_mmfr0 = 0x01130003;
875 cpu->id_mmfr1 = 0x10030302;
876 cpu->id_mmfr2 = 0x01222110;
877 cpu->id_isar0 = 0x00140011;
878 cpu->id_isar1 = 0x12002111;
879 cpu->id_isar2 = 0x11231111;
880 cpu->id_isar3 = 0x01102131;
881 cpu->id_isar4 = 0x141;
882 cpu->reset_auxcr = 7;
883 }
884
885 static void arm1136_initfn(Object *obj)
886 {
887 ARMCPU *cpu = ARM_CPU(obj);
888
889 cpu->dtb_compatible = "arm,arm1136";
890 set_feature(&cpu->env, ARM_FEATURE_V6K);
891 set_feature(&cpu->env, ARM_FEATURE_V6);
892 set_feature(&cpu->env, ARM_FEATURE_VFP);
893 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
894 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
895 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
896 cpu->midr = 0x4117b363;
897 cpu->reset_fpsid = 0x410120b4;
898 cpu->mvfr0 = 0x11111111;
899 cpu->mvfr1 = 0x00000000;
900 cpu->ctr = 0x1dd20d2;
901 cpu->reset_sctlr = 0x00050078;
902 cpu->id_pfr0 = 0x111;
903 cpu->id_pfr1 = 0x1;
904 cpu->id_dfr0 = 0x2;
905 cpu->id_afr0 = 0x3;
906 cpu->id_mmfr0 = 0x01130003;
907 cpu->id_mmfr1 = 0x10030302;
908 cpu->id_mmfr2 = 0x01222110;
909 cpu->id_isar0 = 0x00140011;
910 cpu->id_isar1 = 0x12002111;
911 cpu->id_isar2 = 0x11231111;
912 cpu->id_isar3 = 0x01102131;
913 cpu->id_isar4 = 0x141;
914 cpu->reset_auxcr = 7;
915 }
916
917 static void arm1176_initfn(Object *obj)
918 {
919 ARMCPU *cpu = ARM_CPU(obj);
920
921 cpu->dtb_compatible = "arm,arm1176";
922 set_feature(&cpu->env, ARM_FEATURE_V6K);
923 set_feature(&cpu->env, ARM_FEATURE_VFP);
924 set_feature(&cpu->env, ARM_FEATURE_VAPA);
925 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
926 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
927 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
928 set_feature(&cpu->env, ARM_FEATURE_EL3);
929 cpu->midr = 0x410fb767;
930 cpu->reset_fpsid = 0x410120b5;
931 cpu->mvfr0 = 0x11111111;
932 cpu->mvfr1 = 0x00000000;
933 cpu->ctr = 0x1dd20d2;
934 cpu->reset_sctlr = 0x00050078;
935 cpu->id_pfr0 = 0x111;
936 cpu->id_pfr1 = 0x11;
937 cpu->id_dfr0 = 0x33;
938 cpu->id_afr0 = 0;
939 cpu->id_mmfr0 = 0x01130003;
940 cpu->id_mmfr1 = 0x10030302;
941 cpu->id_mmfr2 = 0x01222100;
942 cpu->id_isar0 = 0x0140011;
943 cpu->id_isar1 = 0x12002111;
944 cpu->id_isar2 = 0x11231121;
945 cpu->id_isar3 = 0x01102131;
946 cpu->id_isar4 = 0x01141;
947 cpu->reset_auxcr = 7;
948 }
949
950 static void arm11mpcore_initfn(Object *obj)
951 {
952 ARMCPU *cpu = ARM_CPU(obj);
953
954 cpu->dtb_compatible = "arm,arm11mpcore";
955 set_feature(&cpu->env, ARM_FEATURE_V6K);
956 set_feature(&cpu->env, ARM_FEATURE_VFP);
957 set_feature(&cpu->env, ARM_FEATURE_VAPA);
958 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
959 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
960 cpu->midr = 0x410fb022;
961 cpu->reset_fpsid = 0x410120b4;
962 cpu->mvfr0 = 0x11111111;
963 cpu->mvfr1 = 0x00000000;
964 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
965 cpu->id_pfr0 = 0x111;
966 cpu->id_pfr1 = 0x1;
967 cpu->id_dfr0 = 0;
968 cpu->id_afr0 = 0x2;
969 cpu->id_mmfr0 = 0x01100103;
970 cpu->id_mmfr1 = 0x10020302;
971 cpu->id_mmfr2 = 0x01222000;
972 cpu->id_isar0 = 0x00100011;
973 cpu->id_isar1 = 0x12002111;
974 cpu->id_isar2 = 0x11221011;
975 cpu->id_isar3 = 0x01102131;
976 cpu->id_isar4 = 0x141;
977 cpu->reset_auxcr = 1;
978 }
979
980 static void cortex_m3_initfn(Object *obj)
981 {
982 ARMCPU *cpu = ARM_CPU(obj);
983 set_feature(&cpu->env, ARM_FEATURE_V7);
984 set_feature(&cpu->env, ARM_FEATURE_M);
985 cpu->midr = 0x410fc231;
986 }
987
988 static void cortex_m4_initfn(Object *obj)
989 {
990 ARMCPU *cpu = ARM_CPU(obj);
991
992 set_feature(&cpu->env, ARM_FEATURE_V7);
993 set_feature(&cpu->env, ARM_FEATURE_M);
994 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
995 cpu->midr = 0x410fc240; /* r0p0 */
996 }
997 static void arm_v7m_class_init(ObjectClass *oc, void *data)
998 {
999 CPUClass *cc = CPU_CLASS(oc);
1000
1001 #ifndef CONFIG_USER_ONLY
1002 cc->do_interrupt = arm_v7m_cpu_do_interrupt;
1003 #endif
1004
1005 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
1006 }
1007
1008 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
1009 /* Dummy the TCM region regs for the moment */
1010 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1011 .access = PL1_RW, .type = ARM_CP_CONST },
1012 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1013 .access = PL1_RW, .type = ARM_CP_CONST },
1014 REGINFO_SENTINEL
1015 };
1016
1017 static void cortex_r5_initfn(Object *obj)
1018 {
1019 ARMCPU *cpu = ARM_CPU(obj);
1020
1021 set_feature(&cpu->env, ARM_FEATURE_V7);
1022 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
1023 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1024 set_feature(&cpu->env, ARM_FEATURE_V7MP);
1025 set_feature(&cpu->env, ARM_FEATURE_MPU);
1026 cpu->midr = 0x411fc153; /* r1p3 */
1027 cpu->id_pfr0 = 0x0131;
1028 cpu->id_pfr1 = 0x001;
1029 cpu->id_dfr0 = 0x010400;
1030 cpu->id_afr0 = 0x0;
1031 cpu->id_mmfr0 = 0x0210030;
1032 cpu->id_mmfr1 = 0x00000000;
1033 cpu->id_mmfr2 = 0x01200000;
1034 cpu->id_mmfr3 = 0x0211;
1035 cpu->id_isar0 = 0x2101111;
1036 cpu->id_isar1 = 0x13112111;
1037 cpu->id_isar2 = 0x21232141;
1038 cpu->id_isar3 = 0x01112131;
1039 cpu->id_isar4 = 0x0010142;
1040 cpu->id_isar5 = 0x0;
1041 cpu->mp_is_up = true;
1042 define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
1043 }
1044
1045 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
1046 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
1047 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1048 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1049 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1050 REGINFO_SENTINEL
1051 };
1052
1053 static void cortex_a8_initfn(Object *obj)
1054 {
1055 ARMCPU *cpu = ARM_CPU(obj);
1056
1057 cpu->dtb_compatible = "arm,cortex-a8";
1058 set_feature(&cpu->env, ARM_FEATURE_V7);
1059 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1060 set_feature(&cpu->env, ARM_FEATURE_NEON);
1061 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1062 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1063 set_feature(&cpu->env, ARM_FEATURE_EL3);
1064 cpu->midr = 0x410fc080;
1065 cpu->reset_fpsid = 0x410330c0;
1066 cpu->mvfr0 = 0x11110222;
1067 cpu->mvfr1 = 0x00011111;
1068 cpu->ctr = 0x82048004;
1069 cpu->reset_sctlr = 0x00c50078;
1070 cpu->id_pfr0 = 0x1031;
1071 cpu->id_pfr1 = 0x11;
1072 cpu->id_dfr0 = 0x400;
1073 cpu->id_afr0 = 0;
1074 cpu->id_mmfr0 = 0x31100003;
1075 cpu->id_mmfr1 = 0x20000000;
1076 cpu->id_mmfr2 = 0x01202000;
1077 cpu->id_mmfr3 = 0x11;
1078 cpu->id_isar0 = 0x00101111;
1079 cpu->id_isar1 = 0x12112111;
1080 cpu->id_isar2 = 0x21232031;
1081 cpu->id_isar3 = 0x11112131;
1082 cpu->id_isar4 = 0x00111142;
1083 cpu->dbgdidr = 0x15141000;
1084 cpu->clidr = (1 << 27) | (2 << 24) | 3;
1085 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
1086 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
1087 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
1088 cpu->reset_auxcr = 2;
1089 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
1090 }
1091
1092 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1093 /* power_control should be set to maximum latency. Again,
1094 * default to 0 and set by private hook
1095 */
1096 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1097 .access = PL1_RW, .resetvalue = 0,
1098 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1099 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1100 .access = PL1_RW, .resetvalue = 0,
1101 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1102 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1103 .access = PL1_RW, .resetvalue = 0,
1104 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1105 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1106 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1107 /* TLB lockdown control */
1108 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1109 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1110 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1111 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1112 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1113 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1114 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1115 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1116 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1117 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1118 REGINFO_SENTINEL
1119 };
1120
1121 static void cortex_a9_initfn(Object *obj)
1122 {
1123 ARMCPU *cpu = ARM_CPU(obj);
1124
1125 cpu->dtb_compatible = "arm,cortex-a9";
1126 set_feature(&cpu->env, ARM_FEATURE_V7);
1127 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1128 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
1129 set_feature(&cpu->env, ARM_FEATURE_NEON);
1130 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1131 set_feature(&cpu->env, ARM_FEATURE_EL3);
1132 /* Note that A9 supports the MP extensions even for
1133 * A9UP and single-core A9MP (which are both different
1134 * and valid configurations; we don't model A9UP).
1135 */
1136 set_feature(&cpu->env, ARM_FEATURE_V7MP);
1137 set_feature(&cpu->env, ARM_FEATURE_CBAR);
1138 cpu->midr = 0x410fc090;
1139 cpu->reset_fpsid = 0x41033090;
1140 cpu->mvfr0 = 0x11110222;
1141 cpu->mvfr1 = 0x01111111;
1142 cpu->ctr = 0x80038003;
1143 cpu->reset_sctlr = 0x00c50078;
1144 cpu->id_pfr0 = 0x1031;
1145 cpu->id_pfr1 = 0x11;
1146 cpu->id_dfr0 = 0x000;
1147 cpu->id_afr0 = 0;
1148 cpu->id_mmfr0 = 0x00100103;
1149 cpu->id_mmfr1 = 0x20000000;
1150 cpu->id_mmfr2 = 0x01230000;
1151 cpu->id_mmfr3 = 0x00002111;
1152 cpu->id_isar0 = 0x00101111;
1153 cpu->id_isar1 = 0x13112111;
1154 cpu->id_isar2 = 0x21232041;
1155 cpu->id_isar3 = 0x11112131;
1156 cpu->id_isar4 = 0x00111142;
1157 cpu->dbgdidr = 0x35141000;
1158 cpu->clidr = (1 << 27) | (1 << 24) | 3;
1159 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
1160 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
1161 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1162 }
1163
1164 #ifndef CONFIG_USER_ONLY
1165 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1166 {
1167 /* Linux wants the number of processors from here.
1168 * Might as well set the interrupt-controller bit too.
1169 */
1170 return ((smp_cpus - 1) << 24) | (1 << 23);
1171 }
1172 #endif
1173
1174 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1175 #ifndef CONFIG_USER_ONLY
1176 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1177 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1178 .writefn = arm_cp_write_ignore, },
1179 #endif
1180 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1181 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1182 REGINFO_SENTINEL
1183 };
1184
1185 static void cortex_a7_initfn(Object *obj)
1186 {
1187 ARMCPU *cpu = ARM_CPU(obj);
1188
1189 cpu->dtb_compatible = "arm,cortex-a7";
1190 set_feature(&cpu->env, ARM_FEATURE_V7);
1191 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1192 set_feature(&cpu->env, ARM_FEATURE_NEON);
1193 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1194 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1195 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1196 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1197 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1198 set_feature(&cpu->env, ARM_FEATURE_LPAE);
1199 set_feature(&cpu->env, ARM_FEATURE_EL3);
1200 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
1201 cpu->midr = 0x410fc075;
1202 cpu->reset_fpsid = 0x41023075;
1203 cpu->mvfr0 = 0x10110222;
1204 cpu->mvfr1 = 0x11111111;
1205 cpu->ctr = 0x84448003;
1206 cpu->reset_sctlr = 0x00c50078;
1207 cpu->id_pfr0 = 0x00001131;
1208 cpu->id_pfr1 = 0x00011011;
1209 cpu->id_dfr0 = 0x02010555;
1210 cpu->pmceid0 = 0x00000000;
1211 cpu->pmceid1 = 0x00000000;
1212 cpu->id_afr0 = 0x00000000;
1213 cpu->id_mmfr0 = 0x10101105;
1214 cpu->id_mmfr1 = 0x40000000;
1215 cpu->id_mmfr2 = 0x01240000;
1216 cpu->id_mmfr3 = 0x02102211;
1217 cpu->id_isar0 = 0x01101110;
1218 cpu->id_isar1 = 0x13112111;
1219 cpu->id_isar2 = 0x21232041;
1220 cpu->id_isar3 = 0x11112131;
1221 cpu->id_isar4 = 0x10011142;
1222 cpu->dbgdidr = 0x3515f005;
1223 cpu->clidr = 0x0a200023;
1224 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1225 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1226 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1227 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
1228 }
1229
1230 static void cortex_a15_initfn(Object *obj)
1231 {
1232 ARMCPU *cpu = ARM_CPU(obj);
1233
1234 cpu->dtb_compatible = "arm,cortex-a15";
1235 set_feature(&cpu->env, ARM_FEATURE_V7);
1236 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1237 set_feature(&cpu->env, ARM_FEATURE_NEON);
1238 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1239 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1240 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1241 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1242 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1243 set_feature(&cpu->env, ARM_FEATURE_LPAE);
1244 set_feature(&cpu->env, ARM_FEATURE_EL3);
1245 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1246 cpu->midr = 0x412fc0f1;
1247 cpu->reset_fpsid = 0x410430f0;
1248 cpu->mvfr0 = 0x10110222;
1249 cpu->mvfr1 = 0x11111111;
1250 cpu->ctr = 0x8444c004;
1251 cpu->reset_sctlr = 0x00c50078;
1252 cpu->id_pfr0 = 0x00001131;
1253 cpu->id_pfr1 = 0x00011011;
1254 cpu->id_dfr0 = 0x02010555;
1255 cpu->pmceid0 = 0x0000000;
1256 cpu->pmceid1 = 0x00000000;
1257 cpu->id_afr0 = 0x00000000;
1258 cpu->id_mmfr0 = 0x10201105;
1259 cpu->id_mmfr1 = 0x20000000;
1260 cpu->id_mmfr2 = 0x01240000;
1261 cpu->id_mmfr3 = 0x02102211;
1262 cpu->id_isar0 = 0x02101110;
1263 cpu->id_isar1 = 0x13112111;
1264 cpu->id_isar2 = 0x21232041;
1265 cpu->id_isar3 = 0x11112131;
1266 cpu->id_isar4 = 0x10011142;
1267 cpu->dbgdidr = 0x3515f021;
1268 cpu->clidr = 0x0a200023;
1269 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1270 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1271 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1272 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1273 }
1274
1275 static void ti925t_initfn(Object *obj)
1276 {
1277 ARMCPU *cpu = ARM_CPU(obj);
1278 set_feature(&cpu->env, ARM_FEATURE_V4T);
1279 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1280 cpu->midr = ARM_CPUID_TI925T;
1281 cpu->ctr = 0x5109149;
1282 cpu->reset_sctlr = 0x00000070;
1283 }
1284
1285 static void sa1100_initfn(Object *obj)
1286 {
1287 ARMCPU *cpu = ARM_CPU(obj);
1288
1289 cpu->dtb_compatible = "intel,sa1100";
1290 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1291 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1292 cpu->midr = 0x4401A11B;
1293 cpu->reset_sctlr = 0x00000070;
1294 }
1295
1296 static void sa1110_initfn(Object *obj)
1297 {
1298 ARMCPU *cpu = ARM_CPU(obj);
1299 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1300 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1301 cpu->midr = 0x6901B119;
1302 cpu->reset_sctlr = 0x00000070;
1303 }
1304
1305 static void pxa250_initfn(Object *obj)
1306 {
1307 ARMCPU *cpu = ARM_CPU(obj);
1308
1309 cpu->dtb_compatible = "marvell,xscale";
1310 set_feature(&cpu->env, ARM_FEATURE_V5);
1311 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1312 cpu->midr = 0x69052100;
1313 cpu->ctr = 0xd172172;
1314 cpu->reset_sctlr = 0x00000078;
1315 }
1316
1317 static void pxa255_initfn(Object *obj)
1318 {
1319 ARMCPU *cpu = ARM_CPU(obj);
1320
1321 cpu->dtb_compatible = "marvell,xscale";
1322 set_feature(&cpu->env, ARM_FEATURE_V5);
1323 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1324 cpu->midr = 0x69052d00;
1325 cpu->ctr = 0xd172172;
1326 cpu->reset_sctlr = 0x00000078;
1327 }
1328
1329 static void pxa260_initfn(Object *obj)
1330 {
1331 ARMCPU *cpu = ARM_CPU(obj);
1332
1333 cpu->dtb_compatible = "marvell,xscale";
1334 set_feature(&cpu->env, ARM_FEATURE_V5);
1335 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1336 cpu->midr = 0x69052903;
1337 cpu->ctr = 0xd172172;
1338 cpu->reset_sctlr = 0x00000078;
1339 }
1340
1341 static void pxa261_initfn(Object *obj)
1342 {
1343 ARMCPU *cpu = ARM_CPU(obj);
1344
1345 cpu->dtb_compatible = "marvell,xscale";
1346 set_feature(&cpu->env, ARM_FEATURE_V5);
1347 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1348 cpu->midr = 0x69052d05;
1349 cpu->ctr = 0xd172172;
1350 cpu->reset_sctlr = 0x00000078;
1351 }
1352
1353 static void pxa262_initfn(Object *obj)
1354 {
1355 ARMCPU *cpu = ARM_CPU(obj);
1356
1357 cpu->dtb_compatible = "marvell,xscale";
1358 set_feature(&cpu->env, ARM_FEATURE_V5);
1359 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1360 cpu->midr = 0x69052d06;
1361 cpu->ctr = 0xd172172;
1362 cpu->reset_sctlr = 0x00000078;
1363 }
1364
1365 static void pxa270a0_initfn(Object *obj)
1366 {
1367 ARMCPU *cpu = ARM_CPU(obj);
1368
1369 cpu->dtb_compatible = "marvell,xscale";
1370 set_feature(&cpu->env, ARM_FEATURE_V5);
1371 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1372 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1373 cpu->midr = 0x69054110;
1374 cpu->ctr = 0xd172172;
1375 cpu->reset_sctlr = 0x00000078;
1376 }
1377
1378 static void pxa270a1_initfn(Object *obj)
1379 {
1380 ARMCPU *cpu = ARM_CPU(obj);
1381
1382 cpu->dtb_compatible = "marvell,xscale";
1383 set_feature(&cpu->env, ARM_FEATURE_V5);
1384 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1385 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1386 cpu->midr = 0x69054111;
1387 cpu->ctr = 0xd172172;
1388 cpu->reset_sctlr = 0x00000078;
1389 }
1390
1391 static void pxa270b0_initfn(Object *obj)
1392 {
1393 ARMCPU *cpu = ARM_CPU(obj);
1394
1395 cpu->dtb_compatible = "marvell,xscale";
1396 set_feature(&cpu->env, ARM_FEATURE_V5);
1397 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1398 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1399 cpu->midr = 0x69054112;
1400 cpu->ctr = 0xd172172;
1401 cpu->reset_sctlr = 0x00000078;
1402 }
1403
1404 static void pxa270b1_initfn(Object *obj)
1405 {
1406 ARMCPU *cpu = ARM_CPU(obj);
1407
1408 cpu->dtb_compatible = "marvell,xscale";
1409 set_feature(&cpu->env, ARM_FEATURE_V5);
1410 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1411 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1412 cpu->midr = 0x69054113;
1413 cpu->ctr = 0xd172172;
1414 cpu->reset_sctlr = 0x00000078;
1415 }
1416
1417 static void pxa270c0_initfn(Object *obj)
1418 {
1419 ARMCPU *cpu = ARM_CPU(obj);
1420
1421 cpu->dtb_compatible = "marvell,xscale";
1422 set_feature(&cpu->env, ARM_FEATURE_V5);
1423 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1424 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1425 cpu->midr = 0x69054114;
1426 cpu->ctr = 0xd172172;
1427 cpu->reset_sctlr = 0x00000078;
1428 }
1429
1430 static void pxa270c5_initfn(Object *obj)
1431 {
1432 ARMCPU *cpu = ARM_CPU(obj);
1433
1434 cpu->dtb_compatible = "marvell,xscale";
1435 set_feature(&cpu->env, ARM_FEATURE_V5);
1436 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1437 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1438 cpu->midr = 0x69054117;
1439 cpu->ctr = 0xd172172;
1440 cpu->reset_sctlr = 0x00000078;
1441 }
1442
1443 #ifdef CONFIG_USER_ONLY
1444 static void arm_any_initfn(Object *obj)
1445 {
1446 ARMCPU *cpu = ARM_CPU(obj);
1447 set_feature(&cpu->env, ARM_FEATURE_V8);
1448 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1449 set_feature(&cpu->env, ARM_FEATURE_NEON);
1450 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1451 set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1452 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1453 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1454 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1455 set_feature(&cpu->env, ARM_FEATURE_CRC);
1456 cpu->midr = 0xffffffff;
1457 }
1458 #endif
1459
1460 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1461
1462 typedef struct ARMCPUInfo {
1463 const char *name;
1464 void (*initfn)(Object *obj);
1465 void (*class_init)(ObjectClass *oc, void *data);
1466 } ARMCPUInfo;
1467
1468 static const ARMCPUInfo arm_cpus[] = {
1469 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1470 { .name = "arm926", .initfn = arm926_initfn },
1471 { .name = "arm946", .initfn = arm946_initfn },
1472 { .name = "arm1026", .initfn = arm1026_initfn },
1473 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1474 * older core than plain "arm1136". In particular this does not
1475 * have the v6K features.
1476 */
1477 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1478 { .name = "arm1136", .initfn = arm1136_initfn },
1479 { .name = "arm1176", .initfn = arm1176_initfn },
1480 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1481 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
1482 .class_init = arm_v7m_class_init },
1483 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
1484 .class_init = arm_v7m_class_init },
1485 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
1486 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
1487 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
1488 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
1489 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
1490 { .name = "ti925t", .initfn = ti925t_initfn },
1491 { .name = "sa1100", .initfn = sa1100_initfn },
1492 { .name = "sa1110", .initfn = sa1110_initfn },
1493 { .name = "pxa250", .initfn = pxa250_initfn },
1494 { .name = "pxa255", .initfn = pxa255_initfn },
1495 { .name = "pxa260", .initfn = pxa260_initfn },
1496 { .name = "pxa261", .initfn = pxa261_initfn },
1497 { .name = "pxa262", .initfn = pxa262_initfn },
1498 /* "pxa270" is an alias for "pxa270-a0" */
1499 { .name = "pxa270", .initfn = pxa270a0_initfn },
1500 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1501 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1502 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1503 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1504 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1505 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
1506 #ifdef CONFIG_USER_ONLY
1507 { .name = "any", .initfn = arm_any_initfn },
1508 #endif
1509 #endif
1510 { .name = NULL }
1511 };
1512
1513 static Property arm_cpu_properties[] = {
1514 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1515 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1516 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1517 DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
1518 mp_affinity, ARM64_AFFINITY_INVALID),
1519 DEFINE_PROP_END_OF_LIST()
1520 };
1521
1522 #ifdef CONFIG_USER_ONLY
1523 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
1524 int mmu_idx)
1525 {
1526 ARMCPU *cpu = ARM_CPU(cs);
1527 CPUARMState *env = &cpu->env;
1528
1529 env->exception.vaddress = address;
1530 if (rw == 2) {
1531 cs->exception_index = EXCP_PREFETCH_ABORT;
1532 } else {
1533 cs->exception_index = EXCP_DATA_ABORT;
1534 }
1535 return 1;
1536 }
1537 #endif
1538
1539 static gchar *arm_gdb_arch_name(CPUState *cs)
1540 {
1541 ARMCPU *cpu = ARM_CPU(cs);
1542 CPUARMState *env = &cpu->env;
1543
1544 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
1545 return g_strdup("iwmmxt");
1546 }
1547 return g_strdup("arm");
1548 }
1549
1550 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1551 {
1552 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1553 CPUClass *cc = CPU_CLASS(acc);
1554 DeviceClass *dc = DEVICE_CLASS(oc);
1555
1556 acc->parent_realize = dc->realize;
1557 dc->realize = arm_cpu_realizefn;
1558 dc->props = arm_cpu_properties;
1559
1560 acc->parent_reset = cc->reset;
1561 cc->reset = arm_cpu_reset;
1562
1563 cc->class_by_name = arm_cpu_class_by_name;
1564 cc->has_work = arm_cpu_has_work;
1565 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1566 cc->dump_state = arm_cpu_dump_state;
1567 cc->set_pc = arm_cpu_set_pc;
1568 cc->gdb_read_register = arm_cpu_gdb_read_register;
1569 cc->gdb_write_register = arm_cpu_gdb_write_register;
1570 #ifdef CONFIG_USER_ONLY
1571 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1572 #else
1573 cc->do_interrupt = arm_cpu_do_interrupt;
1574 cc->do_unaligned_access = arm_cpu_do_unaligned_access;
1575 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
1576 cc->asidx_from_attrs = arm_asidx_from_attrs;
1577 cc->vmsd = &vmstate_arm_cpu;
1578 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
1579 cc->write_elf64_note = arm_cpu_write_elf64_note;
1580 cc->write_elf32_note = arm_cpu_write_elf32_note;
1581 #endif
1582 cc->gdb_num_core_regs = 26;
1583 cc->gdb_core_xml_file = "arm-core.xml";
1584 cc->gdb_arch_name = arm_gdb_arch_name;
1585 cc->gdb_stop_before_watchpoint = true;
1586 cc->debug_excp_handler = arm_debug_excp_handler;
1587 cc->debug_check_watchpoint = arm_debug_check_watchpoint;
1588
1589 cc->disas_set_info = arm_disas_set_info;
1590 }
1591
1592 static void cpu_register(const ARMCPUInfo *info)
1593 {
1594 TypeInfo type_info = {
1595 .parent = TYPE_ARM_CPU,
1596 .instance_size = sizeof(ARMCPU),
1597 .instance_init = info->initfn,
1598 .class_size = sizeof(ARMCPUClass),
1599 .class_init = info->class_init,
1600 };
1601
1602 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1603 type_register(&type_info);
1604 g_free((void *)type_info.name);
1605 }
1606
1607 static const TypeInfo arm_cpu_type_info = {
1608 .name = TYPE_ARM_CPU,
1609 .parent = TYPE_CPU,
1610 .instance_size = sizeof(ARMCPU),
1611 .instance_init = arm_cpu_initfn,
1612 .instance_post_init = arm_cpu_post_init,
1613 .instance_finalize = arm_cpu_finalizefn,
1614 .abstract = true,
1615 .class_size = sizeof(ARMCPUClass),
1616 .class_init = arm_cpu_class_init,
1617 };
1618
1619 static void arm_cpu_register_types(void)
1620 {
1621 const ARMCPUInfo *info = arm_cpus;
1622
1623 type_register_static(&arm_cpu_type_info);
1624
1625 while (info->name) {
1626 cpu_register(info);
1627 info++;
1628 }
1629 }
1630
1631 type_init(arm_cpu_register_types)