gdbstub: extend GByteArray to read register helpers
[qemu.git] / target / arm / cpu.h
1 /*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef ARM_CPU_H
21 #define ARM_CPU_H
22
23 #include "kvm-consts.h"
24 #include "hw/registerfields.h"
25 #include "cpu-qom.h"
26 #include "exec/cpu-defs.h"
27
28 /* ARM processors have a weak memory model */
29 #define TCG_GUEST_DEFAULT_MO (0)
30
31 #define EXCP_UDEF 1 /* undefined instruction */
32 #define EXCP_SWI 2 /* software interrupt */
33 #define EXCP_PREFETCH_ABORT 3
34 #define EXCP_DATA_ABORT 4
35 #define EXCP_IRQ 5
36 #define EXCP_FIQ 6
37 #define EXCP_BKPT 7
38 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
39 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
40 #define EXCP_HVC 11 /* HyperVisor Call */
41 #define EXCP_HYP_TRAP 12
42 #define EXCP_SMC 13 /* Secure Monitor Call */
43 #define EXCP_VIRQ 14
44 #define EXCP_VFIQ 15
45 #define EXCP_SEMIHOST 16 /* semihosting call */
46 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */
47 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
48 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */
49 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */
50 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */
51 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */
52 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
53
54 #define ARMV7M_EXCP_RESET 1
55 #define ARMV7M_EXCP_NMI 2
56 #define ARMV7M_EXCP_HARD 3
57 #define ARMV7M_EXCP_MEM 4
58 #define ARMV7M_EXCP_BUS 5
59 #define ARMV7M_EXCP_USAGE 6
60 #define ARMV7M_EXCP_SECURE 7
61 #define ARMV7M_EXCP_SVC 11
62 #define ARMV7M_EXCP_DEBUG 12
63 #define ARMV7M_EXCP_PENDSV 14
64 #define ARMV7M_EXCP_SYSTICK 15
65
66 /* For M profile, some registers are banked secure vs non-secure;
67 * these are represented as a 2-element array where the first element
68 * is the non-secure copy and the second is the secure copy.
69 * When the CPU does not have implement the security extension then
70 * only the first element is used.
71 * This means that the copy for the current security state can be
72 * accessed via env->registerfield[env->v7m.secure] (whether the security
73 * extension is implemented or not).
74 */
75 enum {
76 M_REG_NS = 0,
77 M_REG_S = 1,
78 M_REG_NUM_BANKS = 2,
79 };
80
81 /* ARM-specific interrupt pending bits. */
82 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
83 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
84 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
85
86 /* The usual mapping for an AArch64 system register to its AArch32
87 * counterpart is for the 32 bit world to have access to the lower
88 * half only (with writes leaving the upper half untouched). It's
89 * therefore useful to be able to pass TCG the offset of the least
90 * significant half of a uint64_t struct member.
91 */
92 #ifdef HOST_WORDS_BIGENDIAN
93 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
94 #define offsetofhigh32(S, M) offsetof(S, M)
95 #else
96 #define offsetoflow32(S, M) offsetof(S, M)
97 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
98 #endif
99
100 /* Meanings of the ARMCPU object's four inbound GPIO lines */
101 #define ARM_CPU_IRQ 0
102 #define ARM_CPU_FIQ 1
103 #define ARM_CPU_VIRQ 2
104 #define ARM_CPU_VFIQ 3
105
106 /* ARM-specific extra insn start words:
107 * 1: Conditional execution bits
108 * 2: Partial exception syndrome for data aborts
109 */
110 #define TARGET_INSN_START_EXTRA_WORDS 2
111
112 /* The 2nd extra word holding syndrome info for data aborts does not use
113 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to
114 * help the sleb128 encoder do a better job.
115 * When restoring the CPU state, we shift it back up.
116 */
117 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
118 #define ARM_INSN_START_WORD2_SHIFT 14
119
120 /* We currently assume float and double are IEEE single and double
121 precision respectively.
122 Doing runtime conversions is tricky because VFP registers may contain
123 integer values (eg. as the result of a FTOSI instruction).
124 s<2n> maps to the least significant half of d<n>
125 s<2n+1> maps to the most significant half of d<n>
126 */
127
128 /**
129 * DynamicGDBXMLInfo:
130 * @desc: Contains the XML descriptions.
131 * @num_cpregs: Number of the Coprocessor registers seen by GDB.
132 * @cpregs_keys: Array that contains the corresponding Key of
133 * a given cpreg with the same order of the cpreg in the XML description.
134 */
135 typedef struct DynamicGDBXMLInfo {
136 char *desc;
137 int num_cpregs;
138 uint32_t *cpregs_keys;
139 } DynamicGDBXMLInfo;
140
141 /* CPU state for each instance of a generic timer (in cp15 c14) */
142 typedef struct ARMGenericTimer {
143 uint64_t cval; /* Timer CompareValue register */
144 uint64_t ctl; /* Timer Control register */
145 } ARMGenericTimer;
146
147 #define GTIMER_PHYS 0
148 #define GTIMER_VIRT 1
149 #define GTIMER_HYP 2
150 #define GTIMER_SEC 3
151 #define GTIMER_HYPVIRT 4
152 #define NUM_GTIMERS 5
153
154 typedef struct {
155 uint64_t raw_tcr;
156 uint32_t mask;
157 uint32_t base_mask;
158 } TCR;
159
160 /* Define a maximum sized vector register.
161 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
162 * For 64-bit, this is a 2048-bit SVE register.
163 *
164 * Note that the mapping between S, D, and Q views of the register bank
165 * differs between AArch64 and AArch32.
166 * In AArch32:
167 * Qn = regs[n].d[1]:regs[n].d[0]
168 * Dn = regs[n / 2].d[n & 1]
169 * Sn = regs[n / 4].d[n % 4 / 2],
170 * bits 31..0 for even n, and bits 63..32 for odd n
171 * (and regs[16] to regs[31] are inaccessible)
172 * In AArch64:
173 * Zn = regs[n].d[*]
174 * Qn = regs[n].d[1]:regs[n].d[0]
175 * Dn = regs[n].d[0]
176 * Sn = regs[n].d[0] bits 31..0
177 * Hn = regs[n].d[0] bits 15..0
178 *
179 * This corresponds to the architecturally defined mapping between
180 * the two execution states, and means we do not need to explicitly
181 * map these registers when changing states.
182 *
183 * Align the data for use with TCG host vector operations.
184 */
185
186 #ifdef TARGET_AARCH64
187 # define ARM_MAX_VQ 16
188 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
189 #else
190 # define ARM_MAX_VQ 1
191 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
192 #endif
193
194 typedef struct ARMVectorReg {
195 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
196 } ARMVectorReg;
197
198 #ifdef TARGET_AARCH64
199 /* In AArch32 mode, predicate registers do not exist at all. */
200 typedef struct ARMPredicateReg {
201 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
202 } ARMPredicateReg;
203
204 /* In AArch32 mode, PAC keys do not exist at all. */
205 typedef struct ARMPACKey {
206 uint64_t lo, hi;
207 } ARMPACKey;
208 #endif
209
210
211 typedef struct CPUARMState {
212 /* Regs for current mode. */
213 uint32_t regs[16];
214
215 /* 32/64 switch only happens when taking and returning from
216 * exceptions so the overlap semantics are taken care of then
217 * instead of having a complicated union.
218 */
219 /* Regs for A64 mode. */
220 uint64_t xregs[32];
221 uint64_t pc;
222 /* PSTATE isn't an architectural register for ARMv8. However, it is
223 * convenient for us to assemble the underlying state into a 32 bit format
224 * identical to the architectural format used for the SPSR. (This is also
225 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
226 * 'pstate' register are.) Of the PSTATE bits:
227 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
228 * semantics as for AArch32, as described in the comments on each field)
229 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
230 * DAIF (exception masks) are kept in env->daif
231 * BTYPE is kept in env->btype
232 * all other bits are stored in their correct places in env->pstate
233 */
234 uint32_t pstate;
235 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
236
237 /* Cached TBFLAGS state. See below for which bits are included. */
238 uint32_t hflags;
239
240 /* Frequently accessed CPSR bits are stored separately for efficiency.
241 This contains all the other bits. Use cpsr_{read,write} to access
242 the whole CPSR. */
243 uint32_t uncached_cpsr;
244 uint32_t spsr;
245
246 /* Banked registers. */
247 uint64_t banked_spsr[8];
248 uint32_t banked_r13[8];
249 uint32_t banked_r14[8];
250
251 /* These hold r8-r12. */
252 uint32_t usr_regs[5];
253 uint32_t fiq_regs[5];
254
255 /* cpsr flag cache for faster execution */
256 uint32_t CF; /* 0 or 1 */
257 uint32_t VF; /* V is the bit 31. All other bits are undefined */
258 uint32_t NF; /* N is bit 31. All other bits are undefined. */
259 uint32_t ZF; /* Z set if zero. */
260 uint32_t QF; /* 0 or 1 */
261 uint32_t GE; /* cpsr[19:16] */
262 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
263 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
264 uint32_t btype; /* BTI branch type. spsr[11:10]. */
265 uint64_t daif; /* exception masks, in the bits they are in PSTATE */
266
267 uint64_t elr_el[4]; /* AArch64 exception link regs */
268 uint64_t sp_el[4]; /* AArch64 banked stack pointers */
269
270 /* System control coprocessor (cp15) */
271 struct {
272 uint32_t c0_cpuid;
273 union { /* Cache size selection */
274 struct {
275 uint64_t _unused_csselr0;
276 uint64_t csselr_ns;
277 uint64_t _unused_csselr1;
278 uint64_t csselr_s;
279 };
280 uint64_t csselr_el[4];
281 };
282 union { /* System control register. */
283 struct {
284 uint64_t _unused_sctlr;
285 uint64_t sctlr_ns;
286 uint64_t hsctlr;
287 uint64_t sctlr_s;
288 };
289 uint64_t sctlr_el[4];
290 };
291 uint64_t cpacr_el1; /* Architectural feature access control register */
292 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */
293 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
294 uint64_t sder; /* Secure debug enable register. */
295 uint32_t nsacr; /* Non-secure access control register. */
296 union { /* MMU translation table base 0. */
297 struct {
298 uint64_t _unused_ttbr0_0;
299 uint64_t ttbr0_ns;
300 uint64_t _unused_ttbr0_1;
301 uint64_t ttbr0_s;
302 };
303 uint64_t ttbr0_el[4];
304 };
305 union { /* MMU translation table base 1. */
306 struct {
307 uint64_t _unused_ttbr1_0;
308 uint64_t ttbr1_ns;
309 uint64_t _unused_ttbr1_1;
310 uint64_t ttbr1_s;
311 };
312 uint64_t ttbr1_el[4];
313 };
314 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */
315 /* MMU translation table base control. */
316 TCR tcr_el[4];
317 TCR vtcr_el2; /* Virtualization Translation Control. */
318 uint32_t c2_data; /* MPU data cacheable bits. */
319 uint32_t c2_insn; /* MPU instruction cacheable bits. */
320 union { /* MMU domain access control register
321 * MPU write buffer control.
322 */
323 struct {
324 uint64_t dacr_ns;
325 uint64_t dacr_s;
326 };
327 struct {
328 uint64_t dacr32_el2;
329 };
330 };
331 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
332 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
333 uint64_t hcr_el2; /* Hypervisor configuration register */
334 uint64_t scr_el3; /* Secure configuration register. */
335 union { /* Fault status registers. */
336 struct {
337 uint64_t ifsr_ns;
338 uint64_t ifsr_s;
339 };
340 struct {
341 uint64_t ifsr32_el2;
342 };
343 };
344 union {
345 struct {
346 uint64_t _unused_dfsr;
347 uint64_t dfsr_ns;
348 uint64_t hsr;
349 uint64_t dfsr_s;
350 };
351 uint64_t esr_el[4];
352 };
353 uint32_t c6_region[8]; /* MPU base/size registers. */
354 union { /* Fault address registers. */
355 struct {
356 uint64_t _unused_far0;
357 #ifdef HOST_WORDS_BIGENDIAN
358 uint32_t ifar_ns;
359 uint32_t dfar_ns;
360 uint32_t ifar_s;
361 uint32_t dfar_s;
362 #else
363 uint32_t dfar_ns;
364 uint32_t ifar_ns;
365 uint32_t dfar_s;
366 uint32_t ifar_s;
367 #endif
368 uint64_t _unused_far3;
369 };
370 uint64_t far_el[4];
371 };
372 uint64_t hpfar_el2;
373 uint64_t hstr_el2;
374 union { /* Translation result. */
375 struct {
376 uint64_t _unused_par_0;
377 uint64_t par_ns;
378 uint64_t _unused_par_1;
379 uint64_t par_s;
380 };
381 uint64_t par_el[4];
382 };
383
384 uint32_t c9_insn; /* Cache lockdown registers. */
385 uint32_t c9_data;
386 uint64_t c9_pmcr; /* performance monitor control register */
387 uint64_t c9_pmcnten; /* perf monitor counter enables */
388 uint64_t c9_pmovsr; /* perf monitor overflow status */
389 uint64_t c9_pmuserenr; /* perf monitor user enable */
390 uint64_t c9_pmselr; /* perf monitor counter selection register */
391 uint64_t c9_pminten; /* perf monitor interrupt enables */
392 union { /* Memory attribute redirection */
393 struct {
394 #ifdef HOST_WORDS_BIGENDIAN
395 uint64_t _unused_mair_0;
396 uint32_t mair1_ns;
397 uint32_t mair0_ns;
398 uint64_t _unused_mair_1;
399 uint32_t mair1_s;
400 uint32_t mair0_s;
401 #else
402 uint64_t _unused_mair_0;
403 uint32_t mair0_ns;
404 uint32_t mair1_ns;
405 uint64_t _unused_mair_1;
406 uint32_t mair0_s;
407 uint32_t mair1_s;
408 #endif
409 };
410 uint64_t mair_el[4];
411 };
412 union { /* vector base address register */
413 struct {
414 uint64_t _unused_vbar;
415 uint64_t vbar_ns;
416 uint64_t hvbar;
417 uint64_t vbar_s;
418 };
419 uint64_t vbar_el[4];
420 };
421 uint32_t mvbar; /* (monitor) vector base address register */
422 struct { /* FCSE PID. */
423 uint32_t fcseidr_ns;
424 uint32_t fcseidr_s;
425 };
426 union { /* Context ID. */
427 struct {
428 uint64_t _unused_contextidr_0;
429 uint64_t contextidr_ns;
430 uint64_t _unused_contextidr_1;
431 uint64_t contextidr_s;
432 };
433 uint64_t contextidr_el[4];
434 };
435 union { /* User RW Thread register. */
436 struct {
437 uint64_t tpidrurw_ns;
438 uint64_t tpidrprw_ns;
439 uint64_t htpidr;
440 uint64_t _tpidr_el3;
441 };
442 uint64_t tpidr_el[4];
443 };
444 /* The secure banks of these registers don't map anywhere */
445 uint64_t tpidrurw_s;
446 uint64_t tpidrprw_s;
447 uint64_t tpidruro_s;
448
449 union { /* User RO Thread register. */
450 uint64_t tpidruro_ns;
451 uint64_t tpidrro_el[1];
452 };
453 uint64_t c14_cntfrq; /* Counter Frequency register */
454 uint64_t c14_cntkctl; /* Timer Control register */
455 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
456 uint64_t cntvoff_el2; /* Counter Virtual Offset register */
457 ARMGenericTimer c14_timer[NUM_GTIMERS];
458 uint32_t c15_cpar; /* XScale Coprocessor Access Register */
459 uint32_t c15_ticonfig; /* TI925T configuration byte. */
460 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
461 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
462 uint32_t c15_threadid; /* TI debugger thread-ID. */
463 uint32_t c15_config_base_address; /* SCU base address. */
464 uint32_t c15_diagnostic; /* diagnostic register */
465 uint32_t c15_power_diagnostic;
466 uint32_t c15_power_control; /* power control */
467 uint64_t dbgbvr[16]; /* breakpoint value registers */
468 uint64_t dbgbcr[16]; /* breakpoint control registers */
469 uint64_t dbgwvr[16]; /* watchpoint value registers */
470 uint64_t dbgwcr[16]; /* watchpoint control registers */
471 uint64_t mdscr_el1;
472 uint64_t oslsr_el1; /* OS Lock Status */
473 uint64_t mdcr_el2;
474 uint64_t mdcr_el3;
475 /* Stores the architectural value of the counter *the last time it was
476 * updated* by pmccntr_op_start. Accesses should always be surrounded
477 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest
478 * architecturally-correct value is being read/set.
479 */
480 uint64_t c15_ccnt;
481 /* Stores the delta between the architectural value and the underlying
482 * cycle count during normal operation. It is used to update c15_ccnt
483 * to be the correct architectural value before accesses. During
484 * accesses, c15_ccnt_delta contains the underlying count being used
485 * for the access, after which it reverts to the delta value in
486 * pmccntr_op_finish.
487 */
488 uint64_t c15_ccnt_delta;
489 uint64_t c14_pmevcntr[31];
490 uint64_t c14_pmevcntr_delta[31];
491 uint64_t c14_pmevtyper[31];
492 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
493 uint64_t vpidr_el2; /* Virtualization Processor ID Register */
494 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
495 } cp15;
496
497 struct {
498 /* M profile has up to 4 stack pointers:
499 * a Main Stack Pointer and a Process Stack Pointer for each
500 * of the Secure and Non-Secure states. (If the CPU doesn't support
501 * the security extension then it has only two SPs.)
502 * In QEMU we always store the currently active SP in regs[13],
503 * and the non-active SP for the current security state in
504 * v7m.other_sp. The stack pointers for the inactive security state
505 * are stored in other_ss_msp and other_ss_psp.
506 * switch_v7m_security_state() is responsible for rearranging them
507 * when we change security state.
508 */
509 uint32_t other_sp;
510 uint32_t other_ss_msp;
511 uint32_t other_ss_psp;
512 uint32_t vecbase[M_REG_NUM_BANKS];
513 uint32_t basepri[M_REG_NUM_BANKS];
514 uint32_t control[M_REG_NUM_BANKS];
515 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */
516 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
517 uint32_t hfsr; /* HardFault Status */
518 uint32_t dfsr; /* Debug Fault Status Register */
519 uint32_t sfsr; /* Secure Fault Status Register */
520 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
521 uint32_t bfar; /* BusFault Address */
522 uint32_t sfar; /* Secure Fault Address Register */
523 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
524 int exception;
525 uint32_t primask[M_REG_NUM_BANKS];
526 uint32_t faultmask[M_REG_NUM_BANKS];
527 uint32_t aircr; /* only holds r/w state if security extn implemented */
528 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
529 uint32_t csselr[M_REG_NUM_BANKS];
530 uint32_t scr[M_REG_NUM_BANKS];
531 uint32_t msplim[M_REG_NUM_BANKS];
532 uint32_t psplim[M_REG_NUM_BANKS];
533 uint32_t fpcar[M_REG_NUM_BANKS];
534 uint32_t fpccr[M_REG_NUM_BANKS];
535 uint32_t fpdscr[M_REG_NUM_BANKS];
536 uint32_t cpacr[M_REG_NUM_BANKS];
537 uint32_t nsacr;
538 } v7m;
539
540 /* Information associated with an exception about to be taken:
541 * code which raises an exception must set cs->exception_index and
542 * the relevant parts of this structure; the cpu_do_interrupt function
543 * will then set the guest-visible registers as part of the exception
544 * entry process.
545 */
546 struct {
547 uint32_t syndrome; /* AArch64 format syndrome register */
548 uint32_t fsr; /* AArch32 format fault status register info */
549 uint64_t vaddress; /* virtual addr associated with exception, if any */
550 uint32_t target_el; /* EL the exception should be targeted for */
551 /* If we implement EL2 we will also need to store information
552 * about the intermediate physical address for stage 2 faults.
553 */
554 } exception;
555
556 /* Information associated with an SError */
557 struct {
558 uint8_t pending;
559 uint8_t has_esr;
560 uint64_t esr;
561 } serror;
562
563 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
564 uint32_t irq_line_state;
565
566 /* Thumb-2 EE state. */
567 uint32_t teecr;
568 uint32_t teehbr;
569
570 /* VFP coprocessor state. */
571 struct {
572 ARMVectorReg zregs[32];
573
574 #ifdef TARGET_AARCH64
575 /* Store FFR as pregs[16] to make it easier to treat as any other. */
576 #define FFR_PRED_NUM 16
577 ARMPredicateReg pregs[17];
578 /* Scratch space for aa64 sve predicate temporary. */
579 ARMPredicateReg preg_tmp;
580 #endif
581
582 /* We store these fpcsr fields separately for convenience. */
583 uint32_t qc[4] QEMU_ALIGNED(16);
584 int vec_len;
585 int vec_stride;
586
587 uint32_t xregs[16];
588
589 /* Scratch space for aa32 neon expansion. */
590 uint32_t scratch[8];
591
592 /* There are a number of distinct float control structures:
593 *
594 * fp_status: is the "normal" fp status.
595 * fp_status_fp16: used for half-precision calculations
596 * standard_fp_status : the ARM "Standard FPSCR Value"
597 *
598 * Half-precision operations are governed by a separate
599 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
600 * status structure to control this.
601 *
602 * The "Standard FPSCR", ie default-NaN, flush-to-zero,
603 * round-to-nearest and is used by any operations (generally
604 * Neon) which the architecture defines as controlled by the
605 * standard FPSCR value rather than the FPSCR.
606 *
607 * To avoid having to transfer exception bits around, we simply
608 * say that the FPSCR cumulative exception flags are the logical
609 * OR of the flags in the three fp statuses. This relies on the
610 * only thing which needs to read the exception flags being
611 * an explicit FPSCR read.
612 */
613 float_status fp_status;
614 float_status fp_status_f16;
615 float_status standard_fp_status;
616
617 /* ZCR_EL[1-3] */
618 uint64_t zcr_el[4];
619 } vfp;
620 uint64_t exclusive_addr;
621 uint64_t exclusive_val;
622 uint64_t exclusive_high;
623
624 /* iwMMXt coprocessor state. */
625 struct {
626 uint64_t regs[16];
627 uint64_t val;
628
629 uint32_t cregs[16];
630 } iwmmxt;
631
632 #ifdef TARGET_AARCH64
633 struct {
634 ARMPACKey apia;
635 ARMPACKey apib;
636 ARMPACKey apda;
637 ARMPACKey apdb;
638 ARMPACKey apga;
639 } keys;
640 #endif
641
642 #if defined(CONFIG_USER_ONLY)
643 /* For usermode syscall translation. */
644 int eabi;
645 #endif
646
647 struct CPUBreakpoint *cpu_breakpoint[16];
648 struct CPUWatchpoint *cpu_watchpoint[16];
649
650 /* Fields up to this point are cleared by a CPU reset */
651 struct {} end_reset_fields;
652
653 /* Fields after this point are preserved across CPU reset. */
654
655 /* Internal CPU feature flags. */
656 uint64_t features;
657
658 /* PMSAv7 MPU */
659 struct {
660 uint32_t *drbar;
661 uint32_t *drsr;
662 uint32_t *dracr;
663 uint32_t rnr[M_REG_NUM_BANKS];
664 } pmsav7;
665
666 /* PMSAv8 MPU */
667 struct {
668 /* The PMSAv8 implementation also shares some PMSAv7 config
669 * and state:
670 * pmsav7.rnr (region number register)
671 * pmsav7_dregion (number of configured regions)
672 */
673 uint32_t *rbar[M_REG_NUM_BANKS];
674 uint32_t *rlar[M_REG_NUM_BANKS];
675 uint32_t mair0[M_REG_NUM_BANKS];
676 uint32_t mair1[M_REG_NUM_BANKS];
677 } pmsav8;
678
679 /* v8M SAU */
680 struct {
681 uint32_t *rbar;
682 uint32_t *rlar;
683 uint32_t rnr;
684 uint32_t ctrl;
685 } sau;
686
687 void *nvic;
688 const struct arm_boot_info *boot_info;
689 /* Store GICv3CPUState to access from this struct */
690 void *gicv3state;
691 } CPUARMState;
692
693 /**
694 * ARMELChangeHookFn:
695 * type of a function which can be registered via arm_register_el_change_hook()
696 * to get callbacks when the CPU changes its exception level or mode.
697 */
698 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
699 typedef struct ARMELChangeHook ARMELChangeHook;
700 struct ARMELChangeHook {
701 ARMELChangeHookFn *hook;
702 void *opaque;
703 QLIST_ENTRY(ARMELChangeHook) node;
704 };
705
706 /* These values map onto the return values for
707 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */
708 typedef enum ARMPSCIState {
709 PSCI_ON = 0,
710 PSCI_OFF = 1,
711 PSCI_ON_PENDING = 2
712 } ARMPSCIState;
713
714 typedef struct ARMISARegisters ARMISARegisters;
715
716 /**
717 * ARMCPU:
718 * @env: #CPUARMState
719 *
720 * An ARM CPU core.
721 */
722 struct ARMCPU {
723 /*< private >*/
724 CPUState parent_obj;
725 /*< public >*/
726
727 CPUNegativeOffsetState neg;
728 CPUARMState env;
729
730 /* Coprocessor information */
731 GHashTable *cp_regs;
732 /* For marshalling (mostly coprocessor) register state between the
733 * kernel and QEMU (for KVM) and between two QEMUs (for migration),
734 * we use these arrays.
735 */
736 /* List of register indexes managed via these arrays; (full KVM style
737 * 64 bit indexes, not CPRegInfo 32 bit indexes)
738 */
739 uint64_t *cpreg_indexes;
740 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
741 uint64_t *cpreg_values;
742 /* Length of the indexes, values, reset_values arrays */
743 int32_t cpreg_array_len;
744 /* These are used only for migration: incoming data arrives in
745 * these fields and is sanity checked in post_load before copying
746 * to the working data structures above.
747 */
748 uint64_t *cpreg_vmstate_indexes;
749 uint64_t *cpreg_vmstate_values;
750 int32_t cpreg_vmstate_array_len;
751
752 DynamicGDBXMLInfo dyn_xml;
753
754 /* Timers used by the generic (architected) timer */
755 QEMUTimer *gt_timer[NUM_GTIMERS];
756 /*
757 * Timer used by the PMU. Its state is restored after migration by
758 * pmu_op_finish() - it does not need other handling during migration
759 */
760 QEMUTimer *pmu_timer;
761 /* GPIO outputs for generic timer */
762 qemu_irq gt_timer_outputs[NUM_GTIMERS];
763 /* GPIO output for GICv3 maintenance interrupt signal */
764 qemu_irq gicv3_maintenance_interrupt;
765 /* GPIO output for the PMU interrupt */
766 qemu_irq pmu_interrupt;
767
768 /* MemoryRegion to use for secure physical accesses */
769 MemoryRegion *secure_memory;
770
771 /* For v8M, pointer to the IDAU interface provided by board/SoC */
772 Object *idau;
773
774 /* 'compatible' string for this CPU for Linux device trees */
775 const char *dtb_compatible;
776
777 /* PSCI version for this CPU
778 * Bits[31:16] = Major Version
779 * Bits[15:0] = Minor Version
780 */
781 uint32_t psci_version;
782
783 /* Should CPU start in PSCI powered-off state? */
784 bool start_powered_off;
785
786 /* Current power state, access guarded by BQL */
787 ARMPSCIState power_state;
788
789 /* CPU has virtualization extension */
790 bool has_el2;
791 /* CPU has security extension */
792 bool has_el3;
793 /* CPU has PMU (Performance Monitor Unit) */
794 bool has_pmu;
795 /* CPU has VFP */
796 bool has_vfp;
797 /* CPU has Neon */
798 bool has_neon;
799 /* CPU has M-profile DSP extension */
800 bool has_dsp;
801
802 /* CPU has memory protection unit */
803 bool has_mpu;
804 /* PMSAv7 MPU number of supported regions */
805 uint32_t pmsav7_dregion;
806 /* v8M SAU number of supported regions */
807 uint32_t sau_sregion;
808
809 /* PSCI conduit used to invoke PSCI methods
810 * 0 - disabled, 1 - smc, 2 - hvc
811 */
812 uint32_t psci_conduit;
813
814 /* For v8M, initial value of the Secure VTOR */
815 uint32_t init_svtor;
816
817 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
818 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
819 */
820 uint32_t kvm_target;
821
822 /* KVM init features for this CPU */
823 uint32_t kvm_init_features[7];
824
825 /* KVM CPU state */
826
827 /* KVM virtual time adjustment */
828 bool kvm_adjvtime;
829 bool kvm_vtime_dirty;
830 uint64_t kvm_vtime;
831
832 /* Uniprocessor system with MP extensions */
833 bool mp_is_up;
834
835 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init
836 * and the probe failed (so we need to report the error in realize)
837 */
838 bool host_cpu_probe_failed;
839
840 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
841 * register.
842 */
843 int32_t core_count;
844
845 /* The instance init functions for implementation-specific subclasses
846 * set these fields to specify the implementation-dependent values of
847 * various constant registers and reset values of non-constant
848 * registers.
849 * Some of these might become QOM properties eventually.
850 * Field names match the official register names as defined in the
851 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
852 * is used for reset values of non-constant registers; no reset_
853 * prefix means a constant register.
854 * Some of these registers are split out into a substructure that
855 * is shared with the translators to control the ISA.
856 *
857 * Note that if you add an ID register to the ARMISARegisters struct
858 * you need to also update the 32-bit and 64-bit versions of the
859 * kvm_arm_get_host_cpu_features() function to correctly populate the
860 * field by reading the value from the KVM vCPU.
861 */
862 struct ARMISARegisters {
863 uint32_t id_isar0;
864 uint32_t id_isar1;
865 uint32_t id_isar2;
866 uint32_t id_isar3;
867 uint32_t id_isar4;
868 uint32_t id_isar5;
869 uint32_t id_isar6;
870 uint32_t id_mmfr0;
871 uint32_t id_mmfr1;
872 uint32_t id_mmfr2;
873 uint32_t id_mmfr3;
874 uint32_t id_mmfr4;
875 uint32_t mvfr0;
876 uint32_t mvfr1;
877 uint32_t mvfr2;
878 uint32_t id_dfr0;
879 uint32_t dbgdidr;
880 uint64_t id_aa64isar0;
881 uint64_t id_aa64isar1;
882 uint64_t id_aa64pfr0;
883 uint64_t id_aa64pfr1;
884 uint64_t id_aa64mmfr0;
885 uint64_t id_aa64mmfr1;
886 uint64_t id_aa64mmfr2;
887 uint64_t id_aa64dfr0;
888 uint64_t id_aa64dfr1;
889 } isar;
890 uint32_t midr;
891 uint32_t revidr;
892 uint32_t reset_fpsid;
893 uint32_t ctr;
894 uint32_t reset_sctlr;
895 uint32_t id_pfr0;
896 uint32_t id_pfr1;
897 uint64_t pmceid0;
898 uint64_t pmceid1;
899 uint32_t id_afr0;
900 uint64_t id_aa64afr0;
901 uint64_t id_aa64afr1;
902 uint32_t clidr;
903 uint64_t mp_affinity; /* MP ID without feature bits */
904 /* The elements of this array are the CCSIDR values for each cache,
905 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
906 */
907 uint64_t ccsidr[16];
908 uint64_t reset_cbar;
909 uint32_t reset_auxcr;
910 bool reset_hivecs;
911 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
912 uint32_t dcz_blocksize;
913 uint64_t rvbar;
914
915 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
916 int gic_num_lrs; /* number of list registers */
917 int gic_vpribits; /* number of virtual priority bits */
918 int gic_vprebits; /* number of virtual preemption bits */
919
920 /* Whether the cfgend input is high (i.e. this CPU should reset into
921 * big-endian mode). This setting isn't used directly: instead it modifies
922 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
923 * architecture version.
924 */
925 bool cfgend;
926
927 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
928 QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
929
930 int32_t node_id; /* NUMA node this CPU belongs to */
931
932 /* Used to synchronize KVM and QEMU in-kernel device levels */
933 uint8_t device_irq_level;
934
935 /* Used to set the maximum vector length the cpu will support. */
936 uint32_t sve_max_vq;
937
938 /*
939 * In sve_vq_map each set bit is a supported vector length of
940 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector
941 * length in quadwords.
942 *
943 * While processing properties during initialization, corresponding
944 * sve_vq_init bits are set for bits in sve_vq_map that have been
945 * set by properties.
946 */
947 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ);
948 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ);
949
950 /* Generic timer counter frequency, in Hz */
951 uint64_t gt_cntfrq_hz;
952 };
953
954 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
955
956 void arm_cpu_post_init(Object *obj);
957
958 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
959
960 #ifndef CONFIG_USER_ONLY
961 extern const VMStateDescription vmstate_arm_cpu;
962 #endif
963
964 void arm_cpu_do_interrupt(CPUState *cpu);
965 void arm_v7m_cpu_do_interrupt(CPUState *cpu);
966 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
967
968 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
969 MemTxAttrs *attrs);
970
971 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
972 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
973
974 /* Dynamically generates for gdb stub an XML description of the sysregs from
975 * the cp_regs hashtable. Returns the registered sysregs number.
976 */
977 int arm_gen_dynamic_xml(CPUState *cpu);
978
979 /* Returns the dynamically generated XML for the gdb stub.
980 * Returns a pointer to the XML contents for the specified XML file or NULL
981 * if the XML name doesn't match the predefined one.
982 */
983 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
984
985 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
986 int cpuid, void *opaque);
987 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
988 int cpuid, void *opaque);
989
990 #ifdef TARGET_AARCH64
991 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
992 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
993 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
994 void aarch64_sve_change_el(CPUARMState *env, int old_el,
995 int new_el, bool el0_a64);
996 void aarch64_add_sve_properties(Object *obj);
997
998 /*
999 * SVE registers are encoded in KVM's memory in an endianness-invariant format.
1000 * The byte at offset i from the start of the in-memory representation contains
1001 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
1002 * lowest offsets are stored in the lowest memory addresses, then that nearly
1003 * matches QEMU's representation, which is to use an array of host-endian
1004 * uint64_t's, where the lower offsets are at the lower indices. To complete
1005 * the translation we just need to byte swap the uint64_t's on big-endian hosts.
1006 */
1007 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
1008 {
1009 #ifdef HOST_WORDS_BIGENDIAN
1010 int i;
1011
1012 for (i = 0; i < nr; ++i) {
1013 dst[i] = bswap64(src[i]);
1014 }
1015
1016 return dst;
1017 #else
1018 return src;
1019 #endif
1020 }
1021
1022 #else
1023 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
1024 static inline void aarch64_sve_change_el(CPUARMState *env, int o,
1025 int n, bool a)
1026 { }
1027 static inline void aarch64_add_sve_properties(Object *obj) { }
1028 #endif
1029
1030 #if !defined(CONFIG_TCG)
1031 static inline target_ulong do_arm_semihosting(CPUARMState *env)
1032 {
1033 g_assert_not_reached();
1034 }
1035 #else
1036 target_ulong do_arm_semihosting(CPUARMState *env);
1037 #endif
1038 void aarch64_sync_32_to_64(CPUARMState *env);
1039 void aarch64_sync_64_to_32(CPUARMState *env);
1040
1041 int fp_exception_el(CPUARMState *env, int cur_el);
1042 int sve_exception_el(CPUARMState *env, int cur_el);
1043 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el);
1044
1045 static inline bool is_a64(CPUARMState *env)
1046 {
1047 return env->aarch64;
1048 }
1049
1050 /* you can call this signal handler from your SIGBUS and SIGSEGV
1051 signal handlers to inform the virtual CPU of exceptions. non zero
1052 is returned if the signal was handled by the virtual CPU. */
1053 int cpu_arm_signal_handler(int host_signum, void *pinfo,
1054 void *puc);
1055
1056 /**
1057 * pmu_op_start/finish
1058 * @env: CPUARMState
1059 *
1060 * Convert all PMU counters between their delta form (the typical mode when
1061 * they are enabled) and the guest-visible values. These two calls must
1062 * surround any action which might affect the counters.
1063 */
1064 void pmu_op_start(CPUARMState *env);
1065 void pmu_op_finish(CPUARMState *env);
1066
1067 /*
1068 * Called when a PMU counter is due to overflow
1069 */
1070 void arm_pmu_timer_cb(void *opaque);
1071
1072 /**
1073 * Functions to register as EL change hooks for PMU mode filtering
1074 */
1075 void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1076 void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1077
1078 /*
1079 * pmu_init
1080 * @cpu: ARMCPU
1081 *
1082 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state
1083 * for the current configuration
1084 */
1085 void pmu_init(ARMCPU *cpu);
1086
1087 /* SCTLR bit meanings. Several bits have been reused in newer
1088 * versions of the architecture; in that case we define constants
1089 * for both old and new bit meanings. Code which tests against those
1090 * bits should probably check or otherwise arrange that the CPU
1091 * is the architectural version it expects.
1092 */
1093 #define SCTLR_M (1U << 0)
1094 #define SCTLR_A (1U << 1)
1095 #define SCTLR_C (1U << 2)
1096 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
1097 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1098 #define SCTLR_SA (1U << 3) /* AArch64 only */
1099 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
1100 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
1101 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
1102 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
1103 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
1104 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
1105 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */
1106 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
1107 #define SCTLR_ITD (1U << 7) /* v8 onward */
1108 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
1109 #define SCTLR_SED (1U << 8) /* v8 onward */
1110 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
1111 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
1112 #define SCTLR_F (1U << 10) /* up to v6 */
1113 #define SCTLR_SW (1U << 10) /* v7 */
1114 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */
1115 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */
1116 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */
1117 #define SCTLR_I (1U << 12)
1118 #define SCTLR_V (1U << 13) /* AArch32 only */
1119 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */
1120 #define SCTLR_RR (1U << 14) /* up to v7 */
1121 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
1122 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
1123 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
1124 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
1125 #define SCTLR_nTWI (1U << 16) /* v8 onward */
1126 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */
1127 #define SCTLR_BR (1U << 17) /* PMSA only */
1128 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
1129 #define SCTLR_nTWE (1U << 18) /* v8 onward */
1130 #define SCTLR_WXN (1U << 19)
1131 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
1132 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */
1133 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */
1134 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
1135 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */
1136 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */
1137 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
1138 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */
1139 #define SCTLR_VE (1U << 24) /* up to v7 */
1140 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
1141 #define SCTLR_EE (1U << 25)
1142 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
1143 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
1144 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */
1145 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */
1146 #define SCTLR_TRE (1U << 28) /* AArch32 only */
1147 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
1148 #define SCTLR_AFE (1U << 29) /* AArch32 only */
1149 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
1150 #define SCTLR_TE (1U << 30) /* AArch32 only */
1151 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */
1152 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */
1153 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
1154 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
1155 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
1156 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */
1157 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */
1158 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
1159 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
1160 #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */
1161
1162 #define CPTR_TCPAC (1U << 31)
1163 #define CPTR_TTA (1U << 20)
1164 #define CPTR_TFP (1U << 10)
1165 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */
1166 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */
1167
1168 #define MDCR_EPMAD (1U << 21)
1169 #define MDCR_EDAD (1U << 20)
1170 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */
1171 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
1172 #define MDCR_SDD (1U << 16)
1173 #define MDCR_SPD (3U << 14)
1174 #define MDCR_TDRA (1U << 11)
1175 #define MDCR_TDOSA (1U << 10)
1176 #define MDCR_TDA (1U << 9)
1177 #define MDCR_TDE (1U << 8)
1178 #define MDCR_HPME (1U << 7)
1179 #define MDCR_TPM (1U << 6)
1180 #define MDCR_TPMCR (1U << 5)
1181 #define MDCR_HPMN (0x1fU)
1182
1183 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
1184 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
1185
1186 #define CPSR_M (0x1fU)
1187 #define CPSR_T (1U << 5)
1188 #define CPSR_F (1U << 6)
1189 #define CPSR_I (1U << 7)
1190 #define CPSR_A (1U << 8)
1191 #define CPSR_E (1U << 9)
1192 #define CPSR_IT_2_7 (0xfc00U)
1193 #define CPSR_GE (0xfU << 16)
1194 #define CPSR_IL (1U << 20)
1195 #define CPSR_PAN (1U << 22)
1196 #define CPSR_J (1U << 24)
1197 #define CPSR_IT_0_1 (3U << 25)
1198 #define CPSR_Q (1U << 27)
1199 #define CPSR_V (1U << 28)
1200 #define CPSR_C (1U << 29)
1201 #define CPSR_Z (1U << 30)
1202 #define CPSR_N (1U << 31)
1203 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1204 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1205
1206 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1207 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1208 | CPSR_NZCV)
1209 /* Bits writable in user mode. */
1210 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
1211 /* Execution state bits. MRS read as zero, MSR writes ignored. */
1212 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1213
1214 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */
1215 #define XPSR_EXCP 0x1ffU
1216 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */
1217 #define XPSR_IT_2_7 CPSR_IT_2_7
1218 #define XPSR_GE CPSR_GE
1219 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */
1220 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */
1221 #define XPSR_IT_0_1 CPSR_IT_0_1
1222 #define XPSR_Q CPSR_Q
1223 #define XPSR_V CPSR_V
1224 #define XPSR_C CPSR_C
1225 #define XPSR_Z CPSR_Z
1226 #define XPSR_N CPSR_N
1227 #define XPSR_NZCV CPSR_NZCV
1228 #define XPSR_IT CPSR_IT
1229
1230 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
1231 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
1232 #define TTBCR_PD0 (1U << 4)
1233 #define TTBCR_PD1 (1U << 5)
1234 #define TTBCR_EPD0 (1U << 7)
1235 #define TTBCR_IRGN0 (3U << 8)
1236 #define TTBCR_ORGN0 (3U << 10)
1237 #define TTBCR_SH0 (3U << 12)
1238 #define TTBCR_T1SZ (3U << 16)
1239 #define TTBCR_A1 (1U << 22)
1240 #define TTBCR_EPD1 (1U << 23)
1241 #define TTBCR_IRGN1 (3U << 24)
1242 #define TTBCR_ORGN1 (3U << 26)
1243 #define TTBCR_SH1 (1U << 28)
1244 #define TTBCR_EAE (1U << 31)
1245
1246 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
1247 * Only these are valid when in AArch64 mode; in
1248 * AArch32 mode SPSRs are basically CPSR-format.
1249 */
1250 #define PSTATE_SP (1U)
1251 #define PSTATE_M (0xFU)
1252 #define PSTATE_nRW (1U << 4)
1253 #define PSTATE_F (1U << 6)
1254 #define PSTATE_I (1U << 7)
1255 #define PSTATE_A (1U << 8)
1256 #define PSTATE_D (1U << 9)
1257 #define PSTATE_BTYPE (3U << 10)
1258 #define PSTATE_IL (1U << 20)
1259 #define PSTATE_SS (1U << 21)
1260 #define PSTATE_PAN (1U << 22)
1261 #define PSTATE_UAO (1U << 23)
1262 #define PSTATE_V (1U << 28)
1263 #define PSTATE_C (1U << 29)
1264 #define PSTATE_Z (1U << 30)
1265 #define PSTATE_N (1U << 31)
1266 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1267 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1268 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1269 /* Mode values for AArch64 */
1270 #define PSTATE_MODE_EL3h 13
1271 #define PSTATE_MODE_EL3t 12
1272 #define PSTATE_MODE_EL2h 9
1273 #define PSTATE_MODE_EL2t 8
1274 #define PSTATE_MODE_EL1h 5
1275 #define PSTATE_MODE_EL1t 4
1276 #define PSTATE_MODE_EL0t 0
1277
1278 /* Write a new value to v7m.exception, thus transitioning into or out
1279 * of Handler mode; this may result in a change of active stack pointer.
1280 */
1281 void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1282
1283 /* Map EL and handler into a PSTATE_MODE. */
1284 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1285 {
1286 return (el << 2) | handler;
1287 }
1288
1289 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1290 * interprocessing, so we don't attempt to sync with the cpsr state used by
1291 * the 32 bit decoder.
1292 */
1293 static inline uint32_t pstate_read(CPUARMState *env)
1294 {
1295 int ZF;
1296
1297 ZF = (env->ZF == 0);
1298 return (env->NF & 0x80000000) | (ZF << 30)
1299 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1300 | env->pstate | env->daif | (env->btype << 10);
1301 }
1302
1303 static inline void pstate_write(CPUARMState *env, uint32_t val)
1304 {
1305 env->ZF = (~val) & PSTATE_Z;
1306 env->NF = val;
1307 env->CF = (val >> 29) & 1;
1308 env->VF = (val << 3) & 0x80000000;
1309 env->daif = val & PSTATE_DAIF;
1310 env->btype = (val >> 10) & 3;
1311 env->pstate = val & ~CACHED_PSTATE_BITS;
1312 }
1313
1314 /* Return the current CPSR value. */
1315 uint32_t cpsr_read(CPUARMState *env);
1316
1317 typedef enum CPSRWriteType {
1318 CPSRWriteByInstr = 0, /* from guest MSR or CPS */
1319 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
1320 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */
1321 CPSRWriteByGDBStub = 3, /* from the GDB stub */
1322 } CPSRWriteType;
1323
1324 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/
1325 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1326 CPSRWriteType write_type);
1327
1328 /* Return the current xPSR value. */
1329 static inline uint32_t xpsr_read(CPUARMState *env)
1330 {
1331 int ZF;
1332 ZF = (env->ZF == 0);
1333 return (env->NF & 0x80000000) | (ZF << 30)
1334 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1335 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1336 | ((env->condexec_bits & 0xfc) << 8)
1337 | (env->GE << 16)
1338 | env->v7m.exception;
1339 }
1340
1341 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
1342 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1343 {
1344 if (mask & XPSR_NZCV) {
1345 env->ZF = (~val) & XPSR_Z;
1346 env->NF = val;
1347 env->CF = (val >> 29) & 1;
1348 env->VF = (val << 3) & 0x80000000;
1349 }
1350 if (mask & XPSR_Q) {
1351 env->QF = ((val & XPSR_Q) != 0);
1352 }
1353 if (mask & XPSR_GE) {
1354 env->GE = (val & XPSR_GE) >> 16;
1355 }
1356 #ifndef CONFIG_USER_ONLY
1357 if (mask & XPSR_T) {
1358 env->thumb = ((val & XPSR_T) != 0);
1359 }
1360 if (mask & XPSR_IT_0_1) {
1361 env->condexec_bits &= ~3;
1362 env->condexec_bits |= (val >> 25) & 3;
1363 }
1364 if (mask & XPSR_IT_2_7) {
1365 env->condexec_bits &= 3;
1366 env->condexec_bits |= (val >> 8) & 0xfc;
1367 }
1368 if (mask & XPSR_EXCP) {
1369 /* Note that this only happens on exception exit */
1370 write_v7m_exception(env, val & XPSR_EXCP);
1371 }
1372 #endif
1373 }
1374
1375 #define HCR_VM (1ULL << 0)
1376 #define HCR_SWIO (1ULL << 1)
1377 #define HCR_PTW (1ULL << 2)
1378 #define HCR_FMO (1ULL << 3)
1379 #define HCR_IMO (1ULL << 4)
1380 #define HCR_AMO (1ULL << 5)
1381 #define HCR_VF (1ULL << 6)
1382 #define HCR_VI (1ULL << 7)
1383 #define HCR_VSE (1ULL << 8)
1384 #define HCR_FB (1ULL << 9)
1385 #define HCR_BSU_MASK (3ULL << 10)
1386 #define HCR_DC (1ULL << 12)
1387 #define HCR_TWI (1ULL << 13)
1388 #define HCR_TWE (1ULL << 14)
1389 #define HCR_TID0 (1ULL << 15)
1390 #define HCR_TID1 (1ULL << 16)
1391 #define HCR_TID2 (1ULL << 17)
1392 #define HCR_TID3 (1ULL << 18)
1393 #define HCR_TSC (1ULL << 19)
1394 #define HCR_TIDCP (1ULL << 20)
1395 #define HCR_TACR (1ULL << 21)
1396 #define HCR_TSW (1ULL << 22)
1397 #define HCR_TPCP (1ULL << 23)
1398 #define HCR_TPU (1ULL << 24)
1399 #define HCR_TTLB (1ULL << 25)
1400 #define HCR_TVM (1ULL << 26)
1401 #define HCR_TGE (1ULL << 27)
1402 #define HCR_TDZ (1ULL << 28)
1403 #define HCR_HCD (1ULL << 29)
1404 #define HCR_TRVM (1ULL << 30)
1405 #define HCR_RW (1ULL << 31)
1406 #define HCR_CD (1ULL << 32)
1407 #define HCR_ID (1ULL << 33)
1408 #define HCR_E2H (1ULL << 34)
1409 #define HCR_TLOR (1ULL << 35)
1410 #define HCR_TERR (1ULL << 36)
1411 #define HCR_TEA (1ULL << 37)
1412 #define HCR_MIOCNCE (1ULL << 38)
1413 /* RES0 bit 39 */
1414 #define HCR_APK (1ULL << 40)
1415 #define HCR_API (1ULL << 41)
1416 #define HCR_NV (1ULL << 42)
1417 #define HCR_NV1 (1ULL << 43)
1418 #define HCR_AT (1ULL << 44)
1419 #define HCR_NV2 (1ULL << 45)
1420 #define HCR_FWB (1ULL << 46)
1421 #define HCR_FIEN (1ULL << 47)
1422 /* RES0 bit 48 */
1423 #define HCR_TID4 (1ULL << 49)
1424 #define HCR_TICAB (1ULL << 50)
1425 #define HCR_AMVOFFEN (1ULL << 51)
1426 #define HCR_TOCU (1ULL << 52)
1427 #define HCR_ENSCXT (1ULL << 53)
1428 #define HCR_TTLBIS (1ULL << 54)
1429 #define HCR_TTLBOS (1ULL << 55)
1430 #define HCR_ATA (1ULL << 56)
1431 #define HCR_DCT (1ULL << 57)
1432 #define HCR_TID5 (1ULL << 58)
1433 #define HCR_TWEDEN (1ULL << 59)
1434 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
1435
1436 #define SCR_NS (1U << 0)
1437 #define SCR_IRQ (1U << 1)
1438 #define SCR_FIQ (1U << 2)
1439 #define SCR_EA (1U << 3)
1440 #define SCR_FW (1U << 4)
1441 #define SCR_AW (1U << 5)
1442 #define SCR_NET (1U << 6)
1443 #define SCR_SMD (1U << 7)
1444 #define SCR_HCE (1U << 8)
1445 #define SCR_SIF (1U << 9)
1446 #define SCR_RW (1U << 10)
1447 #define SCR_ST (1U << 11)
1448 #define SCR_TWI (1U << 12)
1449 #define SCR_TWE (1U << 13)
1450 #define SCR_TLOR (1U << 14)
1451 #define SCR_TERR (1U << 15)
1452 #define SCR_APK (1U << 16)
1453 #define SCR_API (1U << 17)
1454 #define SCR_EEL2 (1U << 18)
1455 #define SCR_EASE (1U << 19)
1456 #define SCR_NMEA (1U << 20)
1457 #define SCR_FIEN (1U << 21)
1458 #define SCR_ENSCXT (1U << 25)
1459 #define SCR_ATA (1U << 26)
1460
1461 /* Return the current FPSCR value. */
1462 uint32_t vfp_get_fpscr(CPUARMState *env);
1463 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1464
1465 /* FPCR, Floating Point Control Register
1466 * FPSR, Floating Poiht Status Register
1467 *
1468 * For A64 the FPSCR is split into two logically distinct registers,
1469 * FPCR and FPSR. However since they still use non-overlapping bits
1470 * we store the underlying state in fpscr and just mask on read/write.
1471 */
1472 #define FPSR_MASK 0xf800009f
1473 #define FPCR_MASK 0x07ff9f00
1474
1475 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */
1476 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */
1477 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */
1478 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */
1479 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */
1480 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */
1481 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
1482 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
1483 #define FPCR_DN (1 << 25) /* Default NaN enable bit */
1484 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */
1485
1486 static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1487 {
1488 return vfp_get_fpscr(env) & FPSR_MASK;
1489 }
1490
1491 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1492 {
1493 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1494 vfp_set_fpscr(env, new_fpscr);
1495 }
1496
1497 static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1498 {
1499 return vfp_get_fpscr(env) & FPCR_MASK;
1500 }
1501
1502 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1503 {
1504 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1505 vfp_set_fpscr(env, new_fpscr);
1506 }
1507
1508 enum arm_cpu_mode {
1509 ARM_CPU_MODE_USR = 0x10,
1510 ARM_CPU_MODE_FIQ = 0x11,
1511 ARM_CPU_MODE_IRQ = 0x12,
1512 ARM_CPU_MODE_SVC = 0x13,
1513 ARM_CPU_MODE_MON = 0x16,
1514 ARM_CPU_MODE_ABT = 0x17,
1515 ARM_CPU_MODE_HYP = 0x1a,
1516 ARM_CPU_MODE_UND = 0x1b,
1517 ARM_CPU_MODE_SYS = 0x1f
1518 };
1519
1520 /* VFP system registers. */
1521 #define ARM_VFP_FPSID 0
1522 #define ARM_VFP_FPSCR 1
1523 #define ARM_VFP_MVFR2 5
1524 #define ARM_VFP_MVFR1 6
1525 #define ARM_VFP_MVFR0 7
1526 #define ARM_VFP_FPEXC 8
1527 #define ARM_VFP_FPINST 9
1528 #define ARM_VFP_FPINST2 10
1529
1530 /* iwMMXt coprocessor control registers. */
1531 #define ARM_IWMMXT_wCID 0
1532 #define ARM_IWMMXT_wCon 1
1533 #define ARM_IWMMXT_wCSSF 2
1534 #define ARM_IWMMXT_wCASF 3
1535 #define ARM_IWMMXT_wCGR0 8
1536 #define ARM_IWMMXT_wCGR1 9
1537 #define ARM_IWMMXT_wCGR2 10
1538 #define ARM_IWMMXT_wCGR3 11
1539
1540 /* V7M CCR bits */
1541 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1542 FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1543 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1544 FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1545 FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1546 FIELD(V7M_CCR, STKALIGN, 9, 1)
1547 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1548 FIELD(V7M_CCR, DC, 16, 1)
1549 FIELD(V7M_CCR, IC, 17, 1)
1550 FIELD(V7M_CCR, BP, 18, 1)
1551
1552 /* V7M SCR bits */
1553 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1554 FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1555 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1556 FIELD(V7M_SCR, SEVONPEND, 4, 1)
1557
1558 /* V7M AIRCR bits */
1559 FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1560 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1561 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1562 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1563 FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1564 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1565 FIELD(V7M_AIRCR, PRIS, 14, 1)
1566 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1567 FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1568
1569 /* V7M CFSR bits for MMFSR */
1570 FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1571 FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1572 FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1573 FIELD(V7M_CFSR, MSTKERR, 4, 1)
1574 FIELD(V7M_CFSR, MLSPERR, 5, 1)
1575 FIELD(V7M_CFSR, MMARVALID, 7, 1)
1576
1577 /* V7M CFSR bits for BFSR */
1578 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1579 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1580 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1581 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1582 FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1583 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1584 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1585
1586 /* V7M CFSR bits for UFSR */
1587 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1588 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1589 FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1590 FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1591 FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1592 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1593 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1594
1595 /* V7M CFSR bit masks covering all of the subregister bits */
1596 FIELD(V7M_CFSR, MMFSR, 0, 8)
1597 FIELD(V7M_CFSR, BFSR, 8, 8)
1598 FIELD(V7M_CFSR, UFSR, 16, 16)
1599
1600 /* V7M HFSR bits */
1601 FIELD(V7M_HFSR, VECTTBL, 1, 1)
1602 FIELD(V7M_HFSR, FORCED, 30, 1)
1603 FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1604
1605 /* V7M DFSR bits */
1606 FIELD(V7M_DFSR, HALTED, 0, 1)
1607 FIELD(V7M_DFSR, BKPT, 1, 1)
1608 FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1609 FIELD(V7M_DFSR, VCATCH, 3, 1)
1610 FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1611
1612 /* V7M SFSR bits */
1613 FIELD(V7M_SFSR, INVEP, 0, 1)
1614 FIELD(V7M_SFSR, INVIS, 1, 1)
1615 FIELD(V7M_SFSR, INVER, 2, 1)
1616 FIELD(V7M_SFSR, AUVIOL, 3, 1)
1617 FIELD(V7M_SFSR, INVTRAN, 4, 1)
1618 FIELD(V7M_SFSR, LSPERR, 5, 1)
1619 FIELD(V7M_SFSR, SFARVALID, 6, 1)
1620 FIELD(V7M_SFSR, LSERR, 7, 1)
1621
1622 /* v7M MPU_CTRL bits */
1623 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1624 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1625 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1626
1627 /* v7M CLIDR bits */
1628 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1629 FIELD(V7M_CLIDR, LOUIS, 21, 3)
1630 FIELD(V7M_CLIDR, LOC, 24, 3)
1631 FIELD(V7M_CLIDR, LOUU, 27, 3)
1632 FIELD(V7M_CLIDR, ICB, 30, 2)
1633
1634 FIELD(V7M_CSSELR, IND, 0, 1)
1635 FIELD(V7M_CSSELR, LEVEL, 1, 3)
1636 /* We use the combination of InD and Level to index into cpu->ccsidr[];
1637 * define a mask for this and check that it doesn't permit running off
1638 * the end of the array.
1639 */
1640 FIELD(V7M_CSSELR, INDEX, 0, 4)
1641
1642 /* v7M FPCCR bits */
1643 FIELD(V7M_FPCCR, LSPACT, 0, 1)
1644 FIELD(V7M_FPCCR, USER, 1, 1)
1645 FIELD(V7M_FPCCR, S, 2, 1)
1646 FIELD(V7M_FPCCR, THREAD, 3, 1)
1647 FIELD(V7M_FPCCR, HFRDY, 4, 1)
1648 FIELD(V7M_FPCCR, MMRDY, 5, 1)
1649 FIELD(V7M_FPCCR, BFRDY, 6, 1)
1650 FIELD(V7M_FPCCR, SFRDY, 7, 1)
1651 FIELD(V7M_FPCCR, MONRDY, 8, 1)
1652 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1653 FIELD(V7M_FPCCR, UFRDY, 10, 1)
1654 FIELD(V7M_FPCCR, RES0, 11, 15)
1655 FIELD(V7M_FPCCR, TS, 26, 1)
1656 FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1657 FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1658 FIELD(V7M_FPCCR, LSPENS, 29, 1)
1659 FIELD(V7M_FPCCR, LSPEN, 30, 1)
1660 FIELD(V7M_FPCCR, ASPEN, 31, 1)
1661 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */
1662 #define R_V7M_FPCCR_BANKED_MASK \
1663 (R_V7M_FPCCR_LSPACT_MASK | \
1664 R_V7M_FPCCR_USER_MASK | \
1665 R_V7M_FPCCR_THREAD_MASK | \
1666 R_V7M_FPCCR_MMRDY_MASK | \
1667 R_V7M_FPCCR_SPLIMVIOL_MASK | \
1668 R_V7M_FPCCR_UFRDY_MASK | \
1669 R_V7M_FPCCR_ASPEN_MASK)
1670
1671 /*
1672 * System register ID fields.
1673 */
1674 FIELD(MIDR_EL1, REVISION, 0, 4)
1675 FIELD(MIDR_EL1, PARTNUM, 4, 12)
1676 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
1677 FIELD(MIDR_EL1, VARIANT, 20, 4)
1678 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
1679
1680 FIELD(ID_ISAR0, SWAP, 0, 4)
1681 FIELD(ID_ISAR0, BITCOUNT, 4, 4)
1682 FIELD(ID_ISAR0, BITFIELD, 8, 4)
1683 FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
1684 FIELD(ID_ISAR0, COPROC, 16, 4)
1685 FIELD(ID_ISAR0, DEBUG, 20, 4)
1686 FIELD(ID_ISAR0, DIVIDE, 24, 4)
1687
1688 FIELD(ID_ISAR1, ENDIAN, 0, 4)
1689 FIELD(ID_ISAR1, EXCEPT, 4, 4)
1690 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
1691 FIELD(ID_ISAR1, EXTEND, 12, 4)
1692 FIELD(ID_ISAR1, IFTHEN, 16, 4)
1693 FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
1694 FIELD(ID_ISAR1, INTERWORK, 24, 4)
1695 FIELD(ID_ISAR1, JAZELLE, 28, 4)
1696
1697 FIELD(ID_ISAR2, LOADSTORE, 0, 4)
1698 FIELD(ID_ISAR2, MEMHINT, 4, 4)
1699 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
1700 FIELD(ID_ISAR2, MULT, 12, 4)
1701 FIELD(ID_ISAR2, MULTS, 16, 4)
1702 FIELD(ID_ISAR2, MULTU, 20, 4)
1703 FIELD(ID_ISAR2, PSR_AR, 24, 4)
1704 FIELD(ID_ISAR2, REVERSAL, 28, 4)
1705
1706 FIELD(ID_ISAR3, SATURATE, 0, 4)
1707 FIELD(ID_ISAR3, SIMD, 4, 4)
1708 FIELD(ID_ISAR3, SVC, 8, 4)
1709 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
1710 FIELD(ID_ISAR3, TABBRANCH, 16, 4)
1711 FIELD(ID_ISAR3, T32COPY, 20, 4)
1712 FIELD(ID_ISAR3, TRUENOP, 24, 4)
1713 FIELD(ID_ISAR3, T32EE, 28, 4)
1714
1715 FIELD(ID_ISAR4, UNPRIV, 0, 4)
1716 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
1717 FIELD(ID_ISAR4, WRITEBACK, 8, 4)
1718 FIELD(ID_ISAR4, SMC, 12, 4)
1719 FIELD(ID_ISAR4, BARRIER, 16, 4)
1720 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
1721 FIELD(ID_ISAR4, PSR_M, 24, 4)
1722 FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
1723
1724 FIELD(ID_ISAR5, SEVL, 0, 4)
1725 FIELD(ID_ISAR5, AES, 4, 4)
1726 FIELD(ID_ISAR5, SHA1, 8, 4)
1727 FIELD(ID_ISAR5, SHA2, 12, 4)
1728 FIELD(ID_ISAR5, CRC32, 16, 4)
1729 FIELD(ID_ISAR5, RDM, 24, 4)
1730 FIELD(ID_ISAR5, VCMA, 28, 4)
1731
1732 FIELD(ID_ISAR6, JSCVT, 0, 4)
1733 FIELD(ID_ISAR6, DP, 4, 4)
1734 FIELD(ID_ISAR6, FHM, 8, 4)
1735 FIELD(ID_ISAR6, SB, 12, 4)
1736 FIELD(ID_ISAR6, SPECRES, 16, 4)
1737
1738 FIELD(ID_MMFR3, CMAINTVA, 0, 4)
1739 FIELD(ID_MMFR3, CMAINTSW, 4, 4)
1740 FIELD(ID_MMFR3, BPMAINT, 8, 4)
1741 FIELD(ID_MMFR3, MAINTBCST, 12, 4)
1742 FIELD(ID_MMFR3, PAN, 16, 4)
1743 FIELD(ID_MMFR3, COHWALK, 20, 4)
1744 FIELD(ID_MMFR3, CMEMSZ, 24, 4)
1745 FIELD(ID_MMFR3, SUPERSEC, 28, 4)
1746
1747 FIELD(ID_MMFR4, SPECSEI, 0, 4)
1748 FIELD(ID_MMFR4, AC2, 4, 4)
1749 FIELD(ID_MMFR4, XNX, 8, 4)
1750 FIELD(ID_MMFR4, CNP, 12, 4)
1751 FIELD(ID_MMFR4, HPDS, 16, 4)
1752 FIELD(ID_MMFR4, LSM, 20, 4)
1753 FIELD(ID_MMFR4, CCIDX, 24, 4)
1754 FIELD(ID_MMFR4, EVT, 28, 4)
1755
1756 FIELD(ID_AA64ISAR0, AES, 4, 4)
1757 FIELD(ID_AA64ISAR0, SHA1, 8, 4)
1758 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
1759 FIELD(ID_AA64ISAR0, CRC32, 16, 4)
1760 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
1761 FIELD(ID_AA64ISAR0, RDM, 28, 4)
1762 FIELD(ID_AA64ISAR0, SHA3, 32, 4)
1763 FIELD(ID_AA64ISAR0, SM3, 36, 4)
1764 FIELD(ID_AA64ISAR0, SM4, 40, 4)
1765 FIELD(ID_AA64ISAR0, DP, 44, 4)
1766 FIELD(ID_AA64ISAR0, FHM, 48, 4)
1767 FIELD(ID_AA64ISAR0, TS, 52, 4)
1768 FIELD(ID_AA64ISAR0, TLB, 56, 4)
1769 FIELD(ID_AA64ISAR0, RNDR, 60, 4)
1770
1771 FIELD(ID_AA64ISAR1, DPB, 0, 4)
1772 FIELD(ID_AA64ISAR1, APA, 4, 4)
1773 FIELD(ID_AA64ISAR1, API, 8, 4)
1774 FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
1775 FIELD(ID_AA64ISAR1, FCMA, 16, 4)
1776 FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
1777 FIELD(ID_AA64ISAR1, GPA, 24, 4)
1778 FIELD(ID_AA64ISAR1, GPI, 28, 4)
1779 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
1780 FIELD(ID_AA64ISAR1, SB, 36, 4)
1781 FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
1782
1783 FIELD(ID_AA64PFR0, EL0, 0, 4)
1784 FIELD(ID_AA64PFR0, EL1, 4, 4)
1785 FIELD(ID_AA64PFR0, EL2, 8, 4)
1786 FIELD(ID_AA64PFR0, EL3, 12, 4)
1787 FIELD(ID_AA64PFR0, FP, 16, 4)
1788 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
1789 FIELD(ID_AA64PFR0, GIC, 24, 4)
1790 FIELD(ID_AA64PFR0, RAS, 28, 4)
1791 FIELD(ID_AA64PFR0, SVE, 32, 4)
1792
1793 FIELD(ID_AA64PFR1, BT, 0, 4)
1794 FIELD(ID_AA64PFR1, SBSS, 4, 4)
1795 FIELD(ID_AA64PFR1, MTE, 8, 4)
1796 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
1797
1798 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
1799 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
1800 FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
1801 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
1802 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
1803 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
1804 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
1805 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
1806 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
1807 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
1808 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
1809 FIELD(ID_AA64MMFR0, EXS, 44, 4)
1810
1811 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
1812 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
1813 FIELD(ID_AA64MMFR1, VH, 8, 4)
1814 FIELD(ID_AA64MMFR1, HPDS, 12, 4)
1815 FIELD(ID_AA64MMFR1, LO, 16, 4)
1816 FIELD(ID_AA64MMFR1, PAN, 20, 4)
1817 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
1818 FIELD(ID_AA64MMFR1, XNX, 28, 4)
1819
1820 FIELD(ID_AA64MMFR2, CNP, 0, 4)
1821 FIELD(ID_AA64MMFR2, UAO, 4, 4)
1822 FIELD(ID_AA64MMFR2, LSM, 8, 4)
1823 FIELD(ID_AA64MMFR2, IESB, 12, 4)
1824 FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
1825 FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
1826 FIELD(ID_AA64MMFR2, NV, 24, 4)
1827 FIELD(ID_AA64MMFR2, ST, 28, 4)
1828 FIELD(ID_AA64MMFR2, AT, 32, 4)
1829 FIELD(ID_AA64MMFR2, IDS, 36, 4)
1830 FIELD(ID_AA64MMFR2, FWB, 40, 4)
1831 FIELD(ID_AA64MMFR2, TTL, 48, 4)
1832 FIELD(ID_AA64MMFR2, BBM, 52, 4)
1833 FIELD(ID_AA64MMFR2, EVT, 56, 4)
1834 FIELD(ID_AA64MMFR2, E0PD, 60, 4)
1835
1836 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
1837 FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
1838 FIELD(ID_AA64DFR0, PMUVER, 8, 4)
1839 FIELD(ID_AA64DFR0, BRPS, 12, 4)
1840 FIELD(ID_AA64DFR0, WRPS, 20, 4)
1841 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
1842 FIELD(ID_AA64DFR0, PMSVER, 32, 4)
1843 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
1844 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
1845
1846 FIELD(ID_DFR0, COPDBG, 0, 4)
1847 FIELD(ID_DFR0, COPSDBG, 4, 4)
1848 FIELD(ID_DFR0, MMAPDBG, 8, 4)
1849 FIELD(ID_DFR0, COPTRC, 12, 4)
1850 FIELD(ID_DFR0, MMAPTRC, 16, 4)
1851 FIELD(ID_DFR0, MPROFDBG, 20, 4)
1852 FIELD(ID_DFR0, PERFMON, 24, 4)
1853 FIELD(ID_DFR0, TRACEFILT, 28, 4)
1854
1855 FIELD(DBGDIDR, SE_IMP, 12, 1)
1856 FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
1857 FIELD(DBGDIDR, VERSION, 16, 4)
1858 FIELD(DBGDIDR, CTX_CMPS, 20, 4)
1859 FIELD(DBGDIDR, BRPS, 24, 4)
1860 FIELD(DBGDIDR, WRPS, 28, 4)
1861
1862 FIELD(MVFR0, SIMDREG, 0, 4)
1863 FIELD(MVFR0, FPSP, 4, 4)
1864 FIELD(MVFR0, FPDP, 8, 4)
1865 FIELD(MVFR0, FPTRAP, 12, 4)
1866 FIELD(MVFR0, FPDIVIDE, 16, 4)
1867 FIELD(MVFR0, FPSQRT, 20, 4)
1868 FIELD(MVFR0, FPSHVEC, 24, 4)
1869 FIELD(MVFR0, FPROUND, 28, 4)
1870
1871 FIELD(MVFR1, FPFTZ, 0, 4)
1872 FIELD(MVFR1, FPDNAN, 4, 4)
1873 FIELD(MVFR1, SIMDLS, 8, 4)
1874 FIELD(MVFR1, SIMDINT, 12, 4)
1875 FIELD(MVFR1, SIMDSP, 16, 4)
1876 FIELD(MVFR1, SIMDHP, 20, 4)
1877 FIELD(MVFR1, FPHP, 24, 4)
1878 FIELD(MVFR1, SIMDFMAC, 28, 4)
1879
1880 FIELD(MVFR2, SIMDMISC, 0, 4)
1881 FIELD(MVFR2, FPMISC, 4, 4)
1882
1883 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
1884
1885 /* If adding a feature bit which corresponds to a Linux ELF
1886 * HWCAP bit, remember to update the feature-bit-to-hwcap
1887 * mapping in linux-user/elfload.c:get_elf_hwcap().
1888 */
1889 enum arm_features {
1890 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
1891 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
1892 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
1893 ARM_FEATURE_V6,
1894 ARM_FEATURE_V6K,
1895 ARM_FEATURE_V7,
1896 ARM_FEATURE_THUMB2,
1897 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */
1898 ARM_FEATURE_NEON,
1899 ARM_FEATURE_M, /* Microcontroller profile. */
1900 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
1901 ARM_FEATURE_THUMB2EE,
1902 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
1903 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
1904 ARM_FEATURE_V4T,
1905 ARM_FEATURE_V5,
1906 ARM_FEATURE_STRONGARM,
1907 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
1908 ARM_FEATURE_GENERIC_TIMER,
1909 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
1910 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
1911 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
1912 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
1913 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
1914 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
1915 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
1916 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
1917 ARM_FEATURE_V8,
1918 ARM_FEATURE_AARCH64, /* supports 64 bit mode */
1919 ARM_FEATURE_CBAR, /* has cp15 CBAR */
1920 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */
1921 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
1922 ARM_FEATURE_EL2, /* has EL2 Virtualization support */
1923 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
1924 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
1925 ARM_FEATURE_PMU, /* has PMU support */
1926 ARM_FEATURE_VBAR, /* has cp15 VBAR */
1927 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
1928 ARM_FEATURE_M_MAIN, /* M profile Main Extension */
1929 };
1930
1931 static inline int arm_feature(CPUARMState *env, int feature)
1932 {
1933 return (env->features & (1ULL << feature)) != 0;
1934 }
1935
1936 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
1937
1938 #if !defined(CONFIG_USER_ONLY)
1939 /* Return true if exception levels below EL3 are in secure state,
1940 * or would be following an exception return to that level.
1941 * Unlike arm_is_secure() (which is always a question about the
1942 * _current_ state of the CPU) this doesn't care about the current
1943 * EL or mode.
1944 */
1945 static inline bool arm_is_secure_below_el3(CPUARMState *env)
1946 {
1947 if (arm_feature(env, ARM_FEATURE_EL3)) {
1948 return !(env->cp15.scr_el3 & SCR_NS);
1949 } else {
1950 /* If EL3 is not supported then the secure state is implementation
1951 * defined, in which case QEMU defaults to non-secure.
1952 */
1953 return false;
1954 }
1955 }
1956
1957 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
1958 static inline bool arm_is_el3_or_mon(CPUARMState *env)
1959 {
1960 if (arm_feature(env, ARM_FEATURE_EL3)) {
1961 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
1962 /* CPU currently in AArch64 state and EL3 */
1963 return true;
1964 } else if (!is_a64(env) &&
1965 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
1966 /* CPU currently in AArch32 state and monitor mode */
1967 return true;
1968 }
1969 }
1970 return false;
1971 }
1972
1973 /* Return true if the processor is in secure state */
1974 static inline bool arm_is_secure(CPUARMState *env)
1975 {
1976 if (arm_is_el3_or_mon(env)) {
1977 return true;
1978 }
1979 return arm_is_secure_below_el3(env);
1980 }
1981
1982 #else
1983 static inline bool arm_is_secure_below_el3(CPUARMState *env)
1984 {
1985 return false;
1986 }
1987
1988 static inline bool arm_is_secure(CPUARMState *env)
1989 {
1990 return false;
1991 }
1992 #endif
1993
1994 /**
1995 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2.
1996 * E.g. when in secure state, fields in HCR_EL2 are suppressed,
1997 * "for all purposes other than a direct read or write access of HCR_EL2."
1998 * Not included here is HCR_RW.
1999 */
2000 uint64_t arm_hcr_el2_eff(CPUARMState *env);
2001
2002 /* Return true if the specified exception level is running in AArch64 state. */
2003 static inline bool arm_el_is_aa64(CPUARMState *env, int el)
2004 {
2005 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
2006 * and if we're not in EL0 then the state of EL0 isn't well defined.)
2007 */
2008 assert(el >= 1 && el <= 3);
2009 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
2010
2011 /* The highest exception level is always at the maximum supported
2012 * register width, and then lower levels have a register width controlled
2013 * by bits in the SCR or HCR registers.
2014 */
2015 if (el == 3) {
2016 return aa64;
2017 }
2018
2019 if (arm_feature(env, ARM_FEATURE_EL3)) {
2020 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
2021 }
2022
2023 if (el == 2) {
2024 return aa64;
2025 }
2026
2027 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) {
2028 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
2029 }
2030
2031 return aa64;
2032 }
2033
2034 /* Function for determing whether guest cp register reads and writes should
2035 * access the secure or non-secure bank of a cp register. When EL3 is
2036 * operating in AArch32 state, the NS-bit determines whether the secure
2037 * instance of a cp register should be used. When EL3 is AArch64 (or if
2038 * it doesn't exist at all) then there is no register banking, and all
2039 * accesses are to the non-secure version.
2040 */
2041 static inline bool access_secure_reg(CPUARMState *env)
2042 {
2043 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
2044 !arm_el_is_aa64(env, 3) &&
2045 !(env->cp15.scr_el3 & SCR_NS));
2046
2047 return ret;
2048 }
2049
2050 /* Macros for accessing a specified CP register bank */
2051 #define A32_BANKED_REG_GET(_env, _regname, _secure) \
2052 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
2053
2054 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
2055 do { \
2056 if (_secure) { \
2057 (_env)->cp15._regname##_s = (_val); \
2058 } else { \
2059 (_env)->cp15._regname##_ns = (_val); \
2060 } \
2061 } while (0)
2062
2063 /* Macros for automatically accessing a specific CP register bank depending on
2064 * the current secure state of the system. These macros are not intended for
2065 * supporting instruction translation reads/writes as these are dependent
2066 * solely on the SCR.NS bit and not the mode.
2067 */
2068 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
2069 A32_BANKED_REG_GET((_env), _regname, \
2070 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
2071
2072 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
2073 A32_BANKED_REG_SET((_env), _regname, \
2074 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
2075 (_val))
2076
2077 void arm_cpu_list(void);
2078 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
2079 uint32_t cur_el, bool secure);
2080
2081 /* Interface between CPU and Interrupt controller. */
2082 #ifndef CONFIG_USER_ONLY
2083 bool armv7m_nvic_can_take_pending_exception(void *opaque);
2084 #else
2085 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
2086 {
2087 return true;
2088 }
2089 #endif
2090 /**
2091 * armv7m_nvic_set_pending: mark the specified exception as pending
2092 * @opaque: the NVIC
2093 * @irq: the exception number to mark pending
2094 * @secure: false for non-banked exceptions or for the nonsecure
2095 * version of a banked exception, true for the secure version of a banked
2096 * exception.
2097 *
2098 * Marks the specified exception as pending. Note that we will assert()
2099 * if @secure is true and @irq does not specify one of the fixed set
2100 * of architecturally banked exceptions.
2101 */
2102 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
2103 /**
2104 * armv7m_nvic_set_pending_derived: mark this derived exception as pending
2105 * @opaque: the NVIC
2106 * @irq: the exception number to mark pending
2107 * @secure: false for non-banked exceptions or for the nonsecure
2108 * version of a banked exception, true for the secure version of a banked
2109 * exception.
2110 *
2111 * Similar to armv7m_nvic_set_pending(), but specifically for derived
2112 * exceptions (exceptions generated in the course of trying to take
2113 * a different exception).
2114 */
2115 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
2116 /**
2117 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
2118 * @opaque: the NVIC
2119 * @irq: the exception number to mark pending
2120 * @secure: false for non-banked exceptions or for the nonsecure
2121 * version of a banked exception, true for the secure version of a banked
2122 * exception.
2123 *
2124 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
2125 * generated in the course of lazy stacking of FP registers.
2126 */
2127 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
2128 /**
2129 * armv7m_nvic_get_pending_irq_info: return highest priority pending
2130 * exception, and whether it targets Secure state
2131 * @opaque: the NVIC
2132 * @pirq: set to pending exception number
2133 * @ptargets_secure: set to whether pending exception targets Secure
2134 *
2135 * This function writes the number of the highest priority pending
2136 * exception (the one which would be made active by
2137 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
2138 * to true if the current highest priority pending exception should
2139 * be taken to Secure state, false for NS.
2140 */
2141 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
2142 bool *ptargets_secure);
2143 /**
2144 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
2145 * @opaque: the NVIC
2146 *
2147 * Move the current highest priority pending exception from the pending
2148 * state to the active state, and update v7m.exception to indicate that
2149 * it is the exception currently being handled.
2150 */
2151 void armv7m_nvic_acknowledge_irq(void *opaque);
2152 /**
2153 * armv7m_nvic_complete_irq: complete specified interrupt or exception
2154 * @opaque: the NVIC
2155 * @irq: the exception number to complete
2156 * @secure: true if this exception was secure
2157 *
2158 * Returns: -1 if the irq was not active
2159 * 1 if completing this irq brought us back to base (no active irqs)
2160 * 0 if there is still an irq active after this one was completed
2161 * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
2162 */
2163 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
2164 /**
2165 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
2166 * @opaque: the NVIC
2167 * @irq: the exception number to mark pending
2168 * @secure: false for non-banked exceptions or for the nonsecure
2169 * version of a banked exception, true for the secure version of a banked
2170 * exception.
2171 *
2172 * Return whether an exception is "ready", i.e. whether the exception is
2173 * enabled and is configured at a priority which would allow it to
2174 * interrupt the current execution priority. This controls whether the
2175 * RDY bit for it in the FPCCR is set.
2176 */
2177 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
2178 /**
2179 * armv7m_nvic_raw_execution_priority: return the raw execution priority
2180 * @opaque: the NVIC
2181 *
2182 * Returns: the raw execution priority as defined by the v8M architecture.
2183 * This is the execution priority minus the effects of AIRCR.PRIS,
2184 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
2185 * (v8M ARM ARM I_PKLD.)
2186 */
2187 int armv7m_nvic_raw_execution_priority(void *opaque);
2188 /**
2189 * armv7m_nvic_neg_prio_requested: return true if the requested execution
2190 * priority is negative for the specified security state.
2191 * @opaque: the NVIC
2192 * @secure: the security state to test
2193 * This corresponds to the pseudocode IsReqExecPriNeg().
2194 */
2195 #ifndef CONFIG_USER_ONLY
2196 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
2197 #else
2198 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
2199 {
2200 return false;
2201 }
2202 #endif
2203
2204 /* Interface for defining coprocessor registers.
2205 * Registers are defined in tables of arm_cp_reginfo structs
2206 * which are passed to define_arm_cp_regs().
2207 */
2208
2209 /* When looking up a coprocessor register we look for it
2210 * via an integer which encodes all of:
2211 * coprocessor number
2212 * Crn, Crm, opc1, opc2 fields
2213 * 32 or 64 bit register (ie is it accessed via MRC/MCR
2214 * or via MRRC/MCRR?)
2215 * non-secure/secure bank (AArch32 only)
2216 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
2217 * (In this case crn and opc2 should be zero.)
2218 * For AArch64, there is no 32/64 bit size distinction;
2219 * instead all registers have a 2 bit op0, 3 bit op1 and op2,
2220 * and 4 bit CRn and CRm. The encoding patterns are chosen
2221 * to be easy to convert to and from the KVM encodings, and also
2222 * so that the hashtable can contain both AArch32 and AArch64
2223 * registers (to allow for interprocessing where we might run
2224 * 32 bit code on a 64 bit core).
2225 */
2226 /* This bit is private to our hashtable cpreg; in KVM register
2227 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
2228 * in the upper bits of the 64 bit ID.
2229 */
2230 #define CP_REG_AA64_SHIFT 28
2231 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
2232
2233 /* To enable banking of coprocessor registers depending on ns-bit we
2234 * add a bit to distinguish between secure and non-secure cpregs in the
2235 * hashtable.
2236 */
2237 #define CP_REG_NS_SHIFT 29
2238 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
2239
2240 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
2241 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
2242 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
2243
2244 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
2245 (CP_REG_AA64_MASK | \
2246 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
2247 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
2248 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
2249 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
2250 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
2251 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
2252
2253 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
2254 * version used as a key for the coprocessor register hashtable
2255 */
2256 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
2257 {
2258 uint32_t cpregid = kvmid;
2259 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
2260 cpregid |= CP_REG_AA64_MASK;
2261 } else {
2262 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
2263 cpregid |= (1 << 15);
2264 }
2265
2266 /* KVM is always non-secure so add the NS flag on AArch32 register
2267 * entries.
2268 */
2269 cpregid |= 1 << CP_REG_NS_SHIFT;
2270 }
2271 return cpregid;
2272 }
2273
2274 /* Convert a truncated 32 bit hashtable key into the full
2275 * 64 bit KVM register ID.
2276 */
2277 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
2278 {
2279 uint64_t kvmid;
2280
2281 if (cpregid & CP_REG_AA64_MASK) {
2282 kvmid = cpregid & ~CP_REG_AA64_MASK;
2283 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
2284 } else {
2285 kvmid = cpregid & ~(1 << 15);
2286 if (cpregid & (1 << 15)) {
2287 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
2288 } else {
2289 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
2290 }
2291 }
2292 return kvmid;
2293 }
2294
2295 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
2296 * special-behaviour cp reg and bits [11..8] indicate what behaviour
2297 * it has. Otherwise it is a simple cp reg, where CONST indicates that
2298 * TCG can assume the value to be constant (ie load at translate time)
2299 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
2300 * indicates that the TB should not be ended after a write to this register
2301 * (the default is that the TB ends after cp writes). OVERRIDE permits
2302 * a register definition to override a previous definition for the
2303 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
2304 * old must have the OVERRIDE bit set.
2305 * ALIAS indicates that this register is an alias view of some underlying
2306 * state which is also visible via another register, and that the other
2307 * register is handling migration and reset; registers marked ALIAS will not be
2308 * migrated but may have their state set by syncing of register state from KVM.
2309 * NO_RAW indicates that this register has no underlying state and does not
2310 * support raw access for state saving/loading; it will not be used for either
2311 * migration or KVM state synchronization. (Typically this is for "registers"
2312 * which are actually used as instructions for cache maintenance and so on.)
2313 * IO indicates that this register does I/O and therefore its accesses
2314 * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
2315 * registers which implement clocks or timers require this.
2316 * RAISES_EXC is for when the read or write hook might raise an exception;
2317 * the generated code will synchronize the CPU state before calling the hook
2318 * so that it is safe for the hook to call raise_exception().
2319 * NEWEL is for writes to registers that might change the exception
2320 * level - typically on older ARM chips. For those cases we need to
2321 * re-read the new el when recomputing the translation flags.
2322 */
2323 #define ARM_CP_SPECIAL 0x0001
2324 #define ARM_CP_CONST 0x0002
2325 #define ARM_CP_64BIT 0x0004
2326 #define ARM_CP_SUPPRESS_TB_END 0x0008
2327 #define ARM_CP_OVERRIDE 0x0010
2328 #define ARM_CP_ALIAS 0x0020
2329 #define ARM_CP_IO 0x0040
2330 #define ARM_CP_NO_RAW 0x0080
2331 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100)
2332 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200)
2333 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
2334 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
2335 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
2336 #define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
2337 #define ARM_CP_FPU 0x1000
2338 #define ARM_CP_SVE 0x2000
2339 #define ARM_CP_NO_GDB 0x4000
2340 #define ARM_CP_RAISES_EXC 0x8000
2341 #define ARM_CP_NEWEL 0x10000
2342 /* Used only as a terminator for ARMCPRegInfo lists */
2343 #define ARM_CP_SENTINEL 0xfffff
2344 /* Mask of only the flag bits in a type field */
2345 #define ARM_CP_FLAG_MASK 0x1f0ff
2346
2347 /* Valid values for ARMCPRegInfo state field, indicating which of
2348 * the AArch32 and AArch64 execution states this register is visible in.
2349 * If the reginfo doesn't explicitly specify then it is AArch32 only.
2350 * If the reginfo is declared to be visible in both states then a second
2351 * reginfo is synthesised for the AArch32 view of the AArch64 register,
2352 * such that the AArch32 view is the lower 32 bits of the AArch64 one.
2353 * Note that we rely on the values of these enums as we iterate through
2354 * the various states in some places.
2355 */
2356 enum {
2357 ARM_CP_STATE_AA32 = 0,
2358 ARM_CP_STATE_AA64 = 1,
2359 ARM_CP_STATE_BOTH = 2,
2360 };
2361
2362 /* ARM CP register secure state flags. These flags identify security state
2363 * attributes for a given CP register entry.
2364 * The existence of both or neither secure and non-secure flags indicates that
2365 * the register has both a secure and non-secure hash entry. A single one of
2366 * these flags causes the register to only be hashed for the specified
2367 * security state.
2368 * Although definitions may have any combination of the S/NS bits, each
2369 * registered entry will only have one to identify whether the entry is secure
2370 * or non-secure.
2371 */
2372 enum {
2373 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */
2374 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */
2375 };
2376
2377 /* Return true if cptype is a valid type field. This is used to try to
2378 * catch errors where the sentinel has been accidentally left off the end
2379 * of a list of registers.
2380 */
2381 static inline bool cptype_valid(int cptype)
2382 {
2383 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
2384 || ((cptype & ARM_CP_SPECIAL) &&
2385 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
2386 }
2387
2388 /* Access rights:
2389 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
2390 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
2391 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
2392 * (ie any of the privileged modes in Secure state, or Monitor mode).
2393 * If a register is accessible in one privilege level it's always accessible
2394 * in higher privilege levels too. Since "Secure PL1" also follows this rule
2395 * (ie anything visible in PL2 is visible in S-PL1, some things are only
2396 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
2397 * terminology a little and call this PL3.
2398 * In AArch64 things are somewhat simpler as the PLx bits line up exactly
2399 * with the ELx exception levels.
2400 *
2401 * If access permissions for a register are more complex than can be
2402 * described with these bits, then use a laxer set of restrictions, and
2403 * do the more restrictive/complex check inside a helper function.
2404 */
2405 #define PL3_R 0x80
2406 #define PL3_W 0x40
2407 #define PL2_R (0x20 | PL3_R)
2408 #define PL2_W (0x10 | PL3_W)
2409 #define PL1_R (0x08 | PL2_R)
2410 #define PL1_W (0x04 | PL2_W)
2411 #define PL0_R (0x02 | PL1_R)
2412 #define PL0_W (0x01 | PL1_W)
2413
2414 /*
2415 * For user-mode some registers are accessible to EL0 via a kernel
2416 * trap-and-emulate ABI. In this case we define the read permissions
2417 * as actually being PL0_R. However some bits of any given register
2418 * may still be masked.
2419 */
2420 #ifdef CONFIG_USER_ONLY
2421 #define PL0U_R PL0_R
2422 #else
2423 #define PL0U_R PL1_R
2424 #endif
2425
2426 #define PL3_RW (PL3_R | PL3_W)
2427 #define PL2_RW (PL2_R | PL2_W)
2428 #define PL1_RW (PL1_R | PL1_W)
2429 #define PL0_RW (PL0_R | PL0_W)
2430
2431 /* Return the highest implemented Exception Level */
2432 static inline int arm_highest_el(CPUARMState *env)
2433 {
2434 if (arm_feature(env, ARM_FEATURE_EL3)) {
2435 return 3;
2436 }
2437 if (arm_feature(env, ARM_FEATURE_EL2)) {
2438 return 2;
2439 }
2440 return 1;
2441 }
2442
2443 /* Return true if a v7M CPU is in Handler mode */
2444 static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2445 {
2446 return env->v7m.exception != 0;
2447 }
2448
2449 /* Return the current Exception Level (as per ARMv8; note that this differs
2450 * from the ARMv7 Privilege Level).
2451 */
2452 static inline int arm_current_el(CPUARMState *env)
2453 {
2454 if (arm_feature(env, ARM_FEATURE_M)) {
2455 return arm_v7m_is_handler_mode(env) ||
2456 !(env->v7m.control[env->v7m.secure] & 1);
2457 }
2458
2459 if (is_a64(env)) {
2460 return extract32(env->pstate, 2, 2);
2461 }
2462
2463 switch (env->uncached_cpsr & 0x1f) {
2464 case ARM_CPU_MODE_USR:
2465 return 0;
2466 case ARM_CPU_MODE_HYP:
2467 return 2;
2468 case ARM_CPU_MODE_MON:
2469 return 3;
2470 default:
2471 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2472 /* If EL3 is 32-bit then all secure privileged modes run in
2473 * EL3
2474 */
2475 return 3;
2476 }
2477
2478 return 1;
2479 }
2480 }
2481
2482 typedef struct ARMCPRegInfo ARMCPRegInfo;
2483
2484 typedef enum CPAccessResult {
2485 /* Access is permitted */
2486 CP_ACCESS_OK = 0,
2487 /* Access fails due to a configurable trap or enable which would
2488 * result in a categorized exception syndrome giving information about
2489 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
2490 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
2491 * PL1 if in EL0, otherwise to the current EL).
2492 */
2493 CP_ACCESS_TRAP = 1,
2494 /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
2495 * Note that this is not a catch-all case -- the set of cases which may
2496 * result in this failure is specifically defined by the architecture.
2497 */
2498 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
2499 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
2500 CP_ACCESS_TRAP_EL2 = 3,
2501 CP_ACCESS_TRAP_EL3 = 4,
2502 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
2503 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
2504 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
2505 /* Access fails and results in an exception syndrome for an FP access,
2506 * trapped directly to EL2 or EL3
2507 */
2508 CP_ACCESS_TRAP_FP_EL2 = 7,
2509 CP_ACCESS_TRAP_FP_EL3 = 8,
2510 } CPAccessResult;
2511
2512 /* Access functions for coprocessor registers. These cannot fail and
2513 * may not raise exceptions.
2514 */
2515 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2516 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
2517 uint64_t value);
2518 /* Access permission check functions for coprocessor registers. */
2519 typedef CPAccessResult CPAccessFn(CPUARMState *env,
2520 const ARMCPRegInfo *opaque,
2521 bool isread);
2522 /* Hook function for register reset */
2523 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2524
2525 #define CP_ANY 0xff
2526
2527 /* Definition of an ARM coprocessor register */
2528 struct ARMCPRegInfo {
2529 /* Name of register (useful mainly for debugging, need not be unique) */
2530 const char *name;
2531 /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
2532 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
2533 * 'wildcard' field -- any value of that field in the MRC/MCR insn
2534 * will be decoded to this register. The register read and write
2535 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
2536 * used by the program, so it is possible to register a wildcard and
2537 * then behave differently on read/write if necessary.
2538 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
2539 * must both be zero.
2540 * For AArch64-visible registers, opc0 is also used.
2541 * Since there are no "coprocessors" in AArch64, cp is purely used as a
2542 * way to distinguish (for KVM's benefit) guest-visible system registers
2543 * from demuxed ones provided to preserve the "no side effects on
2544 * KVM register read/write from QEMU" semantics. cp==0x13 is guest
2545 * visible (to match KVM's encoding); cp==0 will be converted to
2546 * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
2547 */
2548 uint8_t cp;
2549 uint8_t crn;
2550 uint8_t crm;
2551 uint8_t opc0;
2552 uint8_t opc1;
2553 uint8_t opc2;
2554 /* Execution state in which this register is visible: ARM_CP_STATE_* */
2555 int state;
2556 /* Register type: ARM_CP_* bits/values */
2557 int type;
2558 /* Access rights: PL*_[RW] */
2559 int access;
2560 /* Security state: ARM_CP_SECSTATE_* bits/values */
2561 int secure;
2562 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
2563 * this register was defined: can be used to hand data through to the
2564 * register read/write functions, since they are passed the ARMCPRegInfo*.
2565 */
2566 void *opaque;
2567 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
2568 * fieldoffset is non-zero, the reset value of the register.
2569 */
2570 uint64_t resetvalue;
2571 /* Offset of the field in CPUARMState for this register.
2572 *
2573 * This is not needed if either:
2574 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
2575 * 2. both readfn and writefn are specified
2576 */
2577 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
2578
2579 /* Offsets of the secure and non-secure fields in CPUARMState for the
2580 * register if it is banked. These fields are only used during the static
2581 * registration of a register. During hashing the bank associated
2582 * with a given security state is copied to fieldoffset which is used from
2583 * there on out.
2584 *
2585 * It is expected that register definitions use either fieldoffset or
2586 * bank_fieldoffsets in the definition but not both. It is also expected
2587 * that both bank offsets are set when defining a banked register. This
2588 * use indicates that a register is banked.
2589 */
2590 ptrdiff_t bank_fieldoffsets[2];
2591
2592 /* Function for making any access checks for this register in addition to
2593 * those specified by the 'access' permissions bits. If NULL, no extra
2594 * checks required. The access check is performed at runtime, not at
2595 * translate time.
2596 */
2597 CPAccessFn *accessfn;
2598 /* Function for handling reads of this register. If NULL, then reads
2599 * will be done by loading from the offset into CPUARMState specified
2600 * by fieldoffset.
2601 */
2602 CPReadFn *readfn;
2603 /* Function for handling writes of this register. If NULL, then writes
2604 * will be done by writing to the offset into CPUARMState specified
2605 * by fieldoffset.
2606 */
2607 CPWriteFn *writefn;
2608 /* Function for doing a "raw" read; used when we need to copy
2609 * coprocessor state to the kernel for KVM or out for
2610 * migration. This only needs to be provided if there is also a
2611 * readfn and it has side effects (for instance clear-on-read bits).
2612 */
2613 CPReadFn *raw_readfn;
2614 /* Function for doing a "raw" write; used when we need to copy KVM
2615 * kernel coprocessor state into userspace, or for inbound
2616 * migration. This only needs to be provided if there is also a
2617 * writefn and it masks out "unwritable" bits or has write-one-to-clear
2618 * or similar behaviour.
2619 */
2620 CPWriteFn *raw_writefn;
2621 /* Function for resetting the register. If NULL, then reset will be done
2622 * by writing resetvalue to the field specified in fieldoffset. If
2623 * fieldoffset is 0 then no reset will be done.
2624 */
2625 CPResetFn *resetfn;
2626
2627 /*
2628 * "Original" writefn and readfn.
2629 * For ARMv8.1-VHE register aliases, we overwrite the read/write
2630 * accessor functions of various EL1/EL0 to perform the runtime
2631 * check for which sysreg should actually be modified, and then
2632 * forwards the operation. Before overwriting the accessors,
2633 * the original function is copied here, so that accesses that
2634 * really do go to the EL1/EL0 version proceed normally.
2635 * (The corresponding EL2 register is linked via opaque.)
2636 */
2637 CPReadFn *orig_readfn;
2638 CPWriteFn *orig_writefn;
2639 };
2640
2641 /* Macros which are lvalues for the field in CPUARMState for the
2642 * ARMCPRegInfo *ri.
2643 */
2644 #define CPREG_FIELD32(env, ri) \
2645 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
2646 #define CPREG_FIELD64(env, ri) \
2647 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
2648
2649 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
2650
2651 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2652 const ARMCPRegInfo *regs, void *opaque);
2653 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2654 const ARMCPRegInfo *regs, void *opaque);
2655 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
2656 {
2657 define_arm_cp_regs_with_opaque(cpu, regs, 0);
2658 }
2659 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
2660 {
2661 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
2662 }
2663 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
2664
2665 /*
2666 * Definition of an ARM co-processor register as viewed from
2667 * userspace. This is used for presenting sanitised versions of
2668 * registers to userspace when emulating the Linux AArch64 CPU
2669 * ID/feature ABI (advertised as HWCAP_CPUID).
2670 */
2671 typedef struct ARMCPRegUserSpaceInfo {
2672 /* Name of register */
2673 const char *name;
2674
2675 /* Is the name actually a glob pattern */
2676 bool is_glob;
2677
2678 /* Only some bits are exported to user space */
2679 uint64_t exported_bits;
2680
2681 /* Fixed bits are applied after the mask */
2682 uint64_t fixed_bits;
2683 } ARMCPRegUserSpaceInfo;
2684
2685 #define REGUSERINFO_SENTINEL { .name = NULL }
2686
2687 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
2688
2689 /* CPWriteFn that can be used to implement writes-ignored behaviour */
2690 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2691 uint64_t value);
2692 /* CPReadFn that can be used for read-as-zero behaviour */
2693 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
2694
2695 /* CPResetFn that does nothing, for use if no reset is required even
2696 * if fieldoffset is non zero.
2697 */
2698 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
2699
2700 /* Return true if this reginfo struct's field in the cpu state struct
2701 * is 64 bits wide.
2702 */
2703 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
2704 {
2705 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
2706 }
2707
2708 static inline bool cp_access_ok(int current_el,
2709 const ARMCPRegInfo *ri, int isread)
2710 {
2711 return (ri->access >> ((current_el * 2) + isread)) & 1;
2712 }
2713
2714 /* Raw read of a coprocessor register (as needed for migration, etc) */
2715 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
2716
2717 /**
2718 * write_list_to_cpustate
2719 * @cpu: ARMCPU
2720 *
2721 * For each register listed in the ARMCPU cpreg_indexes list, write
2722 * its value from the cpreg_values list into the ARMCPUState structure.
2723 * This updates TCG's working data structures from KVM data or
2724 * from incoming migration state.
2725 *
2726 * Returns: true if all register values were updated correctly,
2727 * false if some register was unknown or could not be written.
2728 * Note that we do not stop early on failure -- we will attempt
2729 * writing all registers in the list.
2730 */
2731 bool write_list_to_cpustate(ARMCPU *cpu);
2732
2733 /**
2734 * write_cpustate_to_list:
2735 * @cpu: ARMCPU
2736 * @kvm_sync: true if this is for syncing back to KVM
2737 *
2738 * For each register listed in the ARMCPU cpreg_indexes list, write
2739 * its value from the ARMCPUState structure into the cpreg_values list.
2740 * This is used to copy info from TCG's working data structures into
2741 * KVM or for outbound migration.
2742 *
2743 * @kvm_sync is true if we are doing this in order to sync the
2744 * register state back to KVM. In this case we will only update
2745 * values in the list if the previous list->cpustate sync actually
2746 * successfully wrote the CPU state. Otherwise we will keep the value
2747 * that is in the list.
2748 *
2749 * Returns: true if all register values were read correctly,
2750 * false if some register was unknown or could not be read.
2751 * Note that we do not stop early on failure -- we will attempt
2752 * reading all registers in the list.
2753 */
2754 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
2755
2756 #define ARM_CPUID_TI915T 0x54029152
2757 #define ARM_CPUID_TI925T 0x54029252
2758
2759 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
2760 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
2761 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2762
2763 #define cpu_signal_handler cpu_arm_signal_handler
2764 #define cpu_list arm_cpu_list
2765
2766 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
2767 *
2768 * If EL3 is 64-bit:
2769 * + NonSecure EL1 & 0 stage 1
2770 * + NonSecure EL1 & 0 stage 2
2771 * + NonSecure EL2
2772 * + NonSecure EL2 & 0 (ARMv8.1-VHE)
2773 * + Secure EL1 & 0
2774 * + Secure EL3
2775 * If EL3 is 32-bit:
2776 * + NonSecure PL1 & 0 stage 1
2777 * + NonSecure PL1 & 0 stage 2
2778 * + NonSecure PL2
2779 * + Secure PL0
2780 * + Secure PL1
2781 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
2782 *
2783 * For QEMU, an mmu_idx is not quite the same as a translation regime because:
2784 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes,
2785 * because they may differ in access permissions even if the VA->PA map is
2786 * the same
2787 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2788 * translation, which means that we have one mmu_idx that deals with two
2789 * concatenated translation regimes [this sort of combined s1+2 TLB is
2790 * architecturally permitted]
2791 * 3. we don't need to allocate an mmu_idx to translations that we won't be
2792 * handling via the TLB. The only way to do a stage 1 translation without
2793 * the immediate stage 2 translation is via the ATS or AT system insns,
2794 * which can be slow-pathed and always do a page table walk.
2795 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
2796 * translation regimes, because they map reasonably well to each other
2797 * and they can't both be active at the same time.
2798 * 5. we want to be able to use the TLB for accesses done as part of a
2799 * stage1 page table walk, rather than having to walk the stage2 page
2800 * table over and over.
2801 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
2802 * Never (PAN) bit within PSTATE.
2803 *
2804 * This gives us the following list of cases:
2805 *
2806 * NS EL0 EL1&0 stage 1+2 (aka NS PL0)
2807 * NS EL1 EL1&0 stage 1+2 (aka NS PL1)
2808 * NS EL1 EL1&0 stage 1+2 +PAN
2809 * NS EL0 EL2&0
2810 * NS EL2 EL2&0 +PAN
2811 * NS EL2 (aka NS PL2)
2812 * S EL0 EL1&0 (aka S PL0)
2813 * S EL1 EL1&0 (not used if EL3 is 32 bit)
2814 * S EL1 EL1&0 +PAN
2815 * S EL3 (aka S PL1)
2816 * NS EL1&0 stage 2
2817 *
2818 * for a total of 12 different mmu_idx.
2819 *
2820 * R profile CPUs have an MPU, but can use the same set of MMU indexes
2821 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and
2822 * NS EL2 if we ever model a Cortex-R52).
2823 *
2824 * M profile CPUs are rather different as they do not have a true MMU.
2825 * They have the following different MMU indexes:
2826 * User
2827 * Privileged
2828 * User, execution priority negative (ie the MPU HFNMIENA bit may apply)
2829 * Privileged, execution priority negative (ditto)
2830 * If the CPU supports the v8M Security Extension then there are also:
2831 * Secure User
2832 * Secure Privileged
2833 * Secure User, execution priority negative
2834 * Secure Privileged, execution priority negative
2835 *
2836 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
2837 * are not quite the same -- different CPU types (most notably M profile
2838 * vs A/R profile) would like to use MMU indexes with different semantics,
2839 * but since we don't ever need to use all of those in a single CPU we
2840 * can avoid setting NB_MMU_MODES to more than 8. The lower bits of
2841 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
2842 * the same for any particular CPU.
2843 * Variables of type ARMMUIdx are always full values, and the core
2844 * index values are in variables of type 'int'.
2845 *
2846 * Our enumeration includes at the end some entries which are not "true"
2847 * mmu_idx values in that they don't have corresponding TLBs and are only
2848 * valid for doing slow path page table walks.
2849 *
2850 * The constant names here are patterned after the general style of the names
2851 * of the AT/ATS operations.
2852 * The values used are carefully arranged to make mmu_idx => EL lookup easy.
2853 * For M profile we arrange them to have a bit for priv, a bit for negpri
2854 * and a bit for secure.
2855 */
2856 #define ARM_MMU_IDX_A 0x10 /* A profile */
2857 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
2858 #define ARM_MMU_IDX_M 0x40 /* M profile */
2859
2860 /* Meanings of the bits for M profile mmu idx values */
2861 #define ARM_MMU_IDX_M_PRIV 0x1
2862 #define ARM_MMU_IDX_M_NEGPRI 0x2
2863 #define ARM_MMU_IDX_M_S 0x4 /* Secure */
2864
2865 #define ARM_MMU_IDX_TYPE_MASK \
2866 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
2867 #define ARM_MMU_IDX_COREIDX_MASK 0xf
2868
2869 typedef enum ARMMMUIdx {
2870 /*
2871 * A-profile.
2872 */
2873 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A,
2874 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A,
2875
2876 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A,
2877 ARMMMUIdx_E10_1_PAN = 3 | ARM_MMU_IDX_A,
2878
2879 ARMMMUIdx_E2 = 4 | ARM_MMU_IDX_A,
2880 ARMMMUIdx_E20_2 = 5 | ARM_MMU_IDX_A,
2881 ARMMMUIdx_E20_2_PAN = 6 | ARM_MMU_IDX_A,
2882
2883 ARMMMUIdx_SE10_0 = 7 | ARM_MMU_IDX_A,
2884 ARMMMUIdx_SE10_1 = 8 | ARM_MMU_IDX_A,
2885 ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A,
2886 ARMMMUIdx_SE3 = 10 | ARM_MMU_IDX_A,
2887
2888 ARMMMUIdx_Stage2 = 11 | ARM_MMU_IDX_A,
2889
2890 /*
2891 * These are not allocated TLBs and are used only for AT system
2892 * instructions or for the first stage of an S12 page table walk.
2893 */
2894 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
2895 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
2896 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
2897
2898 /*
2899 * M-profile.
2900 */
2901 ARMMMUIdx_MUser = ARM_MMU_IDX_M,
2902 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
2903 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
2904 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
2905 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
2906 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
2907 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
2908 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
2909 } ARMMMUIdx;
2910
2911 /*
2912 * Bit macros for the core-mmu-index values for each index,
2913 * for use when calling tlb_flush_by_mmuidx() and friends.
2914 */
2915 #define TO_CORE_BIT(NAME) \
2916 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
2917
2918 typedef enum ARMMMUIdxBit {
2919 TO_CORE_BIT(E10_0),
2920 TO_CORE_BIT(E20_0),
2921 TO_CORE_BIT(E10_1),
2922 TO_CORE_BIT(E10_1_PAN),
2923 TO_CORE_BIT(E2),
2924 TO_CORE_BIT(E20_2),
2925 TO_CORE_BIT(E20_2_PAN),
2926 TO_CORE_BIT(SE10_0),
2927 TO_CORE_BIT(SE10_1),
2928 TO_CORE_BIT(SE10_1_PAN),
2929 TO_CORE_BIT(SE3),
2930 TO_CORE_BIT(Stage2),
2931
2932 TO_CORE_BIT(MUser),
2933 TO_CORE_BIT(MPriv),
2934 TO_CORE_BIT(MUserNegPri),
2935 TO_CORE_BIT(MPrivNegPri),
2936 TO_CORE_BIT(MSUser),
2937 TO_CORE_BIT(MSPriv),
2938 TO_CORE_BIT(MSUserNegPri),
2939 TO_CORE_BIT(MSPrivNegPri),
2940 } ARMMMUIdxBit;
2941
2942 #undef TO_CORE_BIT
2943
2944 #define MMU_USER_IDX 0
2945
2946 /* Indexes used when registering address spaces with cpu_address_space_init */
2947 typedef enum ARMASIdx {
2948 ARMASIdx_NS = 0,
2949 ARMASIdx_S = 1,
2950 } ARMASIdx;
2951
2952 /* Return the Exception Level targeted by debug exceptions. */
2953 static inline int arm_debug_target_el(CPUARMState *env)
2954 {
2955 bool secure = arm_is_secure(env);
2956 bool route_to_el2 = false;
2957
2958 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
2959 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
2960 env->cp15.mdcr_el2 & MDCR_TDE;
2961 }
2962
2963 if (route_to_el2) {
2964 return 2;
2965 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
2966 !arm_el_is_aa64(env, 3) && secure) {
2967 return 3;
2968 } else {
2969 return 1;
2970 }
2971 }
2972
2973 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
2974 {
2975 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and
2976 * CSSELR is RAZ/WI.
2977 */
2978 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
2979 }
2980
2981 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */
2982 static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
2983 {
2984 int cur_el = arm_current_el(env);
2985 int debug_el;
2986
2987 if (cur_el == 3) {
2988 return false;
2989 }
2990
2991 /* MDCR_EL3.SDD disables debug events from Secure state */
2992 if (arm_is_secure_below_el3(env)
2993 && extract32(env->cp15.mdcr_el3, 16, 1)) {
2994 return false;
2995 }
2996
2997 /*
2998 * Same EL to same EL debug exceptions need MDSCR_KDE enabled
2999 * while not masking the (D)ebug bit in DAIF.
3000 */
3001 debug_el = arm_debug_target_el(env);
3002
3003 if (cur_el == debug_el) {
3004 return extract32(env->cp15.mdscr_el1, 13, 1)
3005 && !(env->daif & PSTATE_D);
3006 }
3007
3008 /* Otherwise the debug target needs to be a higher EL */
3009 return debug_el > cur_el;
3010 }
3011
3012 static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
3013 {
3014 int el = arm_current_el(env);
3015
3016 if (el == 0 && arm_el_is_aa64(env, 1)) {
3017 return aa64_generate_debug_exceptions(env);
3018 }
3019
3020 if (arm_is_secure(env)) {
3021 int spd;
3022
3023 if (el == 0 && (env->cp15.sder & 1)) {
3024 /* SDER.SUIDEN means debug exceptions from Secure EL0
3025 * are always enabled. Otherwise they are controlled by
3026 * SDCR.SPD like those from other Secure ELs.
3027 */
3028 return true;
3029 }
3030
3031 spd = extract32(env->cp15.mdcr_el3, 14, 2);
3032 switch (spd) {
3033 case 1:
3034 /* SPD == 0b01 is reserved, but behaves as 0b00. */
3035 case 0:
3036 /* For 0b00 we return true if external secure invasive debug
3037 * is enabled. On real hardware this is controlled by external
3038 * signals to the core. QEMU always permits debug, and behaves
3039 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
3040 */
3041 return true;
3042 case 2:
3043 return false;
3044 case 3:
3045 return true;
3046 }
3047 }
3048
3049 return el != 2;
3050 }
3051
3052 /* Return true if debugging exceptions are currently enabled.
3053 * This corresponds to what in ARM ARM pseudocode would be
3054 * if UsingAArch32() then
3055 * return AArch32.GenerateDebugExceptions()
3056 * else
3057 * return AArch64.GenerateDebugExceptions()
3058 * We choose to push the if() down into this function for clarity,
3059 * since the pseudocode has it at all callsites except for the one in
3060 * CheckSoftwareStep(), where it is elided because both branches would
3061 * always return the same value.
3062 */
3063 static inline bool arm_generate_debug_exceptions(CPUARMState *env)
3064 {
3065 if (env->aarch64) {
3066 return aa64_generate_debug_exceptions(env);
3067 } else {
3068 return aa32_generate_debug_exceptions(env);
3069 }
3070 }
3071
3072 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check
3073 * implicitly means this always returns false in pre-v8 CPUs.)
3074 */
3075 static inline bool arm_singlestep_active(CPUARMState *env)
3076 {
3077 return extract32(env->cp15.mdscr_el1, 0, 1)
3078 && arm_el_is_aa64(env, arm_debug_target_el(env))
3079 && arm_generate_debug_exceptions(env);
3080 }
3081
3082 static inline bool arm_sctlr_b(CPUARMState *env)
3083 {
3084 return
3085 /* We need not implement SCTLR.ITD in user-mode emulation, so
3086 * let linux-user ignore the fact that it conflicts with SCTLR_B.
3087 * This lets people run BE32 binaries with "-cpu any".
3088 */
3089 #ifndef CONFIG_USER_ONLY
3090 !arm_feature(env, ARM_FEATURE_V7) &&
3091 #endif
3092 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
3093 }
3094
3095 uint64_t arm_sctlr(CPUARMState *env, int el);
3096
3097 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
3098 bool sctlr_b)
3099 {
3100 #ifdef CONFIG_USER_ONLY
3101 /*
3102 * In system mode, BE32 is modelled in line with the
3103 * architecture (as word-invariant big-endianness), where loads
3104 * and stores are done little endian but from addresses which
3105 * are adjusted by XORing with the appropriate constant. So the
3106 * endianness to use for the raw data access is not affected by
3107 * SCTLR.B.
3108 * In user mode, however, we model BE32 as byte-invariant
3109 * big-endianness (because user-only code cannot tell the
3110 * difference), and so we need to use a data access endianness
3111 * that depends on SCTLR.B.
3112 */
3113 if (sctlr_b) {
3114 return true;
3115 }
3116 #endif
3117 /* In 32bit endianness is determined by looking at CPSR's E bit */
3118 return env->uncached_cpsr & CPSR_E;
3119 }
3120
3121 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
3122 {
3123 return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
3124 }
3125
3126 /* Return true if the processor is in big-endian mode. */
3127 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
3128 {
3129 if (!is_a64(env)) {
3130 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
3131 } else {
3132 int cur_el = arm_current_el(env);
3133 uint64_t sctlr = arm_sctlr(env, cur_el);
3134 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
3135 }
3136 }
3137
3138 typedef CPUARMState CPUArchState;
3139 typedef ARMCPU ArchCPU;
3140
3141 #include "exec/cpu-all.h"
3142
3143 /*
3144 * Bit usage in the TB flags field: bit 31 indicates whether we are
3145 * in 32 or 64 bit mode. The meaning of the other bits depends on that.
3146 * We put flags which are shared between 32 and 64 bit mode at the top
3147 * of the word, and flags which apply to only one mode at the bottom.
3148 *
3149 * 31 20 18 14 9 0
3150 * +--------------+-----+-----+----------+--------------+
3151 * | | | TBFLAG_A32 | |
3152 * | | +-----+----------+ TBFLAG_AM32 |
3153 * | TBFLAG_ANY | |TBFLAG_M32| |
3154 * | | +-+----------+--------------|
3155 * | | | TBFLAG_A64 |
3156 * +--------------+---------+---------------------------+
3157 * 31 20 15 0
3158 *
3159 * Unless otherwise noted, these bits are cached in env->hflags.
3160 */
3161 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
3162 FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1)
3163 FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */
3164 FIELD(TBFLAG_ANY, BE_DATA, 28, 1)
3165 FIELD(TBFLAG_ANY, MMUIDX, 24, 4)
3166 /* Target EL if we take a floating-point-disabled exception */
3167 FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2)
3168 /* For A-profile only, target EL for debug exceptions. */
3169 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2)
3170
3171 /*
3172 * Bit usage when in AArch32 state, both A- and M-profile.
3173 */
3174 FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */
3175 FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */
3176
3177 /*
3178 * Bit usage when in AArch32 state, for A-profile only.
3179 */
3180 FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */
3181 FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */
3182 /*
3183 * We store the bottom two bits of the CPAR as TB flags and handle
3184 * checks on the other bits at runtime. This shares the same bits as
3185 * VECSTRIDE, which is OK as no XScale CPU has VFP.
3186 * Not cached, because VECLEN+VECSTRIDE are not cached.
3187 */
3188 FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2)
3189 FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */
3190 FIELD(TBFLAG_A32, SCTLR_B, 15, 1)
3191 FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1)
3192 /*
3193 * Indicates whether cp register reads and writes by guest code should access
3194 * the secure or nonsecure bank of banked registers; note that this is not
3195 * the same thing as the current security state of the processor!
3196 */
3197 FIELD(TBFLAG_A32, NS, 17, 1)
3198
3199 /*
3200 * Bit usage when in AArch32 state, for M-profile only.
3201 */
3202 /* Handler (ie not Thread) mode */
3203 FIELD(TBFLAG_M32, HANDLER, 9, 1)
3204 /* Whether we should generate stack-limit checks */
3205 FIELD(TBFLAG_M32, STACKCHECK, 10, 1)
3206 /* Set if FPCCR.LSPACT is set */
3207 FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */
3208 /* Set if we must create a new FP context */
3209 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */
3210 /* Set if FPCCR.S does not match current security state */
3211 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */
3212
3213 /*
3214 * Bit usage when in AArch64 state
3215 */
3216 FIELD(TBFLAG_A64, TBII, 0, 2)
3217 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
3218 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
3219 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3220 FIELD(TBFLAG_A64, BT, 9, 1)
3221 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */
3222 FIELD(TBFLAG_A64, TBID, 12, 2)
3223 FIELD(TBFLAG_A64, UNPRIV, 14, 1)
3224
3225 /**
3226 * cpu_mmu_index:
3227 * @env: The cpu environment
3228 * @ifetch: True for code access, false for data access.
3229 *
3230 * Return the core mmu index for the current translation regime.
3231 * This function is used by generic TCG code paths.
3232 */
3233 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
3234 {
3235 return FIELD_EX32(env->hflags, TBFLAG_ANY, MMUIDX);
3236 }
3237
3238 static inline bool bswap_code(bool sctlr_b)
3239 {
3240 #ifdef CONFIG_USER_ONLY
3241 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian.
3242 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0
3243 * would also end up as a mixed-endian mode with BE code, LE data.
3244 */
3245 return
3246 #ifdef TARGET_WORDS_BIGENDIAN
3247 1 ^
3248 #endif
3249 sctlr_b;
3250 #else
3251 /* All code access in ARM is little endian, and there are no loaders
3252 * doing swaps that need to be reversed
3253 */
3254 return 0;
3255 #endif
3256 }
3257
3258 #ifdef CONFIG_USER_ONLY
3259 static inline bool arm_cpu_bswap_data(CPUARMState *env)
3260 {
3261 return
3262 #ifdef TARGET_WORDS_BIGENDIAN
3263 1 ^
3264 #endif
3265 arm_cpu_data_is_big_endian(env);
3266 }
3267 #endif
3268
3269 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
3270 target_ulong *cs_base, uint32_t *flags);
3271
3272 enum {
3273 QEMU_PSCI_CONDUIT_DISABLED = 0,
3274 QEMU_PSCI_CONDUIT_SMC = 1,
3275 QEMU_PSCI_CONDUIT_HVC = 2,
3276 };
3277
3278 #ifndef CONFIG_USER_ONLY
3279 /* Return the address space index to use for a memory access */
3280 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3281 {
3282 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3283 }
3284
3285 /* Return the AddressSpace to use for a memory access
3286 * (which depends on whether the access is S or NS, and whether
3287 * the board gave us a separate AddressSpace for S accesses).
3288 */
3289 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3290 {
3291 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3292 }
3293 #endif
3294
3295 /**
3296 * arm_register_pre_el_change_hook:
3297 * Register a hook function which will be called immediately before this
3298 * CPU changes exception level or mode. The hook function will be
3299 * passed a pointer to the ARMCPU and the opaque data pointer passed
3300 * to this function when the hook was registered.
3301 *
3302 * Note that if a pre-change hook is called, any registered post-change hooks
3303 * are guaranteed to subsequently be called.
3304 */
3305 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3306 void *opaque);
3307 /**
3308 * arm_register_el_change_hook:
3309 * Register a hook function which will be called immediately after this
3310 * CPU changes exception level or mode. The hook function will be
3311 * passed a pointer to the ARMCPU and the opaque data pointer passed
3312 * to this function when the hook was registered.
3313 *
3314 * Note that any registered hooks registered here are guaranteed to be called
3315 * if pre-change hooks have been.
3316 */
3317 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3318 *opaque);
3319
3320 /**
3321 * arm_rebuild_hflags:
3322 * Rebuild the cached TBFLAGS for arbitrary changed processor state.
3323 */
3324 void arm_rebuild_hflags(CPUARMState *env);
3325
3326 /**
3327 * aa32_vfp_dreg:
3328 * Return a pointer to the Dn register within env in 32-bit mode.
3329 */
3330 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3331 {
3332 return &env->vfp.zregs[regno >> 1].d[regno & 1];
3333 }
3334
3335 /**
3336 * aa32_vfp_qreg:
3337 * Return a pointer to the Qn register within env in 32-bit mode.
3338 */
3339 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3340 {
3341 return &env->vfp.zregs[regno].d[0];
3342 }
3343
3344 /**
3345 * aa64_vfp_qreg:
3346 * Return a pointer to the Qn register within env in 64-bit mode.
3347 */
3348 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3349 {
3350 return &env->vfp.zregs[regno].d[0];
3351 }
3352
3353 /* Shared between translate-sve.c and sve_helper.c. */
3354 extern const uint64_t pred_esz_masks[4];
3355
3356 /*
3357 * Naming convention for isar_feature functions:
3358 * Functions which test 32-bit ID registers should have _aa32_ in
3359 * their name. Functions which test 64-bit ID registers should have
3360 * _aa64_ in their name. These must only be used in code where we
3361 * know for certain that the CPU has AArch32 or AArch64 respectively
3362 * or where the correct answer for a CPU which doesn't implement that
3363 * CPU state is "false" (eg when generating A32 or A64 code, if adding
3364 * system registers that are specific to that CPU state, for "should
3365 * we let this system register bit be set" tests where the 32-bit
3366 * flavour of the register doesn't have the bit, and so on).
3367 * Functions which simply ask "does this feature exist at all" have
3368 * _any_ in their name, and always return the logical OR of the _aa64_
3369 * and the _aa32_ function.
3370 */
3371
3372 /*
3373 * 32-bit feature tests via id registers.
3374 */
3375 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
3376 {
3377 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
3378 }
3379
3380 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
3381 {
3382 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
3383 }
3384
3385 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
3386 {
3387 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
3388 }
3389
3390 static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
3391 {
3392 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
3393 }
3394
3395 static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
3396 {
3397 return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
3398 }
3399
3400 static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
3401 {
3402 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
3403 }
3404
3405 static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
3406 {
3407 return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
3408 }
3409
3410 static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
3411 {
3412 return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
3413 }
3414
3415 static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
3416 {
3417 return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
3418 }
3419
3420 static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
3421 {
3422 return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
3423 }
3424
3425 static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
3426 {
3427 return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
3428 }
3429
3430 static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
3431 {
3432 return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
3433 }
3434
3435 static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
3436 {
3437 return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
3438 }
3439
3440 static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
3441 {
3442 return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
3443 }
3444
3445 static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
3446 {
3447 return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
3448 }
3449
3450 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
3451 {
3452 /*
3453 * This is a placeholder for use by VCMA until the rest of
3454 * the ARMv8.2-FP16 extension is implemented for aa32 mode.
3455 * At which point we can properly set and check MVFR1.FPHP.
3456 */
3457 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
3458 }
3459
3460 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
3461 {
3462 /*
3463 * Return true if either VFP or SIMD is implemented.
3464 * In this case, a minimum of VFP w/ D0-D15.
3465 */
3466 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0;
3467 }
3468
3469 static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id)
3470 {
3471 /* Return true if D16-D31 are implemented */
3472 return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
3473 }
3474
3475 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
3476 {
3477 return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
3478 }
3479
3480 static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id)
3481 {
3482 /* Return true if CPU supports single precision floating point, VFPv2 */
3483 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0;
3484 }
3485
3486 static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id)
3487 {
3488 /* Return true if CPU supports single precision floating point, VFPv3 */
3489 return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >= 2;
3490 }
3491
3492 static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
3493 {
3494 /* Return true if CPU supports double precision floating point, VFPv2 */
3495 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
3496 }
3497
3498 static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id)
3499 {
3500 /* Return true if CPU supports double precision floating point, VFPv3 */
3501 return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >= 2;
3502 }
3503
3504 static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id)
3505 {
3506 return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id);
3507 }
3508
3509 /*
3510 * We always set the FP and SIMD FP16 fields to indicate identical
3511 * levels of support (assuming SIMD is implemented at all), so
3512 * we only need one set of accessors.
3513 */
3514 static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
3515 {
3516 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
3517 }
3518
3519 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
3520 {
3521 return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
3522 }
3523
3524 /*
3525 * Note that this ID register field covers both VFP and Neon FMAC,
3526 * so should usually be tested in combination with some other
3527 * check that confirms the presence of whichever of VFP or Neon is
3528 * relevant, to avoid accidentally enabling a Neon feature on
3529 * a VFP-no-Neon core or vice-versa.
3530 */
3531 static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id)
3532 {
3533 return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) != 0;
3534 }
3535
3536 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
3537 {
3538 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
3539 }
3540
3541 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
3542 {
3543 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
3544 }
3545
3546 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
3547 {
3548 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
3549 }
3550
3551 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
3552 {
3553 return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
3554 }
3555
3556 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
3557 {
3558 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
3559 }
3560
3561 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
3562 {
3563 return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
3564 }
3565
3566 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id)
3567 {
3568 /* 0xf means "non-standard IMPDEF PMU" */
3569 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
3570 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3571 }
3572
3573 static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id)
3574 {
3575 /* 0xf means "non-standard IMPDEF PMU" */
3576 return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 &&
3577 FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
3578 }
3579
3580 static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
3581 {
3582 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
3583 }
3584
3585 static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
3586 {
3587 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
3588 }
3589
3590 static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
3591 {
3592 return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
3593 }
3594
3595 /*
3596 * 64-bit feature tests via id registers.
3597 */
3598 static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
3599 {
3600 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
3601 }
3602
3603 static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
3604 {
3605 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
3606 }
3607
3608 static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
3609 {
3610 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
3611 }
3612
3613 static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
3614 {
3615 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
3616 }
3617
3618 static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
3619 {
3620 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
3621 }
3622
3623 static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
3624 {
3625 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
3626 }
3627
3628 static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
3629 {
3630 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
3631 }
3632
3633 static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
3634 {
3635 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
3636 }
3637
3638 static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
3639 {
3640 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
3641 }
3642
3643 static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
3644 {
3645 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
3646 }
3647
3648 static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
3649 {
3650 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
3651 }
3652
3653 static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
3654 {
3655 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
3656 }
3657
3658 static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
3659 {
3660 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
3661 }
3662
3663 static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
3664 {
3665 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
3666 }
3667
3668 static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
3669 {
3670 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
3671 }
3672
3673 static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
3674 {
3675 return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
3676 }
3677
3678 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
3679 {
3680 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
3681 }
3682
3683 static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
3684 {
3685 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
3686 }
3687
3688 static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
3689 {
3690 /*
3691 * Note that while QEMU will only implement the architected algorithm
3692 * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation
3693 * defined algorithms, and thus API+GPI, and this predicate controls
3694 * migration of the 128-bit keys.
3695 */
3696 return (id->id_aa64isar1 &
3697 (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) |
3698 FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) |
3699 FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) |
3700 FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
3701 }
3702
3703 static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
3704 {
3705 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
3706 }
3707
3708 static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
3709 {
3710 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
3711 }
3712
3713 static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
3714 {
3715 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
3716 }
3717
3718 static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id)
3719 {
3720 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0;
3721 }
3722
3723 static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
3724 {
3725 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
3726 }
3727
3728 static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
3729 {
3730 /* We always set the AdvSIMD and FP fields identically. */
3731 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
3732 }
3733
3734 static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
3735 {
3736 /* We always set the AdvSIMD and FP fields identically wrt FP16. */
3737 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
3738 }
3739
3740 static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
3741 {
3742 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
3743 }
3744
3745 static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
3746 {
3747 return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
3748 }
3749
3750 static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
3751 {
3752 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
3753 }
3754
3755 static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
3756 {
3757 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
3758 }
3759
3760 static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
3761 {
3762 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
3763 }
3764
3765 static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
3766 {
3767 return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
3768 }
3769
3770 static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
3771 {
3772 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
3773 }
3774
3775 static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
3776 {
3777 return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
3778 }
3779
3780 static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id)
3781 {
3782 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
3783 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
3784 }
3785
3786 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id)
3787 {
3788 return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
3789 FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
3790 }
3791
3792 static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
3793 {
3794 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
3795 }
3796
3797 static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
3798 {
3799 return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
3800 }
3801
3802 static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
3803 {
3804 return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
3805 }
3806
3807 /*
3808 * Feature tests for "does this exist in either 32-bit or 64-bit?"
3809 */
3810 static inline bool isar_feature_any_fp16(const ARMISARegisters *id)
3811 {
3812 return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id);
3813 }
3814
3815 static inline bool isar_feature_any_predinv(const ARMISARegisters *id)
3816 {
3817 return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id);
3818