migration: increase max-bandwidth to 128 MiB/s (1 Gib/s)
[qemu.git] / target / arm / cpu.h
1 /*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef ARM_CPU_H
21 #define ARM_CPU_H
22
23 #include "kvm-consts.h"
24 #include "hw/registerfields.h"
25 #include "cpu-qom.h"
26 #include "exec/cpu-defs.h"
27
28 /* ARM processors have a weak memory model */
29 #define TCG_GUEST_DEFAULT_MO (0)
30
31 #ifdef TARGET_AARCH64
32 #define KVM_HAVE_MCE_INJECTION 1
33 #endif
34
35 #define EXCP_UDEF 1 /* undefined instruction */
36 #define EXCP_SWI 2 /* software interrupt */
37 #define EXCP_PREFETCH_ABORT 3
38 #define EXCP_DATA_ABORT 4
39 #define EXCP_IRQ 5
40 #define EXCP_FIQ 6
41 #define EXCP_BKPT 7
42 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
43 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
44 #define EXCP_HVC 11 /* HyperVisor Call */
45 #define EXCP_HYP_TRAP 12
46 #define EXCP_SMC 13 /* Secure Monitor Call */
47 #define EXCP_VIRQ 14
48 #define EXCP_VFIQ 15
49 #define EXCP_SEMIHOST 16 /* semihosting call */
50 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */
51 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
52 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */
53 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */
54 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */
55 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */
56 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
57
58 #define ARMV7M_EXCP_RESET 1
59 #define ARMV7M_EXCP_NMI 2
60 #define ARMV7M_EXCP_HARD 3
61 #define ARMV7M_EXCP_MEM 4
62 #define ARMV7M_EXCP_BUS 5
63 #define ARMV7M_EXCP_USAGE 6
64 #define ARMV7M_EXCP_SECURE 7
65 #define ARMV7M_EXCP_SVC 11
66 #define ARMV7M_EXCP_DEBUG 12
67 #define ARMV7M_EXCP_PENDSV 14
68 #define ARMV7M_EXCP_SYSTICK 15
69
70 /* For M profile, some registers are banked secure vs non-secure;
71 * these are represented as a 2-element array where the first element
72 * is the non-secure copy and the second is the secure copy.
73 * When the CPU does not have implement the security extension then
74 * only the first element is used.
75 * This means that the copy for the current security state can be
76 * accessed via env->registerfield[env->v7m.secure] (whether the security
77 * extension is implemented or not).
78 */
79 enum {
80 M_REG_NS = 0,
81 M_REG_S = 1,
82 M_REG_NUM_BANKS = 2,
83 };
84
85 /* ARM-specific interrupt pending bits. */
86 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
87 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
88 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
89
90 /* The usual mapping for an AArch64 system register to its AArch32
91 * counterpart is for the 32 bit world to have access to the lower
92 * half only (with writes leaving the upper half untouched). It's
93 * therefore useful to be able to pass TCG the offset of the least
94 * significant half of a uint64_t struct member.
95 */
96 #ifdef HOST_WORDS_BIGENDIAN
97 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
98 #define offsetofhigh32(S, M) offsetof(S, M)
99 #else
100 #define offsetoflow32(S, M) offsetof(S, M)
101 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
102 #endif
103
104 /* Meanings of the ARMCPU object's four inbound GPIO lines */
105 #define ARM_CPU_IRQ 0
106 #define ARM_CPU_FIQ 1
107 #define ARM_CPU_VIRQ 2
108 #define ARM_CPU_VFIQ 3
109
110 /* ARM-specific extra insn start words:
111 * 1: Conditional execution bits
112 * 2: Partial exception syndrome for data aborts
113 */
114 #define TARGET_INSN_START_EXTRA_WORDS 2
115
116 /* The 2nd extra word holding syndrome info for data aborts does not use
117 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to
118 * help the sleb128 encoder do a better job.
119 * When restoring the CPU state, we shift it back up.
120 */
121 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
122 #define ARM_INSN_START_WORD2_SHIFT 14
123
124 /* We currently assume float and double are IEEE single and double
125 precision respectively.
126 Doing runtime conversions is tricky because VFP registers may contain
127 integer values (eg. as the result of a FTOSI instruction).
128 s<2n> maps to the least significant half of d<n>
129 s<2n+1> maps to the most significant half of d<n>
130 */
131
132 /**
133 * DynamicGDBXMLInfo:
134 * @desc: Contains the XML descriptions.
135 * @num: Number of the registers in this XML seen by GDB.
136 * @data: A union with data specific to the set of registers
137 * @cpregs_keys: Array that contains the corresponding Key of
138 * a given cpreg with the same order of the cpreg
139 * in the XML description.
140 */
141 typedef struct DynamicGDBXMLInfo {
142 char *desc;
143 int num;
144 union {
145 struct {
146 uint32_t *keys;
147 } cpregs;
148 } data;
149 } DynamicGDBXMLInfo;
150
151 /* CPU state for each instance of a generic timer (in cp15 c14) */
152 typedef struct ARMGenericTimer {
153 uint64_t cval; /* Timer CompareValue register */
154 uint64_t ctl; /* Timer Control register */
155 } ARMGenericTimer;
156
157 #define GTIMER_PHYS 0
158 #define GTIMER_VIRT 1
159 #define GTIMER_HYP 2
160 #define GTIMER_SEC 3
161 #define GTIMER_HYPVIRT 4
162 #define NUM_GTIMERS 5
163
164 typedef struct {
165 uint64_t raw_tcr;
166 uint32_t mask;
167 uint32_t base_mask;
168 } TCR;
169
170 /* Define a maximum sized vector register.
171 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
172 * For 64-bit, this is a 2048-bit SVE register.
173 *
174 * Note that the mapping between S, D, and Q views of the register bank
175 * differs between AArch64 and AArch32.
176 * In AArch32:
177 * Qn = regs[n].d[1]:regs[n].d[0]
178 * Dn = regs[n / 2].d[n & 1]
179 * Sn = regs[n / 4].d[n % 4 / 2],
180 * bits 31..0 for even n, and bits 63..32 for odd n
181 * (and regs[16] to regs[31] are inaccessible)
182 * In AArch64:
183 * Zn = regs[n].d[*]
184 * Qn = regs[n].d[1]:regs[n].d[0]
185 * Dn = regs[n].d[0]
186 * Sn = regs[n].d[0] bits 31..0
187 * Hn = regs[n].d[0] bits 15..0
188 *
189 * This corresponds to the architecturally defined mapping between
190 * the two execution states, and means we do not need to explicitly
191 * map these registers when changing states.
192 *
193 * Align the data for use with TCG host vector operations.
194 */
195
196 #ifdef TARGET_AARCH64
197 # define ARM_MAX_VQ 16
198 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
199 #else
200 # define ARM_MAX_VQ 1
201 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
202 #endif
203
204 typedef struct ARMVectorReg {
205 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
206 } ARMVectorReg;
207
208 #ifdef TARGET_AARCH64
209 /* In AArch32 mode, predicate registers do not exist at all. */
210 typedef struct ARMPredicateReg {
211 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
212 } ARMPredicateReg;
213
214 /* In AArch32 mode, PAC keys do not exist at all. */
215 typedef struct ARMPACKey {
216 uint64_t lo, hi;
217 } ARMPACKey;
218 #endif
219
220
221 typedef struct CPUARMState {
222 /* Regs for current mode. */
223 uint32_t regs[16];
224
225 /* 32/64 switch only happens when taking and returning from
226 * exceptions so the overlap semantics are taken care of then
227 * instead of having a complicated union.
228 */
229 /* Regs for A64 mode. */
230 uint64_t xregs[32];
231 uint64_t pc;
232 /* PSTATE isn't an architectural register for ARMv8. However, it is
233 * convenient for us to assemble the underlying state into a 32 bit format
234 * identical to the architectural format used for the SPSR. (This is also
235 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
236 * 'pstate' register are.) Of the PSTATE bits:
237 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
238 * semantics as for AArch32, as described in the comments on each field)
239 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
240 * DAIF (exception masks) are kept in env->daif
241 * BTYPE is kept in env->btype
242 * all other bits are stored in their correct places in env->pstate
243 */
244 uint32_t pstate;
245 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
246
247 /* Cached TBFLAGS state. See below for which bits are included. */
248 uint32_t hflags;
249
250 /* Frequently accessed CPSR bits are stored separately for efficiency.
251 This contains all the other bits. Use cpsr_{read,write} to access
252 the whole CPSR. */
253 uint32_t uncached_cpsr;
254 uint32_t spsr;
255
256 /* Banked registers. */
257 uint64_t banked_spsr[8];
258 uint32_t banked_r13[8];
259 uint32_t banked_r14[8];
260
261 /* These hold r8-r12. */
262 uint32_t usr_regs[5];
263 uint32_t fiq_regs[5];
264
265 /* cpsr flag cache for faster execution */
266 uint32_t CF; /* 0 or 1 */
267 uint32_t VF; /* V is the bit 31. All other bits are undefined */
268 uint32_t NF; /* N is bit 31. All other bits are undefined. */
269 uint32_t ZF; /* Z set if zero. */
270 uint32_t QF; /* 0 or 1 */
271 uint32_t GE; /* cpsr[19:16] */
272 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
273 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
274 uint32_t btype; /* BTI branch type. spsr[11:10]. */
275 uint64_t daif; /* exception masks, in the bits they are in PSTATE */
276
277 uint64_t elr_el[4]; /* AArch64 exception link regs */
278 uint64_t sp_el[4]; /* AArch64 banked stack pointers */
279
280 /* System control coprocessor (cp15) */
281 struct {
282 uint32_t c0_cpuid;
283 union { /* Cache size selection */
284 struct {
285 uint64_t _unused_csselr0;
286 uint64_t csselr_ns;
287 uint64_t _unused_csselr1;
288 uint64_t csselr_s;
289 };
290 uint64_t csselr_el[4];
291 };
292 union { /* System control register. */
293 struct {
294 uint64_t _unused_sctlr;
295 uint64_t sctlr_ns;
296 uint64_t hsctlr;
297 uint64_t sctlr_s;
298 };
299 uint64_t sctlr_el[4];
300 };
301 uint64_t cpacr_el1; /* Architectural feature access control register */
302 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */
303 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
304 uint64_t sder; /* Secure debug enable register. */
305 uint32_t nsacr; /* Non-secure access control register. */
306 union { /* MMU translation table base 0. */
307 struct {
308 uint64_t _unused_ttbr0_0;
309 uint64_t ttbr0_ns;
310 uint64_t _unused_ttbr0_1;
311 uint64_t ttbr0_s;
312 };
313 uint64_t ttbr0_el[4];
314 };
315 union { /* MMU translation table base 1. */
316 struct {
317 uint64_t _unused_ttbr1_0;
318 uint64_t ttbr1_ns;
319 uint64_t _unused_ttbr1_1;
320 uint64_t ttbr1_s;
321 };
322 uint64_t ttbr1_el[4];
323 };
324 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */
325 /* MMU translation table base control. */
326 TCR tcr_el[4];
327 TCR vtcr_el2; /* Virtualization Translation Control. */
328 uint32_t c2_data; /* MPU data cacheable bits. */
329 uint32_t c2_insn; /* MPU instruction cacheable bits. */
330 union { /* MMU domain access control register
331 * MPU write buffer control.
332 */
333 struct {
334 uint64_t dacr_ns;
335 uint64_t dacr_s;
336 };
337 struct {
338 uint64_t dacr32_el2;
339 };
340 };
341 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
342 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
343 uint64_t hcr_el2; /* Hypervisor configuration register */
344 uint64_t scr_el3; /* Secure configuration register. */
345 union { /* Fault status registers. */
346 struct {
347 uint64_t ifsr_ns;
348 uint64_t ifsr_s;
349 };
350 struct {
351 uint64_t ifsr32_el2;
352 };
353 };
354 union {
355 struct {
356 uint64_t _unused_dfsr;
357 uint64_t dfsr_ns;
358 uint64_t hsr;
359 uint64_t dfsr_s;
360 };
361 uint64_t esr_el[4];
362 };
363 uint32_t c6_region[8]; /* MPU base/size registers. */
364 union { /* Fault address registers. */
365 struct {
366 uint64_t _unused_far0;
367 #ifdef HOST_WORDS_BIGENDIAN
368 uint32_t ifar_ns;
369 uint32_t dfar_ns;
370 uint32_t ifar_s;
371 uint32_t dfar_s;
372 #else
373 uint32_t dfar_ns;
374 uint32_t ifar_ns;
375 uint32_t dfar_s;
376 uint32_t ifar_s;
377 #endif
378 uint64_t _unused_far3;
379 };
380 uint64_t far_el[4];
381 };
382 uint64_t hpfar_el2;
383 uint64_t hstr_el2;
384 union { /* Translation result. */
385 struct {
386 uint64_t _unused_par_0;
387 uint64_t par_ns;
388 uint64_t _unused_par_1;
389 uint64_t par_s;
390 };
391 uint64_t par_el[4];
392 };
393
394 uint32_t c9_insn; /* Cache lockdown registers. */
395 uint32_t c9_data;
396 uint64_t c9_pmcr; /* performance monitor control register */
397 uint64_t c9_pmcnten; /* perf monitor counter enables */
398 uint64_t c9_pmovsr; /* perf monitor overflow status */
399 uint64_t c9_pmuserenr; /* perf monitor user enable */
400 uint64_t c9_pmselr; /* perf monitor counter selection register */
401 uint64_t c9_pminten; /* perf monitor interrupt enables */
402 union { /* Memory attribute redirection */
403 struct {
404 #ifdef HOST_WORDS_BIGENDIAN
405 uint64_t _unused_mair_0;
406 uint32_t mair1_ns;
407 uint32_t mair0_ns;
408 uint64_t _unused_mair_1;
409 uint32_t mair1_s;
410 uint32_t mair0_s;
411 #else
412 uint64_t _unused_mair_0;
413 uint32_t mair0_ns;
414 uint32_t mair1_ns;
415 uint64_t _unused_mair_1;
416 uint32_t mair0_s;
417 uint32_t mair1_s;
418 #endif
419 };
420 uint64_t mair_el[4];
421 };
422 union { /* vector base address register */
423 struct {
424 uint64_t _unused_vbar;
425 uint64_t vbar_ns;
426 uint64_t hvbar;
427 uint64_t vbar_s;
428 };
429 uint64_t vbar_el[4];
430 };
431 uint32_t mvbar; /* (monitor) vector base address register */
432 struct { /* FCSE PID. */
433 uint32_t fcseidr_ns;
434 uint32_t fcseidr_s;
435 };
436 union { /* Context ID. */
437 struct {
438 uint64_t _unused_contextidr_0;
439 uint64_t contextidr_ns;
440 uint64_t _unused_contextidr_1;
441 uint64_t contextidr_s;
442 };
443 uint64_t contextidr_el[4];
444 };
445 union { /* User RW Thread register. */
446 struct {
447 uint64_t tpidrurw_ns;
448 uint64_t tpidrprw_ns;
449 uint64_t htpidr;
450 uint64_t _tpidr_el3;
451 };
452 uint64_t tpidr_el[4];
453 };
454 /* The secure banks of these registers don't map anywhere */
455 uint64_t tpidrurw_s;
456 uint64_t tpidrprw_s;
457 uint64_t tpidruro_s;
458
459 union { /* User RO Thread register. */
460 uint64_t tpidruro_ns;
461 uint64_t tpidrro_el[1];
462 };
463 uint64_t c14_cntfrq; /* Counter Frequency register */
464 uint64_t c14_cntkctl; /* Timer Control register */
465 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
466 uint64_t cntvoff_el2; /* Counter Virtual Offset register */
467 ARMGenericTimer c14_timer[NUM_GTIMERS];
468 uint32_t c15_cpar; /* XScale Coprocessor Access Register */
469 uint32_t c15_ticonfig; /* TI925T configuration byte. */
470 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
471 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
472 uint32_t c15_threadid; /* TI debugger thread-ID. */
473 uint32_t c15_config_base_address; /* SCU base address. */
474 uint32_t c15_diagnostic; /* diagnostic register */
475 uint32_t c15_power_diagnostic;
476 uint32_t c15_power_control; /* power control */
477 uint64_t dbgbvr[16]; /* breakpoint value registers */
478 uint64_t dbgbcr[16]; /* breakpoint control registers */
479 uint64_t dbgwvr[16]; /* watchpoint value registers */
480 uint64_t dbgwcr[16]; /* watchpoint control registers */
481 uint64_t mdscr_el1;
482 uint64_t oslsr_el1; /* OS Lock Status */
483 uint64_t mdcr_el2;
484 uint64_t mdcr_el3;
485 /* Stores the architectural value of the counter *the last time it was
486 * updated* by pmccntr_op_start. Accesses should always be surrounded
487 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest
488 * architecturally-correct value is being read/set.
489 */
490 uint64_t c15_ccnt;
491 /* Stores the delta between the architectural value and the underlying
492 * cycle count during normal operation. It is used to update c15_ccnt
493 * to be the correct architectural value before accesses. During
494 * accesses, c15_ccnt_delta contains the underlying count being used
495 * for the access, after which it reverts to the delta value in
496 * pmccntr_op_finish.
497 */
498 uint64_t c15_ccnt_delta;
499 uint64_t c14_pmevcntr[31];
500 uint64_t c14_pmevcntr_delta[31];
501 uint64_t c14_pmevtyper[31];
502 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
503 uint64_t vpidr_el2; /* Virtualization Processor ID Register */
504 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
505 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */
506 uint64_t gcr_el1;
507 uint64_t rgsr_el1;
508 } cp15;
509
510 struct {
511 /* M profile has up to 4 stack pointers:
512 * a Main Stack Pointer and a Process Stack Pointer for each
513 * of the Secure and Non-Secure states. (If the CPU doesn't support
514 * the security extension then it has only two SPs.)
515 * In QEMU we always store the currently active SP in regs[13],
516 * and the non-active SP for the current security state in
517 * v7m.other_sp. The stack pointers for the inactive security state
518 * are stored in other_ss_msp and other_ss_psp.
519 * switch_v7m_security_state() is responsible for rearranging them
520 * when we change security state.
521 */
522 uint32_t other_sp;
523 uint32_t other_ss_msp;
524 uint32_t other_ss_psp;
525 uint32_t vecbase[M_REG_NUM_BANKS];
526 uint32_t basepri[M_REG_NUM_BANKS];
527 uint32_t control[M_REG_NUM_BANKS];
528 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */
529 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
530 uint32_t hfsr; /* HardFault Status */
531 uint32_t dfsr; /* Debug Fault Status Register */
532 uint32_t sfsr; /* Secure Fault Status Register */
533 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
534 uint32_t bfar; /* BusFault Address */
535 uint32_t sfar; /* Secure Fault Address Register */
536 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
537 int exception;
538 uint32_t primask[M_REG_NUM_BANKS];
539 uint32_t faultmask[M_REG_NUM_BANKS];
540 uint32_t aircr; /* only holds r/w state if security extn implemented */
541 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
542 uint32_t csselr[M_REG_NUM_BANKS];
543 uint32_t scr[M_REG_NUM_BANKS];
544 uint32_t msplim[M_REG_NUM_BANKS];
545 uint32_t psplim[M_REG_NUM_BANKS];
546 uint32_t fpcar[M_REG_NUM_BANKS];
547 uint32_t fpccr[M_REG_NUM_BANKS];
548 uint32_t fpdscr[M_REG_NUM_BANKS];
549 uint32_t cpacr[M_REG_NUM_BANKS];
550 uint32_t nsacr;
551 } v7m;
552
553 /* Information associated with an exception about to be taken:
554 * code which raises an exception must set cs->exception_index and
555 * the relevant parts of this structure; the cpu_do_interrupt function
556 * will then set the guest-visible registers as part of the exception
557 * entry process.
558 */
559 struct {
560 uint32_t syndrome; /* AArch64 format syndrome register */
561 uint32_t fsr; /* AArch32 format fault status register info */
562 uint64_t vaddress; /* virtual addr associated with exception, if any */
563 uint32_t target_el; /* EL the exception should be targeted for */
564 /* If we implement EL2 we will also need to store information
565 * about the intermediate physical address for stage 2 faults.
566 */
567 } exception;
568
569 /* Information associated with an SError */
570 struct {
571 uint8_t pending;
572 uint8_t has_esr;
573 uint64_t esr;
574 } serror;
575
576 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
577
578 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
579 uint32_t irq_line_state;
580
581 /* Thumb-2 EE state. */
582 uint32_t teecr;
583 uint32_t teehbr;
584
585 /* VFP coprocessor state. */
586 struct {
587 ARMVectorReg zregs[32];
588
589 #ifdef TARGET_AARCH64
590 /* Store FFR as pregs[16] to make it easier to treat as any other. */
591 #define FFR_PRED_NUM 16
592 ARMPredicateReg pregs[17];
593 /* Scratch space for aa64 sve predicate temporary. */
594 ARMPredicateReg preg_tmp;
595 #endif
596
597 /* We store these fpcsr fields separately for convenience. */
598 uint32_t qc[4] QEMU_ALIGNED(16);
599 int vec_len;
600 int vec_stride;
601
602 uint32_t xregs[16];
603
604 /* Scratch space for aa32 neon expansion. */
605 uint32_t scratch[8];
606
607 /* There are a number of distinct float control structures:
608 *
609 * fp_status: is the "normal" fp status.
610 * fp_status_fp16: used for half-precision calculations
611 * standard_fp_status : the ARM "Standard FPSCR Value"
612 * standard_fp_status_fp16 : used for half-precision
613 * calculations with the ARM "Standard FPSCR Value"
614 *
615 * Half-precision operations are governed by a separate
616 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
617 * status structure to control this.
618 *
619 * The "Standard FPSCR", ie default-NaN, flush-to-zero,
620 * round-to-nearest and is used by any operations (generally
621 * Neon) which the architecture defines as controlled by the
622 * standard FPSCR value rather than the FPSCR.
623 *
624 * The "standard FPSCR but for fp16 ops" is needed because
625 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than
626 * using a fixed value for it.
627 *
628 * To avoid having to transfer exception bits around, we simply
629 * say that the FPSCR cumulative exception flags are the logical
630 * OR of the flags in the four fp statuses. This relies on the
631 * only thing which needs to read the exception flags being
632 * an explicit FPSCR read.
633 */
634 float_status fp_status;
635 float_status fp_status_f16;
636 float_status standard_fp_status;
637 float_status standard_fp_status_f16;
638
639 /* ZCR_EL[1-3] */
640 uint64_t zcr_el[4];
641 } vfp;
642 uint64_t exclusive_addr;
643 uint64_t exclusive_val;
644 uint64_t exclusive_high;
645
646 /* iwMMXt coprocessor state. */
647 struct {
648 uint64_t regs[16];
649 uint64_t val;
650
651 uint32_t cregs[16];
652 } iwmmxt;
653
654 #ifdef TARGET_AARCH64
655 struct {
656 ARMPACKey apia;
657 ARMPACKey apib;
658 ARMPACKey apda;
659 ARMPACKey apdb;
660 ARMPACKey apga;
661 } keys;
662 #endif
663
664 #if defined(CONFIG_USER_ONLY)
665 /* For usermode syscall translation. */
666 int eabi;
667 #endif
668
669 struct CPUBreakpoint *cpu_breakpoint[16];
670 struct CPUWatchpoint *cpu_watchpoint[16];
671
672 /* Fields up to this point are cleared by a CPU reset */
673 struct {} end_reset_fields;
674
675 /* Fields after this point are preserved across CPU reset. */
676
677 /* Internal CPU feature flags. */
678 uint64_t features;
679
680 /* PMSAv7 MPU */
681 struct {
682 uint32_t *drbar;
683 uint32_t *drsr;
684 uint32_t *dracr;
685 uint32_t rnr[M_REG_NUM_BANKS];
686 } pmsav7;
687
688 /* PMSAv8 MPU */
689 struct {
690 /* The PMSAv8 implementation also shares some PMSAv7 config
691 * and state:
692 * pmsav7.rnr (region number register)
693 * pmsav7_dregion (number of configured regions)
694 */
695 uint32_t *rbar[M_REG_NUM_BANKS];
696 uint32_t *rlar[M_REG_NUM_BANKS];
697 uint32_t mair0[M_REG_NUM_BANKS];
698 uint32_t mair1[M_REG_NUM_BANKS];
699 } pmsav8;
700
701 /* v8M SAU */
702 struct {
703 uint32_t *rbar;
704 uint32_t *rlar;
705 uint32_t rnr;
706 uint32_t ctrl;
707 } sau;
708
709 void *nvic;
710 const struct arm_boot_info *boot_info;
711 /* Store GICv3CPUState to access from this struct */
712 void *gicv3state;
713 } CPUARMState;
714
715 static inline void set_feature(CPUARMState *env, int feature)
716 {
717 env->features |= 1ULL << feature;
718 }
719
720 static inline void unset_feature(CPUARMState *env, int feature)
721 {
722 env->features &= ~(1ULL << feature);
723 }
724
725 /**
726 * ARMELChangeHookFn:
727 * type of a function which can be registered via arm_register_el_change_hook()
728 * to get callbacks when the CPU changes its exception level or mode.
729 */
730 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
731 typedef struct ARMELChangeHook ARMELChangeHook;
732 struct ARMELChangeHook {
733 ARMELChangeHookFn *hook;
734 void *opaque;
735 QLIST_ENTRY(ARMELChangeHook) node;
736 };
737
738 /* These values map onto the return values for
739 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */
740 typedef enum ARMPSCIState {
741 PSCI_ON = 0,
742 PSCI_OFF = 1,
743 PSCI_ON_PENDING = 2
744 } ARMPSCIState;
745
746 typedef struct ARMISARegisters ARMISARegisters;
747
748 /**
749 * ARMCPU:
750 * @env: #CPUARMState
751 *
752 * An ARM CPU core.
753 */
754 struct ARMCPU {
755 /*< private >*/
756 CPUState parent_obj;
757 /*< public >*/
758
759 CPUNegativeOffsetState neg;
760 CPUARMState env;
761
762 /* Coprocessor information */
763 GHashTable *cp_regs;
764 /* For marshalling (mostly coprocessor) register state between the
765 * kernel and QEMU (for KVM) and between two QEMUs (for migration),
766 * we use these arrays.
767 */
768 /* List of register indexes managed via these arrays; (full KVM style
769 * 64 bit indexes, not CPRegInfo 32 bit indexes)
770 */
771 uint64_t *cpreg_indexes;
772 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
773 uint64_t *cpreg_values;
774 /* Length of the indexes, values, reset_values arrays */
775 int32_t cpreg_array_len;
776 /* These are used only for migration: incoming data arrives in
777 * these fields and is sanity checked in post_load before copying
778 * to the working data structures above.
779 */
780 uint64_t *cpreg_vmstate_indexes;
781 uint64_t *cpreg_vmstate_values;
782 int32_t cpreg_vmstate_array_len;
783
784 DynamicGDBXMLInfo dyn_sysreg_xml;
785 DynamicGDBXMLInfo dyn_svereg_xml;
786
787 /* Timers used by the generic (architected) timer */
788 QEMUTimer *gt_timer[NUM_GTIMERS];
789 /*
790 * Timer used by the PMU. Its state is restored after migration by
791 * pmu_op_finish() - it does not need other handling during migration
792 */
793 QEMUTimer *pmu_timer;
794 /* GPIO outputs for generic timer */
795 qemu_irq gt_timer_outputs[NUM_GTIMERS];
796 /* GPIO output for GICv3 maintenance interrupt signal */
797 qemu_irq gicv3_maintenance_interrupt;
798 /* GPIO output for the PMU interrupt */
799 qemu_irq pmu_interrupt;
800
801 /* MemoryRegion to use for secure physical accesses */
802 MemoryRegion *secure_memory;
803
804 /* MemoryRegion to use for allocation tag accesses */
805 MemoryRegion *tag_memory;
806 MemoryRegion *secure_tag_memory;
807
808 /* For v8M, pointer to the IDAU interface provided by board/SoC */
809 Object *idau;
810
811 /* 'compatible' string for this CPU for Linux device trees */
812 const char *dtb_compatible;
813
814 /* PSCI version for this CPU
815 * Bits[31:16] = Major Version
816 * Bits[15:0] = Minor Version
817 */
818 uint32_t psci_version;
819
820 /* Current power state, access guarded by BQL */
821 ARMPSCIState power_state;
822
823 /* CPU has virtualization extension */
824 bool has_el2;
825 /* CPU has security extension */
826 bool has_el3;
827 /* CPU has PMU (Performance Monitor Unit) */
828 bool has_pmu;
829 /* CPU has VFP */
830 bool has_vfp;
831 /* CPU has Neon */
832 bool has_neon;
833 /* CPU has M-profile DSP extension */
834 bool has_dsp;
835
836 /* CPU has memory protection unit */
837 bool has_mpu;
838 /* PMSAv7 MPU number of supported regions */
839 uint32_t pmsav7_dregion;
840 /* v8M SAU number of supported regions */
841 uint32_t sau_sregion;
842
843 /* PSCI conduit used to invoke PSCI methods
844 * 0 - disabled, 1 - smc, 2 - hvc
845 */
846 uint32_t psci_conduit;
847
848 /* For v8M, initial value of the Secure VTOR */
849 uint32_t init_svtor;
850
851 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
852 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
853 */
854 uint32_t kvm_target;
855
856 /* KVM init features for this CPU */
857 uint32_t kvm_init_features[7];
858
859 /* KVM CPU state */
860
861 /* KVM virtual time adjustment */
862 bool kvm_adjvtime;
863 bool kvm_vtime_dirty;
864 uint64_t kvm_vtime;
865
866 /* Uniprocessor system with MP extensions */
867 bool mp_is_up;
868
869 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init
870 * and the probe failed (so we need to report the error in realize)
871 */
872 bool host_cpu_probe_failed;
873
874 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
875 * register.
876 */
877 int32_t core_count;
878
879 /* The instance init functions for implementation-specific subclasses
880 * set these fields to specify the implementation-dependent values of
881 * various constant registers and reset values of non-constant
882 * registers.
883 * Some of these might become QOM properties eventually.
884 * Field names match the official register names as defined in the
885 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
886 * is used for reset values of non-constant registers; no reset_
887 * prefix means a constant register.
888 * Some of these registers are split out into a substructure that
889 * is shared with the translators to control the ISA.
890 *
891 * Note that if you add an ID register to the ARMISARegisters struct
892 * you need to also update the 32-bit and 64-bit versions of the
893 * kvm_arm_get_host_cpu_features() function to correctly populate the
894 * field by reading the value from the KVM vCPU.
895 */
896 struct ARMISARegisters {
897 uint32_t id_isar0;
898 uint32_t id_isar1;
899 uint32_t id_isar2;
900 uint32_t id_isar3;
901 uint32_t id_isar4;
902 uint32_t id_isar5;
903 uint32_t id_isar6;
904 uint32_t id_mmfr0;
905 uint32_t id_mmfr1;
906 uint32_t id_mmfr2;
907 uint32_t id_mmfr3;
908 uint32_t id_mmfr4;
909 uint32_t mvfr0;
910 uint32_t mvfr1;
911 uint32_t mvfr2;
912 uint32_t id_dfr0;
913 uint32_t dbgdidr;
914 uint64_t id_aa64isar0;
915 uint64_t id_aa64isar1;
916 uint64_t id_aa64pfr0;
917 uint64_t id_aa64pfr1;
918 uint64_t id_aa64mmfr0;
919 uint64_t id_aa64mmfr1;
920 uint64_t id_aa64mmfr2;
921 uint64_t id_aa64dfr0;
922 uint64_t id_aa64dfr1;
923 } isar;
924 uint64_t midr;
925 uint32_t revidr;
926 uint32_t reset_fpsid;
927 uint32_t ctr;
928 uint32_t reset_sctlr;
929 uint32_t id_pfr0;
930 uint32_t id_pfr1;
931 uint64_t pmceid0;
932 uint64_t pmceid1;
933 uint32_t id_afr0;
934 uint64_t id_aa64afr0;
935 uint64_t id_aa64afr1;
936 uint32_t clidr;
937 uint64_t mp_affinity; /* MP ID without feature bits */
938 /* The elements of this array are the CCSIDR values for each cache,
939 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
940 */
941 uint64_t ccsidr[16];
942 uint64_t reset_cbar;
943 uint32_t reset_auxcr;
944 bool reset_hivecs;
945 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
946 uint32_t dcz_blocksize;
947 uint64_t rvbar;
948
949 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
950 int gic_num_lrs; /* number of list registers */
951 int gic_vpribits; /* number of virtual priority bits */
952 int gic_vprebits; /* number of virtual preemption bits */
953
954 /* Whether the cfgend input is high (i.e. this CPU should reset into
955 * big-endian mode). This setting isn't used directly: instead it modifies
956 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
957 * architecture version.
958 */
959 bool cfgend;
960
961 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
962 QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
963
964 int32_t node_id; /* NUMA node this CPU belongs to */
965
966 /* Used to synchronize KVM and QEMU in-kernel device levels */
967 uint8_t device_irq_level;
968
969 /* Used to set the maximum vector length the cpu will support. */
970 uint32_t sve_max_vq;
971
972 /*
973 * In sve_vq_map each set bit is a supported vector length of
974 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector
975 * length in quadwords.
976 *
977 * While processing properties during initialization, corresponding
978 * sve_vq_init bits are set for bits in sve_vq_map that have been
979 * set by properties.
980 */
981 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ);
982 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ);
983
984 /* Generic timer counter frequency, in Hz */
985 uint64_t gt_cntfrq_hz;
986 };
987
988 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
989
990 void arm_cpu_post_init(Object *obj);
991
992 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
993
994 #ifndef CONFIG_USER_ONLY
995 extern const VMStateDescription vmstate_arm_cpu;
996 #endif
997
998 void arm_cpu_do_interrupt(CPUState *cpu);
999 void arm_v7m_cpu_do_interrupt(CPUState *cpu);
1000 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
1001
1002 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1003 MemTxAttrs *attrs);
1004
1005 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1006 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1007
1008 /*
1009 * Helpers to dynamically generates XML descriptions of the sysregs
1010 * and SVE registers. Returns the number of registers in each set.
1011 */
1012 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
1013 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
1014
1015 /* Returns the dynamically generated XML for the gdb stub.
1016 * Returns a pointer to the XML contents for the specified XML file or NULL
1017 * if the XML name doesn't match the predefined one.
1018 */
1019 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
1020
1021 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1022 int cpuid, void *opaque);
1023 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1024 int cpuid, void *opaque);
1025
1026 #ifdef TARGET_AARCH64
1027 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1028 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1029 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
1030 void aarch64_sve_change_el(CPUARMState *env, int old_el,
1031 int new_el, bool el0_a64);
1032 void aarch64_add_sve_properties(Object *obj);
1033
1034 /*
1035 * SVE registers are encoded in KVM's memory in an endianness-invariant format.
1036 * The byte at offset i from the start of the in-memory representation contains
1037 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
1038 * lowest offsets are stored in the lowest memory addresses, then that nearly
1039 * matches QEMU's representation, which is to use an array of host-endian
1040 * uint64_t's, where the lower offsets are at the lower indices. To complete
1041 * the translation we just need to byte swap the uint64_t's on big-endian hosts.
1042 */
1043 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
1044 {
1045 #ifdef HOST_WORDS_BIGENDIAN
1046 int i;
1047
1048 for (i = 0; i < nr; ++i) {
1049 dst[i] = bswap64(src[i]);
1050 }
1051
1052 return dst;
1053 #else
1054 return src;
1055 #endif
1056 }
1057
1058 #else
1059 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
1060 static inline void aarch64_sve_change_el(CPUARMState *env, int o,
1061 int n, bool a)
1062 { }
1063 static inline void aarch64_add_sve_properties(Object *obj) { }
1064 #endif
1065
1066 #if !defined(CONFIG_TCG)
1067 static inline target_ulong do_arm_semihosting(CPUARMState *env)
1068 {
1069 g_assert_not_reached();
1070 }
1071 #else
1072 target_ulong do_arm_semihosting(CPUARMState *env);
1073 #endif
1074 void aarch64_sync_32_to_64(CPUARMState *env);
1075 void aarch64_sync_64_to_32(CPUARMState *env);
1076
1077 int fp_exception_el(CPUARMState *env, int cur_el);
1078 int sve_exception_el(CPUARMState *env, int cur_el);
1079 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el);
1080
1081 static inline bool is_a64(CPUARMState *env)
1082 {
1083 return env->aarch64;
1084 }
1085
1086 /* you can call this signal handler from your SIGBUS and SIGSEGV
1087 signal handlers to inform the virtual CPU of exceptions. non zero
1088 is returned if the signal was handled by the virtual CPU. */
1089 int cpu_arm_signal_handler(int host_signum, void *pinfo,
1090 void *puc);
1091
1092 /**
1093 * pmu_op_start/finish
1094 * @env: CPUARMState
1095 *
1096 * Convert all PMU counters between their delta form (the typical mode when
1097 * they are enabled) and the guest-visible values. These two calls must
1098 * surround any action which might affect the counters.
1099 */
1100 void pmu_op_start(CPUARMState *env);
1101 void pmu_op_finish(CPUARMState *env);
1102
1103 /*
1104 * Called when a PMU counter is due to overflow
1105 */
1106 void arm_pmu_timer_cb(void *opaque);
1107
1108 /**
1109 * Functions to register as EL change hooks for PMU mode filtering
1110 */
1111 void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1112 void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1113
1114 /*
1115 * pmu_init
1116 * @cpu: ARMCPU
1117 *
1118 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state
1119 * for the current configuration
1120 */
1121 void pmu_init(ARMCPU *cpu);
1122
1123 /* SCTLR bit meanings. Several bits have been reused in newer
1124 * versions of the architecture; in that case we define constants
1125 * for both old and new bit meanings. Code which tests against those
1126 * bits should probably check or otherwise arrange that the CPU
1127 * is the architectural version it expects.
1128 */
1129 #define SCTLR_M (1U << 0)
1130 #define SCTLR_A (1U << 1)
1131 #define SCTLR_C (1U << 2)
1132 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
1133 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1134 #define SCTLR_SA (1U << 3) /* AArch64 only */
1135 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
1136 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
1137 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
1138 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
1139 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
1140 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
1141 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */
1142 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
1143 #define SCTLR_ITD (1U << 7) /* v8 onward */
1144 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
1145 #define SCTLR_SED (1U << 8) /* v8 onward */
1146 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
1147 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
1148 #define SCTLR_F (1U << 10) /* up to v6 */
1149 #define SCTLR_SW (1U << 10) /* v7 */
1150 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */
1151 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */
1152 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */
1153 #define SCTLR_I (1U << 12)
1154 #define SCTLR_V (1U << 13) /* AArch32 only */
1155 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */
1156 #define SCTLR_RR (1U << 14) /* up to v7 */
1157 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
1158 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
1159 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
1160 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
1161 #define SCTLR_nTWI (1U << 16) /* v8 onward */
1162 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */
1163 #define SCTLR_BR (1U << 17) /* PMSA only */
1164 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
1165 #define SCTLR_nTWE (1U << 18) /* v8 onward */
1166 #define SCTLR_WXN (1U << 19)
1167 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
1168 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */
1169 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */
1170 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
1171 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */
1172 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */
1173 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
1174 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */
1175 #define SCTLR_VE (1U << 24) /* up to v7 */
1176 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
1177 #define SCTLR_EE (1U << 25)
1178 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
1179 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
1180 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */
1181 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */
1182 #define SCTLR_TRE (1U << 28) /* AArch32 only */
1183 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
1184 #define SCTLR_AFE (1U << 29) /* AArch32 only */
1185 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
1186 #define SCTLR_TE (1U << 30) /* AArch32 only */
1187 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */
1188 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */
1189 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
1190 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
1191 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
1192 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */
1193 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */
1194 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
1195 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
1196 #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */
1197
1198 #define CPTR_TCPAC (1U << 31)
1199 #define CPTR_TTA (1U << 20)
1200 #define CPTR_TFP (1U << 10)
1201 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */
1202 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */
1203
1204 #define MDCR_EPMAD (1U << 21)
1205 #define MDCR_EDAD (1U << 20)
1206 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */
1207 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
1208 #define MDCR_SDD (1U << 16)
1209 #define MDCR_SPD (3U << 14)
1210 #define MDCR_TDRA (1U << 11)
1211 #define MDCR_TDOSA (1U << 10)
1212 #define MDCR_TDA (1U << 9)
1213 #define MDCR_TDE (1U << 8)
1214 #define MDCR_HPME (1U << 7)
1215 #define MDCR_TPM (1U << 6)
1216 #define MDCR_TPMCR (1U << 5)
1217 #define MDCR_HPMN (0x1fU)
1218
1219 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
1220 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
1221
1222 #define CPSR_M (0x1fU)
1223 #define CPSR_T (1U << 5)
1224 #define CPSR_F (1U << 6)
1225 #define CPSR_I (1U << 7)
1226 #define CPSR_A (1U << 8)
1227 #define CPSR_E (1U << 9)
1228 #define CPSR_IT_2_7 (0xfc00U)
1229 #define CPSR_GE (0xfU << 16)
1230 #define CPSR_IL (1U << 20)
1231 #define CPSR_PAN (1U << 22)
1232 #define CPSR_J (1U << 24)
1233 #define CPSR_IT_0_1 (3U << 25)
1234 #define CPSR_Q (1U << 27)
1235 #define CPSR_V (1U << 28)
1236 #define CPSR_C (1U << 29)
1237 #define CPSR_Z (1U << 30)
1238 #define CPSR_N (1U << 31)
1239 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1240 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1241
1242 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1243 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1244 | CPSR_NZCV)
1245 /* Bits writable in user mode. */
1246 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1247 /* Execution state bits. MRS read as zero, MSR writes ignored. */
1248 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1249
1250 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */
1251 #define XPSR_EXCP 0x1ffU
1252 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */
1253 #define XPSR_IT_2_7 CPSR_IT_2_7
1254 #define XPSR_GE CPSR_GE
1255 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */
1256 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */
1257 #define XPSR_IT_0_1 CPSR_IT_0_1
1258 #define XPSR_Q CPSR_Q
1259 #define XPSR_V CPSR_V
1260 #define XPSR_C CPSR_C
1261 #define XPSR_Z CPSR_Z
1262 #define XPSR_N CPSR_N
1263 #define XPSR_NZCV CPSR_NZCV
1264 #define XPSR_IT CPSR_IT
1265
1266 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
1267 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
1268 #define TTBCR_PD0 (1U << 4)
1269 #define TTBCR_PD1 (1U << 5)
1270 #define TTBCR_EPD0 (1U << 7)
1271 #define TTBCR_IRGN0 (3U << 8)
1272 #define TTBCR_ORGN0 (3U << 10)
1273 #define TTBCR_SH0 (3U << 12)
1274 #define TTBCR_T1SZ (3U << 16)
1275 #define TTBCR_A1 (1U << 22)
1276 #define TTBCR_EPD1 (1U << 23)
1277 #define TTBCR_IRGN1 (3U << 24)
1278 #define TTBCR_ORGN1 (3U << 26)
1279 #define TTBCR_SH1 (1U << 28)
1280 #define TTBCR_EAE (1U << 31)
1281
1282 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
1283 * Only these are valid when in AArch64 mode; in
1284 * AArch32 mode SPSRs are basically CPSR-format.
1285 */
1286 #define PSTATE_SP (1U)
1287 #define PSTATE_M (0xFU)
1288 #define PSTATE_nRW (1U << 4)
1289 #define PSTATE_F (1U << 6)
1290 #define PSTATE_I (1U << 7)
1291 #define PSTATE_A (1U << 8)
1292 #define PSTATE_D (1U << 9)
1293 #define PSTATE_BTYPE (3U << 10)
1294 #define PSTATE_IL (1U << 20)
1295 #define PSTATE_SS (1U << 21)
1296 #define PSTATE_PAN (1U << 22)
1297 #define PSTATE_UAO (1U << 23)
1298 #define PSTATE_TCO (1U << 25)
1299 #define PSTATE_V (1U << 28)
1300 #define PSTATE_C (1U << 29)
1301 #define PSTATE_Z (1U << 30)
1302 #define PSTATE_N (1U << 31)
1303 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1304 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1305 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1306 /* Mode values for AArch64 */
1307 #define PSTATE_MODE_EL3h 13
1308 #define PSTATE_MODE_EL3t 12
1309 #define PSTATE_MODE_EL2h 9
1310 #define PSTATE_MODE_EL2t 8
1311 #define PSTATE_MODE_EL1h 5
1312 #define PSTATE_MODE_EL1t 4
1313 #define PSTATE_MODE_EL0t 0
1314
1315 /* Write a new value to v7m.exception, thus transitioning into or out
1316 * of Handler mode; this may result in a change of active stack pointer.
1317 */
1318 void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1319
1320 /* Map EL and handler into a PSTATE_MODE. */
1321 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1322 {
1323 return (el << 2) | handler;
1324 }
1325
1326 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1327 * interprocessing, so we don't attempt to sync with the cpsr state used by
1328 * the 32 bit decoder.
1329 */
1330 static inline uint32_t pstate_read(CPUARMState *env)
1331 {
1332 int ZF;
1333
1334 ZF = (env->ZF == 0);
1335 return (env->NF & 0x80000000) | (ZF << 30)
1336 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1337 | env->pstate | env->daif | (env->btype << 10);
1338 }
1339
1340 static inline void pstate_write(CPUARMState *env, uint32_t val)
1341 {
1342 env->ZF = (~val) & PSTATE_Z;
1343 env->NF = val;
1344 env->CF = (val >> 29) & 1;
1345 env->VF = (val << 3) & 0x80000000;
1346 env->daif = val & PSTATE_DAIF;
1347 env->btype = (val >> 10) & 3;
1348 env->pstate = val & ~CACHED_PSTATE_BITS;
1349 }
1350
1351 /* Return the current CPSR value. */
1352 uint32_t cpsr_read(CPUARMState *env);
1353
1354 typedef enum CPSRWriteType {
1355 CPSRWriteByInstr = 0, /* from guest MSR or CPS */
1356 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
1357 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */
1358 CPSRWriteByGDBStub = 3, /* from the GDB stub */
1359 } CPSRWriteType;
1360
1361 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/
1362 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1363 CPSRWriteType write_type);
1364
1365 /* Return the current xPSR value. */
1366 static inline uint32_t xpsr_read(CPUARMState *env)
1367 {
1368 int ZF;
1369 ZF = (env->ZF == 0);
1370 return (env->NF & 0x80000000) | (ZF << 30)
1371 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1372 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1373 | ((env->condexec_bits & 0xfc) << 8)
1374 | (env->GE << 16)
1375 | env->v7m.exception;
1376 }
1377
1378 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
1379 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1380 {
1381 if (mask & XPSR_NZCV) {
1382 env->ZF = (~val) & XPSR_Z;
1383 env->NF = val;
1384 env->CF = (val >> 29) & 1;
1385 env->VF = (val << 3) & 0x80000000;
1386 }
1387 if (mask & XPSR_Q) {
1388 env->QF = ((val & XPSR_Q) != 0);
1389 }
1390 if (mask & XPSR_GE) {
1391 env->GE = (val & XPSR_GE) >> 16;
1392 }
1393 #ifndef CONFIG_USER_ONLY
1394 if (mask & XPSR_T) {
1395 env->thumb = ((val & XPSR_T) != 0);
1396 }
1397 if (mask & XPSR_IT_0_1) {
1398 env->condexec_bits &= ~3;
1399 env->condexec_bits |= (val >> 25) & 3;
1400 }
1401 if (mask & XPSR_IT_2_7) {
1402 env->condexec_bits &= 3;
1403 env->condexec_bits |= (val >> 8) & 0xfc;
1404 }
1405 if (mask & XPSR_EXCP) {
1406 /* Note that this only happens on exception exit */
1407 write_v7m_exception(env, val & XPSR_EXCP);
1408 }
1409 #endif
1410 }
1411
1412 #define HCR_VM (1ULL << 0)
1413 #define HCR_SWIO (1ULL << 1)
1414 #define HCR_PTW (1ULL << 2)
1415 #define HCR_FMO (1ULL << 3)
1416 #define HCR_IMO (1ULL << 4)
1417 #define HCR_AMO (1ULL << 5)
1418 #define HCR_VF (1ULL << 6)
1419 #define HCR_VI (1ULL << 7)
1420 #define HCR_VSE (1ULL << 8)
1421 #define HCR_FB (1ULL << 9)
1422 #define HCR_BSU_MASK (3ULL << 10)
1423 #define HCR_DC (1ULL << 12)
1424 #define HCR_TWI (1ULL << 13)
1425 #define HCR_TWE (1ULL << 14)
1426 #define HCR_TID0 (1ULL << 15)
1427 #define HCR_TID1 (1ULL << 16)
1428 #define HCR_TID2 (1ULL << 17)
1429 #define HCR_TID3 (1ULL << 18)
1430 #define HCR_TSC (1ULL << 19)
1431 #define HCR_TIDCP (1ULL << 20)
1432 #define HCR_TACR (1ULL << 21)
1433 #define HCR_TSW (1ULL << 22)
1434 #define HCR_TPCP (1ULL << 23)
1435 #define HCR_TPU (1ULL << 24)
1436 #define HCR_TTLB (1ULL << 25)
1437 #define HCR_TVM (1ULL << 26)
1438 #define HCR_TGE (1ULL << 27)
1439 #define HCR_TDZ (1ULL << 28)
1440 #define HCR_HCD (1ULL << 29)
1441 #define HCR_TRVM (1ULL << 30)
1442 #define HCR_RW (1ULL << 31)
1443 #define HCR_CD (1ULL << 32)
1444 #define HCR_ID (1ULL << 33)
1445 #define HCR_E2H (1ULL << 34)
1446 #define HCR_TLOR (1ULL << 35)
1447 #define HCR_TERR (1ULL << 36)
1448 #define HCR_TEA (1ULL << 37)
1449 #define HCR_MIOCNCE (1ULL << 38)
1450 /* RES0 bit 39 */
1451 #define HCR_APK (1ULL << 40)
1452 #define HCR_API (1ULL << 41)
1453 #define HCR_NV (1ULL << 42)
1454 #define HCR_NV1 (1ULL << 43)
1455 #define HCR_AT (1ULL << 44)
1456 #define HCR_NV2 (1ULL << 45)
1457 #define HCR_FWB (1ULL << 46)
1458 #define HCR_FIEN (1ULL << 47)
1459 /* RES0 bit 48 */
1460 #define HCR_TID4 (1ULL << 49)
1461 #define HCR_TICAB (1ULL << 50)
1462 #define HCR_AMVOFFEN (1ULL << 51)
1463 #define HCR_TOCU (1ULL << 52)
1464 #define HCR_ENSCXT (1ULL << 53)
1465 #define HCR_TTLBIS (1ULL << 54)
1466 #define HCR_TTLBOS (1ULL << 55)
1467 #define HCR_ATA (1ULL << 56)
1468 #define HCR_DCT (1ULL << 57)
1469 #define HCR_TID5 (1ULL << 58)
1470 #define HCR_TWEDEN (1ULL << 59)
1471 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
1472
1473 #define SCR_NS (1U << 0)
1474 #define SCR_IRQ (1U << 1)
1475 #define SCR_FIQ (1U << 2)
1476 #define SCR_EA (1U << 3)
1477 #define SCR_FW (1U << 4)
1478 #define SCR_AW (1U << 5)
1479 #define SCR_NET (1U << 6)
1480 #define SCR_SMD (1U << 7)
1481 #define SCR_HCE (1U << 8)
1482 #define SCR_SIF (1U << 9)
1483 #define SCR_RW (1U << 10)
1484 #define SCR_ST (1U << 11)
1485 #define SCR_TWI (1U << 12)
1486 #define SCR_TWE (1U << 13)
1487 #define SCR_TLOR (1U << 14)
1488 #define SCR_TERR (1U << 15)
1489 #define SCR_APK (1U << 16)
1490 #define SCR_API (1U << 17)
1491 #define SCR_EEL2 (1U << 18)
1492 #define SCR_EASE (1U << 19)
1493 #define SCR_NMEA (1U << 20)
1494 #define SCR_FIEN (1U << 21)
1495 #define SCR_ENSCXT (1U << 25)
1496 #define SCR_ATA (1U << 26)
1497
1498 /* Return the current FPSCR value. */
1499 uint32_t vfp_get_fpscr(CPUARMState *env);
1500 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1501
1502 /* FPCR, Floating Point Control Register
1503 * FPSR, Floating Poiht Status Register
1504 *
1505 * For A64 the FPSCR is split into two logically distinct registers,
1506 * FPCR and FPSR. However since they still use non-overlapping bits
1507 * we store the underlying state in fpscr and just mask on read/write.
1508 */
1509 #define FPSR_MASK 0xf800009f
1510 #define FPCR_MASK 0x07ff9f00
1511
1512 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */
1513 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */
1514 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */
1515 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */
1516 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */
1517 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */
1518 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
1519 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
1520 #define FPCR_DN (1 << 25) /* Default NaN enable bit */
1521 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */
1522
1523 static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1524 {
1525 return vfp_get_fpscr(env) & FPSR_MASK;
1526 }
1527
1528 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1529 {
1530 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1531 vfp_set_fpscr(env, new_fpscr);
1532 }
1533
1534 static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1535 {
1536 return vfp_get_fpscr(env) & FPCR_MASK;
1537 }
1538
1539 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1540 {
1541 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1542 vfp_set_fpscr(env, new_fpscr);
1543 }
1544
1545 enum arm_cpu_mode {
1546 ARM_CPU_MODE_USR = 0x10,
1547 ARM_CPU_MODE_FIQ = 0x11,
1548 ARM_CPU_MODE_IRQ = 0x12,
1549 ARM_CPU_MODE_SVC = 0x13,
1550 ARM_CPU_MODE_MON = 0x16,
1551 ARM_CPU_MODE_ABT = 0x17,
1552 ARM_CPU_MODE_HYP = 0x1a,
1553 ARM_CPU_MODE_UND = 0x1b,
1554 ARM_CPU_MODE_SYS = 0x1f
1555 };
1556
1557 /* VFP system registers. */
1558 #define ARM_VFP_FPSID 0
1559 #define ARM_VFP_FPSCR 1
1560 #define ARM_VFP_MVFR2 5
1561 #define ARM_VFP_MVFR1 6
1562 #define ARM_VFP_MVFR0 7
1563 #define ARM_VFP_FPEXC 8
1564 #define ARM_VFP_FPINST 9
1565 #define ARM_VFP_FPINST2 10
1566
1567 /* iwMMXt coprocessor control registers. */
1568 #define ARM_IWMMXT_wCID 0
1569 #define ARM_IWMMXT_wCon 1
1570 #define ARM_IWMMXT_wCSSF 2
1571 #define ARM_IWMMXT_wCASF 3
1572 #define ARM_IWMMXT_wCGR0 8
1573 #define ARM_IWMMXT_wCGR1 9
1574 #define ARM_IWMMXT_wCGR2 10
1575 #define ARM_IWMMXT_wCGR3 11
1576
1577 /* V7M CCR bits */
1578 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1579 FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1580 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1581 FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1582 FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1583 FIELD(V7M_CCR, STKALIGN, 9, 1)
1584 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1585 FIELD(V7M_CCR, DC, 16, 1)
1586 FIELD(V7M_CCR, IC, 17, 1)
1587 FIELD(V7M_CCR, BP, 18, 1)
1588
1589 /* V7M SCR bits */
1590 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1591 FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1592 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1593 FIELD(V7M_SCR, SEVONPEND, 4, 1)
1594
1595 /* V7M AIRCR bits */
1596 FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1597 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1598 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1599 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1600 FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1601 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1602 FIELD(V7M_AIRCR, PRIS, 14, 1)
1603 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1604 FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1605
1606 /* V7M CFSR bits for MMFSR */
1607 FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1608 FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1609 FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1610 FIELD(V7M_CFSR, MSTKERR, 4, 1)
1611 FIELD(V7M_CFSR, MLSPERR, 5, 1)
1612 FIELD(V7M_CFSR, MMARVALID, 7, 1)
1613
1614 /* V7M CFSR bits for BFSR */
1615 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1616 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1617 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1618 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1619 FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1620 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1621 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1622
1623 /* V7M CFSR bits for UFSR */
1624 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1625 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1626 FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1627 FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1628 FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1629 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1630 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1631
1632 /* V7M CFSR bit masks covering all of the subregister bits */
1633 FIELD(V7M_CFSR, MMFSR, 0, 8)
1634 FIELD(V7M_CFSR, BFSR, 8, 8)
1635 FIELD(V7M_CFSR, UFSR, 16, 16)
1636
1637 /* V7M HFSR bits */
1638 FIELD(V7M_HFSR, VECTTBL, 1, 1)
1639 FIELD(V7M_HFSR, FORCED, 30, 1)
1640 FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1641
1642 /* V7M DFSR bits */
1643 FIELD(V7M_DFSR, HALTED, 0, 1)
1644 FIELD(V7M_DFSR, BKPT, 1, 1)
1645 FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1646 FIELD(V7M_DFSR, VCATCH, 3, 1)
1647 FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1648
1649 /* V7M SFSR bits */
1650 FIELD(V7M_SFSR, INVEP, 0, 1)
1651 FIELD(V7M_SFSR, INVIS, 1, 1)
1652 FIELD(V7M_SFSR, INVER, 2, 1)
1653 FIELD(V7M_SFSR, AUVIOL, 3, 1)
1654 FIELD(V7M_SFSR, INVTRAN, 4, 1)
1655 FIELD(V7M_SFSR, LSPERR, 5, 1)
1656 FIELD(V7M_SFSR, SFARVALID, 6, 1)
1657 FIELD(V7M_SFSR, LSERR, 7, 1)
1658
1659 /* v7M MPU_CTRL bits */
1660 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1661 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1662 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1663
1664 /* v7M CLIDR bits */
1665 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1666 FIELD(V7M_CLIDR, LOUIS, 21, 3)
1667 FIELD(V7M_CLIDR, LOC, 24, 3)
1668 FIELD(V7M_CLIDR, LOUU, 27, 3)
1669 FIELD(V7M_CLIDR, ICB, 30, 2)
1670
1671 FIELD(V7M_CSSELR, IND, 0, 1)
1672 FIELD(V7M_CSSELR, LEVEL, 1, 3)
1673 /* We use the combination of InD and Level to index into cpu->ccsidr[];
1674 * define a mask for this and check that it doesn't permit running off
1675 * the end of the array.
1676 */
1677 FIELD(V7M_CSSELR, INDEX, 0, 4)
1678
1679 /* v7M FPCCR bits */
1680 FIELD(V7M_FPCCR, LSPACT, 0, 1)
1681 FIELD(V7M_FPCCR, USER, 1, 1)
1682 FIELD(V7M_FPCCR, S, 2, 1)
1683 FIELD(V7M_FPCCR, THREAD, 3, 1)
1684 FIELD(V7M_FPCCR, HFRDY, 4, 1)
1685 FIELD(V7M_FPCCR, MMRDY, 5, 1)
1686 FIELD(V7M_FPCCR, BFRDY, 6, 1)
1687 FIELD(V7M_FPCCR, SFRDY, 7, 1)
1688 FIELD(V7M_FPCCR, MONRDY, 8, 1)
1689 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1690 FIELD(V7M_FPCCR, UFRDY, 10, 1)
1691 FIELD(V7M_FPCCR, RES0, 11, 15)
1692 FIELD(V7M_FPCCR, TS, 26, 1)
1693 FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1694 FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1695 FIELD(V7M_FPCCR, LSPENS, 29, 1)
1696 FIELD(V7M_FPCCR, LSPEN, 30, 1)
1697 FIELD(V7M_FPCCR, ASPEN, 31, 1)
1698 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */
1699 #define R_V7M_FPCCR_BANKED_MASK \
1700 (R_V7M_FPCCR_LSPACT_MASK | \
1701 R_V7M_FPCCR_USER_MASK | \
1702 R_V7M_FPCCR_THREAD_MASK | \
1703 R_V7M_FPCCR_MMRDY_MASK | \
1704 R_V7M_FPCCR_SPLIMVIOL_MASK | \
1705 R_V7M_FPCCR_UFRDY_MASK | \
1706 R_V7M_FPCCR_ASPEN_MASK)
1707
1708 /*
1709 * System register ID fields.
1710 */
1711 FIELD(MIDR_EL1, REVISION, 0, 4)
1712 FIELD(MIDR_EL1, PARTNUM, 4, 12)
1713 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
1714 FIELD(MIDR_EL1, VARIANT, 20, 4)
1715 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
1716
1717 FIELD(ID_ISAR0, SWAP, 0, 4)
1718 FIELD(ID_ISAR0, BITCOUNT, 4, 4)
1719 FIELD(ID_ISAR0, BITFIELD, 8, 4)
1720 FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
1721 FIELD(ID_ISAR0, COPROC, 16, 4)
1722 FIELD(ID_ISAR0, DEBUG, 20, 4)
1723 FIELD(ID_ISAR0, DIVIDE, 24, 4)
1724
1725 FIELD(ID_ISAR1, ENDIAN, 0, 4)
1726 FIELD(ID_ISAR1, EXCEPT, 4, 4)
1727 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
1728 FIELD(ID_ISAR1, EXTEND, 12, 4)
1729 FIELD(ID_ISAR1, IFTHEN, 16, 4)
1730 FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
1731 FIELD(ID_ISAR1, INTERWORK, 24, 4)
1732 FIELD(ID_ISAR1, JAZELLE, 28, 4)
1733
1734 FIELD(ID_ISAR2, LOADSTORE, 0, 4)
1735 FIELD(ID_ISAR2, MEMHINT, 4, 4)
1736 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
1737 FIELD(ID_ISAR2, MULT, 12, 4)
1738 FIELD(ID_ISAR2, MULTS, 16, 4)
1739 FIELD(ID_ISAR2, MULTU, 20, 4)
1740 FIELD(ID_ISAR2, PSR_AR, 24, 4)
1741 FIELD(ID_ISAR2, REVERSAL, 28, 4)
1742
1743 FIELD(ID_ISAR3, SATURATE, 0, 4)
1744 FIELD(ID_ISAR3, SIMD, 4, 4)
1745 FIELD(ID_ISAR3, SVC, 8, 4)
1746 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
1747 FIELD(ID_ISAR3, TABBRANCH, 16, 4)
1748 FIELD(ID_ISAR3, T32COPY, 20, 4)
1749 FIELD(ID_ISAR3, TRUENOP, 24, 4)
1750 FIELD(ID_ISAR3, T32EE, 28, 4)
1751
1752 FIELD(ID_ISAR4, UNPRIV, 0, 4)
1753 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
1754 FIELD(ID_ISAR4, WRITEBACK, 8, 4)
1755 FIELD(ID_ISAR4, SMC, 12, 4)
1756 FIELD(ID_ISAR4, BARRIER, 16, 4)
1757 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
1758 FIELD(ID_ISAR4, PSR_M, 24, 4)
1759 FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
1760
1761 FIELD(ID_ISAR5, SEVL, 0, 4)
1762 FIELD(ID_ISAR5, AES, 4, 4)
1763 FIELD(ID_ISAR5, SHA1, 8, 4)
1764 FIELD(ID_ISAR5, SHA2, 12, 4)
1765 FIELD(ID_ISAR5, CRC32, 16, 4)
1766 FIELD(ID_ISAR5, RDM, 24, 4)
1767 FIELD(ID_ISAR5, VCMA, 28, 4)
1768
1769 FIELD(ID_ISAR6, JSCVT, 0, 4)
1770 FIELD(ID_ISAR6, DP, 4, 4)
1771 FIELD(ID_ISAR6, FHM, 8, 4)
1772 FIELD(ID_ISAR6, SB, 12, 4)
1773 FIELD(ID_ISAR6, SPECRES, 16, 4)
1774
1775 FIELD(ID_MMFR3, CMAINTVA, 0, 4)
1776 FIELD(ID_MMFR3, CMAINTSW, 4, 4)
1777 FIELD(ID_MMFR3, BPMAINT, 8, 4)
1778 FIELD(ID_MMFR3, MAINTBCST, 12, 4)
1779 FIELD(ID_MMFR3, PAN, 16, 4)
1780 FIELD(ID_MMFR3, COHWALK, 20, 4)
1781 FIELD(ID_MMFR3, CMEMSZ, 24, 4)
1782 FIELD(ID_MMFR3, SUPERSEC, 28, 4)
1783
1784 FIELD(ID_MMFR4, SPECSEI, 0, 4)
1785 FIELD(ID_MMFR4, AC2, 4, 4)
1786 FIELD(ID_MMFR4, XNX, 8, 4)
1787 FIELD(ID_MMFR4, CNP, 12, 4)
1788 FIELD(ID_MMFR4, HPDS, 16, 4)
1789 FIELD(ID_MMFR4, LSM, 20, 4)
1790 FIELD(ID_MMFR4, CCIDX, 24, 4)
1791 FIELD(ID_MMFR4, EVT, 28, 4)
1792
1793 FIELD(ID_AA64ISAR0, AES, 4, 4)
1794 FIELD(ID_AA64ISAR0, SHA1, 8, 4)
1795 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
1796 FIELD(ID_AA64ISAR0, CRC32, 16, 4)
1797 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
1798 FIELD(ID_AA64ISAR0, RDM, 28, 4)
1799 FIELD(ID_AA64ISAR0, SHA3, 32, 4)
1800 FIELD(ID_AA64ISAR0, SM3, 36, 4)
1801 FIELD(ID_AA64ISAR0, SM4, 40, 4)
1802 FIELD(ID_AA64ISAR0, DP, 44, 4)
1803 FIELD(ID_AA64ISAR0, FHM, 48, 4)
1804 FIELD(ID_AA64ISAR0, TS, 52, 4)
1805 FIELD(ID_AA64ISAR0, TLB, 56, 4)
1806 FIELD(ID_AA64ISAR0, RNDR, 60, 4)
1807
1808 FIELD(ID_AA64ISAR1, DPB, 0, 4)
1809 FIELD(ID_AA64ISAR1, APA, 4, 4)
1810 FIELD(ID_AA64ISAR1, API, 8, 4)
1811 FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
1812 FIELD(ID_AA64ISAR1, FCMA, 16, 4)
1813 FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
1814 FIELD(ID_AA64ISAR1, GPA, 24, 4)
1815 FIELD(ID_AA64ISAR1, GPI, 28, 4)
1816 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
1817 FIELD(ID_AA64ISAR1, SB, 36, 4)
1818 FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
1819
1820 FIELD(ID_AA64PFR0, EL0, 0, 4)
1821 FIELD(ID_AA64PFR0, EL1, 4, 4)
1822 FIELD(ID_AA64PFR0, EL2, 8, 4)
1823 FIELD(ID_AA64PFR0, EL3, 12, 4)
1824 FIELD(ID_AA64PFR0, FP, 16, 4)
1825 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
1826 FIELD(ID_AA64PFR0, GIC, 24, 4)
1827 FIELD(ID_AA64PFR0, RAS, 28, 4)
1828 FIELD(ID_AA64PFR0, SVE, 32, 4)
1829
1830 FIELD(ID_AA64PFR1, BT, 0, 4)
1831 FIELD(ID_AA64PFR1, SBSS, 4, 4)
1832 FIELD(ID_AA64PFR1, MTE, 8, 4)
1833 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
1834
1835 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
1836 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
1837 FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
1838 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
1839 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
1840 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
1841 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
1842 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
1843 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
1844 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
1845 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
1846 FIELD(ID_AA64MMFR0, EXS, 44, 4)
1847
1848 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
1849 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
1850 FIELD(ID_AA64MMFR1, VH, 8, 4)
1851 FIELD(ID_AA64MMFR1, HPDS, 12, 4)
1852 FIELD(ID_AA64MMFR1, LO, 16, 4)
1853 FIELD(ID_AA64MMFR1, PAN, 20, 4)
1854 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
1855 FIELD(ID_AA64MMFR1, XNX, 28, 4)
1856
1857 FIELD(ID_AA64MMFR2, CNP, 0, 4)
1858 FIELD(ID_AA64MMFR2, UAO, 4, 4)
1859 FIELD(ID_AA64MMFR2, LSM, 8, 4)
1860 FIELD(ID_AA64MMFR2, IESB, 12, 4)
1861 FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
1862 FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
1863 FIELD(ID_AA64MMFR2, NV, 24, 4)
1864 FIELD(ID_AA64MMFR2, ST, 28, 4)
1865 FIELD(ID_AA64MMFR2, AT, 32, 4)
1866 FIELD(ID_AA64MMFR2, IDS, 36, 4)
1867 FIELD(ID_AA64MMFR2, FWB, 40, 4)
1868 FIELD(ID_AA64MMFR2, TTL, 48, 4)
1869 FIELD(ID_AA64MMFR2, BBM, 52, 4)
1870 FIELD(ID_AA64MMFR2, EVT, 56, 4)
1871 FIELD(ID_AA64MMFR2, E0PD, 60, 4)
1872
1873 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
1874 FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
1875 FIELD(ID_AA64DFR0, PMUVER, 8, 4)
1876 FIELD(ID_AA64DFR0, BRPS, 12, 4)
1877 FIELD(ID_AA64DFR0, WRPS, 20, 4)
1878 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
1879 FIELD(ID_AA64DFR0, PMSVER, 32, 4)
1880 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
1881 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
1882
1883 FIELD(ID_DFR0, COPDBG, 0, 4)
1884 FIELD(ID_DFR0, COPSDBG, 4, 4)
1885 FIELD(ID_DFR0, MMAPDBG, 8, 4)
1886 FIELD(ID_DFR0, COPTRC, 12, 4)
1887 FIELD(ID_DFR0, MMAPTRC, 16, 4)
1888 FIELD(ID_DFR0, MPROFDBG, 20, 4)
1889 FIELD(ID_DFR0, PERFMON, 24, 4)
1890 FIELD(ID_DFR0, TRACEFILT, 28, 4)
1891
1892 FIELD(DBGDIDR, SE_IMP, 12, 1)
1893 FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
1894 FIELD(DBGDIDR, VERSION, 16, 4)
1895 FIELD(DBGDIDR, CTX_CMPS, 20, 4)
1896 FIELD(DBGDIDR, BRPS, 24, 4)
1897 FIELD(DBGDIDR, WRPS, 28, 4)
1898
1899 FIELD(MVFR0, SIMDREG, 0, 4)
1900 FIELD(MVFR0, FPSP, 4, 4)
1901 FIELD(MVFR0, FPDP, 8, 4)
1902 FIELD(MVFR0, FPTRAP, 12, 4)
1903 FIELD(MVFR0, FPDIVIDE, 16, 4)
1904 FIELD(MVFR0, FPSQRT, 20, 4)
1905 FIELD(MVFR0, FPSHVEC, 24, 4)
1906 FIELD(MVFR0, FPROUND, 28, 4)
1907
1908 FIELD(MVFR1, FPFTZ, 0, 4)
1909 FIELD(MVFR1, FPDNAN, 4, 4)
1910 FIELD(MVFR1, SIMDLS, 8, 4)
1911 FIELD(MVFR1, SIMDINT, 12, 4)
1912 FIELD(MVFR1, SIMDSP, 16, 4)
1913 FIELD(MVFR1, SIMDHP, 20, 4)
1914 FIELD(MVFR1, FPHP, 24, 4)
1915 FIELD(MVFR1, SIMDFMAC, 28, 4)
1916
1917 FIELD(MVFR2, SIMDMISC, 0, 4)
1918 FIELD(MVFR2, FPMISC, 4, 4)
1919
1920 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
1921
1922 /* If adding a feature bit which corresponds to a Linux ELF
1923 * HWCAP bit, remember to update the feature-bit-to-hwcap
1924 * mapping in linux-user/elfload.c:get_elf_hwcap().
1925 */
1926 enum arm_features {
1927 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
1928 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
1929 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
1930 ARM_FEATURE_V6,
1931 ARM_FEATURE_V6K,
1932 ARM_FEATURE_V7,
1933 ARM_FEATURE_THUMB2,
1934 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */
1935 ARM_FEATURE_NEON,
1936 ARM_FEATURE_M, /* Microcontroller profile. */
1937 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
1938 ARM_FEATURE_THUMB2EE,
1939 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
1940 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
1941 ARM_FEATURE_V4T,
1942 ARM_FEATURE_V5,
1943 ARM_FEATURE_STRONGARM,
1944 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
1945 ARM_FEATURE_GENERIC_TIMER,
1946 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
1947 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
1948 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
1949 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
1950 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
1951 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
1952 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
1953 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
1954 ARM_FEATURE_V8,
1955 ARM_FEATURE_AARCH64, /* supports 64 bit mode */
1956 ARM_FEATURE_CBAR, /* has cp15 CBAR */
1957 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
1958 ARM_FEATURE_EL2, /* has EL2 Virtualization support */
1959 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
1960 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
1961 ARM_FEATURE_PMU, /* has PMU support */
1962 ARM_FEATURE_VBAR, /* has cp15 VBAR */
1963 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
1964 ARM_FEATURE_M_MAIN, /* M profile Main Extension */
1965 };
1966
1967 static inline int arm_feature(CPUARMState *env, int feature)
1968 {
1969 return (env->features & (1ULL << feature)) != 0;
1970 }
1971
1972 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
1973
1974 #if !defined(CONFIG_USER_ONLY)
1975 /* Return true if exception levels below EL3 are in secure state,
1976 * or would be following an exception return to that level.
1977 * Unlike arm_is_secure() (which is always a question about the
1978 * _current_ state of the CPU) this doesn't care about the current
1979 * EL or mode.
1980 */
1981 static inline bool arm_is_secure_below_el3(CPUARMState *env)
1982 {
1983 if (arm_feature(env, ARM_FEATURE_EL3)) {
1984 return !(env->cp15.scr_el3 & SCR_NS);
1985 } else {
1986 /* If EL3 is not supported then the secure state is implementation
1987 * defined, in which case QEMU defaults to non-secure.
1988 */
1989 return false;
1990 }
1991 }
1992
1993 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
1994 static inline bool arm_is_el3_or_mon(CPUARMState *env)
1995 {
1996 if (arm_feature(env, ARM_FEATURE_EL3)) {
1997 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
1998 /* CPU currently in AArch64 state and EL3 */
1999 return true;
2000 } else if (!is_a64(env) &&
2001 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
2002 /* CPU currently in AArch32 state and monitor mode */
2003 return true;
2004 }
2005 }
2006 return false;
2007 }
2008
2009 /* Return true if the processor is in secure state */
2010 static inline bool arm_is_secure(CPUARMState *env)
2011 {
2012 if (arm_is_el3_or_mon(env)) {
2013 return true;
2014 }
2015 return arm_is_secure_below_el3(env);
2016 }
2017
2018 #else
2019 static inline bool arm_is_secure_below_el3(CPUARMState *env)
2020 {
2021 return false;
2022 }
2023
2024 static inline bool arm_is_secure(CPUARMState *env)
2025 {
2026 return false;
2027 }
2028 #endif
2029
2030 /**
2031 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2.
2032 * E.g. when in secure state, fields in HCR_EL2 are suppressed,
2033 * "for all purposes other than a direct read or write access of HCR_EL2."
2034 * Not included here is HCR_RW.
2035 */
2036 uint64_t arm_hcr_el2_eff(CPUARMState *env);
2037
2038 /* Return true if the specified exception level is running in AArch64 state. */
2039 static inline bool arm_el_is_aa64(CPUARMState *env, int el)
2040 {
2041 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
2042 * and if we're not in EL0 then the state of EL0 isn't well defined.)
2043 */
2044 assert(el >= 1 && el <= 3);
2045 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
2046
2047 /* The highest exception level is always at the maximum supported
2048 * register width, and then lower levels have a register width controlled
2049 * by bits in the SCR or HCR registers.
2050 */
2051 if (el == 3) {
2052 return aa64;
2053 }
2054
2055 if (arm_feature(env, ARM_FEATURE_EL3)) {
2056 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
2057 }
2058
2059 if (el == 2) {
2060 return aa64;
2061 }
2062
2063 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) {
2064 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
2065 }
2066
2067 return aa64;
2068 }
2069
2070 /* Function for determing whether guest cp register reads and writes should
2071 * access the secure or non-secure bank of a cp register. When EL3 is
2072 * operating in AArch32 state, the NS-bit determines whether the secure
2073 * instance of a cp register should be used. When EL3 is AArch64 (or if
2074 * it doesn't exist at all) then there is no register banking, and all
2075 * accesses are to the non-secure version.
2076 */
2077 static inline bool access_secure_reg(CPUARMState *env)
2078 {
2079 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
2080 !arm_el_is_aa64(env, 3) &&
2081 !(env->cp15.scr_el3 & SCR_NS));
2082
2083 return ret;
2084 }
2085
2086 /* Macros for accessing a specified CP register bank */
2087 #define A32_BANKED_REG_GET(_env, _regname, _secure) \
2088 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
2089
2090 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
2091 do { \
2092 if (_secure) { \
2093 (_env)->cp15._regname##_s = (_val); \
2094 } else { \
2095 (_env)->cp15._regname##_ns = (_val); \
2096 } \
2097 } while (0)
2098
2099 /* Macros for automatically accessing a specific CP register bank depending on
2100 * the current secure state of the system. These macros are not intended for
2101 * supporting instruction translation reads/writes as these are dependent
2102 * solely on the SCR.NS bit and not the mode.
2103 */
2104 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
2105 A32_BANKED_REG_GET((_env), _regname, \
2106 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
2107
2108 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
2109 A32_BANKED_REG_SET((_env), _regname, \
2110 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
2111 (_val))
2112
2113 void arm_cpu_list(void);
2114 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
2115 uint32_t cur_el, bool secure);
2116
2117 /* Interface between CPU and Interrupt controller. */
2118 #ifndef CONFIG_USER_ONLY
2119 bool armv7m_nvic_can_take_pending_exception(void *opaque);
2120 #else
2121 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
2122 {
2123 return true;
2124 }
2125 #endif
2126 /**
2127 * armv7m_nvic_set_pending: mark the specified exception as pending
2128 * @opaque: the NVIC
2129 * @irq: the exception number to mark pending
2130 * @secure: false for non-banked exceptions or for the nonsecure
2131 * version of a banked exception, true for the secure version of a banked
2132 * exception.
2133 *
2134 * Marks the specified exception as pending. Note that we will assert()
2135 * if @secure is true and @irq does not specify one of the fixed set
2136 * of architecturally banked exceptions.
2137 */
2138 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
2139 /**
2140 * armv7m_nvic_set_pending_derived: mark this derived exception as pending
2141 * @opaque: the NVIC
2142 * @irq: the exception number to mark pending
2143 * @secure: false for non-banked exceptions or for the nonsecure
2144 * version of a banked exception, true for the secure version of a banked
2145 * exception.
2146 *
2147 * Similar to armv7m_nvic_set_pending(), but specifically for derived
2148 * exceptions (exceptions generated in the course of trying to take
2149 * a different exception).
2150 */
2151 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
2152 /**
2153 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
2154 * @opaque: the NVIC
2155 * @irq: the exception number to mark pending
2156 * @secure: false for non-banked exceptions or for the nonsecure
2157 * version of a banked exception, true for the secure version of a banked
2158 * exception.
2159 *
2160 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
2161 * generated in the course of lazy stacking of FP registers.
2162 */
2163 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
2164 /**
2165 * armv7m_nvic_get_pending_irq_info: return highest priority pending
2166 * exception, and whether it targets Secure state
2167 * @opaque: the NVIC
2168 * @pirq: set to pending exception number
2169 * @ptargets_secure: set to whether pending exception targets Secure
2170 *
2171 * This function writes the number of the highest priority pending
2172 * exception (the one which would be made active by
2173 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
2174 * to true if the current highest priority pending exception should
2175 * be taken to Secure state, false for NS.
2176 */
2177 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
2178 bool *ptargets_secure);
2179 /**
2180 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
2181 * @opaque: the NVIC
2182 *
2183 * Move the current highest priority pending exception from the pending
2184 * state to the active state, and update v7m.exception to indicate that
2185 * it is the exception currently being handled.
2186 */
2187 void armv7m_nvic_acknowledge_irq(void *opaque);
2188 /**
2189 * armv7m_nvic_complete_irq: complete specified interrupt or exception
2190 * @opaque: the NVIC
2191 * @irq: the exception number to complete
2192 * @secure: true if this exception was secure
2193 *
2194 * Returns: -1 if the irq was not active
2195 * 1 if completing this irq brought us back to base (no active irqs)
2196 * 0 if there is still an irq active after this one was completed
2197 * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
2198 */
2199 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
2200 /**
2201 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
2202 * @opaque: the NVIC
2203 * @irq: the exception number to mark pending
2204 * @secure: false for non-banked exceptions or for the nonsecure
2205 * version of a banked exception, true for the secure version of a banked
2206 * exception.
2207 *
2208 * Return whether an exception is "ready", i.e. whether the exception is
2209 * enabled and is configured at a priority which would allow it to
2210 * interrupt the current execution priority. This controls whether the
2211 * RDY bit for it in the FPCCR is set.
2212 */
2213 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
2214 /**
2215 * armv7m_nvic_raw_execution_priority: return the raw execution priority
2216 * @opaque: the NVIC
2217 *
2218 * Returns: the raw execution priority as defined by the v8M architecture.
2219 * This is the execution priority minus the effects of AIRCR.PRIS,
2220 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
2221 * (v8M ARM ARM I_PKLD.)
2222 */
2223 int armv7m_nvic_raw_execution_priority(void *opaque);
2224 /**
2225 * armv7m_nvic_neg_prio_requested: return true if the requested execution
2226 * priority is negative for the specified security state.
2227 * @opaque: the NVIC
2228 * @secure: the security state to test
2229 * This corresponds to the pseudocode IsReqExecPriNeg().
2230 */
2231 #ifndef CONFIG_USER_ONLY
2232 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
2233 #else
2234 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
2235 {
2236 return false;
2237 }
2238 #endif
2239
2240 /* Interface for defining coprocessor registers.
2241 * Registers are defined in tables of arm_cp_reginfo structs
2242 * which are passed to define_arm_cp_regs().
2243 */
2244
2245 /* When looking up a coprocessor register we look for it
2246 * via an integer which encodes all of:
2247 * coprocessor number
2248 * Crn, Crm, opc1, opc2 fields
2249 * 32 or 64 bit register (ie is it accessed via MRC/MCR
2250 * or via MRRC/MCRR?)
2251 * non-secure/secure bank (AArch32 only)
2252 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
2253 * (In this case crn and opc2 should be zero.)
2254 * For AArch64, there is no 32/64 bit size distinction;
2255 * instead all registers have a 2 bit op0, 3 bit op1 and op2,
2256 * and 4 bit CRn and CRm. The encoding patterns are chosen
2257 * to be easy to convert to and from the KVM encodings, and also
2258 * so that the hashtable can contain both AArch32 and AArch64
2259 * registers (to allow for interprocessing where we might run
2260 * 32 bit code on a 64 bit core).
2261 */
2262 /* This bit is private to our hashtable cpreg; in KVM register
2263 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
2264 * in the upper bits of the 64 bit ID.
2265 */
2266 #define CP_REG_AA64_SHIFT 28
2267 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
2268
2269 /* To enable banking of coprocessor registers depending on ns-bit we
2270 * add a bit to distinguish between secure and non-secure cpregs in the
2271 * hashtable.
2272 */
2273 #define CP_REG_NS_SHIFT 29
2274 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
2275
2276 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
2277 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
2278 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
2279
2280 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
2281 (CP_REG_AA64_MASK | \
2282 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
2283 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
2284 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
2285 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
2286 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
2287 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
2288
2289 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
2290 * version used as a key for the coprocessor register hashtable
2291 */
2292 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
2293 {
2294 uint32_t cpregid = kvmid;
2295 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
2296 cpregid |= CP_REG_AA64_MASK;
2297 } else {
2298 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
2299 cpregid |= (1 << 15);
2300 }
2301
2302 /* KVM is always non-secure so add the NS flag on AArch32 register
2303 * entries.
2304 */
2305 cpregid |= 1 << CP_REG_NS_SHIFT;
2306 }
2307 return cpregid;
2308 }
2309
2310 /* Convert a truncated 32 bit hashtable key into the full
2311 * 64 bit KVM register ID.
2312 */
2313 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
2314 {
2315 uint64_t kvmid;
2316
2317 if (cpregid & CP_REG_AA64_MASK) {
2318 kvmid = cpregid & ~CP_REG_AA64_MASK;
2319 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
2320 } else {
2321 kvmid = cpregid & ~(1 << 15);
2322 if (cpregid & (1 << 15)) {
2323 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
2324 } else {
2325 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
2326 }
2327 }
2328 return kvmid;
2329 }
2330
2331 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
2332 * special-behaviour cp reg and bits [11..8] indicate what behaviour
2333 * it has. Otherwise it is a simple cp reg, where CONST indicates that
2334 * TCG can assume the value to be constant (ie load at translate time)
2335 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
2336 * indicates that the TB should not be ended after a write to this register
2337 * (the default is that the TB ends after cp writes). OVERRIDE permits
2338 * a register definition to override a previous definition for the
2339 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
2340 * old must have the OVERRIDE bit set.
2341 * ALIAS indicates that this register is an alias view of some underlying
2342 * state which is also visible via another register, and that the other
2343 * register is handling migration and reset; registers marked ALIAS will not be
2344 * migrated but may have their state set by syncing of register state from KVM.
2345 * NO_RAW indicates that this register has no underlying state and does not
2346 * support raw access for state saving/loading; it will not be used for either
2347 * migration or KVM state synchronization. (Typically this is for "registers"
2348 * which are actually used as instructions for cache maintenance and so on.)
2349 * IO indicates that this register does I/O and therefore its accesses
2350 * need to be marked with gen_io_start() and also end the TB. In particular,
2351 * registers which implement clocks or timers require this.
2352 * RAISES_EXC is for when the read or write hook might raise an exception;
2353 * the generated code will synchronize the CPU state before calling the hook
2354 * so that it is safe for the hook to call raise_exception().
2355 * NEWEL is for writes to registers that might change the exception
2356 * level - typically on older ARM chips. For those cases we need to
2357 * re-read the new el when recomputing the translation flags.
2358 */
2359 #define ARM_CP_SPECIAL 0x0001
2360 #define ARM_CP_CONST 0x0002
2361 #define ARM_CP_64BIT 0x0004
2362 #define ARM_CP_SUPPRESS_TB_END 0x0008
2363 #define ARM_CP_OVERRIDE 0x0010
2364 #define ARM_CP_ALIAS 0x0020
2365 #define ARM_CP_IO 0x0040
2366 #define ARM_CP_NO_RAW 0x0080
2367 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100)
2368 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200)
2369 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
2370 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
2371 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
2372 #define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600)
2373 #define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700)
2374 #define ARM_LAST_SPECIAL ARM_CP_DC_GZVA
2375 #define ARM_CP_FPU 0x1000
2376 #define ARM_CP_SVE 0x2000
2377 #define ARM_CP_NO_GDB 0x4000
2378 #define ARM_CP_RAISES_EXC 0x8000
2379 #define ARM_CP_NEWEL 0x10000
2380 /* Used only as a terminator for ARMCPRegInfo lists */
2381 #define ARM_CP_SENTINEL 0xfffff
2382 /* Mask of only the flag bits in a type field */
2383 #define ARM_CP_FLAG_MASK 0x1f0ff
2384
2385 /* Valid values for ARMCPRegInfo state field, indicating which of
2386 * the AArch32 and AArch64 execution states this register is visible in.
2387 * If the reginfo doesn't explicitly specify then it is AArch32 only.
2388 * If the reginfo is declared to be visible in both states then a second
2389 * reginfo is synthesised for the AArch32 view of the AArch64 register,
2390 * such that the AArch32 view is the lower 32 bits of the AArch64 one.
2391 * Note that we rely on the values of these enums as we iterate through
2392 * the various states in some places.
2393 */
2394 enum {
2395 ARM_CP_STATE_AA32 = 0,
2396 ARM_CP_STATE_AA64 = 1,
2397 ARM_CP_STATE_BOTH = 2,
2398 };
2399
2400 /* ARM CP register secure state flags. These flags identify security state
2401 * attributes for a given CP register entry.
2402 * The existence of both or neither secure and non-secure flags indicates that
2403 * the register has both a secure and non-secure hash entry. A single one of
2404 * these flags causes the register to only be hashed for the specified
2405 * security state.
2406 * Although definitions may have any combination of the S/NS bits, each
2407 * registered entry will only have one to identify whether the entry is secure
2408 * or non-secure.
2409 */
2410 enum {
2411 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */
2412 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */
2413 };
2414
2415 /* Return true if cptype is a valid type field. This is used to try to
2416 * catch errors where the sentinel has been accidentally left off the end
2417 * of a list of registers.
2418 */
2419 static inline bool cptype_valid(int cptype)
2420 {
2421 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
2422 || ((cptype & ARM_CP_SPECIAL) &&
2423 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
2424 }
2425
2426 /* Access rights:
2427 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
2428 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
2429 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
2430 * (ie any of the privileged modes in Secure state, or Monitor mode).
2431 * If a register is accessible in one privilege level it's always accessible
2432 * in higher privilege levels too. Since "Secure PL1" also follows this rule
2433 * (ie anything visible in PL2 is visible in S-PL1, some things are only
2434 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
2435 * terminology a little and call this PL3.
2436 * In AArch64 things are somewhat simpler as the PLx bits line up exactly
2437 * with the ELx exception levels.
2438 *
2439 * If access permissions for a register are more complex than can be
2440 * described with these bits, then use a laxer set of restrictions, and
2441 * do the more restrictive/complex check inside a helper function.
2442 */
2443 #define PL3_R 0x80
2444 #define PL3_W 0x40
2445 #define PL2_R (0x20 | PL3_R)
2446 #define PL2_W (0x10 | PL3_W)
2447 #define PL1_R (0x08 | PL2_R)
2448 #define PL1_W (0x04 | PL2_W)
2449 #define PL0_R (0x02 | PL1_R)
2450 #define PL0_W (0x01 | PL1_W)
2451
2452 /*
2453 * For user-mode some registers are accessible to EL0 via a kernel
2454 * trap-and-emulate ABI. In this case we define the read permissions
2455 * as actually being PL0_R. However some bits of any given register
2456 * may still be masked.
2457 */
2458 #ifdef CONFIG_USER_ONLY
2459 #define PL0U_R PL0_R
2460 #else
2461 #define PL0U_R PL1_R
2462 #endif
2463
2464 #define PL3_RW (PL3_R | PL3_W)
2465 #define PL2_RW (PL2_R | PL2_W)
2466 #define PL1_RW (PL1_R | PL1_W)
2467 #define PL0_RW (PL0_R | PL0_W)
2468
2469 /* Return the highest implemented Exception Level */
2470 static inline int arm_highest_el(CPUARMState *env)
2471 {
2472 if (arm_feature(env, ARM_FEATURE_EL3)) {
2473 return 3;
2474 }
2475 if (arm_feature(env, ARM_FEATURE_EL2)) {
2476 return 2;
2477 }
2478 return 1;
2479 }
2480
2481 /* Return true if a v7M CPU is in Handler mode */
2482 static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2483 {
2484 return env->v7m.exception != 0;
2485 }
2486
2487 /* Return the current Exception Level (as per ARMv8; note that this differs
2488 * from the ARMv7 Privilege Level).
2489 */
2490 static inline int arm_current_el(CPUARMState *env)
2491 {
2492 if (arm_feature(env, ARM_FEATURE_M)) {
2493 return arm_v7m_is_handler_mode(env) ||
2494 !(env->v7m.control[env->v7m.secure] & 1);
2495 }
2496
2497 if (is_a64(env)) {
2498 return extract32(env->pstate, 2, 2);
2499 }
2500
2501 switch (env->uncached_cpsr & 0x1f) {
2502 case ARM_CPU_MODE_USR:
2503 return 0;
2504 case ARM_CPU_MODE_HYP:
2505 return 2;
2506 case ARM_CPU_MODE_MON:
2507 return 3;
2508 default:
2509 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2510 /* If EL3 is 32-bit then all secure privileged modes run in
2511 * EL3
2512 */
2513 return 3;
2514 }
2515
2516 return 1;
2517 }
2518 }
2519
2520 typedef struct ARMCPRegInfo ARMCPRegInfo;
2521
2522 typedef enum CPAccessResult {
2523 /* Access is permitted */
2524 CP_ACCESS_OK = 0,
2525 /* Access fails due to a configurable trap or enable which would
2526 * result in a categorized exception syndrome giving information about
2527 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
2528 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
2529 * PL1 if in EL0, otherwise to the current EL).
2530 */
2531 CP_ACCESS_TRAP = 1,
2532 /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
2533 * Note that this is not a catch-all case -- the set of cases which may
2534 * result in this failure is specifically defined by the architecture.
2535 */
2536 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
2537 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
2538 CP_ACCESS_TRAP_EL2 = 3,
2539 CP_ACCESS_TRAP_EL3 = 4,
2540 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
2541 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
2542 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
2543 /* Access fails and results in an exception syndrome for an FP access,
2544 * trapped directly to EL2 or EL3
2545 */
2546 CP_ACCESS_TRAP_FP_EL2 = 7,
2547 CP_ACCESS_TRAP_FP_EL3 = 8,
2548 } CPAccessResult;
2549
2550 /* Access functions for coprocessor registers. These cannot fail and
2551 * may not raise exceptions.
2552 */
2553 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2554 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
2555 uint64_t value);
2556 /* Access permission check functions for coprocessor registers. */
2557 typedef CPAccessResult CPAccessFn(CPUARMState *env,
2558 const ARMCPRegInfo *opaque,
2559 bool isread);
2560 /* Hook function for register reset */
2561 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2562
2563 #define CP_ANY 0xff
2564
2565 /* Definition of an ARM coprocessor register */
2566 struct ARMCPRegInfo {
2567 /* Name of register (useful mainly for debugging, need not be unique) */
2568 const char *name;
2569 /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
2570 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
2571 * 'wildcard' field -- any value of that field in the MRC/MCR insn
2572 * will be decoded to this register. The register read and write
2573 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
2574 * used by the program, so it is possible to register a wildcard and
2575 * then behave differently on read/write if necessary.
2576 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
2577 * must both be zero.
2578 * For AArch64-visible registers, opc0 is also used.
2579 * Since there are no "coprocessors" in AArch64, cp is purely used as a
2580 * way to distinguish (for KVM's benefit) guest-visible system registers
2581 * from demuxed ones provided to preserve the "no side effects on
2582 * KVM register read/write from QEMU" semantics. cp==0x13 is guest
2583 * visible (to match KVM's encoding); cp==0 will be converted to
2584 * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
2585 */
2586 uint8_t cp;
2587 uint8_t crn;
2588 uint8_t crm;
2589 uint8_t opc0;
2590 uint8_t opc1;
2591 uint8_t opc2;
2592 /* Execution state in which this register is visible: ARM_CP_STATE_* */
2593 int state;
2594 /* Register type: ARM_CP_* bits/values */
2595 int type;
2596 /* Access rights: PL*_[RW] */
2597 int access;
2598 /* Security state: ARM_CP_SECSTATE_* bits/values */
2599 int secure;
2600 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
2601 * this register was defined: can be used to hand data through to the
2602 * register read/write functions, since they are passed the ARMCPRegInfo*.
2603 */
2604 void *opaque;
2605 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
2606 * fieldoffset is non-zero, the reset value of the register.
2607 */
2608 uint64_t resetvalue;
2609 /* Offset of the field in CPUARMState for this register.
2610 *
2611 * This is not needed if either:
2612 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
2613 * 2. both readfn and writefn are specified
2614 */
2615 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
2616
2617 /* Offsets of the secure and non-secure fields in CPUARMState for the
2618 * register if it is banked. These fields are only used during the static
2619 * registration of a register. During hashing the bank associated
2620 * with a given security state is copied to fieldoffset which is used from
2621 * there on out.
2622 *
2623 * It is expected that register definitions use either fieldoffset or
2624 * bank_fieldoffsets in the definition but not both. It is also expected
2625 * that both bank offsets are set when defining a banked register. This
2626 * use indicates that a register is banked.
2627 */
2628 ptrdiff_t bank_fieldoffsets[2];
2629
2630 /* Function for making any access checks for this register in addition to
2631 * those specified by the 'access' permissions bits. If NULL, no extra
2632 * checks required. The access check is performed at runtime, not at
2633 * translate time.
2634 */
2635 CPAccessFn *accessfn;
2636 /* Function for handling reads of this register. If NULL, then reads
2637 * will be done by loading from the offset into CPUARMState specified
2638 * by fieldoffset.
2639 */
2640 CPReadFn *readfn;
2641 /* Function for handling writes of this register. If NULL, then writes
2642 * will be done by writing to the offset into CPUARMState specified
2643 * by fieldoffset.
2644 */
2645 CPWriteFn *writefn;
2646 /* Function for doing a "raw" read; used when we need to copy
2647 * coprocessor state to the kernel for KVM or out for
2648 * migration. This only needs to be provided if there is also a
2649 * readfn and it has side effects (for instance clear-on-read bits).
2650 */
2651 CPReadFn *raw_readfn;
2652 /* Function for doing a "raw" write; used when we need to copy KVM
2653 * kernel coprocessor state into userspace, or for inbound
2654 * migration. This only needs to be provided if there is also a
2655 * writefn and it masks out "unwritable" bits or has write-one-to-clear
2656 * or similar behaviour.
2657 */
2658 CPWriteFn *raw_writefn;
2659 /* Function for resetting the register. If NULL, then reset will be done
2660 * by writing resetvalue to the field specified in fieldoffset. If
2661 * fieldoffset is 0 then no reset will be done.
2662 */
2663 CPResetFn *resetfn;
2664
2665 /*
2666 * "Original" writefn and readfn.
2667 * For ARMv8.1-VHE register aliases, we overwrite the read/write
2668 * accessor functions of various EL1/EL0 to perform the runtime
2669 * check for which sysreg should actually be modified, and then
2670 * forwards the operation. Before overwriting the accessors,
2671 * the original function is copied here, so that accesses that
2672 * really do go to the EL1/EL0 version proceed normally.
2673 * (The corresponding EL2 register is linked via opaque.)
2674 */
2675 CPReadFn *orig_readfn;
2676 CPWriteFn *orig_writefn;
2677 };
2678
2679 /* Macros which are lvalues for the field in CPUARMState for the
2680 * ARMCPRegInfo *ri.
2681 */
2682 #define CPREG_FIELD32(env, ri) \
2683 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
2684 #define CPREG_FIELD64(env, ri) \
2685 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
2686
2687 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
2688
2689 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2690 const ARMCPRegInfo *regs, void *opaque);
2691 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2692 const ARMCPRegInfo *regs, void *opaque);
2693 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
2694 {
2695 define_arm_cp_regs_with_opaque(cpu, regs, 0);
2696 }
2697 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
2698 {
2699 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
2700 }
2701 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
2702
2703 /*
2704 * Definition of an ARM co-processor register as viewed from
2705 * userspace. This is used for presenting sanitised versions of
2706 * registers to userspace when emulating the Linux AArch64 CPU
2707 * ID/feature ABI (advertised as HWCAP_CPUID).
2708 */
2709 typedef struct ARMCPRegUserSpaceInfo {
2710 /* Name of register */
2711 const char *name;
2712
2713 /* Is the name actually a glob pattern */
2714 bool is_glob;
2715
2716 /* Only some bits are exported to user space */
2717 uint64_t exported_bits;
2718
2719 /* Fixed bits are applied after the mask */
2720 uint64_t fixed_bits;
2721 } ARMCPRegUserSpaceInfo;
2722
2723 #define REGUSERINFO_SENTINEL { .name = NULL }
2724
2725 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
2726
2727 /* CPWriteFn that can be used to implement writes-ignored behaviour */
2728 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2729 uint64_t value);
2730 /* CPReadFn that can be used for read-as-zero behaviour */
2731 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
2732
2733 /* CPResetFn that does nothing, for use if no reset is required even
2734 * if fieldoffset is non zero.
2735 */
2736 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
2737
2738 /* Return true if this reginfo struct's field in the cpu state struct
2739 * is 64 bits wide.
2740 */
2741 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
2742 {
2743 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
2744 }
2745
2746 static inline bool cp_access_ok(int current_el,
2747 const ARMCPRegInfo *ri, int isread)
2748 {
2749 return (ri->access >> ((current_el * 2) + isread)) & 1;
2750 }
2751
2752 /* Raw read of a coprocessor register (as needed for migration, etc) */
2753 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
2754
2755 /**
2756 * write_list_to_cpustate
2757 * @cpu: ARMCPU
2758 *
2759 * For each register listed in the ARMCPU cpreg_indexes list, write
2760 * its value from the cpreg_values list into the ARMCPUState structure.
2761 * This updates TCG's working data structures from KVM data or
2762 * from incoming migration state.
2763 *
2764 * Returns: true if all register values were updated correctly,
2765 * false if some register was unknown or could not be written.
2766 * Note that we do not stop early on failure -- we will attempt
2767 * writing all registers in the list.
2768 */
2769 bool write_list_to_cpustate(ARMCPU *cpu);
2770
2771 /**
2772 * write_cpustate_to_list:
2773 * @cpu: ARMCPU
2774 * @kvm_sync: true if this is for syncing back to KVM
2775 *
2776 * For each register listed in the ARMCPU cpreg_indexes list, write
2777 * its value from the ARMCPUState structure into the cpreg_values list.
2778 * This is used to copy info from TCG's working data structures into
2779 * KVM or for outbound migration.
2780 *
2781 * @kvm_sync is true if we are doing this in order to sync the
2782 * register state back to KVM. In this case we will only update
2783 * values in the list if the previous list->cpustate sync actually
2784 * successfully wrote the CPU state. Otherwise we will keep the value
2785 * that is in the list.
2786 *
2787 * Returns: true if all register values were read correctly,
2788 * false if some register was unknown or could not be read.
2789 * Note that we do not stop early on failure -- we will attempt
2790 * reading all registers in the list.
2791 */
2792 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
2793
2794 #define ARM_CPUID_TI915T 0x54029152
2795 #define ARM_CPUID_TI925T 0x54029252
2796
2797 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
2798 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
2799 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2800
2801 #define cpu_signal_handler cpu_arm_signal_handler
2802 #define cpu_list arm_cpu_list
2803
2804 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
2805 *
2806 * If EL3 is 64-bit:
2807 * + NonSecure EL1 & 0 stage 1
2808 * + NonSecure EL1 & 0 stage 2
2809 * + NonSecure EL2
2810 * + NonSecure EL2 & 0 (ARMv8.1-VHE)
2811 * + Secure EL1 & 0
2812 * + Secure EL3
2813 * If EL3 is 32-bit:
2814 * + NonSecure PL1 & 0 stage 1
2815 * + NonSecure PL1 & 0 stage 2
2816 * + NonSecure PL2
2817 * + Secure PL0
2818 * + Secure PL1
2819 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
2820 *
2821 * For QEMU, an mmu_idx is not quite the same as a translation regime because:
2822 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes,
2823 * because they may differ in access permissions even if the VA->PA map is
2824 * the same
2825 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2826 * translation, which means that we have one mmu_idx that deals with two
2827 * concatenated translation regimes [this sort of combined s1+2 TLB is
2828 * architecturally permitted]
2829 * 3. we don't need to allocate an mmu_idx to translations that we won't be
2830 * handling via the TLB. The only way to do a stage 1 translation without
2831 * the immediate stage 2 translation is via the ATS or AT system insns,
2832 * which can be slow-pathed and always do a page table walk.
2833 * The only use of stage 2 translations is either as part of an s1+2
2834 * lookup or when loading the descriptors during a stage 1 page table walk,
2835 * and in both those cases we don't use the TLB.
2836 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
2837 * translation regimes, because they map reasonably well to each other
2838 * and they can't both be active at the same time.
2839 * 5. we want to be able to use the TLB for accesses done as part of a
2840 * stage1 page table walk, rather than having to walk the stage2 page
2841 * table over and over.
2842 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
2843 * Never (PAN) bit within PSTATE.
2844 *
2845 * This gives us the following list of cases:
2846 *
2847 * NS EL0 EL1&0 stage 1+2 (aka NS PL0)
2848 * NS EL1 EL1&0 stage 1+2 (aka NS PL1)
2849 * NS EL1 EL1&0 stage 1+2 +PAN
2850 * NS EL0 EL2&0
2851 * NS EL2 EL2&0
2852 * NS EL2 EL2&0 +PAN
2853 * NS EL2 (aka NS PL2)
2854 * S EL0 EL1&0 (aka S PL0)
2855 * S EL1 EL1&0 (not used if EL3 is 32 bit)
2856 * S EL1 EL1&0 +PAN
2857 * S EL3 (aka S PL1)
2858 *
2859 * for a total of 11 different mmu_idx.
2860 *
2861 * R profile CPUs have an MPU, but can use the same set of MMU indexes
2862 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and
2863 * NS EL2 if we ever model a Cortex-R52).
2864 *
2865 * M profile CPUs are rather different as they do not have a true MMU.
2866 * They have the following different MMU indexes:
2867 * User
2868 * Privileged
2869 * User, execution priority negative (ie the MPU HFNMIENA bit may apply)
2870 * Privileged, execution priority negative (ditto)
2871 * If the CPU supports the v8M Security Extension then there are also:
2872 * Secure User
2873 * Secure Privileged
2874 * Secure User, execution priority negative
2875 * Secure Privileged, execution priority negative
2876 *
2877 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
2878 * are not quite the same -- different CPU types (most notably M profile
2879 * vs A/R profile) would like to use MMU indexes with different semantics,
2880 * but since we don't ever need to use all of those in a single CPU we
2881 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU
2882 * modes + total number of M profile MMU modes". The lower bits of
2883 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
2884 * the same for any particular CPU.
2885 * Variables of type ARMMUIdx are always full values, and the core
2886 * index values are in variables of type 'int'.
2887 *
2888 * Our enumeration includes at the end some entries which are not "true"
2889 * mmu_idx values in that they don't have corresponding TLBs and are only
2890 * valid for doing slow path page table walks.
2891 *
2892 * The constant names here are patterned after the general style of the names
2893 * of the AT/ATS operations.
2894 * The values used are carefully arranged to make mmu_idx => EL lookup easy.
2895 * For M profile we arrange them to have a bit for priv, a bit for negpri
2896 * and a bit for secure.
2897 */
2898 #define ARM_MMU_IDX_A 0x10 /* A profile */
2899 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
2900 #define ARM_MMU_IDX_M 0x40 /* M profile */
2901
2902 /* Meanings of the bits for M profile mmu idx values */
2903 #define ARM_MMU_IDX_M_PRIV 0x1
2904 #define ARM_MMU_IDX_M_NEGPRI 0x2
2905 #define ARM_MMU_IDX_M_S 0x4 /* Secure */
2906
2907 #define ARM_MMU_IDX_TYPE_MASK \
2908 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
2909 #define ARM_MMU_IDX_COREIDX_MASK 0xf
2910
2911 typedef enum ARMMMUIdx {
2912 /*
2913 * A-profile.
2914 */
2915 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A,
2916 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A,
2917
2918 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A,
2919 ARMMMUIdx_E10_1_PAN = 3 | ARM_MMU_IDX_A,
2920
2921 ARMMMUIdx_E2 = 4 | ARM_MMU_IDX_A,
2922 ARMMMUIdx_E20_2 = 5 | ARM_MMU_IDX_A,
2923 ARMMMUIdx_E20_2_PAN = 6 | ARM_MMU_IDX_A,
2924
2925 ARMMMUIdx_SE10_0 = 7 | ARM_MMU_IDX_A,
2926 ARMMMUIdx_SE10_1 = 8 | ARM_MMU_IDX_A,
2927 ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A,
2928 ARMMMUIdx_SE3 = 10 | ARM_MMU_IDX_A,
2929
2930 /*
2931 * These are not allocated TLBs and are used only for AT system
2932 * instructions or for the first stage of an S12 page table walk.
2933 */
2934 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
2935 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
2936 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
2937 /*
2938 * Not allocated a TLB: used only for second stage of an S12 page
2939 * table walk, or for descriptor loads during first stage of an S1
2940 * page table walk. Note that if we ever want to have a TLB for this
2941 * then various TLB flush insns which currently are no-ops or flush
2942 * only stage 1 MMU indexes will need to change to flush stage 2.
2943 */
2944 ARMMMUIdx_Stage2 = 3 | ARM_MMU_IDX_NOTLB,
2945
2946 /*
2947 * M-profile.
2948 */
2949 ARMMMUIdx_MUser = ARM_MMU_IDX_M,
2950 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
2951 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
2952 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
2953 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
2954 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
2955 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
2956 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
2957 } ARMMMUIdx;
2958
2959 /*
2960 * Bit macros for the core-mmu-index values for each index,
2961 * for use when calling tlb_flush_by_mmuidx() and friends.
2962 */
2963 #define TO_CORE_BIT(NAME) \
2964 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
2965
2966 typedef enum ARMMMUIdxBit {
2967 TO_CORE_BIT(E10_0),
2968 TO_CORE_BIT(E20_0),
2969 TO_CORE_BIT(E10_1),
2970 TO_CORE_BIT(E10_1_PAN),
2971 TO_CORE_BIT(E2),
2972 TO_CORE_BIT(E20_2),
2973 TO_CORE_BIT(E20_2_PAN),
2974 TO_CORE_BIT(SE10_0),
2975 TO_CORE_BIT(SE10_1),
2976 TO_CORE_BIT(SE10_1_PAN),
2977 TO_CORE_BIT(SE3),
2978
2979 TO_CORE_BIT(MUser),
2980 TO_CORE_BIT(MPriv),
2981 TO_CORE_BIT(MUserNegPri),
2982 TO_CORE_BIT(MPrivNegPri),
2983 TO_CORE_BIT(MSUser),
2984 TO_CORE_BIT(MSPriv),
2985 TO_CORE_BIT(MSUserNegPri),
2986 TO_CORE_BIT(MSPrivNegPri),
2987 } ARMMMUIdxBit;
2988
2989 #undef TO_CORE_BIT
2990
2991 #define MMU_USER_IDX 0
2992
2993 /* Indexes used when registering address spaces with cpu_address_space_init */
2994 typedef enum ARMASIdx {
2995 ARMASIdx_NS = 0,
2996 ARMASIdx_S = 1,
2997 ARMASIdx_TagNS = 2,
2998 ARMASIdx_TagS = 3,
2999 } ARMASIdx;
3000
3001 /* Return the Exception Level targeted by debug exceptions. */
3002 static inline int arm_debug_target_el(CPUARMState *env)
3003 {
3004 bool secure = arm_is_secure(env);
3005 bool route_to_el2 = false;
3006
3007 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
3008 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
3009 env->cp15.mdcr_el2 & MDCR_TDE;
3010 }
3011
3012 if (route_to_el2) {
3013 return 2;
3014 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
3015 !arm_el_is_aa64(env, 3) && secure) {
3016 return 3;
3017 } else {
3018 return 1;
3019 }
3020 }
3021
3022 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
3023 {
3024 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and
3025 * CSSELR is RAZ/WI.
3026 */
3027 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
3028 }
3029
3030 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */
3031 static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
3032 {
3033 int cur_el = arm_current_el(env);
3034 int debug_el;
3035
3036 if (cur_el == 3) {
3037 return false;
3038 }
3039
3040 /* MDCR_EL3.SDD disables debug events from Secure state */
3041 if (arm_is_secure_below_el3(env)
3042 && extract32(env->cp15.mdcr_el3, 16, 1)) {
3043 return false;
3044 }
3045
3046 /*
3047 * Same EL to same EL debug exceptions need MDSCR_KDE enabled
3048 * while not masking the (D)ebug bit in DAIF.
3049 */
3050 debug_el = arm_debug_target_el(env);
3051
3052 if (cur_el == debug_el) {
3053 return extract32(env->cp15.mdscr_el1, 13, 1)
3054 && !(env->daif & PSTATE_D);
3055 }
3056
3057 /* Otherwise the debug target needs to be a higher EL */
3058 return debug_el > cur_el;
3059 }
3060
3061 static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
3062 {
3063 int el = arm_current_el(env);
3064
3065 if (el == 0 && arm_el_is_aa64(env, 1)) {
3066 return aa64_generate_debug_exceptions(env);
3067 }
3068
3069 if (arm_is_secure(env)) {
3070 int spd;
3071
3072 if (el == 0 && (env->cp15.sder & 1)) {
3073 /* SDER.SUIDEN means debug exceptions from Secure EL0
3074 * are always enabled. Otherwise they are controlled by
3075 * SDCR.SPD like those from other Secure ELs.
3076 */
3077 return true;
3078 }
3079
3080 spd = extract32(env->cp15.mdcr_el3, 14, 2);
3081 switch (spd) {
3082 case 1:
3083 /* SPD == 0b01 is reserved, but behaves as 0b00. */
3084 case 0:
3085 /* For 0b00 we return true if external secure invasive debug
3086 * is enabled. On real hardware this is controlled by external
3087 * signals to the core. QEMU always permits debug, and behaves
3088 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
3089 */
3090 return true;
3091 case 2:
3092 return false;
3093 case 3:
3094 return true;
3095 }
3096 }
3097
3098 return el != 2;
3099 }
3100
3101 /* Return true if debugging exceptions are currently enabled.
3102 * This corresponds to what in ARM ARM pseudocode would be
3103 * if UsingAArch32() then
3104 * return AArch32.GenerateDebugExceptions()
3105 * else
3106 * return AArch64.GenerateDebugExceptions()
3107 * We choose to push the if() down into this function for clarity,
3108 * since the pseudocode has it at all callsites except for the one in
3109 * CheckSoftwareStep(), where it is elided because both branches would
3110 * always return the same value.
3111 */
3112 static inline bool arm_generate_debug_exceptions(CPUARMState *env)
3113 {
3114 if (env->aarch64) {
3115 return aa64_generate_debug_exceptions(env);
3116 } else {
3117 return aa32_generate_debug_exceptions(env);
3118 }
3119 }
3120
3121 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check
3122 * implicitly means this always returns false in pre-v8 CPUs.)
3123 */
3124 static inline bool arm_singlestep_active(CPUARMState *env)
3125 {
3126 return extract32(env->cp15.mdscr_el1, 0, 1)
3127 && arm_el_is_aa64(env, arm_debug_target_el(env))
3128 && arm_generate_debug_exceptions(env);
3129 }
3130
3131 static inline bool arm_sctlr_b(CPUARMState *env)
3132 {
3133 return
3134 /* We need not implement SCTLR.ITD in user-mode emulation, so
3135 * let linux-user ignore the fact that it conflicts with SCTLR_B.
3136 * This lets people run BE32 binaries with "-cpu any".
3137 */
3138 #ifndef CONFIG_USER_ONLY
3139 !arm_feature(env, ARM_FEATURE_V7) &&
3140 #endif
3141 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
3142 }
3143
3144 uint64_t arm_sctlr(CPUARMState *env, int el);
3145
3146 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
3147 bool sctlr_b)
3148 {
3149 #ifdef CONFIG_USER_ONLY
3150 /*
3151 * In system mode, BE32 is modelled in line with the
3152 * architecture (as word-invariant big-endianness), where loads
3153 * and stores are done little endian but from addresses which
3154 * are adjusted by XORing with the appropriate constant. So the
3155 * endianness to use for the raw data access is not affected by
3156 * SCTLR.B.
3157 * In user mode, however, we model BE32 as byte-invariant
3158 * big-endianness (because user-only code cannot tell the
3159 * difference), and so we need to use a data access endianness
3160 * that depends on SCTLR.B.
3161 */
3162 if (sctlr_b) {
3163 return true;
3164 }
3165 #endif
3166 /* In 32bit endianness is determined by looking at CPSR's E bit */
3167 return env->uncached_cpsr & CPSR_E;
3168 }
3169
3170 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
3171 {
3172 return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
3173 }
3174
3175 /* Return true if the processor is in big-endian mode. */
3176 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
3177 {
3178 if (!is_a64(env)) {
3179 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
3180 } else {
3181 int cur_el = arm_current_el(env);
3182 uint64_t sctlr = arm_sctlr(env, cur_el);
3183 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
3184 }
3185 }
3186
3187 typedef CPUARMState CPUArchState;
3188 typedef ARMCPU ArchCPU;
3189
3190 #include "exec/cpu-all.h"
3191
3192 /*
3193 * Bit usage in the TB flags field: bit 31 indicates whether we are
3194 * in 32 or 64 bit mode. The meaning of the other bits depends on that.
3195 * We put flags which are shared between 32 and 64 bit mode at the top
3196 * of the word, and flags which apply to only one mode at the bottom.
3197 *
3198 * 31 20 18 14 9 0
3199 * +--------------+-----+-----+----------+--------------+
3200 * | | | TBFLAG_A32 | |
3201 * | | +-----+----------+ TBFLAG_AM32 |
3202 * | TBFLAG_ANY | |TBFLAG_M32| |
3203 * | +-----------+----------+--------------|
3204 * | | TBFLAG_A64 |
3205 * +--------------+-------------------------------------+
3206 * 31 20 0
3207 *
3208 * Unless otherwise noted, these bits are cached in env->hflags.
3209 */
3210 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
3211 FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1)
3212 FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */
3213 FIELD(TBFLAG_ANY, BE_DATA, 28, 1)
3214 FIELD(TBFLAG_ANY, MMUIDX, 24, 4)
3215 /* Target EL if we take a floating-point-disabled exception */
3216 FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2)
3217 /* For A-profile only, target EL for debug exceptions. */
3218 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2)
3219
3220 /*
3221 * Bit usage when in AArch32 state, both A- and M-profile.
3222 */
3223 FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */
3224 FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */
3225
3226 /*
3227 * Bit usage when in AArch32 state, for A-profile only.
3228 */
3229 FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */
3230 FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */
3231 /*
3232 * We store the bottom two bits of the CPAR as TB flags and handle
3233 * checks on the other bits at runtime. This shares the same bits as
3234 * VECSTRIDE, which is OK as no XScale CPU has VFP.
3235 * Not cached, because VECLEN+VECSTRIDE are not cached.
3236 */
3237 FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2)
3238 FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */
3239 FIELD(TBFLAG_A32, SCTLR_B, 15, 1)
3240 FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1)
3241 /*
3242 * Indicates whether cp register reads and writes by guest code should access
3243 * the secure or nonsecure bank of banked registers; note that this is not
3244 * the same thing as the current security state of the processor!
3245 */
3246 FIELD(TBFLAG_A32, NS, 17, 1)
3247
3248 /*
3249 * Bit usage when in AArch32 state, for M-profile only.
3250 */
3251 /* Handler (ie not Thread) mode */
3252 FIELD(TBFLAG_M32, HANDLER, 9, 1)
3253 /* Whether we should generate stack-limit checks */
3254 FIELD(TBFLAG_M32, STACKCHECK, 10, 1)
3255 /* Set if FPCCR.LSPACT is set */
3256 FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */
3257 /* Set if we must create a new FP context */
3258 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */
3259 /* Set if FPCCR.S does not match current security state */
3260 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */
3261
3262 /*
3263 * Bit usage when in AArch64 state
3264 */
3265 FIELD(TBFLAG_A64, TBII, 0, 2)
3266 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
3267 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
3268 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3269 FIELD(TBFLAG_A64, BT, 9, 1)
3270 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */
3271 FIELD(TBFLAG_A64, TBID, 12, 2)
3272 FIELD(TBFLAG_A64, UNPRIV, 14, 1)
3273 FIELD(TBFLAG_A64, ATA, 15, 1)
3274 FIELD(TBFLAG_A64, TCMA, 16, 2)
3275 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
3276 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
3277
3278 /**
3279 * cpu_mmu_index:
3280 * @env: The cpu environment
3281 * @ifetch: True for code access, false for data access.
3282 *
3283 * Return the core mmu index for the current translation regime.
3284 * This function is used by generic TCG code paths.
3285 */
3286 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
3287 {
3288 return FIELD_EX32(env->hflags, TBFLAG_ANY, MMUIDX);
3289 }
3290
3291 static inline bool bswap_code(bool sctlr_b)
3292 {
3293 #ifdef CONFIG_USER_ONLY
3294 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian.
3295 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0
3296 * would also end up as a mixed-endian mode with BE code, LE data.
3297 */
3298 return
3299 #ifdef TARGET_WORDS_BIGENDIAN
3300 1 ^
3301 #endif
3302 sctlr_b;
3303 #else
3304 /* All code access in ARM is little endian, and there are no loaders
3305 * doing swaps that need to be reversed
3306 */
3307 return 0;
3308 #endif
3309 }
3310
3311 #ifdef CONFIG_USER_ONLY
3312 static inline bool arm_cpu_bswap_data(CPUARMState *env)
3313 {
3314 return
3315 #ifdef TARGET_WORDS_BIGENDIAN
3316 1 ^
3317 #endif
3318 arm_cpu_data_is_big_endian(env);
3319 }
3320 #endif
3321
3322 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
3323 target_ulong *cs_base, uint32_t *flags);
3324
3325 enum {
3326 QEMU_PSCI_CONDUIT_DISABLED = 0,
3327 QEMU_PSCI_CONDUIT_SMC = 1,
3328 QEMU_PSCI_CONDUIT_HVC = 2,
3329 };
3330
3331 #ifndef CONFIG_USER_ONLY
3332 /* Return the address space index to use for a memory access */
3333 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3334 {
3335 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3336 }
3337
3338 /* Return the AddressSpace to use for a memory access
3339 * (which depends on whether the access is S or NS, and whether
3340 * the board gave us a separate AddressSpace for S accesses).
3341 */
3342 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3343 {
3344 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3345 }
3346 #endif
3347
3348 /**
3349 * arm_register_pre_el_change_hook:
3350 * Register a hook function which will be called immediately before this
3351 * CPU changes exception level or mode. The hook function will be
3352 * passed a pointer to the ARMCPU and the opaque data pointer passed
3353 * to this function when the hook was registered.
3354 *
3355 * Note that if a pre-change hook is called, any registered post-change hooks
3356 * are guaranteed to subsequently be called.
3357 */
3358 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3359 void *opaque);
3360 /**
3361 * arm_register_el_change_hook:
3362 * Register a hook function which will be called immediately after this
3363 * CPU changes exception level or mode. The hook function will be
3364 * passed a pointer to the ARMCPU and the opaque data pointer passed
3365 * to this function when the hook was registered.
3366 *
3367 * Note that any registered hooks registered here are guaranteed to be called
3368 * if pre-change hooks have been.
3369 */
3370 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3371 *opaque);
3372
3373 /**
3374 * arm_rebuild_hflags:
3375 * Rebuild the cached TBFLAGS for arbitrary changed processor state.
3376 */
3377 void arm_rebuild_hflags(CPUARMState *env);
3378
3379 /**
3380 * aa32_vfp_dreg:
3381 * Return a pointer to the Dn register within env in 32-bit mode.
3382 */
3383 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3384 {
3385 return &env->vfp.zregs[regno >> 1].d[regno & 1];
3386 }
3387
3388 /**
3389 * aa32_vfp_qreg:
3390 * Return a pointer to the Qn register within env in 32-bit mode.
3391 */
3392 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3393 {
3394 return &env->vfp.zregs[regno].d[0];
3395 }
3396
3397 /**
3398 * aa64_vfp_qreg:
3399 * Return a pointer to the Qn register within env in 64-bit mode.
3400 */
3401 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3402 {
3403 return &env->vfp.zregs[regno].d[0];
3404 }
3405
3406 /* Shared between translate-sve.c and sve_helper.c. */
3407 extern const uint64_t pred_esz_masks[4];
3408
3409 /* Helper for the macros below, validating the argument type. */
3410 static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
3411 {
3412 return x;
3413 }
3414
3415 /*
3416 * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB.
3417 * Using these should be a bit more self-documenting than using the
3418 * generic target bits directly.
3419 */
3420 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
3421 #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1)
3422
3423 /*
3424 * Naming convention for isar_feature functions:
3425 * Functions which test 32-bit ID registers should have _aa32_ in
3426 * their name. Functions which test 64-bit ID registers should have
3427 * _aa64_ in their name. These must only be used in code where we
3428 * know for certain that the CPU has AArch32 or AArch64 respectively
3429 * or where the correct answer for a CPU which doesn't implement that
3430 * CPU state is "false" (eg when generating A32 or A64 code, if adding
3431 * system registers that are specific to that CPU state, for "should
3432 * we let this system register bit be set" tests where the 32-bit
3433 * flavour of the register doesn't have the bit, and so on).
3434 * Functions which simply ask "does this feature exist at all" have
3435 * _any_ in their name, and always return the logical OR of the _aa64_
3436 * and the _aa32_ function.
3437 */
3438
3439 /*
3440 * 32-bit feature tests via id registers.
3441 */
3442 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
3443 {
3444 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
3445 }
3446
3447 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
3448 {
3449 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
3450 }
3451
3452 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
3453 {
3454 return FIELD_EX32(id