target/arm: Implement v8.1M NOCP handling
[qemu.git] / target / arm / cpu.h
1 /*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef ARM_CPU_H
21 #define ARM_CPU_H
22
23 #include "kvm-consts.h"
24 #include "hw/registerfields.h"
25 #include "cpu-qom.h"
26 #include "exec/cpu-defs.h"
27 #include "qapi/qapi-types-common.h"
28
29 /* ARM processors have a weak memory model */
30 #define TCG_GUEST_DEFAULT_MO (0)
31
32 #ifdef TARGET_AARCH64
33 #define KVM_HAVE_MCE_INJECTION 1
34 #endif
35
36 #define EXCP_UDEF 1 /* undefined instruction */
37 #define EXCP_SWI 2 /* software interrupt */
38 #define EXCP_PREFETCH_ABORT 3
39 #define EXCP_DATA_ABORT 4
40 #define EXCP_IRQ 5
41 #define EXCP_FIQ 6
42 #define EXCP_BKPT 7
43 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
44 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
45 #define EXCP_HVC 11 /* HyperVisor Call */
46 #define EXCP_HYP_TRAP 12
47 #define EXCP_SMC 13 /* Secure Monitor Call */
48 #define EXCP_VIRQ 14
49 #define EXCP_VFIQ 15
50 #define EXCP_SEMIHOST 16 /* semihosting call */
51 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */
52 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
53 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */
54 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */
55 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */
56 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */
57 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
58
59 #define ARMV7M_EXCP_RESET 1
60 #define ARMV7M_EXCP_NMI 2
61 #define ARMV7M_EXCP_HARD 3
62 #define ARMV7M_EXCP_MEM 4
63 #define ARMV7M_EXCP_BUS 5
64 #define ARMV7M_EXCP_USAGE 6
65 #define ARMV7M_EXCP_SECURE 7
66 #define ARMV7M_EXCP_SVC 11
67 #define ARMV7M_EXCP_DEBUG 12
68 #define ARMV7M_EXCP_PENDSV 14
69 #define ARMV7M_EXCP_SYSTICK 15
70
71 /* For M profile, some registers are banked secure vs non-secure;
72 * these are represented as a 2-element array where the first element
73 * is the non-secure copy and the second is the secure copy.
74 * When the CPU does not have implement the security extension then
75 * only the first element is used.
76 * This means that the copy for the current security state can be
77 * accessed via env->registerfield[env->v7m.secure] (whether the security
78 * extension is implemented or not).
79 */
80 enum {
81 M_REG_NS = 0,
82 M_REG_S = 1,
83 M_REG_NUM_BANKS = 2,
84 };
85
86 /* ARM-specific interrupt pending bits. */
87 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
88 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
89 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
90
91 /* The usual mapping for an AArch64 system register to its AArch32
92 * counterpart is for the 32 bit world to have access to the lower
93 * half only (with writes leaving the upper half untouched). It's
94 * therefore useful to be able to pass TCG the offset of the least
95 * significant half of a uint64_t struct member.
96 */
97 #ifdef HOST_WORDS_BIGENDIAN
98 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
99 #define offsetofhigh32(S, M) offsetof(S, M)
100 #else
101 #define offsetoflow32(S, M) offsetof(S, M)
102 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
103 #endif
104
105 /* Meanings of the ARMCPU object's four inbound GPIO lines */
106 #define ARM_CPU_IRQ 0
107 #define ARM_CPU_FIQ 1
108 #define ARM_CPU_VIRQ 2
109 #define ARM_CPU_VFIQ 3
110
111 /* ARM-specific extra insn start words:
112 * 1: Conditional execution bits
113 * 2: Partial exception syndrome for data aborts
114 */
115 #define TARGET_INSN_START_EXTRA_WORDS 2
116
117 /* The 2nd extra word holding syndrome info for data aborts does not use
118 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to
119 * help the sleb128 encoder do a better job.
120 * When restoring the CPU state, we shift it back up.
121 */
122 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
123 #define ARM_INSN_START_WORD2_SHIFT 14
124
125 /* We currently assume float and double are IEEE single and double
126 precision respectively.
127 Doing runtime conversions is tricky because VFP registers may contain
128 integer values (eg. as the result of a FTOSI instruction).
129 s<2n> maps to the least significant half of d<n>
130 s<2n+1> maps to the most significant half of d<n>
131 */
132
133 /**
134 * DynamicGDBXMLInfo:
135 * @desc: Contains the XML descriptions.
136 * @num: Number of the registers in this XML seen by GDB.
137 * @data: A union with data specific to the set of registers
138 * @cpregs_keys: Array that contains the corresponding Key of
139 * a given cpreg with the same order of the cpreg
140 * in the XML description.
141 */
142 typedef struct DynamicGDBXMLInfo {
143 char *desc;
144 int num;
145 union {
146 struct {
147 uint32_t *keys;
148 } cpregs;
149 } data;
150 } DynamicGDBXMLInfo;
151
152 /* CPU state for each instance of a generic timer (in cp15 c14) */
153 typedef struct ARMGenericTimer {
154 uint64_t cval; /* Timer CompareValue register */
155 uint64_t ctl; /* Timer Control register */
156 } ARMGenericTimer;
157
158 #define GTIMER_PHYS 0
159 #define GTIMER_VIRT 1
160 #define GTIMER_HYP 2
161 #define GTIMER_SEC 3
162 #define GTIMER_HYPVIRT 4
163 #define NUM_GTIMERS 5
164
165 typedef struct {
166 uint64_t raw_tcr;
167 uint32_t mask;
168 uint32_t base_mask;
169 } TCR;
170
171 /* Define a maximum sized vector register.
172 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
173 * For 64-bit, this is a 2048-bit SVE register.
174 *
175 * Note that the mapping between S, D, and Q views of the register bank
176 * differs between AArch64 and AArch32.
177 * In AArch32:
178 * Qn = regs[n].d[1]:regs[n].d[0]
179 * Dn = regs[n / 2].d[n & 1]
180 * Sn = regs[n / 4].d[n % 4 / 2],
181 * bits 31..0 for even n, and bits 63..32 for odd n
182 * (and regs[16] to regs[31] are inaccessible)
183 * In AArch64:
184 * Zn = regs[n].d[*]
185 * Qn = regs[n].d[1]:regs[n].d[0]
186 * Dn = regs[n].d[0]
187 * Sn = regs[n].d[0] bits 31..0
188 * Hn = regs[n].d[0] bits 15..0
189 *
190 * This corresponds to the architecturally defined mapping between
191 * the two execution states, and means we do not need to explicitly
192 * map these registers when changing states.
193 *
194 * Align the data for use with TCG host vector operations.
195 */
196
197 #ifdef TARGET_AARCH64
198 # define ARM_MAX_VQ 16
199 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
200 #else
201 # define ARM_MAX_VQ 1
202 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
203 #endif
204
205 typedef struct ARMVectorReg {
206 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
207 } ARMVectorReg;
208
209 #ifdef TARGET_AARCH64
210 /* In AArch32 mode, predicate registers do not exist at all. */
211 typedef struct ARMPredicateReg {
212 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
213 } ARMPredicateReg;
214
215 /* In AArch32 mode, PAC keys do not exist at all. */
216 typedef struct ARMPACKey {
217 uint64_t lo, hi;
218 } ARMPACKey;
219 #endif
220
221
222 typedef struct CPUARMState {
223 /* Regs for current mode. */
224 uint32_t regs[16];
225
226 /* 32/64 switch only happens when taking and returning from
227 * exceptions so the overlap semantics are taken care of then
228 * instead of having a complicated union.
229 */
230 /* Regs for A64 mode. */
231 uint64_t xregs[32];
232 uint64_t pc;
233 /* PSTATE isn't an architectural register for ARMv8. However, it is
234 * convenient for us to assemble the underlying state into a 32 bit format
235 * identical to the architectural format used for the SPSR. (This is also
236 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
237 * 'pstate' register are.) Of the PSTATE bits:
238 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
239 * semantics as for AArch32, as described in the comments on each field)
240 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
241 * DAIF (exception masks) are kept in env->daif
242 * BTYPE is kept in env->btype
243 * all other bits are stored in their correct places in env->pstate
244 */
245 uint32_t pstate;
246 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
247
248 /* Cached TBFLAGS state. See below for which bits are included. */
249 uint32_t hflags;
250
251 /* Frequently accessed CPSR bits are stored separately for efficiency.
252 This contains all the other bits. Use cpsr_{read,write} to access
253 the whole CPSR. */
254 uint32_t uncached_cpsr;
255 uint32_t spsr;
256
257 /* Banked registers. */
258 uint64_t banked_spsr[8];
259 uint32_t banked_r13[8];
260 uint32_t banked_r14[8];
261
262 /* These hold r8-r12. */
263 uint32_t usr_regs[5];
264 uint32_t fiq_regs[5];
265
266 /* cpsr flag cache for faster execution */
267 uint32_t CF; /* 0 or 1 */
268 uint32_t VF; /* V is the bit 31. All other bits are undefined */
269 uint32_t NF; /* N is bit 31. All other bits are undefined. */
270 uint32_t ZF; /* Z set if zero. */
271 uint32_t QF; /* 0 or 1 */
272 uint32_t GE; /* cpsr[19:16] */
273 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
274 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
275 uint32_t btype; /* BTI branch type. spsr[11:10]. */
276 uint64_t daif; /* exception masks, in the bits they are in PSTATE */
277
278 uint64_t elr_el[4]; /* AArch64 exception link regs */
279 uint64_t sp_el[4]; /* AArch64 banked stack pointers */
280
281 /* System control coprocessor (cp15) */
282 struct {
283 uint32_t c0_cpuid;
284 union { /* Cache size selection */
285 struct {
286 uint64_t _unused_csselr0;
287 uint64_t csselr_ns;
288 uint64_t _unused_csselr1;
289 uint64_t csselr_s;
290 };
291 uint64_t csselr_el[4];
292 };
293 union { /* System control register. */
294 struct {
295 uint64_t _unused_sctlr;
296 uint64_t sctlr_ns;
297 uint64_t hsctlr;
298 uint64_t sctlr_s;
299 };
300 uint64_t sctlr_el[4];
301 };
302 uint64_t cpacr_el1; /* Architectural feature access control register */
303 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */
304 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
305 uint64_t sder; /* Secure debug enable register. */
306 uint32_t nsacr; /* Non-secure access control register. */
307 union { /* MMU translation table base 0. */
308 struct {
309 uint64_t _unused_ttbr0_0;
310 uint64_t ttbr0_ns;
311 uint64_t _unused_ttbr0_1;
312 uint64_t ttbr0_s;
313 };
314 uint64_t ttbr0_el[4];
315 };
316 union { /* MMU translation table base 1. */
317 struct {
318 uint64_t _unused_ttbr1_0;
319 uint64_t ttbr1_ns;
320 uint64_t _unused_ttbr1_1;
321 uint64_t ttbr1_s;
322 };
323 uint64_t ttbr1_el[4];
324 };
325 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */
326 /* MMU translation table base control. */
327 TCR tcr_el[4];
328 TCR vtcr_el2; /* Virtualization Translation Control. */
329 uint32_t c2_data; /* MPU data cacheable bits. */
330 uint32_t c2_insn; /* MPU instruction cacheable bits. */
331 union { /* MMU domain access control register
332 * MPU write buffer control.
333 */
334 struct {
335 uint64_t dacr_ns;
336 uint64_t dacr_s;
337 };
338 struct {
339 uint64_t dacr32_el2;
340 };
341 };
342 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
343 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
344 uint64_t hcr_el2; /* Hypervisor configuration register */
345 uint64_t scr_el3; /* Secure configuration register. */
346 union { /* Fault status registers. */
347 struct {
348 uint64_t ifsr_ns;
349 uint64_t ifsr_s;
350 };
351 struct {
352 uint64_t ifsr32_el2;
353 };
354 };
355 union {
356 struct {
357 uint64_t _unused_dfsr;
358 uint64_t dfsr_ns;
359 uint64_t hsr;
360 uint64_t dfsr_s;
361 };
362 uint64_t esr_el[4];
363 };
364 uint32_t c6_region[8]; /* MPU base/size registers. */
365 union { /* Fault address registers. */
366 struct {
367 uint64_t _unused_far0;
368 #ifdef HOST_WORDS_BIGENDIAN
369 uint32_t ifar_ns;
370 uint32_t dfar_ns;
371 uint32_t ifar_s;
372 uint32_t dfar_s;
373 #else
374 uint32_t dfar_ns;
375 uint32_t ifar_ns;
376 uint32_t dfar_s;
377 uint32_t ifar_s;
378 #endif
379 uint64_t _unused_far3;
380 };
381 uint64_t far_el[4];
382 };
383 uint64_t hpfar_el2;
384 uint64_t hstr_el2;
385 union { /* Translation result. */
386 struct {
387 uint64_t _unused_par_0;
388 uint64_t par_ns;
389 uint64_t _unused_par_1;
390 uint64_t par_s;
391 };
392 uint64_t par_el[4];
393 };
394
395 uint32_t c9_insn; /* Cache lockdown registers. */
396 uint32_t c9_data;
397 uint64_t c9_pmcr; /* performance monitor control register */
398 uint64_t c9_pmcnten; /* perf monitor counter enables */
399 uint64_t c9_pmovsr; /* perf monitor overflow status */
400 uint64_t c9_pmuserenr; /* perf monitor user enable */
401 uint64_t c9_pmselr; /* perf monitor counter selection register */
402 uint64_t c9_pminten; /* perf monitor interrupt enables */
403 union { /* Memory attribute redirection */
404 struct {
405 #ifdef HOST_WORDS_BIGENDIAN
406 uint64_t _unused_mair_0;
407 uint32_t mair1_ns;
408 uint32_t mair0_ns;
409 uint64_t _unused_mair_1;
410 uint32_t mair1_s;
411 uint32_t mair0_s;
412 #else
413 uint64_t _unused_mair_0;
414 uint32_t mair0_ns;
415 uint32_t mair1_ns;
416 uint64_t _unused_mair_1;
417 uint32_t mair0_s;
418 uint32_t mair1_s;
419 #endif
420 };
421 uint64_t mair_el[4];
422 };
423 union { /* vector base address register */
424 struct {
425 uint64_t _unused_vbar;
426 uint64_t vbar_ns;
427 uint64_t hvbar;
428 uint64_t vbar_s;
429 };
430 uint64_t vbar_el[4];
431 };
432 uint32_t mvbar; /* (monitor) vector base address register */
433 struct { /* FCSE PID. */
434 uint32_t fcseidr_ns;
435 uint32_t fcseidr_s;
436 };
437 union { /* Context ID. */
438 struct {
439 uint64_t _unused_contextidr_0;
440 uint64_t contextidr_ns;
441 uint64_t _unused_contextidr_1;
442 uint64_t contextidr_s;
443 };
444 uint64_t contextidr_el[4];
445 };
446 union { /* User RW Thread register. */
447 struct {
448 uint64_t tpidrurw_ns;
449 uint64_t tpidrprw_ns;
450 uint64_t htpidr;
451 uint64_t _tpidr_el3;
452 };
453 uint64_t tpidr_el[4];
454 };
455 /* The secure banks of these registers don't map anywhere */
456 uint64_t tpidrurw_s;
457 uint64_t tpidrprw_s;
458 uint64_t tpidruro_s;
459
460 union { /* User RO Thread register. */
461 uint64_t tpidruro_ns;
462 uint64_t tpidrro_el[1];
463 };
464 uint64_t c14_cntfrq; /* Counter Frequency register */
465 uint64_t c14_cntkctl; /* Timer Control register */
466 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
467 uint64_t cntvoff_el2; /* Counter Virtual Offset register */
468 ARMGenericTimer c14_timer[NUM_GTIMERS];
469 uint32_t c15_cpar; /* XScale Coprocessor Access Register */
470 uint32_t c15_ticonfig; /* TI925T configuration byte. */
471 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
472 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
473 uint32_t c15_threadid; /* TI debugger thread-ID. */
474 uint32_t c15_config_base_address; /* SCU base address. */
475 uint32_t c15_diagnostic; /* diagnostic register */
476 uint32_t c15_power_diagnostic;
477 uint32_t c15_power_control; /* power control */
478 uint64_t dbgbvr[16]; /* breakpoint value registers */
479 uint64_t dbgbcr[16]; /* breakpoint control registers */
480 uint64_t dbgwvr[16]; /* watchpoint value registers */
481 uint64_t dbgwcr[16]; /* watchpoint control registers */
482 uint64_t mdscr_el1;
483 uint64_t oslsr_el1; /* OS Lock Status */
484 uint64_t mdcr_el2;
485 uint64_t mdcr_el3;
486 /* Stores the architectural value of the counter *the last time it was
487 * updated* by pmccntr_op_start. Accesses should always be surrounded
488 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest
489 * architecturally-correct value is being read/set.
490 */
491 uint64_t c15_ccnt;
492 /* Stores the delta between the architectural value and the underlying
493 * cycle count during normal operation. It is used to update c15_ccnt
494 * to be the correct architectural value before accesses. During
495 * accesses, c15_ccnt_delta contains the underlying count being used
496 * for the access, after which it reverts to the delta value in
497 * pmccntr_op_finish.
498 */
499 uint64_t c15_ccnt_delta;
500 uint64_t c14_pmevcntr[31];
501 uint64_t c14_pmevcntr_delta[31];
502 uint64_t c14_pmevtyper[31];
503 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
504 uint64_t vpidr_el2; /* Virtualization Processor ID Register */
505 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
506 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */
507 uint64_t gcr_el1;
508 uint64_t rgsr_el1;
509 } cp15;
510
511 struct {
512 /* M profile has up to 4 stack pointers:
513 * a Main Stack Pointer and a Process Stack Pointer for each
514 * of the Secure and Non-Secure states. (If the CPU doesn't support
515 * the security extension then it has only two SPs.)
516 * In QEMU we always store the currently active SP in regs[13],
517 * and the non-active SP for the current security state in
518 * v7m.other_sp. The stack pointers for the inactive security state
519 * are stored in other_ss_msp and other_ss_psp.
520 * switch_v7m_security_state() is responsible for rearranging them
521 * when we change security state.
522 */
523 uint32_t other_sp;
524 uint32_t other_ss_msp;
525 uint32_t other_ss_psp;
526 uint32_t vecbase[M_REG_NUM_BANKS];
527 uint32_t basepri[M_REG_NUM_BANKS];
528 uint32_t control[M_REG_NUM_BANKS];
529 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */
530 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
531 uint32_t hfsr; /* HardFault Status */
532 uint32_t dfsr; /* Debug Fault Status Register */
533 uint32_t sfsr; /* Secure Fault Status Register */
534 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
535 uint32_t bfar; /* BusFault Address */
536 uint32_t sfar; /* Secure Fault Address Register */
537 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
538 int exception;
539 uint32_t primask[M_REG_NUM_BANKS];
540 uint32_t faultmask[M_REG_NUM_BANKS];
541 uint32_t aircr; /* only holds r/w state if security extn implemented */
542 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
543 uint32_t csselr[M_REG_NUM_BANKS];
544 uint32_t scr[M_REG_NUM_BANKS];
545 uint32_t msplim[M_REG_NUM_BANKS];
546 uint32_t psplim[M_REG_NUM_BANKS];
547 uint32_t fpcar[M_REG_NUM_BANKS];
548 uint32_t fpccr[M_REG_NUM_BANKS];
549 uint32_t fpdscr[M_REG_NUM_BANKS];
550 uint32_t cpacr[M_REG_NUM_BANKS];
551 uint32_t nsacr;
552 } v7m;
553
554 /* Information associated with an exception about to be taken:
555 * code which raises an exception must set cs->exception_index and
556 * the relevant parts of this structure; the cpu_do_interrupt function
557 * will then set the guest-visible registers as part of the exception
558 * entry process.
559 */
560 struct {
561 uint32_t syndrome; /* AArch64 format syndrome register */
562 uint32_t fsr; /* AArch32 format fault status register info */
563 uint64_t vaddress; /* virtual addr associated with exception, if any */
564 uint32_t target_el; /* EL the exception should be targeted for */
565 /* If we implement EL2 we will also need to store information
566 * about the intermediate physical address for stage 2 faults.
567 */
568 } exception;
569
570 /* Information associated with an SError */
571 struct {
572 uint8_t pending;
573 uint8_t has_esr;
574 uint64_t esr;
575 } serror;
576
577 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
578
579 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
580 uint32_t irq_line_state;
581
582 /* Thumb-2 EE state. */
583 uint32_t teecr;
584 uint32_t teehbr;
585
586 /* VFP coprocessor state. */
587 struct {
588 ARMVectorReg zregs[32];
589
590 #ifdef TARGET_AARCH64
591 /* Store FFR as pregs[16] to make it easier to treat as any other. */
592 #define FFR_PRED_NUM 16
593 ARMPredicateReg pregs[17];
594 /* Scratch space for aa64 sve predicate temporary. */
595 ARMPredicateReg preg_tmp;
596 #endif
597
598 /* We store these fpcsr fields separately for convenience. */
599 uint32_t qc[4] QEMU_ALIGNED(16);
600 int vec_len;
601 int vec_stride;
602
603 uint32_t xregs[16];
604
605 /* Scratch space for aa32 neon expansion. */
606 uint32_t scratch[8];
607
608 /* There are a number of distinct float control structures:
609 *
610 * fp_status: is the "normal" fp status.
611 * fp_status_fp16: used for half-precision calculations
612 * standard_fp_status : the ARM "Standard FPSCR Value"
613 * standard_fp_status_fp16 : used for half-precision
614 * calculations with the ARM "Standard FPSCR Value"
615 *
616 * Half-precision operations are governed by a separate
617 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
618 * status structure to control this.
619 *
620 * The "Standard FPSCR", ie default-NaN, flush-to-zero,
621 * round-to-nearest and is used by any operations (generally
622 * Neon) which the architecture defines as controlled by the
623 * standard FPSCR value rather than the FPSCR.
624 *
625 * The "standard FPSCR but for fp16 ops" is needed because
626 * the "standard FPSCR" tracks the FPSCR.FZ16 bit rather than
627 * using a fixed value for it.
628 *
629 * To avoid having to transfer exception bits around, we simply
630 * say that the FPSCR cumulative exception flags are the logical
631 * OR of the flags in the four fp statuses. This relies on the
632 * only thing which needs to read the exception flags being
633 * an explicit FPSCR read.
634 */
635 float_status fp_status;
636 float_status fp_status_f16;
637 float_status standard_fp_status;
638 float_status standard_fp_status_f16;
639
640 /* ZCR_EL[1-3] */
641 uint64_t zcr_el[4];
642 } vfp;
643 uint64_t exclusive_addr;
644 uint64_t exclusive_val;
645 uint64_t exclusive_high;
646
647 /* iwMMXt coprocessor state. */
648 struct {
649 uint64_t regs[16];
650 uint64_t val;
651
652 uint32_t cregs[16];
653 } iwmmxt;
654
655 #ifdef TARGET_AARCH64
656 struct {
657 ARMPACKey apia;
658 ARMPACKey apib;
659 ARMPACKey apda;
660 ARMPACKey apdb;
661 ARMPACKey apga;
662 } keys;
663 #endif
664
665 #if defined(CONFIG_USER_ONLY)
666 /* For usermode syscall translation. */
667 int eabi;
668 #endif
669
670 struct CPUBreakpoint *cpu_breakpoint[16];
671 struct CPUWatchpoint *cpu_watchpoint[16];
672
673 /* Fields up to this point are cleared by a CPU reset */
674 struct {} end_reset_fields;
675
676 /* Fields after this point are preserved across CPU reset. */
677
678 /* Internal CPU feature flags. */
679 uint64_t features;
680
681 /* PMSAv7 MPU */
682 struct {
683 uint32_t *drbar;
684 uint32_t *drsr;
685 uint32_t *dracr;
686 uint32_t rnr[M_REG_NUM_BANKS];
687 } pmsav7;
688
689 /* PMSAv8 MPU */
690 struct {
691 /* The PMSAv8 implementation also shares some PMSAv7 config
692 * and state:
693 * pmsav7.rnr (region number register)
694 * pmsav7_dregion (number of configured regions)
695 */
696 uint32_t *rbar[M_REG_NUM_BANKS];
697 uint32_t *rlar[M_REG_NUM_BANKS];
698 uint32_t mair0[M_REG_NUM_BANKS];
699 uint32_t mair1[M_REG_NUM_BANKS];
700 } pmsav8;
701
702 /* v8M SAU */
703 struct {
704 uint32_t *rbar;
705 uint32_t *rlar;
706 uint32_t rnr;
707 uint32_t ctrl;
708 } sau;
709
710 void *nvic;
711 const struct arm_boot_info *boot_info;
712 /* Store GICv3CPUState to access from this struct */
713 void *gicv3state;
714 } CPUARMState;
715
716 static inline void set_feature(CPUARMState *env, int feature)
717 {
718 env->features |= 1ULL << feature;
719 }
720
721 static inline void unset_feature(CPUARMState *env, int feature)
722 {
723 env->features &= ~(1ULL << feature);
724 }
725
726 /**
727 * ARMELChangeHookFn:
728 * type of a function which can be registered via arm_register_el_change_hook()
729 * to get callbacks when the CPU changes its exception level or mode.
730 */
731 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
732 typedef struct ARMELChangeHook ARMELChangeHook;
733 struct ARMELChangeHook {
734 ARMELChangeHookFn *hook;
735 void *opaque;
736 QLIST_ENTRY(ARMELChangeHook) node;
737 };
738
739 /* These values map onto the return values for
740 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */
741 typedef enum ARMPSCIState {
742 PSCI_ON = 0,
743 PSCI_OFF = 1,
744 PSCI_ON_PENDING = 2
745 } ARMPSCIState;
746
747 typedef struct ARMISARegisters ARMISARegisters;
748
749 /**
750 * ARMCPU:
751 * @env: #CPUARMState
752 *
753 * An ARM CPU core.
754 */
755 struct ARMCPU {
756 /*< private >*/
757 CPUState parent_obj;
758 /*< public >*/
759
760 CPUNegativeOffsetState neg;
761 CPUARMState env;
762
763 /* Coprocessor information */
764 GHashTable *cp_regs;
765 /* For marshalling (mostly coprocessor) register state between the
766 * kernel and QEMU (for KVM) and between two QEMUs (for migration),
767 * we use these arrays.
768 */
769 /* List of register indexes managed via these arrays; (full KVM style
770 * 64 bit indexes, not CPRegInfo 32 bit indexes)
771 */
772 uint64_t *cpreg_indexes;
773 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
774 uint64_t *cpreg_values;
775 /* Length of the indexes, values, reset_values arrays */
776 int32_t cpreg_array_len;
777 /* These are used only for migration: incoming data arrives in
778 * these fields and is sanity checked in post_load before copying
779 * to the working data structures above.
780 */
781 uint64_t *cpreg_vmstate_indexes;
782 uint64_t *cpreg_vmstate_values;
783 int32_t cpreg_vmstate_array_len;
784
785 DynamicGDBXMLInfo dyn_sysreg_xml;
786 DynamicGDBXMLInfo dyn_svereg_xml;
787
788 /* Timers used by the generic (architected) timer */
789 QEMUTimer *gt_timer[NUM_GTIMERS];
790 /*
791 * Timer used by the PMU. Its state is restored after migration by
792 * pmu_op_finish() - it does not need other handling during migration
793 */
794 QEMUTimer *pmu_timer;
795 /* GPIO outputs for generic timer */
796 qemu_irq gt_timer_outputs[NUM_GTIMERS];
797 /* GPIO output for GICv3 maintenance interrupt signal */
798 qemu_irq gicv3_maintenance_interrupt;
799 /* GPIO output for the PMU interrupt */
800 qemu_irq pmu_interrupt;
801
802 /* MemoryRegion to use for secure physical accesses */
803 MemoryRegion *secure_memory;
804
805 /* MemoryRegion to use for allocation tag accesses */
806 MemoryRegion *tag_memory;
807 MemoryRegion *secure_tag_memory;
808
809 /* For v8M, pointer to the IDAU interface provided by board/SoC */
810 Object *idau;
811
812 /* 'compatible' string for this CPU for Linux device trees */
813 const char *dtb_compatible;
814
815 /* PSCI version for this CPU
816 * Bits[31:16] = Major Version
817 * Bits[15:0] = Minor Version
818 */
819 uint32_t psci_version;
820
821 /* Current power state, access guarded by BQL */
822 ARMPSCIState power_state;
823
824 /* CPU has virtualization extension */
825 bool has_el2;
826 /* CPU has security extension */
827 bool has_el3;
828 /* CPU has PMU (Performance Monitor Unit) */
829 bool has_pmu;
830 /* CPU has VFP */
831 bool has_vfp;
832 /* CPU has Neon */
833 bool has_neon;
834 /* CPU has M-profile DSP extension */
835 bool has_dsp;
836
837 /* CPU has memory protection unit */
838 bool has_mpu;
839 /* PMSAv7 MPU number of supported regions */
840 uint32_t pmsav7_dregion;
841 /* v8M SAU number of supported regions */
842 uint32_t sau_sregion;
843
844 /* PSCI conduit used to invoke PSCI methods
845 * 0 - disabled, 1 - smc, 2 - hvc
846 */
847 uint32_t psci_conduit;
848
849 /* For v8M, initial value of the Secure VTOR */
850 uint32_t init_svtor;
851
852 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
853 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
854 */
855 uint32_t kvm_target;
856
857 /* KVM init features for this CPU */
858 uint32_t kvm_init_features[7];
859
860 /* KVM CPU state */
861
862 /* KVM virtual time adjustment */
863 bool kvm_adjvtime;
864 bool kvm_vtime_dirty;
865 uint64_t kvm_vtime;
866
867 /* KVM steal time */
868 OnOffAuto kvm_steal_time;
869
870 /* Uniprocessor system with MP extensions */
871 bool mp_is_up;
872
873 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init
874 * and the probe failed (so we need to report the error in realize)
875 */
876 bool host_cpu_probe_failed;
877
878 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
879 * register.
880 */
881 int32_t core_count;
882
883 /* The instance init functions for implementation-specific subclasses
884 * set these fields to specify the implementation-dependent values of
885 * various constant registers and reset values of non-constant
886 * registers.
887 * Some of these might become QOM properties eventually.
888 * Field names match the official register names as defined in the
889 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
890 * is used for reset values of non-constant registers; no reset_
891 * prefix means a constant register.
892 * Some of these registers are split out into a substructure that
893 * is shared with the translators to control the ISA.
894 *
895 * Note that if you add an ID register to the ARMISARegisters struct
896 * you need to also update the 32-bit and 64-bit versions of the
897 * kvm_arm_get_host_cpu_features() function to correctly populate the
898 * field by reading the value from the KVM vCPU.
899 */
900 struct ARMISARegisters {
901 uint32_t id_isar0;
902 uint32_t id_isar1;
903 uint32_t id_isar2;
904 uint32_t id_isar3;
905 uint32_t id_isar4;
906 uint32_t id_isar5;
907 uint32_t id_isar6;
908 uint32_t id_mmfr0;
909 uint32_t id_mmfr1;
910 uint32_t id_mmfr2;
911 uint32_t id_mmfr3;
912 uint32_t id_mmfr4;
913 uint32_t id_pfr0;
914 uint32_t id_pfr1;
915 uint32_t mvfr0;
916 uint32_t mvfr1;
917 uint32_t mvfr2;
918 uint32_t id_dfr0;
919 uint32_t dbgdidr;
920 uint64_t id_aa64isar0;
921 uint64_t id_aa64isar1;
922 uint64_t id_aa64pfr0;
923 uint64_t id_aa64pfr1;
924 uint64_t id_aa64mmfr0;
925 uint64_t id_aa64mmfr1;
926 uint64_t id_aa64mmfr2;
927 uint64_t id_aa64dfr0;
928 uint64_t id_aa64dfr1;
929 } isar;
930 uint64_t midr;
931 uint32_t revidr;
932 uint32_t reset_fpsid;
933 uint32_t ctr;
934 uint32_t reset_sctlr;
935 uint64_t pmceid0;
936 uint64_t pmceid1;
937 uint32_t id_afr0;
938 uint64_t id_aa64afr0;
939 uint64_t id_aa64afr1;
940 uint32_t clidr;
941 uint64_t mp_affinity; /* MP ID without feature bits */
942 /* The elements of this array are the CCSIDR values for each cache,
943 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
944 */
945 uint64_t ccsidr[16];
946 uint64_t reset_cbar;
947 uint32_t reset_auxcr;
948 bool reset_hivecs;
949 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
950 uint32_t dcz_blocksize;
951 uint64_t rvbar;
952
953 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
954 int gic_num_lrs; /* number of list registers */
955 int gic_vpribits; /* number of virtual priority bits */
956 int gic_vprebits; /* number of virtual preemption bits */
957
958 /* Whether the cfgend input is high (i.e. this CPU should reset into
959 * big-endian mode). This setting isn't used directly: instead it modifies
960 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
961 * architecture version.
962 */
963 bool cfgend;
964
965 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
966 QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
967
968 int32_t node_id; /* NUMA node this CPU belongs to */
969
970 /* Used to synchronize KVM and QEMU in-kernel device levels */
971 uint8_t device_irq_level;
972
973 /* Used to set the maximum vector length the cpu will support. */
974 uint32_t sve_max_vq;
975
976 /*
977 * In sve_vq_map each set bit is a supported vector length of
978 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector
979 * length in quadwords.
980 *
981 * While processing properties during initialization, corresponding
982 * sve_vq_init bits are set for bits in sve_vq_map that have been
983 * set by properties.
984 */
985 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ);
986 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ);
987
988 /* Generic timer counter frequency, in Hz */
989 uint64_t gt_cntfrq_hz;
990 };
991
992 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
993
994 void arm_cpu_post_init(Object *obj);
995
996 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
997
998 #ifndef CONFIG_USER_ONLY
999 extern const VMStateDescription vmstate_arm_cpu;
1000 #endif
1001
1002 void arm_cpu_do_interrupt(CPUState *cpu);
1003 void arm_v7m_cpu_do_interrupt(CPUState *cpu);
1004 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
1005
1006 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1007 MemTxAttrs *attrs);
1008
1009 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1010 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1011
1012 /*
1013 * Helpers to dynamically generates XML descriptions of the sysregs
1014 * and SVE registers. Returns the number of registers in each set.
1015 */
1016 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
1017 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
1018
1019 /* Returns the dynamically generated XML for the gdb stub.
1020 * Returns a pointer to the XML contents for the specified XML file or NULL
1021 * if the XML name doesn't match the predefined one.
1022 */
1023 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
1024
1025 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1026 int cpuid, void *opaque);
1027 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1028 int cpuid, void *opaque);
1029
1030 #ifdef TARGET_AARCH64
1031 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1032 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1033 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
1034 void aarch64_sve_change_el(CPUARMState *env, int old_el,
1035 int new_el, bool el0_a64);
1036 void aarch64_add_sve_properties(Object *obj);
1037
1038 /*
1039 * SVE registers are encoded in KVM's memory in an endianness-invariant format.
1040 * The byte at offset i from the start of the in-memory representation contains
1041 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
1042 * lowest offsets are stored in the lowest memory addresses, then that nearly
1043 * matches QEMU's representation, which is to use an array of host-endian
1044 * uint64_t's, where the lower offsets are at the lower indices. To complete
1045 * the translation we just need to byte swap the uint64_t's on big-endian hosts.
1046 */
1047 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
1048 {
1049 #ifdef HOST_WORDS_BIGENDIAN
1050 int i;
1051
1052 for (i = 0; i < nr; ++i) {
1053 dst[i] = bswap64(src[i]);
1054 }
1055
1056 return dst;
1057 #else
1058 return src;
1059 #endif
1060 }
1061
1062 #else
1063 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
1064 static inline void aarch64_sve_change_el(CPUARMState *env, int o,
1065 int n, bool a)
1066 { }
1067 static inline void aarch64_add_sve_properties(Object *obj) { }
1068 #endif
1069
1070 #if !defined(CONFIG_TCG)
1071 static inline target_ulong do_arm_semihosting(CPUARMState *env)
1072 {
1073 g_assert_not_reached();
1074 }
1075 #else
1076 target_ulong do_arm_semihosting(CPUARMState *env);
1077 #endif
1078 void aarch64_sync_32_to_64(CPUARMState *env);
1079 void aarch64_sync_64_to_32(CPUARMState *env);
1080
1081 int fp_exception_el(CPUARMState *env, int cur_el);
1082 int sve_exception_el(CPUARMState *env, int cur_el);
1083 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el);
1084
1085 static inline bool is_a64(CPUARMState *env)
1086 {
1087 return env->aarch64;
1088 }
1089
1090 /* you can call this signal handler from your SIGBUS and SIGSEGV
1091 signal handlers to inform the virtual CPU of exceptions. non zero
1092 is returned if the signal was handled by the virtual CPU. */
1093 int cpu_arm_signal_handler(int host_signum, void *pinfo,
1094 void *puc);
1095
1096 /**
1097 * pmu_op_start/finish
1098 * @env: CPUARMState
1099 *
1100 * Convert all PMU counters between their delta form (the typical mode when
1101 * they are enabled) and the guest-visible values. These two calls must
1102 * surround any action which might affect the counters.
1103 */
1104 void pmu_op_start(CPUARMState *env);
1105 void pmu_op_finish(CPUARMState *env);
1106
1107 /*
1108 * Called when a PMU counter is due to overflow
1109 */
1110 void arm_pmu_timer_cb(void *opaque);
1111
1112 /**
1113 * Functions to register as EL change hooks for PMU mode filtering
1114 */
1115 void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1116 void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1117
1118 /*
1119 * pmu_init
1120 * @cpu: ARMCPU
1121 *
1122 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state
1123 * for the current configuration
1124 */
1125 void pmu_init(ARMCPU *cpu);
1126
1127 /* SCTLR bit meanings. Several bits have been reused in newer
1128 * versions of the architecture; in that case we define constants
1129 * for both old and new bit meanings. Code which tests against those
1130 * bits should probably check or otherwise arrange that the CPU
1131 * is the architectural version it expects.
1132 */
1133 #define SCTLR_M (1U << 0)
1134 #define SCTLR_A (1U << 1)
1135 #define SCTLR_C (1U << 2)
1136 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
1137 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1138 #define SCTLR_SA (1U << 3) /* AArch64 only */
1139 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
1140 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
1141 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
1142 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
1143 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
1144 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
1145 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */
1146 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
1147 #define SCTLR_ITD (1U << 7) /* v8 onward */
1148 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
1149 #define SCTLR_SED (1U << 8) /* v8 onward */
1150 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
1151 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
1152 #define SCTLR_F (1U << 10) /* up to v6 */
1153 #define SCTLR_SW (1U << 10) /* v7 */
1154 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */
1155 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */
1156 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */
1157 #define SCTLR_I (1U << 12)
1158 #define SCTLR_V (1U << 13) /* AArch32 only */
1159 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */
1160 #define SCTLR_RR (1U << 14) /* up to v7 */
1161 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
1162 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
1163 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
1164 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
1165 #define SCTLR_nTWI (1U << 16) /* v8 onward */
1166 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */
1167 #define SCTLR_BR (1U << 17) /* PMSA only */
1168 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
1169 #define SCTLR_nTWE (1U << 18) /* v8 onward */
1170 #define SCTLR_WXN (1U << 19)
1171 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
1172 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */
1173 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */
1174 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
1175 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */
1176 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */
1177 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
1178 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */
1179 #define SCTLR_VE (1U << 24) /* up to v7 */
1180 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
1181 #define SCTLR_EE (1U << 25)
1182 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
1183 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
1184 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */
1185 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */
1186 #define SCTLR_TRE (1U << 28) /* AArch32 only */
1187 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
1188 #define SCTLR_AFE (1U << 29) /* AArch32 only */
1189 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
1190 #define SCTLR_TE (1U << 30) /* AArch32 only */
1191 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */
1192 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */
1193 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
1194 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
1195 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
1196 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */
1197 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */
1198 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
1199 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
1200 #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */
1201
1202 #define CPTR_TCPAC (1U << 31)
1203 #define CPTR_TTA (1U << 20)
1204 #define CPTR_TFP (1U << 10)
1205 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */
1206 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */
1207
1208 #define MDCR_EPMAD (1U << 21)
1209 #define MDCR_EDAD (1U << 20)
1210 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */
1211 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
1212 #define MDCR_SDD (1U << 16)
1213 #define MDCR_SPD (3U << 14)
1214 #define MDCR_TDRA (1U << 11)
1215 #define MDCR_TDOSA (1U << 10)
1216 #define MDCR_TDA (1U << 9)
1217 #define MDCR_TDE (1U << 8)
1218 #define MDCR_HPME (1U << 7)
1219 #define MDCR_TPM (1U << 6)
1220 #define MDCR_TPMCR (1U << 5)
1221 #define MDCR_HPMN (0x1fU)
1222
1223 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
1224 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
1225
1226 #define CPSR_M (0x1fU)
1227 #define CPSR_T (1U << 5)
1228 #define CPSR_F (1U << 6)
1229 #define CPSR_I (1U << 7)
1230 #define CPSR_A (1U << 8)
1231 #define CPSR_E (1U << 9)
1232 #define CPSR_IT_2_7 (0xfc00U)
1233 #define CPSR_GE (0xfU << 16)
1234 #define CPSR_IL (1U << 20)
1235 #define CPSR_PAN (1U << 22)
1236 #define CPSR_J (1U << 24)
1237 #define CPSR_IT_0_1 (3U << 25)
1238 #define CPSR_Q (1U << 27)
1239 #define CPSR_V (1U << 28)
1240 #define CPSR_C (1U << 29)
1241 #define CPSR_Z (1U << 30)
1242 #define CPSR_N (1U << 31)
1243 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1244 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1245
1246 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1247 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1248 | CPSR_NZCV)
1249 /* Bits writable in user mode. */
1250 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1251 /* Execution state bits. MRS read as zero, MSR writes ignored. */
1252 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1253
1254 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */
1255 #define XPSR_EXCP 0x1ffU
1256 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */
1257 #define XPSR_IT_2_7 CPSR_IT_2_7
1258 #define XPSR_GE CPSR_GE
1259 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */
1260 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */
1261 #define XPSR_IT_0_1 CPSR_IT_0_1
1262 #define XPSR_Q CPSR_Q
1263 #define XPSR_V CPSR_V
1264 #define XPSR_C CPSR_C
1265 #define XPSR_Z CPSR_Z
1266 #define XPSR_N CPSR_N
1267 #define XPSR_NZCV CPSR_NZCV
1268 #define XPSR_IT CPSR_IT
1269
1270 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
1271 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
1272 #define TTBCR_PD0 (1U << 4)
1273 #define TTBCR_PD1 (1U << 5)
1274 #define TTBCR_EPD0 (1U << 7)
1275 #define TTBCR_IRGN0 (3U << 8)
1276 #define TTBCR_ORGN0 (3U << 10)
1277 #define TTBCR_SH0 (3U << 12)
1278 #define TTBCR_T1SZ (3U << 16)
1279 #define TTBCR_A1 (1U << 22)
1280 #define TTBCR_EPD1 (1U << 23)
1281 #define TTBCR_IRGN1 (3U << 24)
1282 #define TTBCR_ORGN1 (3U << 26)
1283 #define TTBCR_SH1 (1U << 28)
1284 #define TTBCR_EAE (1U << 31)
1285
1286 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
1287 * Only these are valid when in AArch64 mode; in
1288 * AArch32 mode SPSRs are basically CPSR-format.
1289 */
1290 #define PSTATE_SP (1U)
1291 #define PSTATE_M (0xFU)
1292 #define PSTATE_nRW (1U << 4)
1293 #define PSTATE_F (1U << 6)
1294 #define PSTATE_I (1U << 7)
1295 #define PSTATE_A (1U << 8)
1296 #define PSTATE_D (1U << 9)
1297 #define PSTATE_BTYPE (3U << 10)
1298 #define PSTATE_IL (1U << 20)
1299 #define PSTATE_SS (1U << 21)
1300 #define PSTATE_PAN (1U << 22)
1301 #define PSTATE_UAO (1U << 23)
1302 #define PSTATE_TCO (1U << 25)
1303 #define PSTATE_V (1U << 28)
1304 #define PSTATE_C (1U << 29)
1305 #define PSTATE_Z (1U << 30)
1306 #define PSTATE_N (1U << 31)
1307 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1308 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1309 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1310 /* Mode values for AArch64 */
1311 #define PSTATE_MODE_EL3h 13
1312 #define PSTATE_MODE_EL3t 12
1313 #define PSTATE_MODE_EL2h 9
1314 #define PSTATE_MODE_EL2t 8
1315 #define PSTATE_MODE_EL1h 5
1316 #define PSTATE_MODE_EL1t 4
1317 #define PSTATE_MODE_EL0t 0
1318
1319 /* Write a new value to v7m.exception, thus transitioning into or out
1320 * of Handler mode; this may result in a change of active stack pointer.
1321 */
1322 void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1323
1324 /* Map EL and handler into a PSTATE_MODE. */
1325 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1326 {
1327 return (el << 2) | handler;
1328 }
1329
1330 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1331 * interprocessing, so we don't attempt to sync with the cpsr state used by
1332 * the 32 bit decoder.
1333 */
1334 static inline uint32_t pstate_read(CPUARMState *env)
1335 {
1336 int ZF;
1337
1338 ZF = (env->ZF == 0);
1339 return (env->NF & 0x80000000) | (ZF << 30)
1340 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1341 | env->pstate | env->daif | (env->btype << 10);
1342 }
1343
1344 static inline void pstate_write(CPUARMState *env, uint32_t val)
1345 {
1346 env->ZF = (~val) & PSTATE_Z;
1347 env->NF = val;
1348 env->CF = (val >> 29) & 1;
1349 env->VF = (val << 3) & 0x80000000;
1350 env->daif = val & PSTATE_DAIF;
1351 env->btype = (val >> 10) & 3;
1352 env->pstate = val & ~CACHED_PSTATE_BITS;
1353 }
1354
1355 /* Return the current CPSR value. */
1356 uint32_t cpsr_read(CPUARMState *env);
1357
1358 typedef enum CPSRWriteType {
1359 CPSRWriteByInstr = 0, /* from guest MSR or CPS */
1360 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
1361 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */
1362 CPSRWriteByGDBStub = 3, /* from the GDB stub */
1363 } CPSRWriteType;
1364
1365 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/
1366 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1367 CPSRWriteType write_type);
1368
1369 /* Return the current xPSR value. */
1370 static inline uint32_t xpsr_read(CPUARMState *env)
1371 {
1372 int ZF;
1373 ZF = (env->ZF == 0);
1374 return (env->NF & 0x80000000) | (ZF << 30)
1375 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1376 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1377 | ((env->condexec_bits & 0xfc) << 8)
1378 | (env->GE << 16)
1379 | env->v7m.exception;
1380 }
1381
1382 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
1383 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1384 {
1385 if (mask & XPSR_NZCV) {
1386 env->ZF = (~val) & XPSR_Z;
1387 env->NF = val;
1388 env->CF = (val >> 29) & 1;
1389 env->VF = (val << 3) & 0x80000000;
1390 }
1391 if (mask & XPSR_Q) {
1392 env->QF = ((val & XPSR_Q) != 0);
1393 }
1394 if (mask & XPSR_GE) {
1395 env->GE = (val & XPSR_GE) >> 16;
1396 }
1397 #ifndef CONFIG_USER_ONLY
1398 if (mask & XPSR_T) {
1399 env->thumb = ((val & XPSR_T) != 0);
1400 }
1401 if (mask & XPSR_IT_0_1) {
1402 env->condexec_bits &= ~3;
1403 env->condexec_bits |= (val >> 25) & 3;
1404 }
1405 if (mask & XPSR_IT_2_7) {
1406 env->condexec_bits &= 3;
1407 env->condexec_bits |= (val >> 8) & 0xfc;
1408 }
1409 if (mask & XPSR_EXCP) {
1410 /* Note that this only happens on exception exit */
1411 write_v7m_exception(env, val & XPSR_EXCP);
1412 }
1413 #endif
1414 }
1415
1416 #define HCR_VM (1ULL << 0)
1417 #define HCR_SWIO (1ULL << 1)
1418 #define HCR_PTW (1ULL << 2)
1419 #define HCR_FMO (1ULL << 3)
1420 #define HCR_IMO (1ULL << 4)
1421 #define HCR_AMO (1ULL << 5)
1422 #define HCR_VF (1ULL << 6)
1423 #define HCR_VI (1ULL << 7)
1424 #define HCR_VSE (1ULL << 8)
1425 #define HCR_FB (1ULL << 9)
1426 #define HCR_BSU_MASK (3ULL << 10)
1427 #define HCR_DC (1ULL << 12)
1428 #define HCR_TWI (1ULL << 13)
1429 #define HCR_TWE (1ULL << 14)
1430 #define HCR_TID0 (1ULL << 15)
1431 #define HCR_TID1 (1ULL << 16)
1432 #define HCR_TID2 (1ULL << 17)
1433 #define HCR_TID3 (1ULL << 18)
1434 #define HCR_TSC (1ULL << 19)
1435 #define HCR_TIDCP (1ULL << 20)
1436 #define HCR_TACR (1ULL << 21)
1437 #define HCR_TSW (1ULL << 22)
1438 #define HCR_TPCP (1ULL << 23)
1439 #define HCR_TPU (1ULL << 24)
1440 #define HCR_TTLB (1ULL << 25)
1441 #define HCR_TVM (1ULL << 26)
1442 #define HCR_TGE (1ULL << 27)
1443 #define HCR_TDZ (1ULL << 28)
1444 #define HCR_HCD (1ULL << 29)
1445 #define HCR_TRVM (1ULL << 30)
1446 #define HCR_RW (1ULL << 31)
1447 #define HCR_CD (1ULL << 32)
1448 #define HCR_ID (1ULL << 33)
1449 #define HCR_E2H (1ULL << 34)
1450 #define HCR_TLOR (1ULL << 35)
1451 #define HCR_TERR (1ULL << 36)
1452 #define HCR_TEA (1ULL << 37)
1453 #define HCR_MIOCNCE (1ULL << 38)
1454 /* RES0 bit 39 */
1455 #define HCR_APK (1ULL << 40)
1456 #define HCR_API (1ULL << 41)
1457 #define HCR_NV (1ULL << 42)
1458 #define HCR_NV1 (1ULL << 43)
1459 #define HCR_AT (1ULL << 44)
1460 #define HCR_NV2 (1ULL << 45)
1461 #define HCR_FWB (1ULL << 46)
1462 #define HCR_FIEN (1ULL << 47)
1463 /* RES0 bit 48 */
1464 #define HCR_TID4 (1ULL << 49)
1465 #define HCR_TICAB (1ULL << 50)
1466 #define HCR_AMVOFFEN (1ULL << 51)
1467 #define HCR_TOCU (1ULL << 52)
1468 #define HCR_ENSCXT (1ULL << 53)
1469 #define HCR_TTLBIS (1ULL << 54)
1470 #define HCR_TTLBOS (1ULL << 55)
1471 #define HCR_ATA (1ULL << 56)
1472 #define HCR_DCT (1ULL << 57)
1473 #define HCR_TID5 (1ULL << 58)
1474 #define HCR_TWEDEN (1ULL << 59)
1475 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
1476
1477 #define SCR_NS (1U << 0)
1478 #define SCR_IRQ (1U << 1)
1479 #define SCR_FIQ (1U << 2)
1480 #define SCR_EA (1U << 3)
1481 #define SCR_FW (1U << 4)
1482 #define SCR_AW (1U << 5)
1483 #define SCR_NET (1U << 6)
1484 #define SCR_SMD (1U << 7)
1485 #define SCR_HCE (1U << 8)
1486 #define SCR_SIF (1U << 9)
1487 #define SCR_RW (1U << 10)
1488 #define SCR_ST (1U << 11)
1489 #define SCR_TWI (1U << 12)
1490 #define SCR_TWE (1U << 13)
1491 #define SCR_TLOR (1U << 14)
1492 #define SCR_TERR (1U << 15)
1493 #define SCR_APK (1U << 16)
1494 #define SCR_API (1U << 17)
1495 #define SCR_EEL2 (1U << 18)
1496 #define SCR_EASE (1U << 19)
1497 #define SCR_NMEA (1U << 20)
1498 #define SCR_FIEN (1U << 21)
1499 #define SCR_ENSCXT (1U << 25)
1500 #define SCR_ATA (1U << 26)
1501
1502 /* Return the current FPSCR value. */
1503 uint32_t vfp_get_fpscr(CPUARMState *env);
1504 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1505
1506 /* FPCR, Floating Point Control Register
1507 * FPSR, Floating Poiht Status Register
1508 *
1509 * For A64 the FPSCR is split into two logically distinct registers,
1510 * FPCR and FPSR. However since they still use non-overlapping bits
1511 * we store the underlying state in fpscr and just mask on read/write.
1512 */
1513 #define FPSR_MASK 0xf800009f
1514 #define FPCR_MASK 0x07ff9f00
1515
1516 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */
1517 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */
1518 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */
1519 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */
1520 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */
1521 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */
1522 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
1523 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
1524 #define FPCR_DN (1 << 25) /* Default NaN enable bit */
1525 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */
1526
1527 static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1528 {
1529 return vfp_get_fpscr(env) & FPSR_MASK;
1530 }
1531
1532 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1533 {
1534 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1535 vfp_set_fpscr(env, new_fpscr);
1536 }
1537
1538 static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1539 {
1540 return vfp_get_fpscr(env) & FPCR_MASK;
1541 }
1542
1543 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1544 {
1545 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1546 vfp_set_fpscr(env, new_fpscr);
1547 }
1548
1549 enum arm_cpu_mode {
1550 ARM_CPU_MODE_USR = 0x10,
1551 ARM_CPU_MODE_FIQ = 0x11,
1552 ARM_CPU_MODE_IRQ = 0x12,
1553 ARM_CPU_MODE_SVC = 0x13,
1554 ARM_CPU_MODE_MON = 0x16,
1555 ARM_CPU_MODE_ABT = 0x17,
1556 ARM_CPU_MODE_HYP = 0x1a,
1557 ARM_CPU_MODE_UND = 0x1b,
1558 ARM_CPU_MODE_SYS = 0x1f
1559 };
1560
1561 /* VFP system registers. */
1562 #define ARM_VFP_FPSID 0
1563 #define ARM_VFP_FPSCR 1
1564 #define ARM_VFP_MVFR2 5
1565 #define ARM_VFP_MVFR1 6
1566 #define ARM_VFP_MVFR0 7
1567 #define ARM_VFP_FPEXC 8
1568 #define ARM_VFP_FPINST 9
1569 #define ARM_VFP_FPINST2 10
1570
1571 /* iwMMXt coprocessor control registers. */
1572 #define ARM_IWMMXT_wCID 0
1573 #define ARM_IWMMXT_wCon 1
1574 #define ARM_IWMMXT_wCSSF 2
1575 #define ARM_IWMMXT_wCASF 3
1576 #define ARM_IWMMXT_wCGR0 8
1577 #define ARM_IWMMXT_wCGR1 9
1578 #define ARM_IWMMXT_wCGR2 10
1579 #define ARM_IWMMXT_wCGR3 11
1580
1581 /* V7M CCR bits */
1582 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1583 FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1584 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1585 FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1586 FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1587 FIELD(V7M_CCR, STKALIGN, 9, 1)
1588 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1589 FIELD(V7M_CCR, DC, 16, 1)
1590 FIELD(V7M_CCR, IC, 17, 1)
1591 FIELD(V7M_CCR, BP, 18, 1)
1592
1593 /* V7M SCR bits */
1594 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1595 FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1596 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1597 FIELD(V7M_SCR, SEVONPEND, 4, 1)
1598
1599 /* V7M AIRCR bits */
1600 FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1601 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1602 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1603 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1604 FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1605 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1606 FIELD(V7M_AIRCR, PRIS, 14, 1)
1607 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1608 FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1609
1610 /* V7M CFSR bits for MMFSR */
1611 FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1612 FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1613 FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1614 FIELD(V7M_CFSR, MSTKERR, 4, 1)
1615 FIELD(V7M_CFSR, MLSPERR, 5, 1)
1616 FIELD(V7M_CFSR, MMARVALID, 7, 1)
1617
1618 /* V7M CFSR bits for BFSR */
1619 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1620 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1621 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1622 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1623 FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1624 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1625 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1626
1627 /* V7M CFSR bits for UFSR */
1628 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1629 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1630 FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1631 FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1632 FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1633 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1634 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1635
1636 /* V7M CFSR bit masks covering all of the subregister bits */
1637 FIELD(V7M_CFSR, MMFSR, 0, 8)
1638 FIELD(V7M_CFSR, BFSR, 8, 8)
1639 FIELD(V7M_CFSR, UFSR, 16, 16)
1640
1641 /* V7M HFSR bits */
1642 FIELD(V7M_HFSR, VECTTBL, 1, 1)
1643 FIELD(V7M_HFSR, FORCED, 30, 1)
1644 FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1645
1646 /* V7M DFSR bits */
1647 FIELD(V7M_DFSR, HALTED, 0, 1)
1648 FIELD(V7M_DFSR, BKPT, 1, 1)
1649 FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1650 FIELD(V7M_DFSR, VCATCH, 3, 1)
1651 FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1652
1653 /* V7M SFSR bits */
1654 FIELD(V7M_SFSR, INVEP, 0, 1)
1655 FIELD(V7M_SFSR, INVIS, 1, 1)
1656 FIELD(V7M_SFSR, INVER, 2, 1)
1657 FIELD(V7M_SFSR, AUVIOL, 3, 1)
1658 FIELD(V7M_SFSR, INVTRAN, 4, 1)
1659 FIELD(V7M_SFSR, LSPERR, 5, 1)
1660 FIELD(V7M_SFSR, SFARVALID, 6, 1)
1661 FIELD(V7M_SFSR, LSERR, 7, 1)
1662
1663 /* v7M MPU_CTRL bits */
1664 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1665 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1666 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1667
1668 /* v7M CLIDR bits */
1669 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1670 FIELD(V7M_CLIDR, LOUIS, 21, 3)
1671 FIELD(V7M_CLIDR, LOC, 24, 3)
1672 FIELD(V7M_CLIDR, LOUU, 27, 3)
1673 FIELD(V7M_CLIDR, ICB, 30, 2)
1674
1675 FIELD(V7M_CSSELR, IND, 0, 1)
1676 FIELD(V7M_CSSELR, LEVEL, 1, 3)
1677 /* We use the combination of InD and Level to index into cpu->ccsidr[];
1678 * define a mask for this and check that it doesn't permit running off
1679 * the end of the array.
1680 */
1681 FIELD(V7M_CSSELR, INDEX, 0, 4)
1682
1683 /* v7M FPCCR bits */
1684 FIELD(V7M_FPCCR, LSPACT, 0, 1)
1685 FIELD(V7M_FPCCR, USER, 1, 1)
1686 FIELD(V7M_FPCCR, S, 2, 1)
1687 FIELD(V7M_FPCCR, THREAD, 3, 1)
1688 FIELD(V7M_FPCCR, HFRDY, 4, 1)
1689 FIELD(V7M_FPCCR, MMRDY, 5, 1)
1690 FIELD(V7M_FPCCR, BFRDY, 6, 1)
1691 FIELD(V7M_FPCCR, SFRDY, 7, 1)
1692 FIELD(V7M_FPCCR, MONRDY, 8, 1)
1693 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1694 FIELD(V7M_FPCCR, UFRDY, 10, 1)
1695 FIELD(V7M_FPCCR, RES0, 11, 15)
1696 FIELD(V7M_FPCCR, TS, 26, 1)
1697 FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1698 FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1699 FIELD(V7M_FPCCR, LSPENS, 29, 1)
1700 FIELD(V7M_FPCCR, LSPEN, 30, 1)
1701 FIELD(V7M_FPCCR, ASPEN, 31, 1)
1702 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */
1703 #define R_V7M_FPCCR_BANKED_MASK \
1704 (R_V7M_FPCCR_LSPACT_MASK | \
1705 R_V7M_FPCCR_USER_MASK | \
1706 R_V7M_FPCCR_THREAD_MASK | \
1707 R_V7M_FPCCR_MMRDY_MASK | \
1708 R_V7M_FPCCR_SPLIMVIOL_MASK | \
1709 R_V7M_FPCCR_UFRDY_MASK | \
1710 R_V7M_FPCCR_ASPEN_MASK)
1711
1712 /*
1713 * System register ID fields.
1714 */
1715 FIELD(MIDR_EL1, REVISION, 0, 4)
1716 FIELD(MIDR_EL1, PARTNUM, 4, 12)
1717 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
1718 FIELD(MIDR_EL1, VARIANT, 20, 4)
1719 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
1720
1721 FIELD(ID_ISAR0, SWAP, 0, 4)
1722 FIELD(ID_ISAR0, BITCOUNT, 4, 4)
1723 FIELD(ID_ISAR0, BITFIELD, 8, 4)
1724 FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
1725 FIELD(ID_ISAR0, COPROC, 16, 4)
1726 FIELD(ID_ISAR0, DEBUG, 20, 4)
1727 FIELD(ID_ISAR0, DIVIDE, 24, 4)
1728
1729 FIELD(ID_ISAR1, ENDIAN, 0, 4)
1730 FIELD(ID_ISAR1, EXCEPT, 4, 4)
1731 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
1732 FIELD(ID_ISAR1, EXTEND, 12, 4)
1733 FIELD(ID_ISAR1, IFTHEN, 16, 4)
1734 FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
1735 FIELD(ID_ISAR1, INTERWORK, 24, 4)
1736 FIELD(ID_ISAR1, JAZELLE, 28, 4)
1737
1738 FIELD(ID_ISAR2, LOADSTORE, 0, 4)
1739 FIELD(ID_ISAR2, MEMHINT, 4, 4)
1740 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
1741 FIELD(ID_ISAR2, MULT, 12, 4)
1742 FIELD(ID_ISAR2, MULTS, 16, 4)
1743 FIELD(ID_ISAR2, MULTU, 20, 4)
1744 FIELD(ID_ISAR2, PSR_AR, 24, 4)
1745 FIELD(ID_ISAR2, REVERSAL, 28, 4)
1746
1747 FIELD(ID_ISAR3, SATURATE, 0, 4)
1748 FIELD(ID_ISAR3, SIMD, 4, 4)
1749 FIELD(ID_ISAR3, SVC, 8, 4)
1750 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
1751 FIELD(ID_ISAR3, TABBRANCH, 16, 4)
1752 FIELD(ID_ISAR3, T32COPY, 20, 4)
1753 FIELD(ID_ISAR3, TRUENOP, 24, 4)
1754 FIELD(ID_ISAR3, T32EE, 28, 4)
1755
1756 FIELD(ID_ISAR4, UNPRIV, 0, 4)
1757 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
1758 FIELD(ID_ISAR4, WRITEBACK, 8, 4)
1759 FIELD(ID_ISAR4, SMC, 12, 4)
1760 FIELD(ID_ISAR4, BARRIER, 16, 4)
1761 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
1762 FIELD(ID_ISAR4, PSR_M, 24, 4)
1763 FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
1764
1765 FIELD(ID_ISAR5, SEVL, 0, 4)
1766 FIELD(ID_ISAR5, AES, 4, 4)
1767 FIELD(ID_ISAR5, SHA1, 8, 4)
1768 FIELD(ID_ISAR5, SHA2, 12, 4)
1769 FIELD(ID_ISAR5, CRC32, 16, 4)
1770 FIELD(ID_ISAR5, RDM, 24, 4)
1771 FIELD(ID_ISAR5, VCMA, 28, 4)
1772
1773 FIELD(ID_ISAR6, JSCVT, 0, 4)
1774 FIELD(ID_ISAR6, DP, 4, 4)
1775 FIELD(ID_ISAR6, FHM, 8, 4)
1776 FIELD(ID_ISAR6, SB, 12, 4)
1777 FIELD(ID_ISAR6, SPECRES, 16, 4)
1778
1779 FIELD(ID_MMFR0, VMSA, 0, 4)
1780 FIELD(ID_MMFR0, PMSA, 4, 4)
1781 FIELD(ID_MMFR0, OUTERSHR, 8, 4)
1782 FIELD(ID_MMFR0, SHARELVL, 12, 4)
1783 FIELD(ID_MMFR0, TCM, 16, 4)
1784 FIELD(ID_MMFR0, AUXREG, 20, 4)
1785 FIELD(ID_MMFR0, FCSE, 24, 4)
1786 FIELD(ID_MMFR0, INNERSHR, 28, 4)
1787
1788 FIELD(ID_MMFR3, CMAINTVA, 0, 4)
1789 FIELD(ID_MMFR3, CMAINTSW, 4, 4)
1790 FIELD(ID_MMFR3, BPMAINT, 8, 4)
1791 FIELD(ID_MMFR3, MAINTBCST, 12, 4)
1792 FIELD(ID_MMFR3, PAN, 16, 4)
1793 FIELD(ID_MMFR3, COHWALK, 20, 4)
1794 FIELD(ID_MMFR3, CMEMSZ, 24, 4)
1795 FIELD(ID_MMFR3, SUPERSEC, 28, 4)
1796
1797 FIELD(ID_MMFR4, SPECSEI, 0, 4)
1798 FIELD(ID_MMFR4, AC2, 4, 4)
1799 FIELD(ID_MMFR4, XNX, 8, 4)
1800 FIELD(ID_MMFR4, CNP, 12, 4)
1801 FIELD(ID_MMFR4, HPDS, 16, 4)
1802 FIELD(ID_MMFR4, LSM, 20, 4)
1803 FIELD(ID_MMFR4, CCIDX, 24, 4)
1804 FIELD(ID_MMFR4, EVT, 28, 4)
1805
1806 FIELD(ID_PFR1, PROGMOD, 0, 4)
1807 FIELD(ID_PFR1, SECURITY, 4, 4)
1808 FIELD(ID_PFR1, MPROGMOD, 8, 4)
1809 FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
1810 FIELD(ID_PFR1, GENTIMER, 16, 4)
1811 FIELD(ID_PFR1, SEC_FRAC, 20, 4)
1812 FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
1813 FIELD(ID_PFR1, GIC, 28, 4)
1814
1815 FIELD(ID_AA64ISAR0, AES, 4, 4)
1816 FIELD(ID_AA64ISAR0, SHA1, 8, 4)
1817 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
1818 FIELD(ID_AA64ISAR0, CRC32, 16, 4)
1819 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
1820 FIELD(ID_AA64ISAR0, RDM, 28, 4)
1821 FIELD(ID_AA64ISAR0, SHA3, 32, 4)
1822 FIELD(ID_AA64ISAR0, SM3, 36, 4)
1823 FIELD(ID_AA64ISAR0, SM4, 40, 4)
1824 FIELD(ID_AA64ISAR0, DP, 44, 4)
1825 FIELD(ID_AA64ISAR0, FHM, 48, 4)
1826 FIELD(ID_AA64ISAR0, TS, 52, 4)
1827 FIELD(ID_AA64ISAR0, TLB, 56, 4)
1828 FIELD(ID_AA64ISAR0, RNDR, 60, 4)
1829
1830 FIELD(ID_AA64ISAR1, DPB, 0, 4)
1831 FIELD(ID_AA64ISAR1, APA, 4, 4)
1832 FIELD(ID_AA64ISAR1, API, 8, 4)
1833 FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
1834 FIELD(ID_AA64ISAR1, FCMA, 16, 4)
1835 FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
1836 FIELD(ID_AA64ISAR1, GPA, 24, 4)
1837 FIELD(ID_AA64ISAR1, GPI, 28, 4)
1838 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
1839 FIELD(ID_AA64ISAR1, SB, 36, 4)
1840 FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
1841
1842 FIELD(ID_AA64PFR0, EL0, 0, 4)
1843 FIELD(ID_AA64PFR0, EL1, 4, 4)
1844 FIELD(ID_AA64PFR0, EL2, 8, 4)
1845 FIELD(ID_AA64PFR0, EL3, 12, 4)
1846 FIELD(ID_AA64PFR0, FP, 16, 4)
1847 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
1848 FIELD(ID_AA64PFR0, GIC, 24, 4)
1849 FIELD(ID_AA64PFR0, RAS, 28, 4)
1850 FIELD(ID_AA64PFR0, SVE, 32, 4)
1851
1852 FIELD(ID_AA64PFR1, BT, 0, 4)
1853 FIELD(ID_AA64PFR1, SBSS, 4, 4)
1854 FIELD(ID_AA64PFR1, MTE, 8, 4)
1855 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
1856
1857 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
1858 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
1859 FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
1860 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
1861 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
1862 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
1863 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
1864 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
1865 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
1866 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
1867 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
1868 FIELD(ID_AA64MMFR0, EXS, 44, 4)
1869
1870 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
1871 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
1872 FIELD(ID_AA64MMFR1, VH, 8, 4)
1873 FIELD(ID_AA64MMFR1, HPDS, 12, 4)
1874 FIELD(ID_AA64MMFR1, LO, 16, 4)
1875 FIELD(ID_AA64MMFR1, PAN, 20, 4)
1876 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
1877 FIELD(ID_AA64MMFR1, XNX, 28, 4)
1878
1879 FIELD(ID_AA64MMFR2, CNP, 0, 4)
1880 FIELD(ID_AA64MMFR2, UAO, 4, 4)
1881 FIELD(ID_AA64MMFR2, LSM, 8, 4)
1882 FIELD(ID_AA64MMFR2, IESB, 12, 4)
1883 FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
1884 FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
1885 FIELD(ID_AA64MMFR2, NV, 24, 4)
1886 FIELD(ID_AA64MMFR2, ST, 28, 4)
1887 FIELD(ID_AA64MMFR2, AT, 32, 4)
1888 FIELD(ID_AA64MMFR2, IDS, 36, 4)
1889 FIELD(ID_AA64MMFR2, FWB, 40, 4)
1890 FIELD(ID_AA64MMFR2, TTL, 48, 4)
1891 FIELD(ID_AA64MMFR2, BBM, 52, 4)
1892 FIELD(ID_AA64MMFR2, EVT, 56, 4)
1893 FIELD(ID_AA64MMFR2, E0PD, 60, 4)
1894
1895 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
1896 FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
1897 FIELD(ID_AA64DFR0, PMUVER, 8, 4)
1898 FIELD(ID_AA64DFR0, BRPS, 12, 4)
1899 FIELD(ID_AA64DFR0, WRPS, 20, 4)
1900 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
1901 FIELD(ID_AA64DFR0, PMSVER, 32, 4)
1902 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
1903 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
1904
1905 FIELD(ID_DFR0, COPDBG, 0, 4)
1906 FIELD(ID_DFR0, COPSDBG, 4, 4)
1907 FIELD(ID_DFR0, MMAPDBG, 8, 4)
1908 FIELD(ID_DFR0, COPTRC, 12, 4)
1909 FIELD(ID_DFR0, MMAPTRC, 16, 4)
1910 FIELD(ID_DFR0, MPROFDBG, 20, 4)
1911 FIELD(ID_DFR0, PERFMON, 24, 4)
1912 FIELD(ID_DFR0, TRACEFILT, 28, 4)
1913
1914 FIELD(DBGDIDR, SE_IMP, 12, 1)
1915 FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
1916 FIELD(DBGDIDR, VERSION, 16, 4)
1917 FIELD(DBGDIDR, CTX_CMPS, 20, 4)
1918 FIELD(DBGDIDR, BRPS, 24, 4)
1919 FIELD(DBGDIDR, WRPS, 28, 4)
1920
1921 FIELD(MVFR0, SIMDREG, 0, 4)
1922 FIELD(MVFR0, FPSP, 4, 4)
1923 FIELD(MVFR0, FPDP, 8, 4)
1924 FIELD(MVFR0, FPTRAP, 12, 4)
1925 FIELD(MVFR0, FPDIVIDE, 16, 4)
1926 FIELD(MVFR0, FPSQRT, 20, 4)
1927 FIELD(MVFR0, FPSHVEC, 24, 4)
1928 FIELD(MVFR0, FPROUND, 28, 4)
1929
1930 FIELD(MVFR1, FPFTZ, 0, 4)
1931 FIELD(MVFR1, FPDNAN, 4, 4)
1932 FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
1933 FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
1934 FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
1935 FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
1936 FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
1937 FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
1938 FIELD(MVFR1, FPHP, 24, 4)
1939 FIELD(MVFR1, SIMDFMAC, 28, 4)
1940
1941 FIELD(MVFR2, SIMDMISC, 0, 4)
1942 FIELD(MVFR2, FPMISC, 4, 4)
1943
1944 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
1945
1946 /* If adding a feature bit which corresponds to a Linux ELF
1947 * HWCAP bit, remember to update the feature-bit-to-hwcap
1948 * mapping in linux-user/elfload.c:get_elf_hwcap().
1949 */
1950 enum arm_features {
1951 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
1952 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
1953 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
1954 ARM_FEATURE_V6,
1955 ARM_FEATURE_V6K,
1956 ARM_FEATURE_V7,
1957 ARM_FEATURE_THUMB2,
1958 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */
1959 ARM_FEATURE_NEON,
1960 ARM_FEATURE_M, /* Microcontroller profile. */
1961 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
1962 ARM_FEATURE_THUMB2EE,
1963 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
1964 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
1965 ARM_FEATURE_V4T,
1966 ARM_FEATURE_V5,
1967 ARM_FEATURE_STRONGARM,
1968 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
1969 ARM_FEATURE_GENERIC_TIMER,
1970 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
1971 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
1972 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
1973 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
1974 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
1975 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
1976 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
1977 ARM_FEATURE_V8,
1978 ARM_FEATURE_AARCH64, /* supports 64 bit mode */
1979 ARM_FEATURE_CBAR, /* has cp15 CBAR */
1980 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
1981 ARM_FEATURE_EL2, /* has EL2 Virtualization support */
1982 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
1983 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
1984 ARM_FEATURE_PMU, /* has PMU support */
1985 ARM_FEATURE_VBAR, /* has cp15 VBAR */
1986 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
1987 ARM_FEATURE_M_MAIN, /* M profile Main Extension */
1988 ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
1989 };
1990
1991 static inline int arm_feature(CPUARMState *env, int feature)
1992 {
1993 return (env->features & (1ULL << feature)) != 0;
1994 }
1995
1996 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
1997
1998 #if !defined(CONFIG_USER_ONLY)
1999 /* Return true if exception levels below EL3 are in secure state,
2000 * or would be following an exception return to that level.
2001 * Unlike arm_is_secure() (which is always a question about the
2002 * _current_ state of the CPU) this doesn't care about the current
2003 * EL or mode.
2004 */
2005 static inline bool arm_is_secure_below_el3(CPUARMState *env)
2006 {
2007 if (arm_feature(env, ARM_FEATURE_EL3)) {
2008 return !(env->cp15.scr_el3 & SCR_NS);
2009 } else {
2010 /* If EL3 is not supported then the secure state is implementation
2011 * defined, in which case QEMU defaults to non-secure.
2012 */
2013 return false;
2014 }
2015 }
2016
2017 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
2018 static inline bool arm_is_el3_or_mon(CPUARMState *env)
2019 {
2020 if (arm_feature(env, ARM_FEATURE_EL3)) {
2021 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
2022 /* CPU currently in AArch64 state and EL3 */
2023 return true;
2024 } else if (!is_a64(env) &&
2025 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
2026 /* CPU currently in AArch32 state and monitor mode */
2027 return true;
2028 }
2029 }
2030 return false;
2031 }
2032
2033 /* Return true if the processor is in secure state */
2034 static inline bool arm_is_secure(CPUARMState *env)
2035 {
2036 if (arm_is_el3_or_mon(env)) {
2037 return true;
2038 }
2039 return arm_is_secure_below_el3(env);
2040 }
2041
2042 #else
2043 static inline bool arm_is_secure_below_el3(CPUARMState *env)
2044 {
2045 return false;
2046 }
2047
2048 static inline bool arm_is_secure(CPUARMState *env)
2049 {
2050 return false;
2051 }
2052 #endif
2053
2054 /**
2055 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2.
2056 * E.g. when in secure state, fields in HCR_EL2 are suppressed,
2057 * "for all purposes other than a direct read or write access of HCR_EL2."
2058 * Not included here is HCR_RW.
2059 */
2060 uint64_t arm_hcr_el2_eff(CPUARMState *env);
2061
2062 /* Return true if the specified exception level is running in AArch64 state. */
2063 static inline bool arm_el_is_aa64(CPUARMState *env, int el)
2064 {
2065 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
2066 * and if we're not in EL0 then the state of EL0 isn't well defined.)
2067 */
2068 assert(el >= 1 && el <= 3);
2069 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
2070
2071 /* The highest exception level is always at the maximum supported
2072 * register width, and then lower levels have a register width controlled
2073 * by bits in the SCR or HCR registers.
2074 */
2075 if (el == 3) {
2076 return aa64;
2077 }
2078
2079 if (arm_feature(env, ARM_FEATURE_EL3)) {
2080 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
2081 }
2082
2083 if (el == 2) {
2084 return aa64;
2085 }
2086
2087 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) {
2088 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
2089 }
2090
2091 return aa64;
2092 }
2093
2094 /* Function for determing whether guest cp register reads and writes should
2095 * access the secure or non-secure bank of a cp register. When EL3 is
2096 * operating in AArch32 state, the NS-bit determines whether the secure
2097 * instance of a cp register should be used. When EL3 is AArch64 (or if
2098 * it doesn't exist at all) then there is no register banking, and all
2099 * accesses are to the non-secure version.
2100 */
2101 static inline bool access_secure_reg(CPUARMState *env)
2102 {
2103 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
2104 !arm_el_is_aa64(env, 3) &&
2105 !(env->cp15.scr_el3 & SCR_NS));
2106
2107 return ret;
2108 }
2109
2110 /* Macros for accessing a specified CP register bank */
2111 #define A32_BANKED_REG_GET(_env, _regname, _secure) \
2112 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
2113
2114 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
2115 do { \
2116 if (_secure) { \
2117 (_env)->cp15._regname##_s = (_val); \
2118 } else { \
2119 (_env)->cp15._regname##_ns = (_val); \
2120 } \
2121 } while (0)
2122
2123 /* Macros for automatically accessing a specific CP register bank depending on
2124 * the current secure state of the system. These macros are not intended for
2125 * supporting instruction translation reads/writes as these are dependent
2126 * solely on the SCR.NS bit and not the mode.
2127 */
2128 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
2129 A32_BANKED_REG_GET((_env), _regname, \
2130 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
2131
2132 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
2133 A32_BANKED_REG_SET((_env), _regname, \
2134 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
2135 (_val))
2136
2137 void arm_cpu_list(void);
2138 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
2139 uint32_t cur_el, bool secure);
2140
2141 /* Interface between CPU and Interrupt controller. */
2142 #ifndef CONFIG_USER_ONLY
2143 bool armv7m_nvic_can_take_pending_exception(void *opaque);
2144 #else
2145 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
2146 {
2147 return true;
2148 }
2149 #endif
2150 /**
2151 * armv7m_nvic_set_pending: mark the specified exception as pending
2152 * @opaque: the NVIC
2153 * @irq: the exception number to mark pending
2154 * @secure: false for non-banked exceptions or for the nonsecure
2155 * version of a banked exception, true for the secure version of a banked
2156 * exception.
2157 *
2158 * Marks the specified exception as pending. Note that we will assert()
2159 * if @secure is true and @irq does not specify one of the fixed set
2160 * of architecturally banked exceptions.
2161 */
2162 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
2163 /**
2164 * armv7m_nvic_set_pending_derived: mark this derived exception as pending
2165 * @opaque: the NVIC
2166 * @irq: the exception number to mark pending
2167 * @secure: false for non-banked exceptions or for the nonsecure
2168 * version of a banked exception, true for the secure version of a banked
2169 * exception.
2170 *
2171 * Similar to armv7m_nvic_set_pending(), but specifically for derived
2172 * exceptions (exceptions generated in the course of trying to take
2173 * a different exception).
2174 */
2175 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
2176 /**
2177 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
2178 * @opaque: the NVIC
2179 * @irq: the exception number to mark pending
2180 * @secure: false for non-banked exceptions or for the nonsecure
2181 * version of a banked exception, true for the secure version of a banked
2182 * exception.
2183 *
2184 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
2185 * generated in the course of lazy stacking of FP registers.
2186 */
2187 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
2188 /**
2189 * armv7m_nvic_get_pending_irq_info: return highest priority pending
2190 * exception, and whether it targets Secure state
2191 * @opaque: the NVIC
2192 * @pirq: set to pending exception number
2193 * @ptargets_secure: set to whether pending exception targets Secure
2194 *
2195 * This function writes the number of the highest priority pending
2196 * exception (the one which would be made active by
2197 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
2198 * to true if the current highest priority pending exception should
2199 * be taken to Secure state, false for NS.
2200 */
2201 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
2202 bool *ptargets_secure);
2203 /**
2204 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
2205 * @opaque: the NVIC
2206 *
2207 * Move the current highest priority pending exception from the pending
2208 * state to the active state, and update v7m.exception to indicate that
2209 * it is the exception currently being handled.
2210 */
2211 void armv7m_nvic_acknowledge_irq(void *opaque);
2212 /**
2213 * armv7m_nvic_complete_irq: complete specified interrupt or exception
2214 * @opaque: the NVIC
2215 * @irq: the exception number to complete
2216 * @secure: true if this exception was secure
2217 *
2218 * Returns: -1 if the irq was not active
2219 * 1 if completing this irq brought us back to base (no active irqs)
2220 * 0 if there is still an irq active after this one was completed
2221 * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
2222 */
2223 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
2224 /**
2225 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
2226 * @opaque: the NVIC
2227 * @irq: the exception number to mark pending
2228 * @secure: false for non-banked exceptions or for the nonsecure
2229 * version of a banked exception, true for the secure version of a banked
2230 * exception.
2231 *
2232 * Return whether an exception is "ready", i.e. whether the exception is
2233 * enabled and is configured at a priority which would allow it to
2234 * interrupt the current execution priority. This controls whether the
2235 * RDY bit for it in the FPCCR is set.
2236 */
2237 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
2238 /**
2239 * armv7m_nvic_raw_execution_priority: return the raw execution priority
2240 * @opaque: the NVIC
2241 *
2242 * Returns: the raw execution priority as defined by the v8M architecture.
2243 * This is the execution priority minus the effects of AIRCR.PRIS,
2244 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
2245 * (v8M ARM ARM I_PKLD.)
2246 */
2247 int armv7m_nvic_raw_execution_priority(void *opaque);
2248 /**
2249 * armv7m_nvic_neg_prio_requested: return true if the requested execution
2250 * priority is negative for the specified security state.
2251 * @opaque: the NVIC
2252 * @secure: the security state to test
2253 * This corresponds to the pseudocode IsReqExecPriNeg().
2254 */
2255 #ifndef CONFIG_USER_ONLY
2256 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
2257 #else
2258 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
2259 {
2260 return false;
2261 }
2262 #endif
2263
2264 /* Interface for defining coprocessor registers.
2265 * Registers are defined in tables of arm_cp_reginfo structs
2266 * which are passed to define_arm_cp_regs().
2267 */
2268
2269 /* When looking up a coprocessor register we look for it
2270 * via an integer which encodes all of:
2271 * coprocessor number
2272 * Crn, Crm, opc1, opc2 fields
2273 * 32 or 64 bit register (ie is it accessed via MRC/MCR
2274 * or via MRRC/MCRR?)
2275 * non-secure/secure bank (AArch32 only)
2276 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
2277 * (In this case crn and opc2 should be zero.)
2278 * For AArch64, there is no 32/64 bit size distinction;
2279 * instead all registers have a 2 bit op0, 3 bit op1 and op2,
2280 * and 4 bit CRn and CRm. The encoding patterns are chosen
2281 * to be easy to convert to and from the KVM encodings, and also
2282 * so that the hashtable can contain both AArch32 and AArch64
2283 * registers (to allow for interprocessing where we might run
2284 * 32 bit code on a 64 bit core).
2285 */
2286 /* This bit is private to our hashtable cpreg; in KVM register
2287 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
2288 * in the upper bits of the 64 bit ID.
2289 */
2290 #define CP_REG_AA64_SHIFT 28
2291 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
2292
2293 /* To enable banking of coprocessor registers depending on ns-bit we
2294 * add a bit to distinguish between secure and non-secure cpregs in the
2295 * hashtable.
2296 */
2297 #define CP_REG_NS_SHIFT 29
2298 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
2299
2300 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
2301 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
2302 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
2303
2304 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
2305 (CP_REG_AA64_MASK | \
2306 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
2307 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
2308 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
2309 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
2310 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
2311 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
2312
2313 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
2314 * version used as a key for the coprocessor register hashtable
2315 */
2316 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
2317 {
2318 uint32_t cpregid = kvmid;
2319 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
2320 cpregid |= CP_REG_AA64_MASK;
2321 } else {
2322 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
2323 cpregid |= (1 << 15);
2324 }
2325
2326 /* KVM is always non-secure so add the NS flag on AArch32 register
2327 * entries.
2328 */
2329 cpregid |= 1 << CP_REG_NS_SHIFT;
2330 }
2331 return cpregid;
2332 }
2333
2334 /* Convert a truncated 32 bit hashtable key into the full
2335 * 64 bit KVM register ID.
2336 */
2337 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
2338 {
2339 uint64_t kvmid;
2340
2341 if (cpregid & CP_REG_AA64_MASK) {
2342 kvmid = cpregid & ~CP_REG_AA64_MASK;
2343 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
2344 } else {
2345 kvmid = cpregid & ~(1 << 15);
2346 if (cpregid & (1 << 15)) {
2347 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
2348 } else {
2349 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
2350 }
2351 }
2352 return kvmid;
2353 }
2354
2355 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
2356 * special-behaviour cp reg and bits [11..8] indicate what behaviour
2357 * it has. Otherwise it is a simple cp reg, where CONST indicates that
2358 * TCG can assume the value to be constant (ie load at translate time)
2359 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
2360 * indicates that the TB should not be ended after a write to this register
2361 * (the default is that the TB ends after cp writes). OVERRIDE permits
2362 * a register definition to override a previous definition for the
2363 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
2364 * old must have the OVERRIDE bit set.
2365 * ALIAS indicates that this register is an alias view of some underlying
2366 * state which is also visible via another register, and that the other
2367 * register is handling migration and reset; registers marked ALIAS will not be
2368 * migrated but may have their state set by syncing of register state from KVM.
2369 * NO_RAW indicates that this register has no underlying state and does not
2370 * support raw access for state saving/loading; it will not be used for either
2371 * migration or KVM state synchronization. (Typically this is for "registers"
2372 * which are actually used as instructions for cache maintenance and so on.)
2373 * IO indicates that this register does I/O and therefore its accesses
2374 * need to be marked with gen_io_start() and also end the TB. In particular,
2375 * registers which implement clocks or timers require this.
2376 * RAISES_EXC is for when the read or write hook might raise an exception;
2377 * the generated code will synchronize the CPU state before calling the hook
2378 * so that it is safe for the hook to call raise_exception().
2379 * NEWEL is for writes to registers that might change the exception
2380 * level - typically on older ARM chips. For those cases we need to
2381 * re-read the new el when recomputing the translation flags.
2382 */
2383 #define ARM_CP_SPECIAL 0x0001
2384 #define ARM_CP_CONST 0x0002
2385 #define ARM_CP_64BIT 0x0004
2386 #define ARM_CP_SUPPRESS_TB_END 0x0008
2387 #define ARM_CP_OVERRIDE 0x0010
2388 #define ARM_CP_ALIAS 0x0020
2389 #define ARM_CP_IO 0x0040
2390 #define ARM_CP_NO_RAW 0x0080
2391 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100)
2392 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200)
2393 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
2394 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
2395 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
2396 #define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600)
2397 #define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700)
2398 #define ARM_LAST_SPECIAL ARM_CP_DC_GZVA
2399 #define ARM_CP_FPU 0x1000
2400 #define ARM_CP_SVE 0x2000
2401 #define ARM_CP_NO_GDB 0x4000
2402 #define ARM_CP_RAISES_EXC 0x8000
2403 #define ARM_CP_NEWEL 0x10000
2404 /* Used only as a terminator for ARMCPRegInfo lists */
2405 #define ARM_CP_SENTINEL 0xfffff
2406 /* Mask of only the flag bits in a type field */
2407 #define ARM_CP_FLAG_MASK 0x1f0ff
2408
2409 /* Valid values for ARMCPRegInfo state field, indicating which of
2410 * the AArch32 and AArch64 execution states this register is visible in.
2411 * If the reginfo doesn't explicitly specify then it is AArch32 only.
2412 * If the reginfo is declared to be visible in both states then a second
2413 * reginfo is synthesised for the AArch32 view of the AArch64 register,
2414 * such that the AArch32 view is the lower 32 bits of the AArch64 one.
2415 * Note that we rely on the values of these enums as we iterate through
2416 * the various states in some places.
2417 */
2418 enum {
2419 ARM_CP_STATE_AA32 = 0,
2420 ARM_CP_STATE_AA64 = 1,
2421 ARM_CP_STATE_BOTH = 2,
2422 };
2423
2424 /* ARM CP register secure state flags. These flags identify security state
2425 * attributes for a given CP register entry.
2426 * The existence of both or neither secure and non-secure flags indicates that
2427 * the register has both a secure and non-secure hash entry. A single one of
2428 * these flags causes the register to only be hashed for the specified
2429 * security state.
2430 * Although definitions may have any combination of the S/NS bits, each
2431 * registered entry will only have one to identify whether the entry is secure
2432 * or non-secure.
2433 */
2434 enum {
2435 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */
2436 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */
2437 };
2438
2439 /* Return true if cptype is a valid type field. This is used to try to
2440 * catch errors where the sentinel has been accidentally left off the end
2441 * of a list of registers.
2442 */
2443 static inline bool cptype_valid(int cptype)
2444 {
2445 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
2446 || ((cptype & ARM_CP_SPECIAL) &&
2447 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
2448 }
2449
2450 /* Access rights:
2451 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
2452 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
2453 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
2454 * (ie any of the privileged modes in Secure state, or Monitor mode).
2455 * If a register is accessible in one privilege level it's always accessible
2456 * in higher privilege levels too. Since "Secure PL1" also follows this rule
2457 * (ie anything visible in PL2 is visible in S-PL1, some things are only
2458 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
2459 * terminology a little and call this PL3.
2460 * In AArch64 things are somewhat simpler as the PLx bits line up exactly
2461 * with the ELx exception levels.
2462 *
2463 * If access permissions for a register are more complex than can be
2464 * described with these bits, then use a laxer set of restrictions, and
2465 * do the more restrictive/complex check inside a helper function.
2466 */
2467 #define PL3_R 0x80
2468 #define PL3_W 0x40
2469 #define PL2_R (0x20 | PL3_R)
2470 #define PL2_W (0x10 | PL3_W)
2471 #define PL1_R (0x08 | PL2_R)
2472 #define PL1_W (0x04 | PL2_W)
2473 #define PL0_R (0x02 | PL1_R)
2474 #define PL0_W (0x01 | PL1_W)
2475
2476 /*
2477 * For user-mode some registers are accessible to EL0 via a kernel
2478 * trap-and-emulate ABI. In this case we define the read permissions
2479 * as actually being PL0_R. However some bits of any given register
2480 * may still be masked.
2481 */
2482 #ifdef CONFIG_USER_ONLY
2483 #define PL0U_R PL0_R
2484 #else
2485 #define PL0U_R PL1_R
2486 #endif
2487
2488 #define PL3_RW (PL3_R | PL3_W)
2489 #define PL2_RW (PL2_R | PL2_W)
2490 #define PL1_RW (PL1_R | PL1_W)
2491 #define PL0_RW (PL0_R | PL0_W)
2492
2493 /* Return the highest implemented Exception Level */
2494 static inline int arm_highest_el(CPUARMState *env)
2495 {
2496 if (arm_feature(env, ARM_FEATURE_EL3)) {
2497 return 3;
2498 }
2499 if (arm_feature(env, ARM_FEATURE_EL2)) {
2500 return 2;
2501 }
2502 return 1;
2503 }
2504
2505 /* Return true if a v7M CPU is in Handler mode */
2506 static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2507 {
2508 return env->v7m.exception != 0;
2509 }
2510
2511 /* Return the current Exception Level (as per ARMv8; note that this differs
2512 * from the ARMv7 Privilege Level).
2513 */
2514 static inline int arm_current_el(CPUARMState *env)
2515 {
2516 if (arm_feature(env, ARM_FEATURE_M)) {
2517 return arm_v7m_is_handler_mode(env) ||
2518 !(env->v7m.control[env->v7m.secure] & 1);
2519 }
2520
2521 if (is_a64(env)) {
2522 return extract32(env->pstate, 2, 2);
2523 }
2524
2525 switch (env->uncached_cpsr & 0x1f) {
2526 case ARM_CPU_MODE_USR:
2527 return 0;
2528 case ARM_CPU_MODE_HYP:
2529 return 2;
2530 case ARM_CPU_MODE_MON:
2531 return 3;
2532 default:
2533 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2534 /* If EL3 is 32-bit then all secure privileged modes run in
2535 * EL3
2536 */
2537 return 3;
2538 }
2539
2540 return 1;
2541 }
2542 }
2543
2544 typedef struct ARMCPRegInfo ARMCPRegInfo;
2545
2546 typedef enum CPAccessResult {
2547 /* Access is permitted */
2548 CP_ACCESS_OK = 0,
2549 /* Access fails due to a configurable trap or enable which would
2550 * result in a categorized exception syndrome giving information about
2551 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
2552 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
2553 * PL1 if in EL0, otherwise to the current EL).
2554 */
2555 CP_ACCESS_TRAP = 1,
2556 /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
2557 * Note that this is not a catch-all case -- the set of cases which may
2558 * result in this failure is specifically defined by the architecture.
2559 */
2560 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
2561 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
2562 CP_ACCESS_TRAP_EL2 = 3,
2563 CP_ACCESS_TRAP_EL3 = 4,
2564 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
2565 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
2566 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
2567 /* Access fails and results in an exception syndrome for an FP access,
2568 * trapped directly to EL2 or EL3
2569 */
2570 CP_ACCESS_TRAP_FP_EL2 = 7,
2571 CP_ACCESS_TRAP_FP_EL3 = 8,
2572 } CPAccessResult;
2573
2574 /* Access functions for coprocessor registers. These cannot fail and
2575 * may not raise exceptions.
2576 */
2577 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2578 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
2579 uint64_t value);
2580 /* Access permission check functions for coprocessor registers. */
2581 typedef CPAccessResult CPAccessFn(CPUARMState *env,
2582 const ARMCPRegInfo *opaque,
2583 bool isread);
2584 /* Hook function for register reset */
2585 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2586
2587 #define CP_ANY 0xff
2588
2589 /* Definition of an ARM coprocessor register */
2590 struct ARMCPRegInfo {
2591 /* Name of register (useful mainly for debugging, need not be unique) */
2592 const char *name;
2593 /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
2594 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
2595 * 'wildcard' field -- any value of that field in the MRC/MCR insn
2596 * will be decoded to this register. The register read and write
2597 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
2598 * used by the program, so it is possible to register a wildcard and
2599 * then behave differently on read/write if necessary.
2600 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
2601 * must both be zero.
2602 * For AArch64-visible registers, opc0 is also used.
2603 * Since there are no "coprocessors" in AArch64, cp is purely used as a
2604 * way to distinguish (for KVM's benefit) guest-visible system registers
2605 * from demuxed ones provided to preserve the "no side effects on
2606 * KVM register read/write from QEMU" semantics. cp==0x13 is guest
2607 * visible (to match KVM's encoding); cp==0 will be converted to
2608 * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
2609 */
2610 uint8_t cp;
2611 uint8_t crn;
2612 uint8_t crm;
2613 uint8_t opc0;
2614 uint8_t opc1;
2615 uint8_t opc2;
2616 /* Execution state in which this register is visible: ARM_CP_STATE_* */
2617 int state;
2618 /* Register type: ARM_CP_* bits/values */
2619 int type;
2620 /* Access rights: PL*_[RW] */
2621 int access;
2622 /* Security state: ARM_CP_SECSTATE_* bits/values */
2623 int secure;
2624 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
2625 * this register was defined: can be used to hand data through to the
2626 * register read/write functions, since they are passed the ARMCPRegInfo*.
2627 */
2628 void *opaque;
2629 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
2630 * fieldoffset is non-zero, the reset value of the register.
2631 */
2632 uint64_t resetvalue;
2633 /* Offset of the field in CPUARMState for this register.
2634 *
2635 * This is not needed if either:
2636 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
2637 * 2. both readfn and writefn are specified
2638 */
2639 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
2640
2641 /* Offsets of the secure and non-secure fields in CPUARMState for the
2642 * register if it is banked. These fields are only used during the static
2643 * registration of a register. During hashing the bank associated
2644 * with a given security state is copied to fieldoffset which is used from
2645 * there on out.
2646 *
2647 * It is expected that register definitions use either fieldoffset or
2648 * bank_fieldoffsets in the definition but not both. It is also expected
2649 * that both bank offsets are set when defining a banked register. This
2650 * use indicates that a register is banked.
2651 */
2652 ptrdiff_t bank_fieldoffsets[2];
2653
2654 /* Function for making any access checks for this register in addition to
2655 * those specified by the 'access' permissions bits. If NULL, no extra
2656 * checks required. The access check is performed at runtime, not at
2657 * translate time.
2658 */
2659 CPAccessFn *accessfn;
2660 /* Function for handling reads of this register. If NULL, then reads
2661 * will be done by loading from the offset into CPUARMState specified
2662 * by fieldoffset.
2663 */
2664 CPReadFn *readfn;
2665 /* Function for handling writes of this register. If NULL, then writes
2666 * will be done by writing to the offset into CPUARMState specified
2667 * by fieldoffset.
2668 */
2669 CPWriteFn *writefn;
2670 /* Function for doing a "raw" read; used when we need to copy
2671 * coprocessor state to the kernel for KVM or out for
2672 * migration. This only needs to be provided if there is also a
2673 * readfn and it has side effects (for instance clear-on-read bits).
2674 */
2675 CPReadFn *raw_readfn;
2676 /* Function for doing a "raw" write; used when we need to copy KVM
2677 * kernel coprocessor state into userspace, or for inbound
2678 * migration. This only needs to be provided if there is also a
2679 * writefn and it masks out "unwritable" bits or has write-one-to-clear
2680 * or similar behaviour.
2681 */
2682 CPWriteFn *raw_writefn;
2683 /* Function for resetting the register. If NULL, then reset will be done
2684 * by writing resetvalue to the field specified in fieldoffset. If
2685 * fieldoffset is 0 then no reset will be done.
2686 */
2687 CPResetFn *resetfn;
2688
2689 /*
2690 * "Original" writefn and readfn.
2691 * For ARMv8.1-VHE register aliases, we overwrite the read/write
2692 * accessor functions of various EL1/EL0 to perform the runtime
2693 * check for which sysreg should actually be modified, and then
2694 * forwards the operation. Before overwriting the accessors,
2695 * the original function is copied here, so that accesses that
2696 * really do go to the EL1/EL0 version proceed normally.
2697 * (The corresponding EL2 register is linked via opaque.)
2698 */
2699 CPReadFn *orig_readfn;
2700 CPWriteFn *orig_writefn;
2701 };
2702
2703 /* Macros which are lvalues for the field in CPUARMState for the
2704 * ARMCPRegInfo *ri.
2705 */
2706 #define CPREG_FIELD32(env, ri) \
2707 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
2708 #define CPREG_FIELD64(env, ri) \
2709 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
2710
2711 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
2712
2713 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2714 const ARMCPRegInfo *regs, void *opaque);
2715 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2716 const ARMCPRegInfo *regs, void *opaque);
2717 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
2718 {
2719 define_arm_cp_regs_with_opaque(cpu, regs, 0);
2720 }
2721 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
2722 {
2723 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
2724 }
2725 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
2726
2727 /*
2728 * Definition of an ARM co-processor register as viewed from
2729 * userspace. This is used for presenting sanitised versions of
2730 * registers to userspace when emulating the Linux AArch64 CPU
2731 * ID/feature ABI (advertised as HWCAP_CPUID).
2732 */
2733 typedef struct ARMCPRegUserSpaceInfo {
2734 /* Name of register */
2735 const char *name;
2736
2737 /* Is the name actually a glob pattern */
2738 bool is_glob;
2739
2740 /* Only some bits are exported to user space */
2741 uint64_t exported_bits;
2742
2743 /* Fixed bits are applied after the mask */
2744 uint64_t fixed_bits;
2745 } ARMCPRegUserSpaceInfo;
2746
2747 #define REGUSERINFO_SENTINEL { .name = NULL }
2748
2749 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
2750
2751 /* CPWriteFn that can be used to implement writes-ignored behaviour */
2752 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2753 uint64_t value);
2754 /* CPReadFn that can be used for read-as-zero behaviour */
2755 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
2756
2757 /* CPResetFn that does nothing, for use if no reset is required even
2758 * if fieldoffset is non zero.
2759 */
2760 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
2761
2762 /* Return true if this reginfo struct's field in the cpu state struct
2763 * is 64 bits wide.
2764 */
2765 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
2766 {
2767 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
2768 }
2769
2770 static inline bool cp_access_ok(int current_el,
2771 const ARMCPRegInfo *ri, int isread)
2772 {
2773 return (ri->access >> ((current_el * 2) + isread)) & 1;
2774 }
2775
2776 /* Raw read of a coprocessor register (as needed for migration, etc) */
2777 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
2778
2779 /**
2780 * write_list_to_cpustate
2781 * @cpu: ARMCPU
2782 *
2783 * For each register listed in the ARMCPU cpreg_indexes list, write
2784 * its value from the cpreg_values list into the ARMCPUState structure.
2785 * This updates TCG's working data structures from KVM data or
2786 * from incoming migration state.
2787 *
2788 * Returns: true if all register values were updated correctly,
2789 * false if some register was unknown or could not be written.
2790 * Note that we do not stop early on failure -- we will attempt
2791 * writing all registers in the list.
2792 */
2793 bool write_list_to_cpustate(ARMCPU *cpu);
2794
2795 /**
2796 * write_cpustate_to_list:
2797 * @cpu: ARMCPU
2798 * @kvm_sync: true if this is for syncing back to KVM
2799 *
2800 * For each register listed in the ARMCPU cpreg_indexes list, write
2801 * its value from the ARMCPUState structure into the cpreg_values list.
2802 * This is used to copy info from TCG's working data structures into
2803 * KVM or for outbound migration.
2804 *
2805 * @kvm_sync is true if we are doing this in order to sync the
2806 * register state back to KVM. In this case we will only update
2807 * values in the list if the previous list->cpustate sync actually
2808 * successfully wrote the CPU state. Otherwise we will keep the value
2809 * that is in the list.
2810 *
2811 * Returns: true if all register values were read correctly,
2812 * false if some register was unknown or could not be read.
2813 * Note that we do not stop early on failure -- we will attempt
2814 * reading all registers in the list.
2815 */
2816 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
2817
2818 #define ARM_CPUID_TI915T 0x54029152
2819 #define ARM_CPUID_TI925T 0x54029252
2820
2821 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
2822 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
2823 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2824
2825 #define cpu_signal_handler cpu_arm_signal_handler
2826 #define cpu_list arm_cpu_list
2827
2828 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
2829 *
2830 * If EL3 is 64-bit:
2831 * + NonSecure EL1 & 0 stage 1
2832 * + NonSecure EL1 & 0 stage 2
2833 * + NonSecure EL2
2834 * + NonSecure EL2 & 0 (ARMv8.1-VHE)
2835 * + Secure EL1 & 0
2836 * + Secure EL3
2837 * If EL3 is 32-bit:
2838 * + NonSecure PL1 & 0 stage 1
2839 * + NonSecure PL1 & 0 stage 2
2840 * + NonSecure PL2
2841 * + Secure PL0
2842 * + Secure PL1
2843 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
2844 *
2845 * For QEMU, an mmu_idx is not quite the same as a translation regime because:
2846 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes,
2847 * because they may differ in access permissions even if the VA->PA map is
2848 * the same
2849 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2850 * translation, which means that we have one mmu_idx that deals with two
2851 * concatenated translation regimes [this sort of combined s1+2 TLB is
2852 * architecturally permitted]
2853 * 3. we don't need to allocate an mmu_idx to translations that we won't be
2854 * handling via the TLB. The only way to do a stage 1 translation without
2855 * the immediate stage 2 translation is via the ATS or AT system insns,
2856 * which can be slow-pathed and always do a page table walk.
2857 * The only use of stage 2 translations is either as part of an s1+2
2858 * lookup or when loading the descriptors during a stage 1 page table walk,
2859 * and in both those cases we don't use the TLB.
2860 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
2861 * translation regimes, because they map reasonably well to each other
2862 * and they can't both be active at the same time.
2863 * 5. we want to be able to use the TLB for accesses done as part of a
2864 * stage1 page table walk, rather than having to walk the stage2 page
2865 * table over and over.
2866 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
2867 * Never (PAN) bit within PSTATE.
2868 *
2869 * This gives us the following list of cases:
2870 *
2871 * NS EL0 EL1&0 stage 1+2 (aka NS PL0)
2872 * NS EL1 EL1&0 stage 1+2 (aka NS PL1)
2873 * NS EL1 EL1&0 stage 1+2 +PAN
2874 * NS EL0 EL2&0
2875 * NS EL2 EL2&0
2876 * NS EL2 EL2&0 +PAN
2877 * NS EL2 (aka NS PL2)
2878 * S EL0 EL1&0 (aka S PL0)
2879 * S EL1 EL1&0 (not used if EL3 is 32 bit)
2880 * S EL1 EL1&0 +PAN
2881 * S EL3 (aka S PL1)
2882 *
2883 * for a total of 11 different mmu_idx.
2884 *
2885 * R profile CPUs have an MPU, but can use the same set of MMU indexes
2886 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and
2887 * NS EL2 if we ever model a Cortex-R52).
2888 *
2889 * M profile CPUs are rather different as they do not have a true MMU.
2890 * They have the following different MMU indexes:
2891 * User
2892 * Privileged
2893 * User, execution priority negative (ie the MPU HFNMIENA bit may apply)
2894 * Privileged, execution priority negative (ditto)
2895 * If the CPU supports the v8M Security Extension then there are also:
2896 * Secure User
2897 * Secure Privileged
2898 * Secure User, execution priority negative
2899 * Secure Privileged, execution priority negative
2900 *
2901 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
2902 * are not quite the same -- different CPU types (most notably M profile
2903 * vs A/R profile) would like to use MMU indexes with different semantics,
2904 * but since we don't ever need to use all of those in a single CPU we
2905 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU
2906 * modes + total number of M profile MMU modes". The lower bits of
2907 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
2908 * the same for any particular CPU.
2909 * Variables of type ARMMUIdx are always full values, and the core
2910 * index values are in variables of type 'int'.
2911 *
2912 * Our enumeration includes at the end some entries which are not "true"
2913 * mmu_idx values in that they don't have corresponding TLBs and are only
2914 * valid for doing slow path page table walks.
2915 *
2916 * The constant names here are patterned after the general style of the names
2917 * of the AT/ATS operations.
2918 * The values used are carefully arranged to make mmu_idx => EL lookup easy.
2919 * For M profile we arrange them to have a bit for priv, a bit for negpri
2920 * and a bit for secure.
2921 */
2922 #define ARM_MMU_IDX_A 0x10 /* A profile */
2923 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
2924 #define ARM_MMU_IDX_M 0x40 /* M profile */
2925
2926 /* Meanings of the bits for M profile mmu idx values */
2927 #define ARM_MMU_IDX_M_PRIV 0x1
2928 #define ARM_MMU_IDX_M_NEGPRI 0x2
2929 #define ARM_MMU_IDX_M_S 0x4 /* Secure */
2930
2931 #define ARM_MMU_IDX_TYPE_MASK \
2932 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
2933 #define ARM_MMU_IDX_COREIDX_MASK 0xf
2934
2935 typedef enum ARMMMUIdx {
2936 /*
2937 * A-profile.
2938 */
2939 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A,
2940 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A,
2941
2942 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A,
2943 ARMMMUIdx_E10_1_PAN = 3 | ARM_MMU_IDX_A,
2944
2945 ARMMMUIdx_E2 = 4 | ARM_MMU_IDX_A,
2946 ARMMMUIdx_E20_2 = 5 | ARM_MMU_IDX_A,
2947 ARMMMUIdx_E20_2_PAN = 6 | ARM_MMU_IDX_A,
2948
2949 ARMMMUIdx_SE10_0 = 7 | ARM_MMU_IDX_A,
2950 ARMMMUIdx_SE10_1 = 8 | ARM_MMU_IDX_A,
2951 ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A,
2952 ARMMMUIdx_SE3 = 10 | ARM_MMU_IDX_A,
2953
2954 /*
2955 * These are not allocated TLBs and are used only for AT system
2956 * instructions or for the first stage of an S12 page table walk.
2957 */
2958 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
2959 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
2960 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
2961 /*
2962 * Not allocated a TLB: used only for second stage of an S12 page
2963 * table walk, or for descriptor loads during first stage of an S1
2964 * page table walk. Note that if we ever want to have a TLB for this
2965 * then various TLB flush insns which currently are no-ops or flush
2966 * only stage 1 MMU indexes will need to change to flush stage 2.
2967 */
2968 ARMMMUIdx_Stage2 = 3 | ARM_MMU_IDX_NOTLB,
2969
2970 /*
2971 * M-profile.
2972 */
2973 ARMMMUIdx_MUser = ARM_MMU_IDX_M,
2974 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
2975 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
2976 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
2977 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
2978 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
2979 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
2980 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
2981 } ARMMMUIdx;
2982
2983 /*
2984 * Bit macros for the core-mmu-index values for each index,
2985 * for use when calling tlb_flush_by_mmuidx() and friends.
2986 */
2987 #define TO_CORE_BIT(NAME) \
2988 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
2989
2990 typedef enum ARMMMUIdxBit {
2991 TO_CORE_BIT(E10_0),
2992 TO_CORE_BIT(E20_0),
2993 TO_CORE_BIT(E10_1),
2994 TO_CORE_BIT(E10_1_PAN),
2995 TO_CORE_BIT(E2),
2996 TO_CORE_BIT(E20_2),
2997 TO_CORE_BIT(E20_2_PAN),
2998 TO_CORE_BIT(SE10_0),
2999 TO_CORE_BIT(SE10_1),
3000 TO_CORE_BIT(SE10_1_PAN),
3001 TO_CORE_BIT(SE3),
3002
3003 TO_CORE_BIT(MUser),
3004 TO_CORE_BIT(MPriv),
3005 TO_CORE_BIT(MUserNegPri),
3006 TO_CORE_BIT(MPrivNegPri),
3007 TO_CORE_BIT(MSUser),
3008 TO_CORE_BIT(MSPriv),
3009 TO_CORE_BIT(MSUserNegPri),
3010 TO_CORE_BIT(MSPrivNegPri),
3011 } ARMMMUIdxBit;
3012
3013 #undef TO_CORE_BIT
3014
3015 #define MMU_USER_IDX 0
3016
3017 /* Indexes used when registering address spaces with cpu_address_space_init */
3018 typedef enum ARMASIdx {
3019 ARMASIdx_NS = 0,
3020 ARMASIdx_S = 1,
3021 ARMASIdx_TagNS = 2,
3022 ARMASIdx_TagS = 3,
3023 } ARMASIdx;
3024
3025 /* Return the Exception Level targeted by debug exceptions. */
3026 static inline int arm_debug_target_el(CPUARMState *env)
3027 {
3028 bool secure = arm_is_secure(env);
3029 bool route_to_el2 = false;
3030
3031 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
3032 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
3033 env->cp15.mdcr_el2 & MDCR_TDE;
3034 }
3035
3036 if (route_to_el2) {
3037 return 2;
3038 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
3039 !arm_el_is_aa64(env, 3) && secure) {
3040 return 3;
3041 } else {
3042 return 1;
3043 }
3044 }
3045
3046 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
3047 {
3048 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and
3049 * CSSELR is RAZ/WI.
3050 */
3051 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
3052 }
3053
3054 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */
3055 static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
3056 {
3057 int cur_el = arm_current_el(env);
3058 int debug_el;
3059
3060 if (cur_el == 3) {
3061 return false;
3062 }
3063
3064 /* MDCR_EL3.SDD disables debug events from Secure state */
3065 if (arm_is_secure_below_el3(env)
3066 && extract32(env->cp15.mdcr_el3, 16, 1)) {
3067 return false;
3068 }
3069
3070 /*
3071 * Same EL to same EL debug exceptions need MDSCR_KDE enabled
3072 * while not masking the (D)ebug bit in DAIF.
3073 */
3074 debug_el = arm_debug_target_el(env);
3075
3076 if (cur_el == debug_el) {
3077 return extract32(env->cp15.mdscr_el1, 13, 1)
3078 && !(env->daif & PSTATE_D);
3079 }
3080
3081 /* Otherwise the debug target needs to be a higher EL */
3082 return debug_el > cur_el;
3083 }
3084
3085 static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
3086 {
3087 int el = arm_current_el(env);
3088
3089 if (el == 0 && arm_el_is_aa64(env, 1)) {
3090 return aa64_generate_debug_exceptions(env);
3091 }
3092
3093 if (arm_is_secure(env)) {
3094 int spd;
3095
3096 if (el == 0 && (env->cp15.sder & 1)) {
3097 /* SDER.SUIDEN means debug exceptions from Secure EL0
3098 * are always enabled. Otherwise they are controlled by
3099 * SDCR.SPD like those from other Secure ELs.
3100 */
3101 return true;
3102 }
3103
3104 spd = extract32(env->cp15.mdcr_el3, 14, 2);
3105 switch (spd) {
3106 case 1:
3107 /* SPD == 0b01 is reserved, but behaves as 0b00. */
3108 case 0:
3109 /* For 0b00 we return true if external secure invasive debug
3110 * is enabled. On real hardware this is controlled by external
3111 * signals to the core. QEMU always permits debug, and behaves
3112 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
3113 */
3114 return true;
3115 case 2:
3116 return false;
3117 case 3:
3118 return true;
3119 }
3120 }
3121
3122 return el != 2;
3123 }
3124
3125 /* Return true if debugging exceptions are currently enabled.
3126 * This corresponds to what in ARM ARM pseudocode would be
3127 * if UsingAArch32() then
3128 * return AArch32.GenerateDebugExceptions()
3129 * else
3130 * return AArch64.GenerateDebugExceptions()
3131 * We choose to push the if() down into this function for clarity,
3132 * since the pseudocode has it at all callsites except for the one in
3133 * CheckSoftwareStep(), where it is elided because both branches would
3134 * always return the same value.
3135 */
3136 static inline bool arm_generate_debug_exceptions(CPUARMState *env)
3137 {
3138 if (env->aarch64) {
3139 return aa64_generate_debug_exceptions(env);
3140 } else {
3141 return aa32_generate_debug_exceptions(env);
3142 }
3143 }
3144
3145 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check
3146 * implicitly means this always returns false in pre-v8 CPUs.)
3147 */
3148 static inline bool arm_singlestep_active(CPUARMState *env)
3149 {
3150 return extract32(env->cp15.mdscr_el1, 0, 1)
3151 && arm_el_is_aa64(env, arm_debug_target_el(env))
3152 && arm_generate_debug_exceptions(env);
3153 }
3154
3155 static inline bool arm_sctlr_b(CPUARMState *env)
3156 {
3157 return
3158 /* We need not implement SCTLR.ITD in user-mode emulation, so
3159 * let linux-user ignore the fact that it conflicts with SCTLR_B.
3160 * This lets people run BE32 binaries with "-cpu any".
3161 */
3162 #ifndef CONFIG_USER_ONLY
3163 !arm_feature(env, ARM_FEATURE_V7) &&
3164 #endif
3165 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
3166 }
3167
3168 uint64_t arm_sctlr(CPUARMState *env, int el);
3169
3170 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
3171 bool sctlr_b)
3172 {
3173 #ifdef CONFIG_USER_ONLY
3174 /*
3175 * In system mode, BE32 is modelled in line with the
3176 * architecture (as word-invariant big-endianness), where loads
3177 * and stores are done little endian but from addresses which
3178 * are adjusted by XORing with the appropriate constant. So the
3179 * endianness to use for the raw data access is not affected by
3180 * SCTLR.B.
3181 * In user mode, however, we model BE32 as byte-invariant
3182 * big-endianness (because user-only code cannot tell the
3183 * difference), and so we need to use a data access endianness
3184 * that depends on SCTLR.B.
3185 */
3186 if (sctlr_b) {
3187 return true;
3188 }
3189 #endif
3190 /* In 32bit endianness is determined by looking at CPSR's E bit */
3191 return env->uncached_cpsr & CPSR_E;
3192 }
3193
3194 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
3195 {
3196 return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
3197 }
3198
3199 /* Return true if the processor is in big-endian mode. */
3200 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
3201 {
3202 if (!is_a64(env)) {
3203 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
3204 } else {
3205 int cur_el = arm_current_el(env);
3206 uint64_t sctlr = arm_sctlr(env, cur_el);
3207 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
3208 }
3209 }
3210
3211 typedef CPUARMState CPUArchState;
3212 typedef ARMCPU ArchCPU;
3213
3214 #include "exec/cpu-all.h"
3215
3216 /*
3217 * Bit usage in the TB flags field: bit 31 indicates whether we are
3218 * in 32 or 64 bit mode. The meaning of the other bits depends on that.
3219 * We put flags which are shared between 32 and 64 bit mode at the top
3220 * of the word, and flags which apply to only one mode at the bottom.
3221 *
3222 * 31 20 18 14 9 0
3223 * +--------------+-----+-----+----------+--------------+
3224 * | | | TBFLAG_A32 | |
3225 * | | +-----+----------+ TBFLAG_AM32 |
3226 * | TBFLAG_ANY | |TBFLAG_M32| |
3227 * | +-----------+----------+--------------|
3228 * | | TBFLAG_A64 |
3229 * +--------------+-------------------------------------+
3230 * 31 20 0
3231 *
3232 * Unless otherwise noted, these bits are cached in env->hflags.
3233 */
3234 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
3235 FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1)
3236 FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */
3237 FIELD(TBFLAG_ANY, BE_DATA, 28, 1)
3238 FIELD(TBFLAG_ANY, MMUIDX, 24, 4)
3239 /* Target EL if we take a floating-point-disabled exception */
3240 FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2)
3241 /* For A-profile only, target EL for debug exceptions. */
3242 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2)
3243
3244 /*
3245 * Bit usage when in AArch32 state, both A- and M-profile.
3246 */
3247 FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */
3248 FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */
3249
3250 /*
3251 * Bit usage when in AArch32 state, for A-profile only.
3252 */
3253 FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */
3254 FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */
3255 /*
3256 * We store the bottom two bits of the CPAR as TB flags and handle
3257 * checks on the other bits at runtime. This shares the same bits as
3258 * VECSTRIDE, which is OK as no XScale CPU has VFP.
3259 * Not cached, because VECLEN+VECSTRIDE are not cached.
3260 */
3261 FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2)
3262 FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */
3263 FIELD(TBFLAG_A32, SCTLR_B, 15, 1)
3264 FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1)
3265 /*
3266 * Indicates whether cp register reads and writes by guest code should access
3267 * the secure or nonsecure bank of banked registers; note that this is not
3268 * the same thing as the current security state of the processor!
3269 */
3270 FIELD(TBFLAG_A32, NS, 17, 1)
3271
3272 /*
3273 * Bit usage when in AArch32 state, for M-profile only.
3274 */
3275 /* Handler (ie not Thread) mode */
3276 FIELD(TBFLAG_M32, HANDLER, 9, 1)
3277 /* Whether we should generate stack-limit checks */
3278 FIELD(TBFLAG_M32, STACKCHECK, 10, 1)
3279 /* Set if FPCCR.LSPACT is set */
3280 FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */
3281 /* Set if we must create a new FP context */
3282 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */
3283 /* Set if FPCCR.S does not match current security state */
3284 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */
3285
3286 /*
3287 * Bit usage when in AArch64 state
3288 */
3289 FIELD(TBFLAG_A64, TBII, 0, 2)
3290 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
3291 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
3292 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3293 FIELD(TBFLAG_A64, BT, 9, 1)
3294 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */
3295 FIELD(TBFLAG_A64, TBID, 12, 2)
3296 FIELD(TBFLAG_A64, UNPRIV, 14, 1)
3297 FIELD(TBFLAG_A64, ATA, 15, 1)
3298 FIELD(TBFLAG_A64, TCMA, 16, 2)
3299 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
3300 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
3301
3302 /**
3303 * cpu_mmu_index:
3304 * @env: The cpu environment
3305 * @ifetch: True for code access, false for data access.
3306 *
3307 * Return the core mmu index for the current translation regime.
3308 * This function is used by generic TCG code paths.
3309 */
3310 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
3311 {
3312 return FIELD_EX32(env->hflags, TBFLAG_ANY, MMUIDX);
3313 }
3314
3315 static inline bool bswap_code(bool sctlr_b)
3316 {
3317 #ifdef CONFIG_USER_ONLY
3318 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian.
3319 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0
3320 * would also end up as a mixed-endian mode with BE code, LE data.
3321 */
3322 return
3323 #ifdef TARGET_WORDS_BIGENDIAN
3324 1 ^
3325 #endif
3326 sctlr_b;
3327 #else
3328 /* All code access in ARM is little endian, and there are no loaders
3329 * doing swaps that need to be reversed
3330 */
3331 return 0;
3332 #endif
3333 }
3334
3335 #ifdef CONFIG_USER_ONLY
3336 static inline bool arm_cpu_bswap_data(CPUARMState *env)
3337 {
3338 return
3339 #ifdef TARGET_WORDS_BIGENDIAN
3340 1 ^
3341 #endif
3342 arm_cpu_data_is_big_endian(env);
3343 }
3344 #endif
3345
3346 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
3347 target_ulong *cs_base, uint32_t *flags);
3348
3349 enum {
3350 QEMU_PSCI_CONDUIT_DISABLED = 0,
3351 QEMU_PSCI_CONDUIT_SMC = 1,
3352 QEMU_PSCI_CONDUIT_HVC = 2,
3353 };
3354
3355 #ifndef CONFIG_USER_ONLY
3356 /* Return the address space index to use for a memory access */
3357 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3358 {
3359 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3360 }
3361
3362 /* Return the AddressSpace to use for a memory access
3363 * (which depends on whether the access is S or NS, and whether
3364 * the board gave us a separate AddressSpace for S accesses).
3365 */
3366 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3367 {
3368 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3369 }
3370 #endif
3371
3372 /**
3373 * arm_register_pre_el_change_hook:
3374 * Register a hook function which will be called immediately before this
3375 * CPU changes exception level or mode. The hook function will be
3376 * passed a pointer to the ARMCPU and the opaque data pointer passed
3377 * to this function when the hook was registered.
3378 *
3379 * Note that if a pre-change hook is called, any registered post-change hooks
3380 * are guaranteed to subsequently be called.
3381 */
3382 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3383 void *opaque);
3384 /**
3385 * arm_register_el_change_hook:
3386 * Register a hook function which will be called immediately after this
3387 * CPU changes exception level or mode. The hook function will be
3388 * passed a pointer to the ARMCPU and the opaque data pointer passed
3389 * to this function when the hook was registered.
3390 *
3391 * Note that any registered hooks registered here are guaranteed to be called
3392 * if pre-change hooks have been.
3393 */
3394 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3395 *opaque);
3396
3397 /**
3398 * arm_rebuild_hflags:
3399 * Rebuild the cached TBFLAGS for arbitrary changed processor state.
3400 */
3401 void arm_rebuild_hflags(CPUARMState *env);
3402
3403 /**
3404 * aa32_vfp_dreg:
3405 * Return a pointer to the Dn register within env in 32-bit mode.
3406 */
3407 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3408 {
3409 return &env->vfp.zregs[regno >> 1].d[regno & 1];
3410 }
3411
3412 /**
3413 * aa32_vfp_qreg:
3414 * Return a pointer to the Qn register within env in 32-bit mode.
3415 */
3416 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3417 {
3418 return &env->vfp.zregs[regno].d[0];
3419 }
3420
3421 /**
3422 * aa64_vfp_qreg:
3423 * Return a pointer to the Qn register within env in 64-bit mode.
3424 */
3425 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3426 {
3427 return &env->vfp.zregs[regno].d[0];
3428 }
3429
3430 /* Shared between translate-sve.c and sve_helper.c. */
3431 extern const uint64_t pred_esz_masks[4];
3432
3433 /* Helper for the macros below, validating the argument type. */
3434 static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
3435 {
3436 return x;
3437 }
3438
3439 /*
3440 * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB.
3441 * Using these should be a bit more self-documenting than using the
3442 * generic target bits directly.
3443 */
3444 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
3445