meson: target
[qemu.git] / target / arm / cpu.h
1 /*
2 * ARM virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef ARM_CPU_H
21 #define ARM_CPU_H
22
23 #include "kvm-consts.h"
24 #include "hw/registerfields.h"
25 #include "cpu-qom.h"
26 #include "exec/cpu-defs.h"
27
28 /* ARM processors have a weak memory model */
29 #define TCG_GUEST_DEFAULT_MO (0)
30
31 #ifdef TARGET_AARCH64
32 #define KVM_HAVE_MCE_INJECTION 1
33 #endif
34
35 #define EXCP_UDEF 1 /* undefined instruction */
36 #define EXCP_SWI 2 /* software interrupt */
37 #define EXCP_PREFETCH_ABORT 3
38 #define EXCP_DATA_ABORT 4
39 #define EXCP_IRQ 5
40 #define EXCP_FIQ 6
41 #define EXCP_BKPT 7
42 #define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
43 #define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
44 #define EXCP_HVC 11 /* HyperVisor Call */
45 #define EXCP_HYP_TRAP 12
46 #define EXCP_SMC 13 /* Secure Monitor Call */
47 #define EXCP_VIRQ 14
48 #define EXCP_VFIQ 15
49 #define EXCP_SEMIHOST 16 /* semihosting call */
50 #define EXCP_NOCP 17 /* v7M NOCP UsageFault */
51 #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */
52 #define EXCP_STKOF 19 /* v8M STKOF UsageFault */
53 #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */
54 #define EXCP_LSERR 21 /* v8M LSERR SecureFault */
55 #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */
56 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */
57
58 #define ARMV7M_EXCP_RESET 1
59 #define ARMV7M_EXCP_NMI 2
60 #define ARMV7M_EXCP_HARD 3
61 #define ARMV7M_EXCP_MEM 4
62 #define ARMV7M_EXCP_BUS 5
63 #define ARMV7M_EXCP_USAGE 6
64 #define ARMV7M_EXCP_SECURE 7
65 #define ARMV7M_EXCP_SVC 11
66 #define ARMV7M_EXCP_DEBUG 12
67 #define ARMV7M_EXCP_PENDSV 14
68 #define ARMV7M_EXCP_SYSTICK 15
69
70 /* For M profile, some registers are banked secure vs non-secure;
71 * these are represented as a 2-element array where the first element
72 * is the non-secure copy and the second is the secure copy.
73 * When the CPU does not have implement the security extension then
74 * only the first element is used.
75 * This means that the copy for the current security state can be
76 * accessed via env->registerfield[env->v7m.secure] (whether the security
77 * extension is implemented or not).
78 */
79 enum {
80 M_REG_NS = 0,
81 M_REG_S = 1,
82 M_REG_NUM_BANKS = 2,
83 };
84
85 /* ARM-specific interrupt pending bits. */
86 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
87 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2
88 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3
89
90 /* The usual mapping for an AArch64 system register to its AArch32
91 * counterpart is for the 32 bit world to have access to the lower
92 * half only (with writes leaving the upper half untouched). It's
93 * therefore useful to be able to pass TCG the offset of the least
94 * significant half of a uint64_t struct member.
95 */
96 #ifdef HOST_WORDS_BIGENDIAN
97 #define offsetoflow32(S, M) (offsetof(S, M) + sizeof(uint32_t))
98 #define offsetofhigh32(S, M) offsetof(S, M)
99 #else
100 #define offsetoflow32(S, M) offsetof(S, M)
101 #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t))
102 #endif
103
104 /* Meanings of the ARMCPU object's four inbound GPIO lines */
105 #define ARM_CPU_IRQ 0
106 #define ARM_CPU_FIQ 1
107 #define ARM_CPU_VIRQ 2
108 #define ARM_CPU_VFIQ 3
109
110 /* ARM-specific extra insn start words:
111 * 1: Conditional execution bits
112 * 2: Partial exception syndrome for data aborts
113 */
114 #define TARGET_INSN_START_EXTRA_WORDS 2
115
116 /* The 2nd extra word holding syndrome info for data aborts does not use
117 * the upper 6 bits nor the lower 14 bits. We mask and shift it down to
118 * help the sleb128 encoder do a better job.
119 * When restoring the CPU state, we shift it back up.
120 */
121 #define ARM_INSN_START_WORD2_MASK ((1 << 26) - 1)
122 #define ARM_INSN_START_WORD2_SHIFT 14
123
124 /* We currently assume float and double are IEEE single and double
125 precision respectively.
126 Doing runtime conversions is tricky because VFP registers may contain
127 integer values (eg. as the result of a FTOSI instruction).
128 s<2n> maps to the least significant half of d<n>
129 s<2n+1> maps to the most significant half of d<n>
130 */
131
132 /**
133 * DynamicGDBXMLInfo:
134 * @desc: Contains the XML descriptions.
135 * @num: Number of the registers in this XML seen by GDB.
136 * @data: A union with data specific to the set of registers
137 * @cpregs_keys: Array that contains the corresponding Key of
138 * a given cpreg with the same order of the cpreg
139 * in the XML description.
140 */
141 typedef struct DynamicGDBXMLInfo {
142 char *desc;
143 int num;
144 union {
145 struct {
146 uint32_t *keys;
147 } cpregs;
148 } data;
149 } DynamicGDBXMLInfo;
150
151 /* CPU state for each instance of a generic timer (in cp15 c14) */
152 typedef struct ARMGenericTimer {
153 uint64_t cval; /* Timer CompareValue register */
154 uint64_t ctl; /* Timer Control register */
155 } ARMGenericTimer;
156
157 #define GTIMER_PHYS 0
158 #define GTIMER_VIRT 1
159 #define GTIMER_HYP 2
160 #define GTIMER_SEC 3
161 #define GTIMER_HYPVIRT 4
162 #define NUM_GTIMERS 5
163
164 typedef struct {
165 uint64_t raw_tcr;
166 uint32_t mask;
167 uint32_t base_mask;
168 } TCR;
169
170 /* Define a maximum sized vector register.
171 * For 32-bit, this is a 128-bit NEON/AdvSIMD register.
172 * For 64-bit, this is a 2048-bit SVE register.
173 *
174 * Note that the mapping between S, D, and Q views of the register bank
175 * differs between AArch64 and AArch32.
176 * In AArch32:
177 * Qn = regs[n].d[1]:regs[n].d[0]
178 * Dn = regs[n / 2].d[n & 1]
179 * Sn = regs[n / 4].d[n % 4 / 2],
180 * bits 31..0 for even n, and bits 63..32 for odd n
181 * (and regs[16] to regs[31] are inaccessible)
182 * In AArch64:
183 * Zn = regs[n].d[*]
184 * Qn = regs[n].d[1]:regs[n].d[0]
185 * Dn = regs[n].d[0]
186 * Sn = regs[n].d[0] bits 31..0
187 * Hn = regs[n].d[0] bits 15..0
188 *
189 * This corresponds to the architecturally defined mapping between
190 * the two execution states, and means we do not need to explicitly
191 * map these registers when changing states.
192 *
193 * Align the data for use with TCG host vector operations.
194 */
195
196 #ifdef TARGET_AARCH64
197 # define ARM_MAX_VQ 16
198 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
199 #else
200 # define ARM_MAX_VQ 1
201 static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
202 #endif
203
204 typedef struct ARMVectorReg {
205 uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
206 } ARMVectorReg;
207
208 #ifdef TARGET_AARCH64
209 /* In AArch32 mode, predicate registers do not exist at all. */
210 typedef struct ARMPredicateReg {
211 uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
212 } ARMPredicateReg;
213
214 /* In AArch32 mode, PAC keys do not exist at all. */
215 typedef struct ARMPACKey {
216 uint64_t lo, hi;
217 } ARMPACKey;
218 #endif
219
220
221 typedef struct CPUARMState {
222 /* Regs for current mode. */
223 uint32_t regs[16];
224
225 /* 32/64 switch only happens when taking and returning from
226 * exceptions so the overlap semantics are taken care of then
227 * instead of having a complicated union.
228 */
229 /* Regs for A64 mode. */
230 uint64_t xregs[32];
231 uint64_t pc;
232 /* PSTATE isn't an architectural register for ARMv8. However, it is
233 * convenient for us to assemble the underlying state into a 32 bit format
234 * identical to the architectural format used for the SPSR. (This is also
235 * what the Linux kernel's 'pstate' field in signal handlers and KVM's
236 * 'pstate' register are.) Of the PSTATE bits:
237 * NZCV are kept in the split out env->CF/VF/NF/ZF, (which have the same
238 * semantics as for AArch32, as described in the comments on each field)
239 * nRW (also known as M[4]) is kept, inverted, in env->aarch64
240 * DAIF (exception masks) are kept in env->daif
241 * BTYPE is kept in env->btype
242 * all other bits are stored in their correct places in env->pstate
243 */
244 uint32_t pstate;
245 uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
246
247 /* Cached TBFLAGS state. See below for which bits are included. */
248 uint32_t hflags;
249
250 /* Frequently accessed CPSR bits are stored separately for efficiency.
251 This contains all the other bits. Use cpsr_{read,write} to access
252 the whole CPSR. */
253 uint32_t uncached_cpsr;
254 uint32_t spsr;
255
256 /* Banked registers. */
257 uint64_t banked_spsr[8];
258 uint32_t banked_r13[8];
259 uint32_t banked_r14[8];
260
261 /* These hold r8-r12. */
262 uint32_t usr_regs[5];
263 uint32_t fiq_regs[5];
264
265 /* cpsr flag cache for faster execution */
266 uint32_t CF; /* 0 or 1 */
267 uint32_t VF; /* V is the bit 31. All other bits are undefined */
268 uint32_t NF; /* N is bit 31. All other bits are undefined. */
269 uint32_t ZF; /* Z set if zero. */
270 uint32_t QF; /* 0 or 1 */
271 uint32_t GE; /* cpsr[19:16] */
272 uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
273 uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */
274 uint32_t btype; /* BTI branch type. spsr[11:10]. */
275 uint64_t daif; /* exception masks, in the bits they are in PSTATE */
276
277 uint64_t elr_el[4]; /* AArch64 exception link regs */
278 uint64_t sp_el[4]; /* AArch64 banked stack pointers */
279
280 /* System control coprocessor (cp15) */
281 struct {
282 uint32_t c0_cpuid;
283 union { /* Cache size selection */
284 struct {
285 uint64_t _unused_csselr0;
286 uint64_t csselr_ns;
287 uint64_t _unused_csselr1;
288 uint64_t csselr_s;
289 };
290 uint64_t csselr_el[4];
291 };
292 union { /* System control register. */
293 struct {
294 uint64_t _unused_sctlr;
295 uint64_t sctlr_ns;
296 uint64_t hsctlr;
297 uint64_t sctlr_s;
298 };
299 uint64_t sctlr_el[4];
300 };
301 uint64_t cpacr_el1; /* Architectural feature access control register */
302 uint64_t cptr_el[4]; /* ARMv8 feature trap registers */
303 uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
304 uint64_t sder; /* Secure debug enable register. */
305 uint32_t nsacr; /* Non-secure access control register. */
306 union { /* MMU translation table base 0. */
307 struct {
308 uint64_t _unused_ttbr0_0;
309 uint64_t ttbr0_ns;
310 uint64_t _unused_ttbr0_1;
311 uint64_t ttbr0_s;
312 };
313 uint64_t ttbr0_el[4];
314 };
315 union { /* MMU translation table base 1. */
316 struct {
317 uint64_t _unused_ttbr1_0;
318 uint64_t ttbr1_ns;
319 uint64_t _unused_ttbr1_1;
320 uint64_t ttbr1_s;
321 };
322 uint64_t ttbr1_el[4];
323 };
324 uint64_t vttbr_el2; /* Virtualization Translation Table Base. */
325 /* MMU translation table base control. */
326 TCR tcr_el[4];
327 TCR vtcr_el2; /* Virtualization Translation Control. */
328 uint32_t c2_data; /* MPU data cacheable bits. */
329 uint32_t c2_insn; /* MPU instruction cacheable bits. */
330 union { /* MMU domain access control register
331 * MPU write buffer control.
332 */
333 struct {
334 uint64_t dacr_ns;
335 uint64_t dacr_s;
336 };
337 struct {
338 uint64_t dacr32_el2;
339 };
340 };
341 uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
342 uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
343 uint64_t hcr_el2; /* Hypervisor configuration register */
344 uint64_t scr_el3; /* Secure configuration register. */
345 union { /* Fault status registers. */
346 struct {
347 uint64_t ifsr_ns;
348 uint64_t ifsr_s;
349 };
350 struct {
351 uint64_t ifsr32_el2;
352 };
353 };
354 union {
355 struct {
356 uint64_t _unused_dfsr;
357 uint64_t dfsr_ns;
358 uint64_t hsr;
359 uint64_t dfsr_s;
360 };
361 uint64_t esr_el[4];
362 };
363 uint32_t c6_region[8]; /* MPU base/size registers. */
364 union { /* Fault address registers. */
365 struct {
366 uint64_t _unused_far0;
367 #ifdef HOST_WORDS_BIGENDIAN
368 uint32_t ifar_ns;
369 uint32_t dfar_ns;
370 uint32_t ifar_s;
371 uint32_t dfar_s;
372 #else
373 uint32_t dfar_ns;
374 uint32_t ifar_ns;
375 uint32_t dfar_s;
376 uint32_t ifar_s;
377 #endif
378 uint64_t _unused_far3;
379 };
380 uint64_t far_el[4];
381 };
382 uint64_t hpfar_el2;
383 uint64_t hstr_el2;
384 union { /* Translation result. */
385 struct {
386 uint64_t _unused_par_0;
387 uint64_t par_ns;
388 uint64_t _unused_par_1;
389 uint64_t par_s;
390 };
391 uint64_t par_el[4];
392 };
393
394 uint32_t c9_insn; /* Cache lockdown registers. */
395 uint32_t c9_data;
396 uint64_t c9_pmcr; /* performance monitor control register */
397 uint64_t c9_pmcnten; /* perf monitor counter enables */
398 uint64_t c9_pmovsr; /* perf monitor overflow status */
399 uint64_t c9_pmuserenr; /* perf monitor user enable */
400 uint64_t c9_pmselr; /* perf monitor counter selection register */
401 uint64_t c9_pminten; /* perf monitor interrupt enables */
402 union { /* Memory attribute redirection */
403 struct {
404 #ifdef HOST_WORDS_BIGENDIAN
405 uint64_t _unused_mair_0;
406 uint32_t mair1_ns;
407 uint32_t mair0_ns;
408 uint64_t _unused_mair_1;
409 uint32_t mair1_s;
410 uint32_t mair0_s;
411 #else
412 uint64_t _unused_mair_0;
413 uint32_t mair0_ns;
414 uint32_t mair1_ns;
415 uint64_t _unused_mair_1;
416 uint32_t mair0_s;
417 uint32_t mair1_s;
418 #endif
419 };
420 uint64_t mair_el[4];
421 };
422 union { /* vector base address register */
423 struct {
424 uint64_t _unused_vbar;
425 uint64_t vbar_ns;
426 uint64_t hvbar;
427 uint64_t vbar_s;
428 };
429 uint64_t vbar_el[4];
430 };
431 uint32_t mvbar; /* (monitor) vector base address register */
432 struct { /* FCSE PID. */
433 uint32_t fcseidr_ns;
434 uint32_t fcseidr_s;
435 };
436 union { /* Context ID. */
437 struct {
438 uint64_t _unused_contextidr_0;
439 uint64_t contextidr_ns;
440 uint64_t _unused_contextidr_1;
441 uint64_t contextidr_s;
442 };
443 uint64_t contextidr_el[4];
444 };
445 union { /* User RW Thread register. */
446 struct {
447 uint64_t tpidrurw_ns;
448 uint64_t tpidrprw_ns;
449 uint64_t htpidr;
450 uint64_t _tpidr_el3;
451 };
452 uint64_t tpidr_el[4];
453 };
454 /* The secure banks of these registers don't map anywhere */
455 uint64_t tpidrurw_s;
456 uint64_t tpidrprw_s;
457 uint64_t tpidruro_s;
458
459 union { /* User RO Thread register. */
460 uint64_t tpidruro_ns;
461 uint64_t tpidrro_el[1];
462 };
463 uint64_t c14_cntfrq; /* Counter Frequency register */
464 uint64_t c14_cntkctl; /* Timer Control register */
465 uint32_t cnthctl_el2; /* Counter/Timer Hyp Control register */
466 uint64_t cntvoff_el2; /* Counter Virtual Offset register */
467 ARMGenericTimer c14_timer[NUM_GTIMERS];
468 uint32_t c15_cpar; /* XScale Coprocessor Access Register */
469 uint32_t c15_ticonfig; /* TI925T configuration byte. */
470 uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
471 uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
472 uint32_t c15_threadid; /* TI debugger thread-ID. */
473 uint32_t c15_config_base_address; /* SCU base address. */
474 uint32_t c15_diagnostic; /* diagnostic register */
475 uint32_t c15_power_diagnostic;
476 uint32_t c15_power_control; /* power control */
477 uint64_t dbgbvr[16]; /* breakpoint value registers */
478 uint64_t dbgbcr[16]; /* breakpoint control registers */
479 uint64_t dbgwvr[16]; /* watchpoint value registers */
480 uint64_t dbgwcr[16]; /* watchpoint control registers */
481 uint64_t mdscr_el1;
482 uint64_t oslsr_el1; /* OS Lock Status */
483 uint64_t mdcr_el2;
484 uint64_t mdcr_el3;
485 /* Stores the architectural value of the counter *the last time it was
486 * updated* by pmccntr_op_start. Accesses should always be surrounded
487 * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest
488 * architecturally-correct value is being read/set.
489 */
490 uint64_t c15_ccnt;
491 /* Stores the delta between the architectural value and the underlying
492 * cycle count during normal operation. It is used to update c15_ccnt
493 * to be the correct architectural value before accesses. During
494 * accesses, c15_ccnt_delta contains the underlying count being used
495 * for the access, after which it reverts to the delta value in
496 * pmccntr_op_finish.
497 */
498 uint64_t c15_ccnt_delta;
499 uint64_t c14_pmevcntr[31];
500 uint64_t c14_pmevcntr_delta[31];
501 uint64_t c14_pmevtyper[31];
502 uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
503 uint64_t vpidr_el2; /* Virtualization Processor ID Register */
504 uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
505 uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */
506 uint64_t gcr_el1;
507 uint64_t rgsr_el1;
508 } cp15;
509
510 struct {
511 /* M profile has up to 4 stack pointers:
512 * a Main Stack Pointer and a Process Stack Pointer for each
513 * of the Secure and Non-Secure states. (If the CPU doesn't support
514 * the security extension then it has only two SPs.)
515 * In QEMU we always store the currently active SP in regs[13],
516 * and the non-active SP for the current security state in
517 * v7m.other_sp. The stack pointers for the inactive security state
518 * are stored in other_ss_msp and other_ss_psp.
519 * switch_v7m_security_state() is responsible for rearranging them
520 * when we change security state.
521 */
522 uint32_t other_sp;
523 uint32_t other_ss_msp;
524 uint32_t other_ss_psp;
525 uint32_t vecbase[M_REG_NUM_BANKS];
526 uint32_t basepri[M_REG_NUM_BANKS];
527 uint32_t control[M_REG_NUM_BANKS];
528 uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */
529 uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */
530 uint32_t hfsr; /* HardFault Status */
531 uint32_t dfsr; /* Debug Fault Status Register */
532 uint32_t sfsr; /* Secure Fault Status Register */
533 uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */
534 uint32_t bfar; /* BusFault Address */
535 uint32_t sfar; /* Secure Fault Address Register */
536 unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */
537 int exception;
538 uint32_t primask[M_REG_NUM_BANKS];
539 uint32_t faultmask[M_REG_NUM_BANKS];
540 uint32_t aircr; /* only holds r/w state if security extn implemented */
541 uint32_t secure; /* Is CPU in Secure state? (not guest visible) */
542 uint32_t csselr[M_REG_NUM_BANKS];
543 uint32_t scr[M_REG_NUM_BANKS];
544 uint32_t msplim[M_REG_NUM_BANKS];
545 uint32_t psplim[M_REG_NUM_BANKS];
546 uint32_t fpcar[M_REG_NUM_BANKS];
547 uint32_t fpccr[M_REG_NUM_BANKS];
548 uint32_t fpdscr[M_REG_NUM_BANKS];
549 uint32_t cpacr[M_REG_NUM_BANKS];
550 uint32_t nsacr;
551 } v7m;
552
553 /* Information associated with an exception about to be taken:
554 * code which raises an exception must set cs->exception_index and
555 * the relevant parts of this structure; the cpu_do_interrupt function
556 * will then set the guest-visible registers as part of the exception
557 * entry process.
558 */
559 struct {
560 uint32_t syndrome; /* AArch64 format syndrome register */
561 uint32_t fsr; /* AArch32 format fault status register info */
562 uint64_t vaddress; /* virtual addr associated with exception, if any */
563 uint32_t target_el; /* EL the exception should be targeted for */
564 /* If we implement EL2 we will also need to store information
565 * about the intermediate physical address for stage 2 faults.
566 */
567 } exception;
568
569 /* Information associated with an SError */
570 struct {
571 uint8_t pending;
572 uint8_t has_esr;
573 uint64_t esr;
574 } serror;
575
576 uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
577
578 /* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
579 uint32_t irq_line_state;
580
581 /* Thumb-2 EE state. */
582 uint32_t teecr;
583 uint32_t teehbr;
584
585 /* VFP coprocessor state. */
586 struct {
587 ARMVectorReg zregs[32];
588
589 #ifdef TARGET_AARCH64
590 /* Store FFR as pregs[16] to make it easier to treat as any other. */
591 #define FFR_PRED_NUM 16
592 ARMPredicateReg pregs[17];
593 /* Scratch space for aa64 sve predicate temporary. */
594 ARMPredicateReg preg_tmp;
595 #endif
596
597 /* We store these fpcsr fields separately for convenience. */
598 uint32_t qc[4] QEMU_ALIGNED(16);
599 int vec_len;
600 int vec_stride;
601
602 uint32_t xregs[16];
603
604 /* Scratch space for aa32 neon expansion. */
605 uint32_t scratch[8];
606
607 /* There are a number of distinct float control structures:
608 *
609 * fp_status: is the "normal" fp status.
610 * fp_status_fp16: used for half-precision calculations
611 * standard_fp_status : the ARM "Standard FPSCR Value"
612 *
613 * Half-precision operations are governed by a separate
614 * flush-to-zero control bit in FPSCR:FZ16. We pass a separate
615 * status structure to control this.
616 *
617 * The "Standard FPSCR", ie default-NaN, flush-to-zero,
618 * round-to-nearest and is used by any operations (generally
619 * Neon) which the architecture defines as controlled by the
620 * standard FPSCR value rather than the FPSCR.
621 *
622 * To avoid having to transfer exception bits around, we simply
623 * say that the FPSCR cumulative exception flags are the logical
624 * OR of the flags in the three fp statuses. This relies on the
625 * only thing which needs to read the exception flags being
626 * an explicit FPSCR read.
627 */
628 float_status fp_status;
629 float_status fp_status_f16;
630 float_status standard_fp_status;
631
632 /* ZCR_EL[1-3] */
633 uint64_t zcr_el[4];
634 } vfp;
635 uint64_t exclusive_addr;
636 uint64_t exclusive_val;
637 uint64_t exclusive_high;
638
639 /* iwMMXt coprocessor state. */
640 struct {
641 uint64_t regs[16];
642 uint64_t val;
643
644 uint32_t cregs[16];
645 } iwmmxt;
646
647 #ifdef TARGET_AARCH64
648 struct {
649 ARMPACKey apia;
650 ARMPACKey apib;
651 ARMPACKey apda;
652 ARMPACKey apdb;
653 ARMPACKey apga;
654 } keys;
655 #endif
656
657 #if defined(CONFIG_USER_ONLY)
658 /* For usermode syscall translation. */
659 int eabi;
660 #endif
661
662 struct CPUBreakpoint *cpu_breakpoint[16];
663 struct CPUWatchpoint *cpu_watchpoint[16];
664
665 /* Fields up to this point are cleared by a CPU reset */
666 struct {} end_reset_fields;
667
668 /* Fields after this point are preserved across CPU reset. */
669
670 /* Internal CPU feature flags. */
671 uint64_t features;
672
673 /* PMSAv7 MPU */
674 struct {
675 uint32_t *drbar;
676 uint32_t *drsr;
677 uint32_t *dracr;
678 uint32_t rnr[M_REG_NUM_BANKS];
679 } pmsav7;
680
681 /* PMSAv8 MPU */
682 struct {
683 /* The PMSAv8 implementation also shares some PMSAv7 config
684 * and state:
685 * pmsav7.rnr (region number register)
686 * pmsav7_dregion (number of configured regions)
687 */
688 uint32_t *rbar[M_REG_NUM_BANKS];
689 uint32_t *rlar[M_REG_NUM_BANKS];
690 uint32_t mair0[M_REG_NUM_BANKS];
691 uint32_t mair1[M_REG_NUM_BANKS];
692 } pmsav8;
693
694 /* v8M SAU */
695 struct {
696 uint32_t *rbar;
697 uint32_t *rlar;
698 uint32_t rnr;
699 uint32_t ctrl;
700 } sau;
701
702 void *nvic;
703 const struct arm_boot_info *boot_info;
704 /* Store GICv3CPUState to access from this struct */
705 void *gicv3state;
706 } CPUARMState;
707
708 static inline void set_feature(CPUARMState *env, int feature)
709 {
710 env->features |= 1ULL << feature;
711 }
712
713 static inline void unset_feature(CPUARMState *env, int feature)
714 {
715 env->features &= ~(1ULL << feature);
716 }
717
718 /**
719 * ARMELChangeHookFn:
720 * type of a function which can be registered via arm_register_el_change_hook()
721 * to get callbacks when the CPU changes its exception level or mode.
722 */
723 typedef void ARMELChangeHookFn(ARMCPU *cpu, void *opaque);
724 typedef struct ARMELChangeHook ARMELChangeHook;
725 struct ARMELChangeHook {
726 ARMELChangeHookFn *hook;
727 void *opaque;
728 QLIST_ENTRY(ARMELChangeHook) node;
729 };
730
731 /* These values map onto the return values for
732 * QEMU_PSCI_0_2_FN_AFFINITY_INFO */
733 typedef enum ARMPSCIState {
734 PSCI_ON = 0,
735 PSCI_OFF = 1,
736 PSCI_ON_PENDING = 2
737 } ARMPSCIState;
738
739 typedef struct ARMISARegisters ARMISARegisters;
740
741 /**
742 * ARMCPU:
743 * @env: #CPUARMState
744 *
745 * An ARM CPU core.
746 */
747 struct ARMCPU {
748 /*< private >*/
749 CPUState parent_obj;
750 /*< public >*/
751
752 CPUNegativeOffsetState neg;
753 CPUARMState env;
754
755 /* Coprocessor information */
756 GHashTable *cp_regs;
757 /* For marshalling (mostly coprocessor) register state between the
758 * kernel and QEMU (for KVM) and between two QEMUs (for migration),
759 * we use these arrays.
760 */
761 /* List of register indexes managed via these arrays; (full KVM style
762 * 64 bit indexes, not CPRegInfo 32 bit indexes)
763 */
764 uint64_t *cpreg_indexes;
765 /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i]) */
766 uint64_t *cpreg_values;
767 /* Length of the indexes, values, reset_values arrays */
768 int32_t cpreg_array_len;
769 /* These are used only for migration: incoming data arrives in
770 * these fields and is sanity checked in post_load before copying
771 * to the working data structures above.
772 */
773 uint64_t *cpreg_vmstate_indexes;
774 uint64_t *cpreg_vmstate_values;
775 int32_t cpreg_vmstate_array_len;
776
777 DynamicGDBXMLInfo dyn_sysreg_xml;
778 DynamicGDBXMLInfo dyn_svereg_xml;
779
780 /* Timers used by the generic (architected) timer */
781 QEMUTimer *gt_timer[NUM_GTIMERS];
782 /*
783 * Timer used by the PMU. Its state is restored after migration by
784 * pmu_op_finish() - it does not need other handling during migration
785 */
786 QEMUTimer *pmu_timer;
787 /* GPIO outputs for generic timer */
788 qemu_irq gt_timer_outputs[NUM_GTIMERS];
789 /* GPIO output for GICv3 maintenance interrupt signal */
790 qemu_irq gicv3_maintenance_interrupt;
791 /* GPIO output for the PMU interrupt */
792 qemu_irq pmu_interrupt;
793
794 /* MemoryRegion to use for secure physical accesses */
795 MemoryRegion *secure_memory;
796
797 /* MemoryRegion to use for allocation tag accesses */
798 MemoryRegion *tag_memory;
799 MemoryRegion *secure_tag_memory;
800
801 /* For v8M, pointer to the IDAU interface provided by board/SoC */
802 Object *idau;
803
804 /* 'compatible' string for this CPU for Linux device trees */
805 const char *dtb_compatible;
806
807 /* PSCI version for this CPU
808 * Bits[31:16] = Major Version
809 * Bits[15:0] = Minor Version
810 */
811 uint32_t psci_version;
812
813 /* Should CPU start in PSCI powered-off state? */
814 bool start_powered_off;
815
816 /* Current power state, access guarded by BQL */
817 ARMPSCIState power_state;
818
819 /* CPU has virtualization extension */
820 bool has_el2;
821 /* CPU has security extension */
822 bool has_el3;
823 /* CPU has PMU (Performance Monitor Unit) */
824 bool has_pmu;
825 /* CPU has VFP */
826 bool has_vfp;
827 /* CPU has Neon */
828 bool has_neon;
829 /* CPU has M-profile DSP extension */
830 bool has_dsp;
831
832 /* CPU has memory protection unit */
833 bool has_mpu;
834 /* PMSAv7 MPU number of supported regions */
835 uint32_t pmsav7_dregion;
836 /* v8M SAU number of supported regions */
837 uint32_t sau_sregion;
838
839 /* PSCI conduit used to invoke PSCI methods
840 * 0 - disabled, 1 - smc, 2 - hvc
841 */
842 uint32_t psci_conduit;
843
844 /* For v8M, initial value of the Secure VTOR */
845 uint32_t init_svtor;
846
847 /* [QEMU_]KVM_ARM_TARGET_* constant for this CPU, or
848 * QEMU_KVM_ARM_TARGET_NONE if the kernel doesn't support this CPU type.
849 */
850 uint32_t kvm_target;
851
852 /* KVM init features for this CPU */
853 uint32_t kvm_init_features[7];
854
855 /* KVM CPU state */
856
857 /* KVM virtual time adjustment */
858 bool kvm_adjvtime;
859 bool kvm_vtime_dirty;
860 uint64_t kvm_vtime;
861
862 /* Uniprocessor system with MP extensions */
863 bool mp_is_up;
864
865 /* True if we tried kvm_arm_host_cpu_features() during CPU instance_init
866 * and the probe failed (so we need to report the error in realize)
867 */
868 bool host_cpu_probe_failed;
869
870 /* Specify the number of cores in this CPU cluster. Used for the L2CTLR
871 * register.
872 */
873 int32_t core_count;
874
875 /* The instance init functions for implementation-specific subclasses
876 * set these fields to specify the implementation-dependent values of
877 * various constant registers and reset values of non-constant
878 * registers.
879 * Some of these might become QOM properties eventually.
880 * Field names match the official register names as defined in the
881 * ARMv7AR ARM Architecture Reference Manual. A reset_ prefix
882 * is used for reset values of non-constant registers; no reset_
883 * prefix means a constant register.
884 * Some of these registers are split out into a substructure that
885 * is shared with the translators to control the ISA.
886 *
887 * Note that if you add an ID register to the ARMISARegisters struct
888 * you need to also update the 32-bit and 64-bit versions of the
889 * kvm_arm_get_host_cpu_features() function to correctly populate the
890 * field by reading the value from the KVM vCPU.
891 */
892 struct ARMISARegisters {
893 uint32_t id_isar0;
894 uint32_t id_isar1;
895 uint32_t id_isar2;
896 uint32_t id_isar3;
897 uint32_t id_isar4;
898 uint32_t id_isar5;
899 uint32_t id_isar6;
900 uint32_t id_mmfr0;
901 uint32_t id_mmfr1;
902 uint32_t id_mmfr2;
903 uint32_t id_mmfr3;
904 uint32_t id_mmfr4;
905 uint32_t mvfr0;
906 uint32_t mvfr1;
907 uint32_t mvfr2;
908 uint32_t id_dfr0;
909 uint32_t dbgdidr;
910 uint64_t id_aa64isar0;
911 uint64_t id_aa64isar1;
912 uint64_t id_aa64pfr0;
913 uint64_t id_aa64pfr1;
914 uint64_t id_aa64mmfr0;
915 uint64_t id_aa64mmfr1;
916 uint64_t id_aa64mmfr2;
917 uint64_t id_aa64dfr0;
918 uint64_t id_aa64dfr1;
919 } isar;
920 uint64_t midr;
921 uint32_t revidr;
922 uint32_t reset_fpsid;
923 uint32_t ctr;
924 uint32_t reset_sctlr;
925 uint32_t id_pfr0;
926 uint32_t id_pfr1;
927 uint64_t pmceid0;
928 uint64_t pmceid1;
929 uint32_t id_afr0;
930 uint64_t id_aa64afr0;
931 uint64_t id_aa64afr1;
932 uint32_t clidr;
933 uint64_t mp_affinity; /* MP ID without feature bits */
934 /* The elements of this array are the CCSIDR values for each cache,
935 * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
936 */
937 uint64_t ccsidr[16];
938 uint64_t reset_cbar;
939 uint32_t reset_auxcr;
940 bool reset_hivecs;
941 /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
942 uint32_t dcz_blocksize;
943 uint64_t rvbar;
944
945 /* Configurable aspects of GIC cpu interface (which is part of the CPU) */
946 int gic_num_lrs; /* number of list registers */
947 int gic_vpribits; /* number of virtual priority bits */
948 int gic_vprebits; /* number of virtual preemption bits */
949
950 /* Whether the cfgend input is high (i.e. this CPU should reset into
951 * big-endian mode). This setting isn't used directly: instead it modifies
952 * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
953 * architecture version.
954 */
955 bool cfgend;
956
957 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
958 QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
959
960 int32_t node_id; /* NUMA node this CPU belongs to */
961
962 /* Used to synchronize KVM and QEMU in-kernel device levels */
963 uint8_t device_irq_level;
964
965 /* Used to set the maximum vector length the cpu will support. */
966 uint32_t sve_max_vq;
967
968 /*
969 * In sve_vq_map each set bit is a supported vector length of
970 * (bit-number + 1) * 16 bytes, i.e. each bit number + 1 is the vector
971 * length in quadwords.
972 *
973 * While processing properties during initialization, corresponding
974 * sve_vq_init bits are set for bits in sve_vq_map that have been
975 * set by properties.
976 */
977 DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ);
978 DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ);
979
980 /* Generic timer counter frequency, in Hz */
981 uint64_t gt_cntfrq_hz;
982 };
983
984 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
985
986 void arm_cpu_post_init(Object *obj);
987
988 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
989
990 #ifndef CONFIG_USER_ONLY
991 extern const VMStateDescription vmstate_arm_cpu;
992 #endif
993
994 void arm_cpu_do_interrupt(CPUState *cpu);
995 void arm_v7m_cpu_do_interrupt(CPUState *cpu);
996 bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
997
998 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
999 MemTxAttrs *attrs);
1000
1001 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1002 int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1003
1004 /*
1005 * Helpers to dynamically generates XML descriptions of the sysregs
1006 * and SVE registers. Returns the number of registers in each set.
1007 */
1008 int arm_gen_dynamic_sysreg_xml(CPUState *cpu, int base_reg);
1009 int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);
1010
1011 /* Returns the dynamically generated XML for the gdb stub.
1012 * Returns a pointer to the XML contents for the specified XML file or NULL
1013 * if the XML name doesn't match the predefined one.
1014 */
1015 const char *arm_gdb_get_dynamic_xml(CPUState *cpu, const char *xmlname);
1016
1017 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
1018 int cpuid, void *opaque);
1019 int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
1020 int cpuid, void *opaque);
1021
1022 #ifdef TARGET_AARCH64
1023 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1024 int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1025 void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
1026 void aarch64_sve_change_el(CPUARMState *env, int old_el,
1027 int new_el, bool el0_a64);
1028 void aarch64_add_sve_properties(Object *obj);
1029
1030 /*
1031 * SVE registers are encoded in KVM's memory in an endianness-invariant format.
1032 * The byte at offset i from the start of the in-memory representation contains
1033 * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
1034 * lowest offsets are stored in the lowest memory addresses, then that nearly
1035 * matches QEMU's representation, which is to use an array of host-endian
1036 * uint64_t's, where the lower offsets are at the lower indices. To complete
1037 * the translation we just need to byte swap the uint64_t's on big-endian hosts.
1038 */
1039 static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
1040 {
1041 #ifdef HOST_WORDS_BIGENDIAN
1042 int i;
1043
1044 for (i = 0; i < nr; ++i) {
1045 dst[i] = bswap64(src[i]);
1046 }
1047
1048 return dst;
1049 #else
1050 return src;
1051 #endif
1052 }
1053
1054 #else
1055 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
1056 static inline void aarch64_sve_change_el(CPUARMState *env, int o,
1057 int n, bool a)
1058 { }
1059 static inline void aarch64_add_sve_properties(Object *obj) { }
1060 #endif
1061
1062 #if !defined(CONFIG_TCG)
1063 static inline target_ulong do_arm_semihosting(CPUARMState *env)
1064 {
1065 g_assert_not_reached();
1066 }
1067 #else
1068 target_ulong do_arm_semihosting(CPUARMState *env);
1069 #endif
1070 void aarch64_sync_32_to_64(CPUARMState *env);
1071 void aarch64_sync_64_to_32(CPUARMState *env);
1072
1073 int fp_exception_el(CPUARMState *env, int cur_el);
1074 int sve_exception_el(CPUARMState *env, int cur_el);
1075 uint32_t sve_zcr_len_for_el(CPUARMState *env, int el);
1076
1077 static inline bool is_a64(CPUARMState *env)
1078 {
1079 return env->aarch64;
1080 }
1081
1082 /* you can call this signal handler from your SIGBUS and SIGSEGV
1083 signal handlers to inform the virtual CPU of exceptions. non zero
1084 is returned if the signal was handled by the virtual CPU. */
1085 int cpu_arm_signal_handler(int host_signum, void *pinfo,
1086 void *puc);
1087
1088 /**
1089 * pmu_op_start/finish
1090 * @env: CPUARMState
1091 *
1092 * Convert all PMU counters between their delta form (the typical mode when
1093 * they are enabled) and the guest-visible values. These two calls must
1094 * surround any action which might affect the counters.
1095 */
1096 void pmu_op_start(CPUARMState *env);
1097 void pmu_op_finish(CPUARMState *env);
1098
1099 /*
1100 * Called when a PMU counter is due to overflow
1101 */
1102 void arm_pmu_timer_cb(void *opaque);
1103
1104 /**
1105 * Functions to register as EL change hooks for PMU mode filtering
1106 */
1107 void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
1108 void pmu_post_el_change(ARMCPU *cpu, void *ignored);
1109
1110 /*
1111 * pmu_init
1112 * @cpu: ARMCPU
1113 *
1114 * Initialize the CPU's PMCEID[01]_EL0 registers and associated internal state
1115 * for the current configuration
1116 */
1117 void pmu_init(ARMCPU *cpu);
1118
1119 /* SCTLR bit meanings. Several bits have been reused in newer
1120 * versions of the architecture; in that case we define constants
1121 * for both old and new bit meanings. Code which tests against those
1122 * bits should probably check or otherwise arrange that the CPU
1123 * is the architectural version it expects.
1124 */
1125 #define SCTLR_M (1U << 0)
1126 #define SCTLR_A (1U << 1)
1127 #define SCTLR_C (1U << 2)
1128 #define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
1129 #define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
1130 #define SCTLR_SA (1U << 3) /* AArch64 only */
1131 #define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
1132 #define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
1133 #define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
1134 #define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
1135 #define SCTLR_CP15BEN (1U << 5) /* v7 onward */
1136 #define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
1137 #define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */
1138 #define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
1139 #define SCTLR_ITD (1U << 7) /* v8 onward */
1140 #define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
1141 #define SCTLR_SED (1U << 8) /* v8 onward */
1142 #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
1143 #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
1144 #define SCTLR_F (1U << 10) /* up to v6 */
1145 #define SCTLR_SW (1U << 10) /* v7 */
1146 #define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */
1147 #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */
1148 #define SCTLR_EOS (1U << 11) /* v8.5-ExS */
1149 #define SCTLR_I (1U << 12)
1150 #define SCTLR_V (1U << 13) /* AArch32 only */
1151 #define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */
1152 #define SCTLR_RR (1U << 14) /* up to v7 */
1153 #define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
1154 #define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
1155 #define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
1156 #define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
1157 #define SCTLR_nTWI (1U << 16) /* v8 onward */
1158 #define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */
1159 #define SCTLR_BR (1U << 17) /* PMSA only */
1160 #define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
1161 #define SCTLR_nTWE (1U << 18) /* v8 onward */
1162 #define SCTLR_WXN (1U << 19)
1163 #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
1164 #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */
1165 #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */
1166 #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
1167 #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */
1168 #define SCTLR_EIS (1U << 22) /* v8.5-ExS */
1169 #define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
1170 #define SCTLR_SPAN (1U << 23) /* v8.1-PAN */
1171 #define SCTLR_VE (1U << 24) /* up to v7 */
1172 #define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
1173 #define SCTLR_EE (1U << 25)
1174 #define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
1175 #define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
1176 #define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */
1177 #define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */
1178 #define SCTLR_TRE (1U << 28) /* AArch32 only */
1179 #define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
1180 #define SCTLR_AFE (1U << 29) /* AArch32 only */
1181 #define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
1182 #define SCTLR_TE (1U << 30) /* AArch32 only */
1183 #define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */
1184 #define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */
1185 #define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
1186 #define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
1187 #define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
1188 #define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */
1189 #define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */
1190 #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
1191 #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
1192 #define SCTLR_DSSBS (1ULL << 44) /* v8.5 */
1193
1194 #define CPTR_TCPAC (1U << 31)
1195 #define CPTR_TTA (1U << 20)
1196 #define CPTR_TFP (1U << 10)
1197 #define CPTR_TZ (1U << 8) /* CPTR_EL2 */
1198 #define CPTR_EZ (1U << 8) /* CPTR_EL3 */
1199
1200 #define MDCR_EPMAD (1U << 21)
1201 #define MDCR_EDAD (1U << 20)
1202 #define MDCR_SPME (1U << 17) /* MDCR_EL3 */
1203 #define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
1204 #define MDCR_SDD (1U << 16)
1205 #define MDCR_SPD (3U << 14)
1206 #define MDCR_TDRA (1U << 11)
1207 #define MDCR_TDOSA (1U << 10)
1208 #define MDCR_TDA (1U << 9)
1209 #define MDCR_TDE (1U << 8)
1210 #define MDCR_HPME (1U << 7)
1211 #define MDCR_TPM (1U << 6)
1212 #define MDCR_TPMCR (1U << 5)
1213 #define MDCR_HPMN (0x1fU)
1214
1215 /* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
1216 #define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
1217
1218 #define CPSR_M (0x1fU)
1219 #define CPSR_T (1U << 5)
1220 #define CPSR_F (1U << 6)
1221 #define CPSR_I (1U << 7)
1222 #define CPSR_A (1U << 8)
1223 #define CPSR_E (1U << 9)
1224 #define CPSR_IT_2_7 (0xfc00U)
1225 #define CPSR_GE (0xfU << 16)
1226 #define CPSR_IL (1U << 20)
1227 #define CPSR_PAN (1U << 22)
1228 #define CPSR_J (1U << 24)
1229 #define CPSR_IT_0_1 (3U << 25)
1230 #define CPSR_Q (1U << 27)
1231 #define CPSR_V (1U << 28)
1232 #define CPSR_C (1U << 29)
1233 #define CPSR_Z (1U << 30)
1234 #define CPSR_N (1U << 31)
1235 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
1236 #define CPSR_AIF (CPSR_A | CPSR_I | CPSR_F)
1237
1238 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
1239 #define CACHED_CPSR_BITS (CPSR_T | CPSR_AIF | CPSR_GE | CPSR_IT | CPSR_Q \
1240 | CPSR_NZCV)
1241 /* Bits writable in user mode. */
1242 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE | CPSR_E)
1243 /* Execution state bits. MRS read as zero, MSR writes ignored. */
1244 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J | CPSR_IL)
1245
1246 /* Bit definitions for M profile XPSR. Most are the same as CPSR. */
1247 #define XPSR_EXCP 0x1ffU
1248 #define XPSR_SPREALIGN (1U << 9) /* Only set in exception stack frames */
1249 #define XPSR_IT_2_7 CPSR_IT_2_7
1250 #define XPSR_GE CPSR_GE
1251 #define XPSR_SFPA (1U << 20) /* Only set in exception stack frames */
1252 #define XPSR_T (1U << 24) /* Not the same as CPSR_T ! */
1253 #define XPSR_IT_0_1 CPSR_IT_0_1
1254 #define XPSR_Q CPSR_Q
1255 #define XPSR_V CPSR_V
1256 #define XPSR_C CPSR_C
1257 #define XPSR_Z CPSR_Z
1258 #define XPSR_N CPSR_N
1259 #define XPSR_NZCV CPSR_NZCV
1260 #define XPSR_IT CPSR_IT
1261
1262 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
1263 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
1264 #define TTBCR_PD0 (1U << 4)
1265 #define TTBCR_PD1 (1U << 5)
1266 #define TTBCR_EPD0 (1U << 7)
1267 #define TTBCR_IRGN0 (3U << 8)
1268 #define TTBCR_ORGN0 (3U << 10)
1269 #define TTBCR_SH0 (3U << 12)
1270 #define TTBCR_T1SZ (3U << 16)
1271 #define TTBCR_A1 (1U << 22)
1272 #define TTBCR_EPD1 (1U << 23)
1273 #define TTBCR_IRGN1 (3U << 24)
1274 #define TTBCR_ORGN1 (3U << 26)
1275 #define TTBCR_SH1 (1U << 28)
1276 #define TTBCR_EAE (1U << 31)
1277
1278 /* Bit definitions for ARMv8 SPSR (PSTATE) format.
1279 * Only these are valid when in AArch64 mode; in
1280 * AArch32 mode SPSRs are basically CPSR-format.
1281 */
1282 #define PSTATE_SP (1U)
1283 #define PSTATE_M (0xFU)
1284 #define PSTATE_nRW (1U << 4)
1285 #define PSTATE_F (1U << 6)
1286 #define PSTATE_I (1U << 7)
1287 #define PSTATE_A (1U << 8)
1288 #define PSTATE_D (1U << 9)
1289 #define PSTATE_BTYPE (3U << 10)
1290 #define PSTATE_IL (1U << 20)
1291 #define PSTATE_SS (1U << 21)
1292 #define PSTATE_PAN (1U << 22)
1293 #define PSTATE_UAO (1U << 23)
1294 #define PSTATE_TCO (1U << 25)
1295 #define PSTATE_V (1U << 28)
1296 #define PSTATE_C (1U << 29)
1297 #define PSTATE_Z (1U << 30)
1298 #define PSTATE_N (1U << 31)
1299 #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V)
1300 #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F)
1301 #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE)
1302 /* Mode values for AArch64 */
1303 #define PSTATE_MODE_EL3h 13
1304 #define PSTATE_MODE_EL3t 12
1305 #define PSTATE_MODE_EL2h 9
1306 #define PSTATE_MODE_EL2t 8
1307 #define PSTATE_MODE_EL1h 5
1308 #define PSTATE_MODE_EL1t 4
1309 #define PSTATE_MODE_EL0t 0
1310
1311 /* Write a new value to v7m.exception, thus transitioning into or out
1312 * of Handler mode; this may result in a change of active stack pointer.
1313 */
1314 void write_v7m_exception(CPUARMState *env, uint32_t new_exc);
1315
1316 /* Map EL and handler into a PSTATE_MODE. */
1317 static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handler)
1318 {
1319 return (el << 2) | handler;
1320 }
1321
1322 /* Return the current PSTATE value. For the moment we don't support 32<->64 bit
1323 * interprocessing, so we don't attempt to sync with the cpsr state used by
1324 * the 32 bit decoder.
1325 */
1326 static inline uint32_t pstate_read(CPUARMState *env)
1327 {
1328 int ZF;
1329
1330 ZF = (env->ZF == 0);
1331 return (env->NF & 0x80000000) | (ZF << 30)
1332 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3)
1333 | env->pstate | env->daif | (env->btype << 10);
1334 }
1335
1336 static inline void pstate_write(CPUARMState *env, uint32_t val)
1337 {
1338 env->ZF = (~val) & PSTATE_Z;
1339 env->NF = val;
1340 env->CF = (val >> 29) & 1;
1341 env->VF = (val << 3) & 0x80000000;
1342 env->daif = val & PSTATE_DAIF;
1343 env->btype = (val >> 10) & 3;
1344 env->pstate = val & ~CACHED_PSTATE_BITS;
1345 }
1346
1347 /* Return the current CPSR value. */
1348 uint32_t cpsr_read(CPUARMState *env);
1349
1350 typedef enum CPSRWriteType {
1351 CPSRWriteByInstr = 0, /* from guest MSR or CPS */
1352 CPSRWriteExceptionReturn = 1, /* from guest exception return insn */
1353 CPSRWriteRaw = 2, /* trust values, do not switch reg banks */
1354 CPSRWriteByGDBStub = 3, /* from the GDB stub */
1355 } CPSRWriteType;
1356
1357 /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/
1358 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
1359 CPSRWriteType write_type);
1360
1361 /* Return the current xPSR value. */
1362 static inline uint32_t xpsr_read(CPUARMState *env)
1363 {
1364 int ZF;
1365 ZF = (env->ZF == 0);
1366 return (env->NF & 0x80000000) | (ZF << 30)
1367 | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1368 | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
1369 | ((env->condexec_bits & 0xfc) << 8)
1370 | (env->GE << 16)
1371 | env->v7m.exception;
1372 }
1373
1374 /* Set the xPSR. Note that some bits of mask must be all-set or all-clear. */
1375 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1376 {
1377 if (mask & XPSR_NZCV) {
1378 env->ZF = (~val) & XPSR_Z;
1379 env->NF = val;
1380 env->CF = (val >> 29) & 1;
1381 env->VF = (val << 3) & 0x80000000;
1382 }
1383 if (mask & XPSR_Q) {
1384 env->QF = ((val & XPSR_Q) != 0);
1385 }
1386 if (mask & XPSR_GE) {
1387 env->GE = (val & XPSR_GE) >> 16;
1388 }
1389 #ifndef CONFIG_USER_ONLY
1390 if (mask & XPSR_T) {
1391 env->thumb = ((val & XPSR_T) != 0);
1392 }
1393 if (mask & XPSR_IT_0_1) {
1394 env->condexec_bits &= ~3;
1395 env->condexec_bits |= (val >> 25) & 3;
1396 }
1397 if (mask & XPSR_IT_2_7) {
1398 env->condexec_bits &= 3;
1399 env->condexec_bits |= (val >> 8) & 0xfc;
1400 }
1401 if (mask & XPSR_EXCP) {
1402 /* Note that this only happens on exception exit */
1403 write_v7m_exception(env, val & XPSR_EXCP);
1404 }
1405 #endif
1406 }
1407
1408 #define HCR_VM (1ULL << 0)
1409 #define HCR_SWIO (1ULL << 1)
1410 #define HCR_PTW (1ULL << 2)
1411 #define HCR_FMO (1ULL << 3)
1412 #define HCR_IMO (1ULL << 4)
1413 #define HCR_AMO (1ULL << 5)
1414 #define HCR_VF (1ULL << 6)
1415 #define HCR_VI (1ULL << 7)
1416 #define HCR_VSE (1ULL << 8)
1417 #define HCR_FB (1ULL << 9)
1418 #define HCR_BSU_MASK (3ULL << 10)
1419 #define HCR_DC (1ULL << 12)
1420 #define HCR_TWI (1ULL << 13)
1421 #define HCR_TWE (1ULL << 14)
1422 #define HCR_TID0 (1ULL << 15)
1423 #define HCR_TID1 (1ULL << 16)
1424 #define HCR_TID2 (1ULL << 17)
1425 #define HCR_TID3 (1ULL << 18)
1426 #define HCR_TSC (1ULL << 19)
1427 #define HCR_TIDCP (1ULL << 20)
1428 #define HCR_TACR (1ULL << 21)
1429 #define HCR_TSW (1ULL << 22)
1430 #define HCR_TPCP (1ULL << 23)
1431 #define HCR_TPU (1ULL << 24)
1432 #define HCR_TTLB (1ULL << 25)
1433 #define HCR_TVM (1ULL << 26)
1434 #define HCR_TGE (1ULL << 27)
1435 #define HCR_TDZ (1ULL << 28)
1436 #define HCR_HCD (1ULL << 29)
1437 #define HCR_TRVM (1ULL << 30)
1438 #define HCR_RW (1ULL << 31)
1439 #define HCR_CD (1ULL << 32)
1440 #define HCR_ID (1ULL << 33)
1441 #define HCR_E2H (1ULL << 34)
1442 #define HCR_TLOR (1ULL << 35)
1443 #define HCR_TERR (1ULL << 36)
1444 #define HCR_TEA (1ULL << 37)
1445 #define HCR_MIOCNCE (1ULL << 38)
1446 /* RES0 bit 39 */
1447 #define HCR_APK (1ULL << 40)
1448 #define HCR_API (1ULL << 41)
1449 #define HCR_NV (1ULL << 42)
1450 #define HCR_NV1 (1ULL << 43)
1451 #define HCR_AT (1ULL << 44)
1452 #define HCR_NV2 (1ULL << 45)
1453 #define HCR_FWB (1ULL << 46)
1454 #define HCR_FIEN (1ULL << 47)
1455 /* RES0 bit 48 */
1456 #define HCR_TID4 (1ULL << 49)
1457 #define HCR_TICAB (1ULL << 50)
1458 #define HCR_AMVOFFEN (1ULL << 51)
1459 #define HCR_TOCU (1ULL << 52)
1460 #define HCR_ENSCXT (1ULL << 53)
1461 #define HCR_TTLBIS (1ULL << 54)
1462 #define HCR_TTLBOS (1ULL << 55)
1463 #define HCR_ATA (1ULL << 56)
1464 #define HCR_DCT (1ULL << 57)
1465 #define HCR_TID5 (1ULL << 58)
1466 #define HCR_TWEDEN (1ULL << 59)
1467 #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4)
1468
1469 #define SCR_NS (1U << 0)
1470 #define SCR_IRQ (1U << 1)
1471 #define SCR_FIQ (1U << 2)
1472 #define SCR_EA (1U << 3)
1473 #define SCR_FW (1U << 4)
1474 #define SCR_AW (1U << 5)
1475 #define SCR_NET (1U << 6)
1476 #define SCR_SMD (1U << 7)
1477 #define SCR_HCE (1U << 8)
1478 #define SCR_SIF (1U << 9)
1479 #define SCR_RW (1U << 10)
1480 #define SCR_ST (1U << 11)
1481 #define SCR_TWI (1U << 12)
1482 #define SCR_TWE (1U << 13)
1483 #define SCR_TLOR (1U << 14)
1484 #define SCR_TERR (1U << 15)
1485 #define SCR_APK (1U << 16)
1486 #define SCR_API (1U << 17)
1487 #define SCR_EEL2 (1U << 18)
1488 #define SCR_EASE (1U << 19)
1489 #define SCR_NMEA (1U << 20)
1490 #define SCR_FIEN (1U << 21)
1491 #define SCR_ENSCXT (1U << 25)
1492 #define SCR_ATA (1U << 26)
1493
1494 /* Return the current FPSCR value. */
1495 uint32_t vfp_get_fpscr(CPUARMState *env);
1496 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
1497
1498 /* FPCR, Floating Point Control Register
1499 * FPSR, Floating Poiht Status Register
1500 *
1501 * For A64 the FPSCR is split into two logically distinct registers,
1502 * FPCR and FPSR. However since they still use non-overlapping bits
1503 * we store the underlying state in fpscr and just mask on read/write.
1504 */
1505 #define FPSR_MASK 0xf800009f
1506 #define FPCR_MASK 0x07ff9f00
1507
1508 #define FPCR_IOE (1 << 8) /* Invalid Operation exception trap enable */
1509 #define FPCR_DZE (1 << 9) /* Divide by Zero exception trap enable */
1510 #define FPCR_OFE (1 << 10) /* Overflow exception trap enable */
1511 #define FPCR_UFE (1 << 11) /* Underflow exception trap enable */
1512 #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */
1513 #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */
1514 #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
1515 #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
1516 #define FPCR_DN (1 << 25) /* Default NaN enable bit */
1517 #define FPCR_QC (1 << 27) /* Cumulative saturation bit */
1518
1519 static inline uint32_t vfp_get_fpsr(CPUARMState *env)
1520 {
1521 return vfp_get_fpscr(env) & FPSR_MASK;
1522 }
1523
1524 static inline void vfp_set_fpsr(CPUARMState *env, uint32_t val)
1525 {
1526 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPSR_MASK) | (val & FPSR_MASK);
1527 vfp_set_fpscr(env, new_fpscr);
1528 }
1529
1530 static inline uint32_t vfp_get_fpcr(CPUARMState *env)
1531 {
1532 return vfp_get_fpscr(env) & FPCR_MASK;
1533 }
1534
1535 static inline void vfp_set_fpcr(CPUARMState *env, uint32_t val)
1536 {
1537 uint32_t new_fpscr = (vfp_get_fpscr(env) & ~FPCR_MASK) | (val & FPCR_MASK);
1538 vfp_set_fpscr(env, new_fpscr);
1539 }
1540
1541 enum arm_cpu_mode {
1542 ARM_CPU_MODE_USR = 0x10,
1543 ARM_CPU_MODE_FIQ = 0x11,
1544 ARM_CPU_MODE_IRQ = 0x12,
1545 ARM_CPU_MODE_SVC = 0x13,
1546 ARM_CPU_MODE_MON = 0x16,
1547 ARM_CPU_MODE_ABT = 0x17,
1548 ARM_CPU_MODE_HYP = 0x1a,
1549 ARM_CPU_MODE_UND = 0x1b,
1550 ARM_CPU_MODE_SYS = 0x1f
1551 };
1552
1553 /* VFP system registers. */
1554 #define ARM_VFP_FPSID 0
1555 #define ARM_VFP_FPSCR 1
1556 #define ARM_VFP_MVFR2 5
1557 #define ARM_VFP_MVFR1 6
1558 #define ARM_VFP_MVFR0 7
1559 #define ARM_VFP_FPEXC 8
1560 #define ARM_VFP_FPINST 9
1561 #define ARM_VFP_FPINST2 10
1562
1563 /* iwMMXt coprocessor control registers. */
1564 #define ARM_IWMMXT_wCID 0
1565 #define ARM_IWMMXT_wCon 1
1566 #define ARM_IWMMXT_wCSSF 2
1567 #define ARM_IWMMXT_wCASF 3
1568 #define ARM_IWMMXT_wCGR0 8
1569 #define ARM_IWMMXT_wCGR1 9
1570 #define ARM_IWMMXT_wCGR2 10
1571 #define ARM_IWMMXT_wCGR3 11
1572
1573 /* V7M CCR bits */
1574 FIELD(V7M_CCR, NONBASETHRDENA, 0, 1)
1575 FIELD(V7M_CCR, USERSETMPEND, 1, 1)
1576 FIELD(V7M_CCR, UNALIGN_TRP, 3, 1)
1577 FIELD(V7M_CCR, DIV_0_TRP, 4, 1)
1578 FIELD(V7M_CCR, BFHFNMIGN, 8, 1)
1579 FIELD(V7M_CCR, STKALIGN, 9, 1)
1580 FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
1581 FIELD(V7M_CCR, DC, 16, 1)
1582 FIELD(V7M_CCR, IC, 17, 1)
1583 FIELD(V7M_CCR, BP, 18, 1)
1584
1585 /* V7M SCR bits */
1586 FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
1587 FIELD(V7M_SCR, SLEEPDEEP, 2, 1)
1588 FIELD(V7M_SCR, SLEEPDEEPS, 3, 1)
1589 FIELD(V7M_SCR, SEVONPEND, 4, 1)
1590
1591 /* V7M AIRCR bits */
1592 FIELD(V7M_AIRCR, VECTRESET, 0, 1)
1593 FIELD(V7M_AIRCR, VECTCLRACTIVE, 1, 1)
1594 FIELD(V7M_AIRCR, SYSRESETREQ, 2, 1)
1595 FIELD(V7M_AIRCR, SYSRESETREQS, 3, 1)
1596 FIELD(V7M_AIRCR, PRIGROUP, 8, 3)
1597 FIELD(V7M_AIRCR, BFHFNMINS, 13, 1)
1598 FIELD(V7M_AIRCR, PRIS, 14, 1)
1599 FIELD(V7M_AIRCR, ENDIANNESS, 15, 1)
1600 FIELD(V7M_AIRCR, VECTKEY, 16, 16)
1601
1602 /* V7M CFSR bits for MMFSR */
1603 FIELD(V7M_CFSR, IACCVIOL, 0, 1)
1604 FIELD(V7M_CFSR, DACCVIOL, 1, 1)
1605 FIELD(V7M_CFSR, MUNSTKERR, 3, 1)
1606 FIELD(V7M_CFSR, MSTKERR, 4, 1)
1607 FIELD(V7M_CFSR, MLSPERR, 5, 1)
1608 FIELD(V7M_CFSR, MMARVALID, 7, 1)
1609
1610 /* V7M CFSR bits for BFSR */
1611 FIELD(V7M_CFSR, IBUSERR, 8 + 0, 1)
1612 FIELD(V7M_CFSR, PRECISERR, 8 + 1, 1)
1613 FIELD(V7M_CFSR, IMPRECISERR, 8 + 2, 1)
1614 FIELD(V7M_CFSR, UNSTKERR, 8 + 3, 1)
1615 FIELD(V7M_CFSR, STKERR, 8 + 4, 1)
1616 FIELD(V7M_CFSR, LSPERR, 8 + 5, 1)
1617 FIELD(V7M_CFSR, BFARVALID, 8 + 7, 1)
1618
1619 /* V7M CFSR bits for UFSR */
1620 FIELD(V7M_CFSR, UNDEFINSTR, 16 + 0, 1)
1621 FIELD(V7M_CFSR, INVSTATE, 16 + 1, 1)
1622 FIELD(V7M_CFSR, INVPC, 16 + 2, 1)
1623 FIELD(V7M_CFSR, NOCP, 16 + 3, 1)
1624 FIELD(V7M_CFSR, STKOF, 16 + 4, 1)
1625 FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1)
1626 FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1)
1627
1628 /* V7M CFSR bit masks covering all of the subregister bits */
1629 FIELD(V7M_CFSR, MMFSR, 0, 8)
1630 FIELD(V7M_CFSR, BFSR, 8, 8)
1631 FIELD(V7M_CFSR, UFSR, 16, 16)
1632
1633 /* V7M HFSR bits */
1634 FIELD(V7M_HFSR, VECTTBL, 1, 1)
1635 FIELD(V7M_HFSR, FORCED, 30, 1)
1636 FIELD(V7M_HFSR, DEBUGEVT, 31, 1)
1637
1638 /* V7M DFSR bits */
1639 FIELD(V7M_DFSR, HALTED, 0, 1)
1640 FIELD(V7M_DFSR, BKPT, 1, 1)
1641 FIELD(V7M_DFSR, DWTTRAP, 2, 1)
1642 FIELD(V7M_DFSR, VCATCH, 3, 1)
1643 FIELD(V7M_DFSR, EXTERNAL, 4, 1)
1644
1645 /* V7M SFSR bits */
1646 FIELD(V7M_SFSR, INVEP, 0, 1)
1647 FIELD(V7M_SFSR, INVIS, 1, 1)
1648 FIELD(V7M_SFSR, INVER, 2, 1)
1649 FIELD(V7M_SFSR, AUVIOL, 3, 1)
1650 FIELD(V7M_SFSR, INVTRAN, 4, 1)
1651 FIELD(V7M_SFSR, LSPERR, 5, 1)
1652 FIELD(V7M_SFSR, SFARVALID, 6, 1)
1653 FIELD(V7M_SFSR, LSERR, 7, 1)
1654
1655 /* v7M MPU_CTRL bits */
1656 FIELD(V7M_MPU_CTRL, ENABLE, 0, 1)
1657 FIELD(V7M_MPU_CTRL, HFNMIENA, 1, 1)
1658 FIELD(V7M_MPU_CTRL, PRIVDEFENA, 2, 1)
1659
1660 /* v7M CLIDR bits */
1661 FIELD(V7M_CLIDR, CTYPE_ALL, 0, 21)
1662 FIELD(V7M_CLIDR, LOUIS, 21, 3)
1663 FIELD(V7M_CLIDR, LOC, 24, 3)
1664 FIELD(V7M_CLIDR, LOUU, 27, 3)
1665 FIELD(V7M_CLIDR, ICB, 30, 2)
1666
1667 FIELD(V7M_CSSELR, IND, 0, 1)
1668 FIELD(V7M_CSSELR, LEVEL, 1, 3)
1669 /* We use the combination of InD and Level to index into cpu->ccsidr[];
1670 * define a mask for this and check that it doesn't permit running off
1671 * the end of the array.
1672 */
1673 FIELD(V7M_CSSELR, INDEX, 0, 4)
1674
1675 /* v7M FPCCR bits */
1676 FIELD(V7M_FPCCR, LSPACT, 0, 1)
1677 FIELD(V7M_FPCCR, USER, 1, 1)
1678 FIELD(V7M_FPCCR, S, 2, 1)
1679 FIELD(V7M_FPCCR, THREAD, 3, 1)
1680 FIELD(V7M_FPCCR, HFRDY, 4, 1)
1681 FIELD(V7M_FPCCR, MMRDY, 5, 1)
1682 FIELD(V7M_FPCCR, BFRDY, 6, 1)
1683 FIELD(V7M_FPCCR, SFRDY, 7, 1)
1684 FIELD(V7M_FPCCR, MONRDY, 8, 1)
1685 FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1)
1686 FIELD(V7M_FPCCR, UFRDY, 10, 1)
1687 FIELD(V7M_FPCCR, RES0, 11, 15)
1688 FIELD(V7M_FPCCR, TS, 26, 1)
1689 FIELD(V7M_FPCCR, CLRONRETS, 27, 1)
1690 FIELD(V7M_FPCCR, CLRONRET, 28, 1)
1691 FIELD(V7M_FPCCR, LSPENS, 29, 1)
1692 FIELD(V7M_FPCCR, LSPEN, 30, 1)
1693 FIELD(V7M_FPCCR, ASPEN, 31, 1)
1694 /* These bits are banked. Others are non-banked and live in the M_REG_S bank */
1695 #define R_V7M_FPCCR_BANKED_MASK \
1696 (R_V7M_FPCCR_LSPACT_MASK | \
1697 R_V7M_FPCCR_USER_MASK | \
1698 R_V7M_FPCCR_THREAD_MASK | \
1699 R_V7M_FPCCR_MMRDY_MASK | \
1700 R_V7M_FPCCR_SPLIMVIOL_MASK | \
1701 R_V7M_FPCCR_UFRDY_MASK | \
1702 R_V7M_FPCCR_ASPEN_MASK)
1703
1704 /*
1705 * System register ID fields.
1706 */
1707 FIELD(MIDR_EL1, REVISION, 0, 4)
1708 FIELD(MIDR_EL1, PARTNUM, 4, 12)
1709 FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
1710 FIELD(MIDR_EL1, VARIANT, 20, 4)
1711 FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
1712
1713 FIELD(ID_ISAR0, SWAP, 0, 4)
1714 FIELD(ID_ISAR0, BITCOUNT, 4, 4)
1715 FIELD(ID_ISAR0, BITFIELD, 8, 4)
1716 FIELD(ID_ISAR0, CMPBRANCH, 12, 4)
1717 FIELD(ID_ISAR0, COPROC, 16, 4)
1718 FIELD(ID_ISAR0, DEBUG, 20, 4)
1719 FIELD(ID_ISAR0, DIVIDE, 24, 4)
1720
1721 FIELD(ID_ISAR1, ENDIAN, 0, 4)
1722 FIELD(ID_ISAR1, EXCEPT, 4, 4)
1723 FIELD(ID_ISAR1, EXCEPT_AR, 8, 4)
1724 FIELD(ID_ISAR1, EXTEND, 12, 4)
1725 FIELD(ID_ISAR1, IFTHEN, 16, 4)
1726 FIELD(ID_ISAR1, IMMEDIATE, 20, 4)
1727 FIELD(ID_ISAR1, INTERWORK, 24, 4)
1728 FIELD(ID_ISAR1, JAZELLE, 28, 4)
1729
1730 FIELD(ID_ISAR2, LOADSTORE, 0, 4)
1731 FIELD(ID_ISAR2, MEMHINT, 4, 4)
1732 FIELD(ID_ISAR2, MULTIACCESSINT, 8, 4)
1733 FIELD(ID_ISAR2, MULT, 12, 4)
1734 FIELD(ID_ISAR2, MULTS, 16, 4)
1735 FIELD(ID_ISAR2, MULTU, 20, 4)
1736 FIELD(ID_ISAR2, PSR_AR, 24, 4)
1737 FIELD(ID_ISAR2, REVERSAL, 28, 4)
1738
1739 FIELD(ID_ISAR3, SATURATE, 0, 4)
1740 FIELD(ID_ISAR3, SIMD, 4, 4)
1741 FIELD(ID_ISAR3, SVC, 8, 4)
1742 FIELD(ID_ISAR3, SYNCHPRIM, 12, 4)
1743 FIELD(ID_ISAR3, TABBRANCH, 16, 4)
1744 FIELD(ID_ISAR3, T32COPY, 20, 4)
1745 FIELD(ID_ISAR3, TRUENOP, 24, 4)
1746 FIELD(ID_ISAR3, T32EE, 28, 4)
1747
1748 FIELD(ID_ISAR4, UNPRIV, 0, 4)
1749 FIELD(ID_ISAR4, WITHSHIFTS, 4, 4)
1750 FIELD(ID_ISAR4, WRITEBACK, 8, 4)
1751 FIELD(ID_ISAR4, SMC, 12, 4)
1752 FIELD(ID_ISAR4, BARRIER, 16, 4)
1753 FIELD(ID_ISAR4, SYNCHPRIM_FRAC, 20, 4)
1754 FIELD(ID_ISAR4, PSR_M, 24, 4)
1755 FIELD(ID_ISAR4, SWP_FRAC, 28, 4)
1756
1757 FIELD(ID_ISAR5, SEVL, 0, 4)
1758 FIELD(ID_ISAR5, AES, 4, 4)
1759 FIELD(ID_ISAR5, SHA1, 8, 4)
1760 FIELD(ID_ISAR5, SHA2, 12, 4)
1761 FIELD(ID_ISAR5, CRC32, 16, 4)
1762 FIELD(ID_ISAR5, RDM, 24, 4)
1763 FIELD(ID_ISAR5, VCMA, 28, 4)
1764
1765 FIELD(ID_ISAR6, JSCVT, 0, 4)
1766 FIELD(ID_ISAR6, DP, 4, 4)
1767 FIELD(ID_ISAR6, FHM, 8, 4)
1768 FIELD(ID_ISAR6, SB, 12, 4)
1769 FIELD(ID_ISAR6, SPECRES, 16, 4)
1770
1771 FIELD(ID_MMFR3, CMAINTVA, 0, 4)
1772 FIELD(ID_MMFR3, CMAINTSW, 4, 4)
1773 FIELD(ID_MMFR3, BPMAINT, 8, 4)
1774 FIELD(ID_MMFR3, MAINTBCST, 12, 4)
1775 FIELD(ID_MMFR3, PAN, 16, 4)
1776 FIELD(ID_MMFR3, COHWALK, 20, 4)
1777 FIELD(ID_MMFR3, CMEMSZ, 24, 4)
1778 FIELD(ID_MMFR3, SUPERSEC, 28, 4)
1779
1780 FIELD(ID_MMFR4, SPECSEI, 0, 4)
1781 FIELD(ID_MMFR4, AC2, 4, 4)
1782 FIELD(ID_MMFR4, XNX, 8, 4)
1783 FIELD(ID_MMFR4, CNP, 12, 4)
1784 FIELD(ID_MMFR4, HPDS, 16, 4)
1785 FIELD(ID_MMFR4, LSM, 20, 4)
1786 FIELD(ID_MMFR4, CCIDX, 24, 4)
1787 FIELD(ID_MMFR4, EVT, 28, 4)
1788
1789 FIELD(ID_AA64ISAR0, AES, 4, 4)
1790 FIELD(ID_AA64ISAR0, SHA1, 8, 4)
1791 FIELD(ID_AA64ISAR0, SHA2, 12, 4)
1792 FIELD(ID_AA64ISAR0, CRC32, 16, 4)
1793 FIELD(ID_AA64ISAR0, ATOMIC, 20, 4)
1794 FIELD(ID_AA64ISAR0, RDM, 28, 4)
1795 FIELD(ID_AA64ISAR0, SHA3, 32, 4)
1796 FIELD(ID_AA64ISAR0, SM3, 36, 4)
1797 FIELD(ID_AA64ISAR0, SM4, 40, 4)
1798 FIELD(ID_AA64ISAR0, DP, 44, 4)
1799 FIELD(ID_AA64ISAR0, FHM, 48, 4)
1800 FIELD(ID_AA64ISAR0, TS, 52, 4)
1801 FIELD(ID_AA64ISAR0, TLB, 56, 4)
1802 FIELD(ID_AA64ISAR0, RNDR, 60, 4)
1803
1804 FIELD(ID_AA64ISAR1, DPB, 0, 4)
1805 FIELD(ID_AA64ISAR1, APA, 4, 4)
1806 FIELD(ID_AA64ISAR1, API, 8, 4)
1807 FIELD(ID_AA64ISAR1, JSCVT, 12, 4)
1808 FIELD(ID_AA64ISAR1, FCMA, 16, 4)
1809 FIELD(ID_AA64ISAR1, LRCPC, 20, 4)
1810 FIELD(ID_AA64ISAR1, GPA, 24, 4)
1811 FIELD(ID_AA64ISAR1, GPI, 28, 4)
1812 FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
1813 FIELD(ID_AA64ISAR1, SB, 36, 4)
1814 FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
1815
1816 FIELD(ID_AA64PFR0, EL0, 0, 4)
1817 FIELD(ID_AA64PFR0, EL1, 4, 4)
1818 FIELD(ID_AA64PFR0, EL2, 8, 4)
1819 FIELD(ID_AA64PFR0, EL3, 12, 4)
1820 FIELD(ID_AA64PFR0, FP, 16, 4)
1821 FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
1822 FIELD(ID_AA64PFR0, GIC, 24, 4)
1823 FIELD(ID_AA64PFR0, RAS, 28, 4)
1824 FIELD(ID_AA64PFR0, SVE, 32, 4)
1825
1826 FIELD(ID_AA64PFR1, BT, 0, 4)
1827 FIELD(ID_AA64PFR1, SBSS, 4, 4)
1828 FIELD(ID_AA64PFR1, MTE, 8, 4)
1829 FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
1830
1831 FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
1832 FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
1833 FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
1834 FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
1835 FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
1836 FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
1837 FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
1838 FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
1839 FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
1840 FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
1841 FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
1842 FIELD(ID_AA64MMFR0, EXS, 44, 4)
1843
1844 FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
1845 FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
1846 FIELD(ID_AA64MMFR1, VH, 8, 4)
1847 FIELD(ID_AA64MMFR1, HPDS, 12, 4)
1848 FIELD(ID_AA64MMFR1, LO, 16, 4)
1849 FIELD(ID_AA64MMFR1, PAN, 20, 4)
1850 FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
1851 FIELD(ID_AA64MMFR1, XNX, 28, 4)
1852
1853 FIELD(ID_AA64MMFR2, CNP, 0, 4)
1854 FIELD(ID_AA64MMFR2, UAO, 4, 4)
1855 FIELD(ID_AA64MMFR2, LSM, 8, 4)
1856 FIELD(ID_AA64MMFR2, IESB, 12, 4)
1857 FIELD(ID_AA64MMFR2, VARANGE, 16, 4)
1858 FIELD(ID_AA64MMFR2, CCIDX, 20, 4)
1859 FIELD(ID_AA64MMFR2, NV, 24, 4)
1860 FIELD(ID_AA64MMFR2, ST, 28, 4)
1861 FIELD(ID_AA64MMFR2, AT, 32, 4)
1862 FIELD(ID_AA64MMFR2, IDS, 36, 4)
1863 FIELD(ID_AA64MMFR2, FWB, 40, 4)
1864 FIELD(ID_AA64MMFR2, TTL, 48, 4)
1865 FIELD(ID_AA64MMFR2, BBM, 52, 4)
1866 FIELD(ID_AA64MMFR2, EVT, 56, 4)
1867 FIELD(ID_AA64MMFR2, E0PD, 60, 4)
1868
1869 FIELD(ID_AA64DFR0, DEBUGVER, 0, 4)
1870 FIELD(ID_AA64DFR0, TRACEVER, 4, 4)
1871 FIELD(ID_AA64DFR0, PMUVER, 8, 4)
1872 FIELD(ID_AA64DFR0, BRPS, 12, 4)
1873 FIELD(ID_AA64DFR0, WRPS, 20, 4)
1874 FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
1875 FIELD(ID_AA64DFR0, PMSVER, 32, 4)
1876 FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
1877 FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
1878
1879 FIELD(ID_DFR0, COPDBG, 0, 4)
1880 FIELD(ID_DFR0, COPSDBG, 4, 4)
1881 FIELD(ID_DFR0, MMAPDBG, 8, 4)
1882 FIELD(ID_DFR0, COPTRC, 12, 4)
1883 FIELD(ID_DFR0, MMAPTRC, 16, 4)
1884 FIELD(ID_DFR0, MPROFDBG, 20, 4)
1885 FIELD(ID_DFR0, PERFMON, 24, 4)
1886 FIELD(ID_DFR0, TRACEFILT, 28, 4)
1887
1888 FIELD(DBGDIDR, SE_IMP, 12, 1)
1889 FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
1890 FIELD(DBGDIDR, VERSION, 16, 4)
1891 FIELD(DBGDIDR, CTX_CMPS, 20, 4)
1892 FIELD(DBGDIDR, BRPS, 24, 4)
1893 FIELD(DBGDIDR, WRPS, 28, 4)
1894
1895 FIELD(MVFR0, SIMDREG, 0, 4)
1896 FIELD(MVFR0, FPSP, 4, 4)
1897 FIELD(MVFR0, FPDP, 8, 4)
1898 FIELD(MVFR0, FPTRAP, 12, 4)
1899 FIELD(MVFR0, FPDIVIDE, 16, 4)
1900 FIELD(MVFR0, FPSQRT, 20, 4)
1901 FIELD(MVFR0, FPSHVEC, 24, 4)
1902 FIELD(MVFR0, FPROUND, 28, 4)
1903
1904 FIELD(MVFR1, FPFTZ, 0, 4)
1905 FIELD(MVFR1, FPDNAN, 4, 4)
1906 FIELD(MVFR1, SIMDLS, 8, 4)
1907 FIELD(MVFR1, SIMDINT, 12, 4)
1908 FIELD(MVFR1, SIMDSP, 16, 4)
1909 FIELD(MVFR1, SIMDHP, 20, 4)
1910 FIELD(MVFR1, FPHP, 24, 4)
1911 FIELD(MVFR1, SIMDFMAC, 28, 4)
1912
1913 FIELD(MVFR2, SIMDMISC, 0, 4)
1914 FIELD(MVFR2, FPMISC, 4, 4)
1915
1916 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
1917
1918 /* If adding a feature bit which corresponds to a Linux ELF
1919 * HWCAP bit, remember to update the feature-bit-to-hwcap
1920 * mapping in linux-user/elfload.c:get_elf_hwcap().
1921 */
1922 enum arm_features {
1923 ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
1924 ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
1925 ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
1926 ARM_FEATURE_V6,
1927 ARM_FEATURE_V6K,
1928 ARM_FEATURE_V7,
1929 ARM_FEATURE_THUMB2,
1930 ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */
1931 ARM_FEATURE_NEON,
1932 ARM_FEATURE_M, /* Microcontroller profile. */
1933 ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
1934 ARM_FEATURE_THUMB2EE,
1935 ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
1936 ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
1937 ARM_FEATURE_V4T,
1938 ARM_FEATURE_V5,
1939 ARM_FEATURE_STRONGARM,
1940 ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
1941 ARM_FEATURE_GENERIC_TIMER,
1942 ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
1943 ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
1944 ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
1945 ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
1946 ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
1947 ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
1948 ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
1949 ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
1950 ARM_FEATURE_V8,
1951 ARM_FEATURE_AARCH64, /* supports 64 bit mode */
1952 ARM_FEATURE_CBAR, /* has cp15 CBAR */
1953 ARM_FEATURE_CRC, /* ARMv8 CRC instructions */
1954 ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
1955 ARM_FEATURE_EL2, /* has EL2 Virtualization support */
1956 ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
1957 ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
1958 ARM_FEATURE_PMU, /* has PMU support */
1959 ARM_FEATURE_VBAR, /* has cp15 VBAR */
1960 ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
1961 ARM_FEATURE_M_MAIN, /* M profile Main Extension */
1962 };
1963
1964 static inline int arm_feature(CPUARMState *env, int feature)
1965 {
1966 return (env->features & (1ULL << feature)) != 0;
1967 }
1968
1969 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp);
1970
1971 #if !defined(CONFIG_USER_ONLY)
1972 /* Return true if exception levels below EL3 are in secure state,
1973 * or would be following an exception return to that level.
1974 * Unlike arm_is_secure() (which is always a question about the
1975 * _current_ state of the CPU) this doesn't care about the current
1976 * EL or mode.
1977 */
1978 static inline bool arm_is_secure_below_el3(CPUARMState *env)
1979 {
1980 if (arm_feature(env, ARM_FEATURE_EL3)) {
1981 return !(env->cp15.scr_el3 & SCR_NS);
1982 } else {
1983 /* If EL3 is not supported then the secure state is implementation
1984 * defined, in which case QEMU defaults to non-secure.
1985 */
1986 return false;
1987 }
1988 }
1989
1990 /* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
1991 static inline bool arm_is_el3_or_mon(CPUARMState *env)
1992 {
1993 if (arm_feature(env, ARM_FEATURE_EL3)) {
1994 if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
1995 /* CPU currently in AArch64 state and EL3 */
1996 return true;
1997 } else if (!is_a64(env) &&
1998 (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
1999 /* CPU currently in AArch32 state and monitor mode */
2000 return true;
2001 }
2002 }
2003 return false;
2004 }
2005
2006 /* Return true if the processor is in secure state */
2007 static inline bool arm_is_secure(CPUARMState *env)
2008 {
2009 if (arm_is_el3_or_mon(env)) {
2010 return true;
2011 }
2012 return arm_is_secure_below_el3(env);
2013 }
2014
2015 #else
2016 static inline bool arm_is_secure_below_el3(CPUARMState *env)
2017 {
2018 return false;
2019 }
2020
2021 static inline bool arm_is_secure(CPUARMState *env)
2022 {
2023 return false;
2024 }
2025 #endif
2026
2027 /**
2028 * arm_hcr_el2_eff(): Return the effective value of HCR_EL2.
2029 * E.g. when in secure state, fields in HCR_EL2 are suppressed,
2030 * "for all purposes other than a direct read or write access of HCR_EL2."
2031 * Not included here is HCR_RW.
2032 */
2033 uint64_t arm_hcr_el2_eff(CPUARMState *env);
2034
2035 /* Return true if the specified exception level is running in AArch64 state. */
2036 static inline bool arm_el_is_aa64(CPUARMState *env, int el)
2037 {
2038 /* This isn't valid for EL0 (if we're in EL0, is_a64() is what you want,
2039 * and if we're not in EL0 then the state of EL0 isn't well defined.)
2040 */
2041 assert(el >= 1 && el <= 3);
2042 bool aa64 = arm_feature(env, ARM_FEATURE_AARCH64);
2043
2044 /* The highest exception level is always at the maximum supported
2045 * register width, and then lower levels have a register width controlled
2046 * by bits in the SCR or HCR registers.
2047 */
2048 if (el == 3) {
2049 return aa64;
2050 }
2051
2052 if (arm_feature(env, ARM_FEATURE_EL3)) {
2053 aa64 = aa64 && (env->cp15.scr_el3 & SCR_RW);
2054 }
2055
2056 if (el == 2) {
2057 return aa64;
2058 }
2059
2060 if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) {
2061 aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
2062 }
2063
2064 return aa64;
2065 }
2066
2067 /* Function for determing whether guest cp register reads and writes should
2068 * access the secure or non-secure bank of a cp register. When EL3 is
2069 * operating in AArch32 state, the NS-bit determines whether the secure
2070 * instance of a cp register should be used. When EL3 is AArch64 (or if
2071 * it doesn't exist at all) then there is no register banking, and all
2072 * accesses are to the non-secure version.
2073 */
2074 static inline bool access_secure_reg(CPUARMState *env)
2075 {
2076 bool ret = (arm_feature(env, ARM_FEATURE_EL3) &&
2077 !arm_el_is_aa64(env, 3) &&
2078 !(env->cp15.scr_el3 & SCR_NS));
2079
2080 return ret;
2081 }
2082
2083 /* Macros for accessing a specified CP register bank */
2084 #define A32_BANKED_REG_GET(_env, _regname, _secure) \
2085 ((_secure) ? (_env)->cp15._regname##_s : (_env)->cp15._regname##_ns)
2086
2087 #define A32_BANKED_REG_SET(_env, _regname, _secure, _val) \
2088 do { \
2089 if (_secure) { \
2090 (_env)->cp15._regname##_s = (_val); \
2091 } else { \
2092 (_env)->cp15._regname##_ns = (_val); \
2093 } \
2094 } while (0)
2095
2096 /* Macros for automatically accessing a specific CP register bank depending on
2097 * the current secure state of the system. These macros are not intended for
2098 * supporting instruction translation reads/writes as these are dependent
2099 * solely on the SCR.NS bit and not the mode.
2100 */
2101 #define A32_BANKED_CURRENT_REG_GET(_env, _regname) \
2102 A32_BANKED_REG_GET((_env), _regname, \
2103 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)))
2104
2105 #define A32_BANKED_CURRENT_REG_SET(_env, _regname, _val) \
2106 A32_BANKED_REG_SET((_env), _regname, \
2107 (arm_is_secure(_env) && !arm_el_is_aa64((_env), 3)), \
2108 (_val))
2109
2110 void arm_cpu_list(void);
2111 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
2112 uint32_t cur_el, bool secure);
2113
2114 /* Interface between CPU and Interrupt controller. */
2115 #ifndef CONFIG_USER_ONLY
2116 bool armv7m_nvic_can_take_pending_exception(void *opaque);
2117 #else
2118 static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)
2119 {
2120 return true;
2121 }
2122 #endif
2123 /**
2124 * armv7m_nvic_set_pending: mark the specified exception as pending
2125 * @opaque: the NVIC
2126 * @irq: the exception number to mark pending
2127 * @secure: false for non-banked exceptions or for the nonsecure
2128 * version of a banked exception, true for the secure version of a banked
2129 * exception.
2130 *
2131 * Marks the specified exception as pending. Note that we will assert()
2132 * if @secure is true and @irq does not specify one of the fixed set
2133 * of architecturally banked exceptions.
2134 */
2135 void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);
2136 /**
2137 * armv7m_nvic_set_pending_derived: mark this derived exception as pending
2138 * @opaque: the NVIC
2139 * @irq: the exception number to mark pending
2140 * @secure: false for non-banked exceptions or for the nonsecure
2141 * version of a banked exception, true for the secure version of a banked
2142 * exception.
2143 *
2144 * Similar to armv7m_nvic_set_pending(), but specifically for derived
2145 * exceptions (exceptions generated in the course of trying to take
2146 * a different exception).
2147 */
2148 void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure);
2149 /**
2150 * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending
2151 * @opaque: the NVIC
2152 * @irq: the exception number to mark pending
2153 * @secure: false for non-banked exceptions or for the nonsecure
2154 * version of a banked exception, true for the secure version of a banked
2155 * exception.
2156 *
2157 * Similar to armv7m_nvic_set_pending(), but specifically for exceptions
2158 * generated in the course of lazy stacking of FP registers.
2159 */
2160 void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure);
2161 /**
2162 * armv7m_nvic_get_pending_irq_info: return highest priority pending
2163 * exception, and whether it targets Secure state
2164 * @opaque: the NVIC
2165 * @pirq: set to pending exception number
2166 * @ptargets_secure: set to whether pending exception targets Secure
2167 *
2168 * This function writes the number of the highest priority pending
2169 * exception (the one which would be made active by
2170 * armv7m_nvic_acknowledge_irq()) to @pirq, and sets @ptargets_secure
2171 * to true if the current highest priority pending exception should
2172 * be taken to Secure state, false for NS.
2173 */
2174 void armv7m_nvic_get_pending_irq_info(void *opaque, int *pirq,
2175 bool *ptargets_secure);
2176 /**
2177 * armv7m_nvic_acknowledge_irq: make highest priority pending exception active
2178 * @opaque: the NVIC
2179 *
2180 * Move the current highest priority pending exception from the pending
2181 * state to the active state, and update v7m.exception to indicate that
2182 * it is the exception currently being handled.
2183 */
2184 void armv7m_nvic_acknowledge_irq(void *opaque);
2185 /**
2186 * armv7m_nvic_complete_irq: complete specified interrupt or exception
2187 * @opaque: the NVIC
2188 * @irq: the exception number to complete
2189 * @secure: true if this exception was secure
2190 *
2191 * Returns: -1 if the irq was not active
2192 * 1 if completing this irq brought us back to base (no active irqs)
2193 * 0 if there is still an irq active after this one was completed
2194 * (Ignoring -1, this is the same as the RETTOBASE value before completion.)
2195 */
2196 int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);
2197 /**
2198 * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure)
2199 * @opaque: the NVIC
2200 * @irq: the exception number to mark pending
2201 * @secure: false for non-banked exceptions or for the nonsecure
2202 * version of a banked exception, true for the secure version of a banked
2203 * exception.
2204 *
2205 * Return whether an exception is "ready", i.e. whether the exception is
2206 * enabled and is configured at a priority which would allow it to
2207 * interrupt the current execution priority. This controls whether the
2208 * RDY bit for it in the FPCCR is set.
2209 */
2210 bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure);
2211 /**
2212 * armv7m_nvic_raw_execution_priority: return the raw execution priority
2213 * @opaque: the NVIC
2214 *
2215 * Returns: the raw execution priority as defined by the v8M architecture.
2216 * This is the execution priority minus the effects of AIRCR.PRIS,
2217 * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting.
2218 * (v8M ARM ARM I_PKLD.)
2219 */
2220 int armv7m_nvic_raw_execution_priority(void *opaque);
2221 /**
2222 * armv7m_nvic_neg_prio_requested: return true if the requested execution
2223 * priority is negative for the specified security state.
2224 * @opaque: the NVIC
2225 * @secure: the security state to test
2226 * This corresponds to the pseudocode IsReqExecPriNeg().
2227 */
2228 #ifndef CONFIG_USER_ONLY
2229 bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure);
2230 #else
2231 static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure)
2232 {
2233 return false;
2234 }
2235 #endif
2236
2237 /* Interface for defining coprocessor registers.
2238 * Registers are defined in tables of arm_cp_reginfo structs
2239 * which are passed to define_arm_cp_regs().
2240 */
2241
2242 /* When looking up a coprocessor register we look for it
2243 * via an integer which encodes all of:
2244 * coprocessor number
2245 * Crn, Crm, opc1, opc2 fields
2246 * 32 or 64 bit register (ie is it accessed via MRC/MCR
2247 * or via MRRC/MCRR?)
2248 * non-secure/secure bank (AArch32 only)
2249 * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
2250 * (In this case crn and opc2 should be zero.)
2251 * For AArch64, there is no 32/64 bit size distinction;
2252 * instead all registers have a 2 bit op0, 3 bit op1 and op2,
2253 * and 4 bit CRn and CRm. The encoding patterns are chosen
2254 * to be easy to convert to and from the KVM encodings, and also
2255 * so that the hashtable can contain both AArch32 and AArch64
2256 * registers (to allow for interprocessing where we might run
2257 * 32 bit code on a 64 bit core).
2258 */
2259 /* This bit is private to our hashtable cpreg; in KVM register
2260 * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64
2261 * in the upper bits of the 64 bit ID.
2262 */
2263 #define CP_REG_AA64_SHIFT 28
2264 #define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT)
2265
2266 /* To enable banking of coprocessor registers depending on ns-bit we
2267 * add a bit to distinguish between secure and non-secure cpregs in the
2268 * hashtable.
2269 */
2270 #define CP_REG_NS_SHIFT 29
2271 #define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT)
2272
2273 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \
2274 ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \
2275 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
2276
2277 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \
2278 (CP_REG_AA64_MASK | \
2279 ((cp) << CP_REG_ARM_COPROC_SHIFT) | \
2280 ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
2281 ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
2282 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
2283 ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
2284 ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
2285
2286 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
2287 * version used as a key for the coprocessor register hashtable
2288 */
2289 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
2290 {
2291 uint32_t cpregid = kvmid;
2292 if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) {
2293 cpregid |= CP_REG_AA64_MASK;
2294 } else {
2295 if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
2296 cpregid |= (1 << 15);
2297 }
2298
2299 /* KVM is always non-secure so add the NS flag on AArch32 register
2300 * entries.
2301 */
2302 cpregid |= 1 << CP_REG_NS_SHIFT;
2303 }
2304 return cpregid;
2305 }
2306
2307 /* Convert a truncated 32 bit hashtable key into the full
2308 * 64 bit KVM register ID.
2309 */
2310 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
2311 {
2312 uint64_t kvmid;
2313
2314 if (cpregid & CP_REG_AA64_MASK) {
2315 kvmid = cpregid & ~CP_REG_AA64_MASK;
2316 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM64;
2317 } else {
2318 kvmid = cpregid & ~(1 << 15);
2319 if (cpregid & (1 << 15)) {
2320 kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
2321 } else {
2322 kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
2323 }
2324 }
2325 return kvmid;
2326 }
2327
2328 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
2329 * special-behaviour cp reg and bits [11..8] indicate what behaviour
2330 * it has. Otherwise it is a simple cp reg, where CONST indicates that
2331 * TCG can assume the value to be constant (ie load at translate time)
2332 * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
2333 * indicates that the TB should not be ended after a write to this register
2334 * (the default is that the TB ends after cp writes). OVERRIDE permits
2335 * a register definition to override a previous definition for the
2336 * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
2337 * old must have the OVERRIDE bit set.
2338 * ALIAS indicates that this register is an alias view of some underlying
2339 * state which is also visible via another register, and that the other
2340 * register is handling migration and reset; registers marked ALIAS will not be
2341 * migrated but may have their state set by syncing of register state from KVM.
2342 * NO_RAW indicates that this register has no underlying state and does not
2343 * support raw access for state saving/loading; it will not be used for either
2344 * migration or KVM state synchronization. (Typically this is for "registers"
2345 * which are actually used as instructions for cache maintenance and so on.)
2346 * IO indicates that this register does I/O and therefore its accesses
2347 * need to be marked with gen_io_start() and also end the TB. In particular,
2348 * registers which implement clocks or timers require this.
2349 * RAISES_EXC is for when the read or write hook might raise an exception;
2350 * the generated code will synchronize the CPU state before calling the hook
2351 * so that it is safe for the hook to call raise_exception().
2352 * NEWEL is for writes to registers that might change the exception
2353 * level - typically on older ARM chips. For those cases we need to
2354 * re-read the new el when recomputing the translation flags.
2355 */
2356 #define ARM_CP_SPECIAL 0x0001
2357 #define ARM_CP_CONST 0x0002
2358 #define ARM_CP_64BIT 0x0004
2359 #define ARM_CP_SUPPRESS_TB_END 0x0008
2360 #define ARM_CP_OVERRIDE 0x0010
2361 #define ARM_CP_ALIAS 0x0020
2362 #define ARM_CP_IO 0x0040
2363 #define ARM_CP_NO_RAW 0x0080
2364 #define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100)
2365 #define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200)
2366 #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
2367 #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
2368 #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
2369 #define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600)
2370 #define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700)
2371 #define ARM_LAST_SPECIAL ARM_CP_DC_GZVA
2372 #define ARM_CP_FPU 0x1000
2373 #define ARM_CP_SVE 0x2000
2374 #define ARM_CP_NO_GDB 0x4000
2375 #define ARM_CP_RAISES_EXC 0x8000
2376 #define ARM_CP_NEWEL 0x10000
2377 /* Used only as a terminator for ARMCPRegInfo lists */
2378 #define ARM_CP_SENTINEL 0xfffff
2379 /* Mask of only the flag bits in a type field */
2380 #define ARM_CP_FLAG_MASK 0x1f0ff
2381
2382 /* Valid values for ARMCPRegInfo state field, indicating which of
2383 * the AArch32 and AArch64 execution states this register is visible in.
2384 * If the reginfo doesn't explicitly specify then it is AArch32 only.
2385 * If the reginfo is declared to be visible in both states then a second
2386 * reginfo is synthesised for the AArch32 view of the AArch64 register,
2387 * such that the AArch32 view is the lower 32 bits of the AArch64 one.
2388 * Note that we rely on the values of these enums as we iterate through
2389 * the various states in some places.
2390 */
2391 enum {
2392 ARM_CP_STATE_AA32 = 0,
2393 ARM_CP_STATE_AA64 = 1,
2394 ARM_CP_STATE_BOTH = 2,
2395 };
2396
2397 /* ARM CP register secure state flags. These flags identify security state
2398 * attributes for a given CP register entry.
2399 * The existence of both or neither secure and non-secure flags indicates that
2400 * the register has both a secure and non-secure hash entry. A single one of
2401 * these flags causes the register to only be hashed for the specified
2402 * security state.
2403 * Although definitions may have any combination of the S/NS bits, each
2404 * registered entry will only have one to identify whether the entry is secure
2405 * or non-secure.
2406 */
2407 enum {
2408 ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */
2409 ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */
2410 };
2411
2412 /* Return true if cptype is a valid type field. This is used to try to
2413 * catch errors where the sentinel has been accidentally left off the end
2414 * of a list of registers.
2415 */
2416 static inline bool cptype_valid(int cptype)
2417 {
2418 return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
2419 || ((cptype & ARM_CP_SPECIAL) &&
2420 ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
2421 }
2422
2423 /* Access rights:
2424 * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
2425 * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
2426 * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
2427 * (ie any of the privileged modes in Secure state, or Monitor mode).
2428 * If a register is accessible in one privilege level it's always accessible
2429 * in higher privilege levels too. Since "Secure PL1" also follows this rule
2430 * (ie anything visible in PL2 is visible in S-PL1, some things are only
2431 * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
2432 * terminology a little and call this PL3.
2433 * In AArch64 things are somewhat simpler as the PLx bits line up exactly
2434 * with the ELx exception levels.
2435 *
2436 * If access permissions for a register are more complex than can be
2437 * described with these bits, then use a laxer set of restrictions, and
2438 * do the more restrictive/complex check inside a helper function.
2439 */
2440 #define PL3_R 0x80
2441 #define PL3_W 0x40
2442 #define PL2_R (0x20 | PL3_R)
2443 #define PL2_W (0x10 | PL3_W)
2444 #define PL1_R (0x08 | PL2_R)
2445 #define PL1_W (0x04 | PL2_W)
2446 #define PL0_R (0x02 | PL1_R)
2447 #define PL0_W (0x01 | PL1_W)
2448
2449 /*
2450 * For user-mode some registers are accessible to EL0 via a kernel
2451 * trap-and-emulate ABI. In this case we define the read permissions
2452 * as actually being PL0_R. However some bits of any given register
2453 * may still be masked.
2454 */
2455 #ifdef CONFIG_USER_ONLY
2456 #define PL0U_R PL0_R
2457 #else
2458 #define PL0U_R PL1_R
2459 #endif
2460
2461 #define PL3_RW (PL3_R | PL3_W)
2462 #define PL2_RW (PL2_R | PL2_W)
2463 #define PL1_RW (PL1_R | PL1_W)
2464 #define PL0_RW (PL0_R | PL0_W)
2465
2466 /* Return the highest implemented Exception Level */
2467 static inline int arm_highest_el(CPUARMState *env)
2468 {
2469 if (arm_feature(env, ARM_FEATURE_EL3)) {
2470 return 3;
2471 }
2472 if (arm_feature(env, ARM_FEATURE_EL2)) {
2473 return 2;
2474 }
2475 return 1;
2476 }
2477
2478 /* Return true if a v7M CPU is in Handler mode */
2479 static inline bool arm_v7m_is_handler_mode(CPUARMState *env)
2480 {
2481 return env->v7m.exception != 0;
2482 }
2483
2484 /* Return the current Exception Level (as per ARMv8; note that this differs
2485 * from the ARMv7 Privilege Level).
2486 */
2487 static inline int arm_current_el(CPUARMState *env)
2488 {
2489 if (arm_feature(env, ARM_FEATURE_M)) {
2490 return arm_v7m_is_handler_mode(env) ||
2491 !(env->v7m.control[env->v7m.secure] & 1);
2492 }
2493
2494 if (is_a64(env)) {
2495 return extract32(env->pstate, 2, 2);
2496 }
2497
2498 switch (env->uncached_cpsr & 0x1f) {
2499 case ARM_CPU_MODE_USR:
2500 return 0;
2501 case ARM_CPU_MODE_HYP:
2502 return 2;
2503 case ARM_CPU_MODE_MON:
2504 return 3;
2505 default:
2506 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) {
2507 /* If EL3 is 32-bit then all secure privileged modes run in
2508 * EL3
2509 */
2510 return 3;
2511 }
2512
2513 return 1;
2514 }
2515 }
2516
2517 typedef struct ARMCPRegInfo ARMCPRegInfo;
2518
2519 typedef enum CPAccessResult {
2520 /* Access is permitted */
2521 CP_ACCESS_OK = 0,
2522 /* Access fails due to a configurable trap or enable which would
2523 * result in a categorized exception syndrome giving information about
2524 * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6,
2525 * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or
2526 * PL1 if in EL0, otherwise to the current EL).
2527 */
2528 CP_ACCESS_TRAP = 1,
2529 /* Access fails and results in an exception syndrome 0x0 ("uncategorized").
2530 * Note that this is not a catch-all case -- the set of cases which may
2531 * result in this failure is specifically defined by the architecture.
2532 */
2533 CP_ACCESS_TRAP_UNCATEGORIZED = 2,
2534 /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */
2535 CP_ACCESS_TRAP_EL2 = 3,
2536 CP_ACCESS_TRAP_EL3 = 4,
2537 /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
2538 CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
2539 CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
2540 /* Access fails and results in an exception syndrome for an FP access,
2541 * trapped directly to EL2 or EL3
2542 */
2543 CP_ACCESS_TRAP_FP_EL2 = 7,
2544 CP_ACCESS_TRAP_FP_EL3 = 8,
2545 } CPAccessResult;
2546
2547 /* Access functions for coprocessor registers. These cannot fail and
2548 * may not raise exceptions.
2549 */
2550 typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2551 typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
2552 uint64_t value);
2553 /* Access permission check functions for coprocessor registers. */
2554 typedef CPAccessResult CPAccessFn(CPUARMState *env,
2555 const ARMCPRegInfo *opaque,
2556 bool isread);
2557 /* Hook function for register reset */
2558 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
2559
2560 #define CP_ANY 0xff
2561
2562 /* Definition of an ARM coprocessor register */
2563 struct ARMCPRegInfo {
2564 /* Name of register (useful mainly for debugging, need not be unique) */
2565 const char *name;
2566 /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
2567 * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
2568 * 'wildcard' field -- any value of that field in the MRC/MCR insn
2569 * will be decoded to this register. The register read and write
2570 * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
2571 * used by the program, so it is possible to register a wildcard and
2572 * then behave differently on read/write if necessary.
2573 * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
2574 * must both be zero.
2575 * For AArch64-visible registers, opc0 is also used.
2576 * Since there are no "coprocessors" in AArch64, cp is purely used as a
2577 * way to distinguish (for KVM's benefit) guest-visible system registers
2578 * from demuxed ones provided to preserve the "no side effects on
2579 * KVM register read/write from QEMU" semantics. cp==0x13 is guest
2580 * visible (to match KVM's encoding); cp==0 will be converted to
2581 * cp==0x13 when the ARMCPRegInfo is registered, for convenience.
2582 */
2583 uint8_t cp;
2584 uint8_t crn;
2585 uint8_t crm;
2586 uint8_t opc0;
2587 uint8_t opc1;
2588 uint8_t opc2;
2589 /* Execution state in which this register is visible: ARM_CP_STATE_* */
2590 int state;
2591 /* Register type: ARM_CP_* bits/values */
2592 int type;
2593 /* Access rights: PL*_[RW] */
2594 int access;
2595 /* Security state: ARM_CP_SECSTATE_* bits/values */
2596 int secure;
2597 /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
2598 * this register was defined: can be used to hand data through to the
2599 * register read/write functions, since they are passed the ARMCPRegInfo*.
2600 */
2601 void *opaque;
2602 /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
2603 * fieldoffset is non-zero, the reset value of the register.
2604 */
2605 uint64_t resetvalue;
2606 /* Offset of the field in CPUARMState for this register.
2607 *
2608 * This is not needed if either:
2609 * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
2610 * 2. both readfn and writefn are specified
2611 */
2612 ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
2613
2614 /* Offsets of the secure and non-secure fields in CPUARMState for the
2615 * register if it is banked. These fields are only used during the static
2616 * registration of a register. During hashing the bank associated
2617 * with a given security state is copied to fieldoffset which is used from
2618 * there on out.
2619 *
2620 * It is expected that register definitions use either fieldoffset or
2621 * bank_fieldoffsets in the definition but not both. It is also expected
2622 * that both bank offsets are set when defining a banked register. This
2623 * use indicates that a register is banked.
2624 */
2625 ptrdiff_t bank_fieldoffsets[2];
2626
2627 /* Function for making any access checks for this register in addition to
2628 * those specified by the 'access' permissions bits. If NULL, no extra
2629 * checks required. The access check is performed at runtime, not at
2630 * translate time.
2631 */
2632 CPAccessFn *accessfn;
2633 /* Function for handling reads of this register. If NULL, then reads
2634 * will be done by loading from the offset into CPUARMState specified
2635 * by fieldoffset.
2636 */
2637 CPReadFn *readfn;
2638 /* Function for handling writes of this register. If NULL, then writes
2639 * will be done by writing to the offset into CPUARMState specified
2640 * by fieldoffset.
2641 */
2642 CPWriteFn *writefn;
2643 /* Function for doing a "raw" read; used when we need to copy
2644 * coprocessor state to the kernel for KVM or out for
2645 * migration. This only needs to be provided if there is also a
2646 * readfn and it has side effects (for instance clear-on-read bits).
2647 */
2648 CPReadFn *raw_readfn;
2649 /* Function for doing a "raw" write; used when we need to copy KVM
2650 * kernel coprocessor state into userspace, or for inbound
2651 * migration. This only needs to be provided if there is also a
2652 * writefn and it masks out "unwritable" bits or has write-one-to-clear
2653 * or similar behaviour.
2654 */
2655 CPWriteFn *raw_writefn;
2656 /* Function for resetting the register. If NULL, then reset will be done
2657 * by writing resetvalue to the field specified in fieldoffset. If
2658 * fieldoffset is 0 then no reset will be done.
2659 */
2660 CPResetFn *resetfn;
2661
2662 /*
2663 * "Original" writefn and readfn.
2664 * For ARMv8.1-VHE register aliases, we overwrite the read/write
2665 * accessor functions of various EL1/EL0 to perform the runtime
2666 * check for which sysreg should actually be modified, and then
2667 * forwards the operation. Before overwriting the accessors,
2668 * the original function is copied here, so that accesses that
2669 * really do go to the EL1/EL0 version proceed normally.
2670 * (The corresponding EL2 register is linked via opaque.)
2671 */
2672 CPReadFn *orig_readfn;
2673 CPWriteFn *orig_writefn;
2674 };
2675
2676 /* Macros which are lvalues for the field in CPUARMState for the
2677 * ARMCPRegInfo *ri.
2678 */
2679 #define CPREG_FIELD32(env, ri) \
2680 (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
2681 #define CPREG_FIELD64(env, ri) \
2682 (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
2683
2684 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
2685
2686 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2687 const ARMCPRegInfo *regs, void *opaque);
2688 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2689 const ARMCPRegInfo *regs, void *opaque);
2690 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
2691 {
2692 define_arm_cp_regs_with_opaque(cpu, regs, 0);
2693 }
2694 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
2695 {
2696 define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
2697 }
2698 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp);
2699
2700 /*
2701 * Definition of an ARM co-processor register as viewed from
2702 * userspace. This is used for presenting sanitised versions of
2703 * registers to userspace when emulating the Linux AArch64 CPU
2704 * ID/feature ABI (advertised as HWCAP_CPUID).
2705 */
2706 typedef struct ARMCPRegUserSpaceInfo {
2707 /* Name of register */
2708 const char *name;
2709
2710 /* Is the name actually a glob pattern */
2711 bool is_glob;
2712
2713 /* Only some bits are exported to user space */
2714 uint64_t exported_bits;
2715
2716 /* Fixed bits are applied after the mask */
2717 uint64_t fixed_bits;
2718 } ARMCPRegUserSpaceInfo;
2719
2720 #define REGUSERINFO_SENTINEL { .name = NULL }
2721
2722 void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods);
2723
2724 /* CPWriteFn that can be used to implement writes-ignored behaviour */
2725 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2726 uint64_t value);
2727 /* CPReadFn that can be used for read-as-zero behaviour */
2728 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri);
2729
2730 /* CPResetFn that does nothing, for use if no reset is required even
2731 * if fieldoffset is non zero.
2732 */
2733 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
2734
2735 /* Return true if this reginfo struct's field in the cpu state struct
2736 * is 64 bits wide.
2737 */
2738 static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
2739 {
2740 return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
2741 }
2742
2743 static inline bool cp_access_ok(int current_el,
2744 const ARMCPRegInfo *ri, int isread)
2745 {
2746 return (ri->access >> ((current_el * 2) + isread)) & 1;
2747 }
2748
2749 /* Raw read of a coprocessor register (as needed for migration, etc) */
2750 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri);
2751
2752 /**
2753 * write_list_to_cpustate
2754 * @cpu: ARMCPU
2755 *
2756 * For each register listed in the ARMCPU cpreg_indexes list, write
2757 * its value from the cpreg_values list into the ARMCPUState structure.
2758 * This updates TCG's working data structures from KVM data or
2759 * from incoming migration state.
2760 *
2761 * Returns: true if all register values were updated correctly,
2762 * false if some register was unknown or could not be written.
2763 * Note that we do not stop early on failure -- we will attempt
2764 * writing all registers in the list.
2765 */
2766 bool write_list_to_cpustate(ARMCPU *cpu);
2767
2768 /**
2769 * write_cpustate_to_list:
2770 * @cpu: ARMCPU
2771 * @kvm_sync: true if this is for syncing back to KVM
2772 *
2773 * For each register listed in the ARMCPU cpreg_indexes list, write
2774 * its value from the ARMCPUState structure into the cpreg_values list.
2775 * This is used to copy info from TCG's working data structures into
2776 * KVM or for outbound migration.
2777 *
2778 * @kvm_sync is true if we are doing this in order to sync the
2779 * register state back to KVM. In this case we will only update
2780 * values in the list if the previous list->cpustate sync actually
2781 * successfully wrote the CPU state. Otherwise we will keep the value
2782 * that is in the list.
2783 *
2784 * Returns: true if all register values were read correctly,
2785 * false if some register was unknown or could not be read.
2786 * Note that we do not stop early on failure -- we will attempt
2787 * reading all registers in the list.
2788 */
2789 bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
2790
2791 #define ARM_CPUID_TI915T 0x54029152
2792 #define ARM_CPUID_TI925T 0x54029252
2793
2794 #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
2795 #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
2796 #define CPU_RESOLVING_TYPE TYPE_ARM_CPU
2797
2798 #define cpu_signal_handler cpu_arm_signal_handler
2799 #define cpu_list arm_cpu_list
2800
2801 /* ARM has the following "translation regimes" (as the ARM ARM calls them):
2802 *
2803 * If EL3 is 64-bit:
2804 * + NonSecure EL1 & 0 stage 1
2805 * + NonSecure EL1 & 0 stage 2
2806 * + NonSecure EL2
2807 * + NonSecure EL2 & 0 (ARMv8.1-VHE)
2808 * + Secure EL1 & 0
2809 * + Secure EL3
2810 * If EL3 is 32-bit:
2811 * + NonSecure PL1 & 0 stage 1
2812 * + NonSecure PL1 & 0 stage 2
2813 * + NonSecure PL2
2814 * + Secure PL0
2815 * + Secure PL1
2816 * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.)
2817 *
2818 * For QEMU, an mmu_idx is not quite the same as a translation regime because:
2819 * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_idxes,
2820 * because they may differ in access permissions even if the VA->PA map is
2821 * the same
2822 * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage 1+2
2823 * translation, which means that we have one mmu_idx that deals with two
2824 * concatenated translation regimes [this sort of combined s1+2 TLB is
2825 * architecturally permitted]
2826 * 3. we don't need to allocate an mmu_idx to translations that we won't be
2827 * handling via the TLB. The only way to do a stage 1 translation without
2828 * the immediate stage 2 translation is via the ATS or AT system insns,
2829 * which can be slow-pathed and always do a page table walk.
2830 * The only use of stage 2 translations is either as part of an s1+2
2831 * lookup or when loading the descriptors during a stage 1 page table walk,
2832 * and in both those cases we don't use the TLB.
2833 * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3"
2834 * translation regimes, because they map reasonably well to each other
2835 * and they can't both be active at the same time.
2836 * 5. we want to be able to use the TLB for accesses done as part of a
2837 * stage1 page table walk, rather than having to walk the stage2 page
2838 * table over and over.
2839 * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
2840 * Never (PAN) bit within PSTATE.
2841 *
2842 * This gives us the following list of cases:
2843 *
2844 * NS EL0 EL1&0 stage 1+2 (aka NS PL0)
2845 * NS EL1 EL1&0 stage 1+2 (aka NS PL1)
2846 * NS EL1 EL1&0 stage 1+2 +PAN
2847 * NS EL0 EL2&0
2848 * NS EL2 EL2&0
2849 * NS EL2 EL2&0 +PAN
2850 * NS EL2 (aka NS PL2)
2851 * S EL0 EL1&0 (aka S PL0)
2852 * S EL1 EL1&0 (not used if EL3 is 32 bit)
2853 * S EL1 EL1&0 +PAN
2854 * S EL3 (aka S PL1)
2855 *
2856 * for a total of 11 different mmu_idx.
2857 *
2858 * R profile CPUs have an MPU, but can use the same set of MMU indexes
2859 * as A profile. They only need to distinguish NS EL0 and NS EL1 (and
2860 * NS EL2 if we ever model a Cortex-R52).
2861 *
2862 * M profile CPUs are rather different as they do not have a true MMU.
2863 * They have the following different MMU indexes:
2864 * User
2865 * Privileged
2866 * User, execution priority negative (ie the MPU HFNMIENA bit may apply)
2867 * Privileged, execution priority negative (ditto)
2868 * If the CPU supports the v8M Security Extension then there are also:
2869 * Secure User
2870 * Secure Privileged
2871 * Secure User, execution priority negative
2872 * Secure Privileged, execution priority negative
2873 *
2874 * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code
2875 * are not quite the same -- different CPU types (most notably M profile
2876 * vs A/R profile) would like to use MMU indexes with different semantics,
2877 * but since we don't ever need to use all of those in a single CPU we
2878 * can avoid having to set NB_MMU_MODES to "total number of A profile MMU
2879 * modes + total number of M profile MMU modes". The lower bits of
2880 * ARMMMUIdx are the core TLB mmu index, and the higher bits are always
2881 * the same for any particular CPU.
2882 * Variables of type ARMMUIdx are always full values, and the core
2883 * index values are in variables of type 'int'.
2884 *
2885 * Our enumeration includes at the end some entries which are not "true"
2886 * mmu_idx values in that they don't have corresponding TLBs and are only
2887 * valid for doing slow path page table walks.
2888 *
2889 * The constant names here are patterned after the general style of the names
2890 * of the AT/ATS operations.
2891 * The values used are carefully arranged to make mmu_idx => EL lookup easy.
2892 * For M profile we arrange them to have a bit for priv, a bit for negpri
2893 * and a bit for secure.
2894 */
2895 #define ARM_MMU_IDX_A 0x10 /* A profile */
2896 #define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
2897 #define ARM_MMU_IDX_M 0x40 /* M profile */
2898
2899 /* Meanings of the bits for M profile mmu idx values */
2900 #define ARM_MMU_IDX_M_PRIV 0x1
2901 #define ARM_MMU_IDX_M_NEGPRI 0x2
2902 #define ARM_MMU_IDX_M_S 0x4 /* Secure */
2903
2904 #define ARM_MMU_IDX_TYPE_MASK \
2905 (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB)
2906 #define ARM_MMU_IDX_COREIDX_MASK 0xf
2907
2908 typedef enum ARMMMUIdx {
2909 /*
2910 * A-profile.
2911 */
2912 ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A,
2913 ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A,
2914
2915 ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A,
2916 ARMMMUIdx_E10_1_PAN = 3 | ARM_MMU_IDX_A,
2917
2918 ARMMMUIdx_E2 = 4 | ARM_MMU_IDX_A,
2919 ARMMMUIdx_E20_2 = 5 | ARM_MMU_IDX_A,
2920 ARMMMUIdx_E20_2_PAN = 6 | ARM_MMU_IDX_A,
2921
2922 ARMMMUIdx_SE10_0 = 7 | ARM_MMU_IDX_A,
2923 ARMMMUIdx_SE10_1 = 8 | ARM_MMU_IDX_A,
2924 ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A,
2925 ARMMMUIdx_SE3 = 10 | ARM_MMU_IDX_A,
2926
2927 /*
2928 * These are not allocated TLBs and are used only for AT system
2929 * instructions or for the first stage of an S12 page table walk.
2930 */
2931 ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
2932 ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
2933 ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
2934 /*
2935 * Not allocated a TLB: used only for second stage of an S12 page
2936 * table walk, or for descriptor loads during first stage of an S1
2937 * page table walk. Note that if we ever want to have a TLB for this
2938 * then various TLB flush insns which currently are no-ops or flush
2939 * only stage 1 MMU indexes will need to change to flush stage 2.
2940 */
2941 ARMMMUIdx_Stage2 = 3 | ARM_MMU_IDX_NOTLB,
2942
2943 /*
2944 * M-profile.
2945 */
2946 ARMMMUIdx_MUser = ARM_MMU_IDX_M,
2947 ARMMMUIdx_MPriv = ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV,
2948 ARMMMUIdx_MUserNegPri = ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI,
2949 ARMMMUIdx_MPrivNegPri = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI,
2950 ARMMMUIdx_MSUser = ARMMMUIdx_MUser | ARM_MMU_IDX_M_S,
2951 ARMMMUIdx_MSPriv = ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S,
2952 ARMMMUIdx_MSUserNegPri = ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S,
2953 ARMMMUIdx_MSPrivNegPri = ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S,
2954 } ARMMMUIdx;
2955
2956 /*
2957 * Bit macros for the core-mmu-index values for each index,
2958 * for use when calling tlb_flush_by_mmuidx() and friends.
2959 */
2960 #define TO_CORE_BIT(NAME) \
2961 ARMMMUIdxBit_##NAME = 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_MASK)
2962
2963 typedef enum ARMMMUIdxBit {
2964 TO_CORE_BIT(E10_0),
2965 TO_CORE_BIT(E20_0),
2966 TO_CORE_BIT(E10_1),
2967 TO_CORE_BIT(E10_1_PAN),
2968 TO_CORE_BIT(E2),
2969 TO_CORE_BIT(E20_2),
2970 TO_CORE_BIT(E20_2_PAN),
2971 TO_CORE_BIT(SE10_0),
2972 TO_CORE_BIT(SE10_1),
2973 TO_CORE_BIT(SE10_1_PAN),
2974 TO_CORE_BIT(SE3),
2975
2976 TO_CORE_BIT(MUser),
2977 TO_CORE_BIT(MPriv),
2978 TO_CORE_BIT(MUserNegPri),
2979 TO_CORE_BIT(MPrivNegPri),
2980 TO_CORE_BIT(MSUser),
2981 TO_CORE_BIT(MSPriv),
2982 TO_CORE_BIT(MSUserNegPri),
2983 TO_CORE_BIT(MSPrivNegPri),
2984 } ARMMMUIdxBit;
2985
2986 #undef TO_CORE_BIT
2987
2988 #define MMU_USER_IDX 0
2989
2990 /* Indexes used when registering address spaces with cpu_address_space_init */
2991 typedef enum ARMASIdx {
2992 ARMASIdx_NS = 0,
2993 ARMASIdx_S = 1,
2994 ARMASIdx_TagNS = 2,
2995 ARMASIdx_TagS = 3,
2996 } ARMASIdx;
2997
2998 /* Return the Exception Level targeted by debug exceptions. */
2999 static inline int arm_debug_target_el(CPUARMState *env)
3000 {
3001 bool secure = arm_is_secure(env);
3002 bool route_to_el2 = false;
3003
3004 if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
3005 route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
3006 env->cp15.mdcr_el2 & MDCR_TDE;
3007 }
3008
3009 if (route_to_el2) {
3010 return 2;
3011 } else if (arm_feature(env, ARM_FEATURE_EL3) &&
3012 !arm_el_is_aa64(env, 3) && secure) {
3013 return 3;
3014 } else {
3015 return 1;
3016 }
3017 }
3018
3019 static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu)
3020 {
3021 /* If all the CLIDR.Ctypem bits are 0 there are no caches, and
3022 * CSSELR is RAZ/WI.
3023 */
3024 return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0;
3025 }
3026
3027 /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */
3028 static inline bool aa64_generate_debug_exceptions(CPUARMState *env)
3029 {
3030 int cur_el = arm_current_el(env);
3031 int debug_el;
3032
3033 if (cur_el == 3) {
3034 return false;
3035 }
3036
3037 /* MDCR_EL3.SDD disables debug events from Secure state */
3038 if (arm_is_secure_below_el3(env)
3039 && extract32(env->cp15.mdcr_el3, 16, 1)) {
3040 return false;
3041 }
3042
3043 /*
3044 * Same EL to same EL debug exceptions need MDSCR_KDE enabled
3045 * while not masking the (D)ebug bit in DAIF.
3046 */
3047 debug_el = arm_debug_target_el(env);
3048
3049 if (cur_el == debug_el) {
3050 return extract32(env->cp15.mdscr_el1, 13, 1)
3051 && !(env->daif & PSTATE_D);
3052 }
3053
3054 /* Otherwise the debug target needs to be a higher EL */
3055 return debug_el > cur_el;
3056 }
3057
3058 static inline bool aa32_generate_debug_exceptions(CPUARMState *env)
3059 {
3060 int el = arm_current_el(env);
3061
3062 if (el == 0 && arm_el_is_aa64(env, 1)) {
3063 return aa64_generate_debug_exceptions(env);
3064 }
3065
3066 if (arm_is_secure(env)) {
3067 int spd;
3068
3069 if (el == 0 && (env->cp15.sder & 1)) {
3070 /* SDER.SUIDEN means debug exceptions from Secure EL0
3071 * are always enabled. Otherwise they are controlled by
3072 * SDCR.SPD like those from other Secure ELs.
3073 */
3074 return true;
3075 }
3076
3077 spd = extract32(env->cp15.mdcr_el3, 14, 2);
3078 switch (spd) {
3079 case 1:
3080 /* SPD == 0b01 is reserved, but behaves as 0b00. */
3081 case 0:
3082 /* For 0b00 we return true if external secure invasive debug
3083 * is enabled. On real hardware this is controlled by external
3084 * signals to the core. QEMU always permits debug, and behaves
3085 * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high.
3086 */
3087 return true;
3088 case 2:
3089 return false;
3090 case 3:
3091 return true;
3092 }
3093 }
3094
3095 return el != 2;
3096 }
3097
3098 /* Return true if debugging exceptions are currently enabled.
3099 * This corresponds to what in ARM ARM pseudocode would be
3100 * if UsingAArch32() then
3101 * return AArch32.GenerateDebugExceptions()
3102 * else
3103 * return AArch64.GenerateDebugExceptions()
3104 * We choose to push the if() down into this function for clarity,
3105 * since the pseudocode has it at all callsites except for the one in
3106 * CheckSoftwareStep(), where it is elided because both branches would
3107 * always return the same value.
3108 */
3109 static inline bool arm_generate_debug_exceptions(CPUARMState *env)
3110 {
3111 if (env->aarch64) {
3112 return aa64_generate_debug_exceptions(env);
3113 } else {
3114 return aa32_generate_debug_exceptions(env);
3115 }
3116 }
3117
3118 /* Is single-stepping active? (Note that the "is EL_D AArch64?" check
3119 * implicitly means this always returns false in pre-v8 CPUs.)
3120 */
3121 static inline bool arm_singlestep_active(CPUARMState *env)
3122 {
3123 return extract32(env->cp15.mdscr_el1, 0, 1)
3124 && arm_el_is_aa64(env, arm_debug_target_el(env))
3125 && arm_generate_debug_exceptions(env);
3126 }
3127
3128 static inline bool arm_sctlr_b(CPUARMState *env)
3129 {
3130 return
3131 /* We need not implement SCTLR.ITD in user-mode emulation, so
3132 * let linux-user ignore the fact that it conflicts with SCTLR_B.
3133 * This lets people run BE32 binaries with "-cpu any".
3134 */
3135 #ifndef CONFIG_USER_ONLY
3136 !arm_feature(env, ARM_FEATURE_V7) &&
3137 #endif
3138 (env->cp15.sctlr_el[1] & SCTLR_B) != 0;
3139 }
3140
3141 uint64_t arm_sctlr(CPUARMState *env, int el);
3142
3143 static inline bool arm_cpu_data_is_big_endian_a32(CPUARMState *env,
3144 bool sctlr_b)
3145 {
3146 #ifdef CONFIG_USER_ONLY
3147 /*
3148 * In system mode, BE32 is modelled in line with the
3149 * architecture (as word-invariant big-endianness), where loads
3150 * and stores are done little endian but from addresses which
3151 * are adjusted by XORing with the appropriate constant. So the
3152 * endianness to use for the raw data access is not affected by
3153 * SCTLR.B.
3154 * In user mode, however, we model BE32 as byte-invariant
3155 * big-endianness (because user-only code cannot tell the
3156 * difference), and so we need to use a data access endianness
3157 * that depends on SCTLR.B.
3158 */
3159 if (sctlr_b) {
3160 return true;
3161 }
3162 #endif
3163 /* In 32bit endianness is determined by looking at CPSR's E bit */
3164 return env->uncached_cpsr & CPSR_E;
3165 }
3166
3167 static inline bool arm_cpu_data_is_big_endian_a64(int el, uint64_t sctlr)
3168 {
3169 return sctlr & (el ? SCTLR_EE : SCTLR_E0E);
3170 }
3171
3172 /* Return true if the processor is in big-endian mode. */
3173 static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
3174 {
3175 if (!is_a64(env)) {
3176 return arm_cpu_data_is_big_endian_a32(env, arm_sctlr_b(env));
3177 } else {
3178 int cur_el = arm_current_el(env);
3179 uint64_t sctlr = arm_sctlr(env, cur_el);
3180 return arm_cpu_data_is_big_endian_a64(cur_el, sctlr);
3181 }
3182 }
3183
3184 typedef CPUARMState CPUArchState;
3185 typedef ARMCPU ArchCPU;
3186
3187 #include "exec/cpu-all.h"
3188
3189 /*
3190 * Bit usage in the TB flags field: bit 31 indicates whether we are
3191 * in 32 or 64 bit mode. The meaning of the other bits depends on that.
3192 * We put flags which are shared between 32 and 64 bit mode at the top
3193 * of the word, and flags which apply to only one mode at the bottom.
3194 *
3195 * 31 20 18 14 9 0
3196 * +--------------+-----+-----+----------+--------------+
3197 * | | | TBFLAG_A32 | |
3198 * | | +-----+----------+ TBFLAG_AM32 |
3199 * | TBFLAG_ANY | |TBFLAG_M32| |
3200 * | +-----------+----------+--------------|
3201 * | | TBFLAG_A64 |
3202 * +--------------+-------------------------------------+
3203 * 31 20 0
3204 *
3205 * Unless otherwise noted, these bits are cached in env->hflags.
3206 */
3207 FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
3208 FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1)
3209 FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */
3210 FIELD(TBFLAG_ANY, BE_DATA, 28, 1)
3211 FIELD(TBFLAG_ANY, MMUIDX, 24, 4)
3212 /* Target EL if we take a floating-point-disabled exception */
3213 FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2)
3214 /* For A-profile only, target EL for debug exceptions. */
3215 FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2)
3216
3217 /*
3218 * Bit usage when in AArch32 state, both A- and M-profile.
3219 */
3220 FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */
3221 FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */
3222
3223 /*
3224 * Bit usage when in AArch32 state, for A-profile only.
3225 */
3226 FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */
3227 FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */
3228 /*
3229 * We store the bottom two bits of the CPAR as TB flags and handle
3230 * checks on the other bits at runtime. This shares the same bits as
3231 * VECSTRIDE, which is OK as no XScale CPU has VFP.
3232 * Not cached, because VECLEN+VECSTRIDE are not cached.
3233 */
3234 FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2)
3235 FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */
3236 FIELD(TBFLAG_A32, SCTLR_B, 15, 1)
3237 FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1)
3238 /*
3239 * Indicates whether cp register reads and writes by guest code should access
3240 * the secure or nonsecure bank of banked registers; note that this is not
3241 * the same thing as the current security state of the processor!
3242 */
3243 FIELD(TBFLAG_A32, NS, 17, 1)
3244
3245 /*
3246 * Bit usage when in AArch32 state, for M-profile only.
3247 */
3248 /* Handler (ie not Thread) mode */
3249 FIELD(TBFLAG_M32, HANDLER, 9, 1)
3250 /* Whether we should generate stack-limit checks */
3251 FIELD(TBFLAG_M32, STACKCHECK, 10, 1)
3252 /* Set if FPCCR.LSPACT is set */
3253 FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */
3254 /* Set if we must create a new FP context */
3255 FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */
3256 /* Set if FPCCR.S does not match current security state */
3257 FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */
3258
3259 /*
3260 * Bit usage when in AArch64 state
3261 */
3262 FIELD(TBFLAG_A64, TBII, 0, 2)
3263 FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
3264 FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
3265 FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
3266 FIELD(TBFLAG_A64, BT, 9, 1)
3267 FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */
3268 FIELD(TBFLAG_A64, TBID, 12, 2)
3269 FIELD(TBFLAG_A64, UNPRIV, 14, 1)
3270 FIELD(TBFLAG_A64, ATA, 15, 1)
3271 FIELD(TBFLAG_A64, TCMA, 16, 2)
3272 FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
3273 FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
3274
3275 /**
3276 * cpu_mmu_index:
3277 * @env: The cpu environment
3278 * @ifetch: True for code access, false for data access.
3279 *
3280 * Return the core mmu index for the current translation regime.
3281 * This function is used by generic TCG code paths.
3282 */
3283 static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
3284 {
3285 return FIELD_EX32(env->hflags, TBFLAG_ANY, MMUIDX);
3286 }
3287
3288 static inline bool bswap_code(bool sctlr_b)
3289 {
3290 #ifdef CONFIG_USER_ONLY
3291 /* BE8 (SCTLR.B = 0, TARGET_WORDS_BIGENDIAN = 1) is mixed endian.
3292 * The invalid combination SCTLR.B=1/CPSR.E=1/TARGET_WORDS_BIGENDIAN=0
3293 * would also end up as a mixed-endian mode with BE code, LE data.
3294 */
3295 return
3296 #ifdef TARGET_WORDS_BIGENDIAN
3297 1 ^
3298 #endif
3299 sctlr_b;
3300 #else
3301 /* All code access in ARM is little endian, and there are no loaders
3302 * doing swaps that need to be reversed
3303 */
3304 return 0;
3305 #endif
3306 }
3307
3308 #ifdef CONFIG_USER_ONLY
3309 static inline bool arm_cpu_bswap_data(CPUARMState *env)
3310 {
3311 return
3312 #ifdef TARGET_WORDS_BIGENDIAN
3313 1 ^
3314 #endif
3315 arm_cpu_data_is_big_endian(env);
3316 }
3317 #endif
3318
3319 void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
3320 target_ulong *cs_base, uint32_t *flags);
3321
3322 enum {
3323 QEMU_PSCI_CONDUIT_DISABLED = 0,
3324 QEMU_PSCI_CONDUIT_SMC = 1,
3325 QEMU_PSCI_CONDUIT_HVC = 2,
3326 };
3327
3328 #ifndef CONFIG_USER_ONLY
3329 /* Return the address space index to use for a memory access */
3330 static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
3331 {
3332 return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
3333 }
3334
3335 /* Return the AddressSpace to use for a memory access
3336 * (which depends on whether the access is S or NS, and whether
3337 * the board gave us a separate AddressSpace for S accesses).
3338 */
3339 static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
3340 {
3341 return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
3342 }
3343 #endif
3344
3345 /**
3346 * arm_register_pre_el_change_hook:
3347 * Register a hook function which will be called immediately before this
3348 * CPU changes exception level or mode. The hook function will be
3349 * passed a pointer to the ARMCPU and the opaque data pointer passed
3350 * to this function when the hook was registered.
3351 *
3352 * Note that if a pre-change hook is called, any registered post-change hooks
3353 * are guaranteed to subsequently be called.
3354 */
3355 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
3356 void *opaque);
3357 /**
3358 * arm_register_el_change_hook:
3359 * Register a hook function which will be called immediately after this
3360 * CPU changes exception level or mode. The hook function will be
3361 * passed a pointer to the ARMCPU and the opaque data pointer passed
3362 * to this function when the hook was registered.
3363 *
3364 * Note that any registered hooks registered here are guaranteed to be called
3365 * if pre-change hooks have been.
3366 */
3367 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void
3368 *opaque);
3369
3370 /**
3371 * arm_rebuild_hflags:
3372 * Rebuild the cached TBFLAGS for arbitrary changed processor state.
3373 */
3374 void arm_rebuild_hflags(CPUARMState *env);
3375
3376 /**
3377 * aa32_vfp_dreg:
3378 * Return a pointer to the Dn register within env in 32-bit mode.
3379 */
3380 static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno)
3381 {
3382 return &env->vfp.zregs[regno >> 1].d[regno & 1];
3383 }
3384
3385 /**
3386 * aa32_vfp_qreg:
3387 * Return a pointer to the Qn register within env in 32-bit mode.
3388 */
3389 static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno)
3390 {
3391 return &env->vfp.zregs[regno].d[0];
3392 }
3393
3394 /**
3395 * aa64_vfp_qreg:
3396 * Return a pointer to the Qn register within env in 64-bit mode.
3397 */
3398 static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno)
3399 {
3400 return &env->vfp.zregs[regno].d[0];
3401 }
3402
3403 /* Shared between translate-sve.c and sve_helper.c. */
3404 extern const uint64_t pred_esz_masks[4];
3405
3406 /* Helper for the macros below, validating the argument type. */
3407 static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x)
3408 {
3409 return x;
3410 }
3411
3412 /*
3413 * Lvalue macros for ARM TLB bits that we must cache in the TCG TLB.
3414 * Using these should be a bit more self-documenting than using the
3415 * generic target bits directly.
3416 */
3417 #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0)
3418 #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1)
3419
3420 /*
3421 * Naming convention for isar_feature functions:
3422 * Functions which test 32-bit ID registers should have _aa32_ in
3423 * their name. Functions which test 64-bit ID registers should have
3424 * _aa64_ in their name. These must only be used in code where we
3425 * know for certain that the CPU has AArch32 or AArch64 respectively
3426 * or where the correct answer for a CPU which doesn't implement that
3427 * CPU state is "false" (eg when generating A32 or A64 code, if adding
3428 * system registers that are specific to that CPU state, for "should
3429 * we let this system register bit be set" tests where the 32-bit
3430 * flavour of the register doesn't have the bit, and so on).
3431 * Functions which simply ask "does this feature exist at all" have
3432 * _any_ in their name, and always return the logical OR of the _aa64_
3433 * and the _aa32_ function.
3434 */
3435
3436 /*
3437 * 32-bit feature tests via id registers.
3438 */
3439 static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
3440 {
3441 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
3442 }
3443
3444 static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
3445 {
3446 return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
3447 }
3448
3449 static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
3450 {
3451 return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
3452 }
3453
3454 static inline bool isar_feat