virtio-scsi: suppress virtqueue kick during processing
[qemu.git] / target / arm / internals.h
1 /*
2 * QEMU ARM CPU -- internal functions and types
3 *
4 * Copyright (c) 2014 Linaro Ltd
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 *
20 * This header defines functions, types, etc which need to be shared
21 * between different source files within target/arm/ but which are
22 * private to it and not required by the rest of QEMU.
23 */
24
25 #ifndef TARGET_ARM_INTERNALS_H
26 #define TARGET_ARM_INTERNALS_H
27
28 /* register banks for CPU modes */
29 #define BANK_USRSYS 0
30 #define BANK_SVC 1
31 #define BANK_ABT 2
32 #define BANK_UND 3
33 #define BANK_IRQ 4
34 #define BANK_FIQ 5
35 #define BANK_HYP 6
36 #define BANK_MON 7
37
38 static inline bool excp_is_internal(int excp)
39 {
40 /* Return true if this exception number represents a QEMU-internal
41 * exception that will not be passed to the guest.
42 */
43 return excp == EXCP_INTERRUPT
44 || excp == EXCP_HLT
45 || excp == EXCP_DEBUG
46 || excp == EXCP_HALTED
47 || excp == EXCP_EXCEPTION_EXIT
48 || excp == EXCP_KERNEL_TRAP
49 || excp == EXCP_SEMIHOST;
50 }
51
52 /* Exception names for debug logging; note that not all of these
53 * precisely correspond to architectural exceptions.
54 */
55 static const char * const excnames[] = {
56 [EXCP_UDEF] = "Undefined Instruction",
57 [EXCP_SWI] = "SVC",
58 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
59 [EXCP_DATA_ABORT] = "Data Abort",
60 [EXCP_IRQ] = "IRQ",
61 [EXCP_FIQ] = "FIQ",
62 [EXCP_BKPT] = "Breakpoint",
63 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
64 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
65 [EXCP_HVC] = "Hypervisor Call",
66 [EXCP_HYP_TRAP] = "Hypervisor Trap",
67 [EXCP_SMC] = "Secure Monitor Call",
68 [EXCP_VIRQ] = "Virtual IRQ",
69 [EXCP_VFIQ] = "Virtual FIQ",
70 [EXCP_SEMIHOST] = "Semihosting call",
71 };
72
73 /* Scale factor for generic timers, ie number of ns per tick.
74 * This gives a 62.5MHz timer.
75 */
76 #define GTIMER_SCALE 16
77
78 /*
79 * For AArch64, map a given EL to an index in the banked_spsr array.
80 * Note that this mapping and the AArch32 mapping defined in bank_number()
81 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally
82 * mandated mapping between each other.
83 */
84 static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
85 {
86 static const unsigned int map[4] = {
87 [1] = BANK_SVC, /* EL1. */
88 [2] = BANK_HYP, /* EL2. */
89 [3] = BANK_MON, /* EL3. */
90 };
91 assert(el >= 1 && el <= 3);
92 return map[el];
93 }
94
95 /* Map CPU modes onto saved register banks. */
96 static inline int bank_number(int mode)
97 {
98 switch (mode) {
99 case ARM_CPU_MODE_USR:
100 case ARM_CPU_MODE_SYS:
101 return BANK_USRSYS;
102 case ARM_CPU_MODE_SVC:
103 return BANK_SVC;
104 case ARM_CPU_MODE_ABT:
105 return BANK_ABT;
106 case ARM_CPU_MODE_UND:
107 return BANK_UND;
108 case ARM_CPU_MODE_IRQ:
109 return BANK_IRQ;
110 case ARM_CPU_MODE_FIQ:
111 return BANK_FIQ;
112 case ARM_CPU_MODE_HYP:
113 return BANK_HYP;
114 case ARM_CPU_MODE_MON:
115 return BANK_MON;
116 }
117 g_assert_not_reached();
118 }
119
120 void switch_mode(CPUARMState *, int);
121 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
122 void arm_translate_init(void);
123
124 enum arm_fprounding {
125 FPROUNDING_TIEEVEN,
126 FPROUNDING_POSINF,
127 FPROUNDING_NEGINF,
128 FPROUNDING_ZERO,
129 FPROUNDING_TIEAWAY,
130 FPROUNDING_ODD
131 };
132
133 int arm_rmode_to_sf(int rmode);
134
135 static inline void aarch64_save_sp(CPUARMState *env, int el)
136 {
137 if (env->pstate & PSTATE_SP) {
138 env->sp_el[el] = env->xregs[31];
139 } else {
140 env->sp_el[0] = env->xregs[31];
141 }
142 }
143
144 static inline void aarch64_restore_sp(CPUARMState *env, int el)
145 {
146 if (env->pstate & PSTATE_SP) {
147 env->xregs[31] = env->sp_el[el];
148 } else {
149 env->xregs[31] = env->sp_el[0];
150 }
151 }
152
153 static inline void update_spsel(CPUARMState *env, uint32_t imm)
154 {
155 unsigned int cur_el = arm_current_el(env);
156 /* Update PSTATE SPSel bit; this requires us to update the
157 * working stack pointer in xregs[31].
158 */
159 if (!((imm ^ env->pstate) & PSTATE_SP)) {
160 return;
161 }
162 aarch64_save_sp(env, cur_el);
163 env->pstate = deposit32(env->pstate, 0, 1, imm);
164
165 /* We rely on illegal updates to SPsel from EL0 to get trapped
166 * at translation time.
167 */
168 assert(cur_el >= 1 && cur_el <= 3);
169 aarch64_restore_sp(env, cur_el);
170 }
171
172 /*
173 * arm_pamax
174 * @cpu: ARMCPU
175 *
176 * Returns the implementation defined bit-width of physical addresses.
177 * The ARMv8 reference manuals refer to this as PAMax().
178 */
179 static inline unsigned int arm_pamax(ARMCPU *cpu)
180 {
181 static const unsigned int pamax_map[] = {
182 [0] = 32,
183 [1] = 36,
184 [2] = 40,
185 [3] = 42,
186 [4] = 44,
187 [5] = 48,
188 };
189 unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4);
190
191 /* id_aa64mmfr0 is a read-only register so values outside of the
192 * supported mappings can be considered an implementation error. */
193 assert(parange < ARRAY_SIZE(pamax_map));
194 return pamax_map[parange];
195 }
196
197 /* Return true if extended addresses are enabled.
198 * This is always the case if our translation regime is 64 bit,
199 * but depends on TTBCR.EAE for 32 bit.
200 */
201 static inline bool extended_addresses_enabled(CPUARMState *env)
202 {
203 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
204 return arm_el_is_aa64(env, 1) ||
205 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
206 }
207
208 /* Valid Syndrome Register EC field values */
209 enum arm_exception_class {
210 EC_UNCATEGORIZED = 0x00,
211 EC_WFX_TRAP = 0x01,
212 EC_CP15RTTRAP = 0x03,
213 EC_CP15RRTTRAP = 0x04,
214 EC_CP14RTTRAP = 0x05,
215 EC_CP14DTTRAP = 0x06,
216 EC_ADVSIMDFPACCESSTRAP = 0x07,
217 EC_FPIDTRAP = 0x08,
218 EC_CP14RRTTRAP = 0x0c,
219 EC_ILLEGALSTATE = 0x0e,
220 EC_AA32_SVC = 0x11,
221 EC_AA32_HVC = 0x12,
222 EC_AA32_SMC = 0x13,
223 EC_AA64_SVC = 0x15,
224 EC_AA64_HVC = 0x16,
225 EC_AA64_SMC = 0x17,
226 EC_SYSTEMREGISTERTRAP = 0x18,
227 EC_INSNABORT = 0x20,
228 EC_INSNABORT_SAME_EL = 0x21,
229 EC_PCALIGNMENT = 0x22,
230 EC_DATAABORT = 0x24,
231 EC_DATAABORT_SAME_EL = 0x25,
232 EC_SPALIGNMENT = 0x26,
233 EC_AA32_FPTRAP = 0x28,
234 EC_AA64_FPTRAP = 0x2c,
235 EC_SERROR = 0x2f,
236 EC_BREAKPOINT = 0x30,
237 EC_BREAKPOINT_SAME_EL = 0x31,
238 EC_SOFTWARESTEP = 0x32,
239 EC_SOFTWARESTEP_SAME_EL = 0x33,
240 EC_WATCHPOINT = 0x34,
241 EC_WATCHPOINT_SAME_EL = 0x35,
242 EC_AA32_BKPT = 0x38,
243 EC_VECTORCATCH = 0x3a,
244 EC_AA64_BKPT = 0x3c,
245 };
246
247 #define ARM_EL_EC_SHIFT 26
248 #define ARM_EL_IL_SHIFT 25
249 #define ARM_EL_ISV_SHIFT 24
250 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
251 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)
252
253 /* Utility functions for constructing various kinds of syndrome value.
254 * Note that in general we follow the AArch64 syndrome values; in a
255 * few cases the value in HSR for exceptions taken to AArch32 Hyp
256 * mode differs slightly, so if we ever implemented Hyp mode then the
257 * syndrome value would need some massaging on exception entry.
258 * (One example of this is that AArch64 defaults to IL bit set for
259 * exceptions which don't specifically indicate information about the
260 * trapping instruction, whereas AArch32 defaults to IL bit clear.)
261 */
262 static inline uint32_t syn_uncategorized(void)
263 {
264 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
265 }
266
267 static inline uint32_t syn_aa64_svc(uint32_t imm16)
268 {
269 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
270 }
271
272 static inline uint32_t syn_aa64_hvc(uint32_t imm16)
273 {
274 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
275 }
276
277 static inline uint32_t syn_aa64_smc(uint32_t imm16)
278 {
279 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
280 }
281
282 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)
283 {
284 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
285 | (is_16bit ? 0 : ARM_EL_IL);
286 }
287
288 static inline uint32_t syn_aa32_hvc(uint32_t imm16)
289 {
290 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
291 }
292
293 static inline uint32_t syn_aa32_smc(void)
294 {
295 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;
296 }
297
298 static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
299 {
300 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
301 }
302
303 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)
304 {
305 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
306 | (is_16bit ? 0 : ARM_EL_IL);
307 }
308
309 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
310 int crn, int crm, int rt,
311 int isread)
312 {
313 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
314 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
315 | (crm << 1) | isread;
316 }
317
318 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
319 int crn, int crm, int rt, int isread,
320 bool is_16bit)
321 {
322 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
323 | (is_16bit ? 0 : ARM_EL_IL)
324 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
325 | (crn << 10) | (rt << 5) | (crm << 1) | isread;
326 }
327
328 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
329 int crn, int crm, int rt, int isread,
330 bool is_16bit)
331 {
332 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
333 | (is_16bit ? 0 : ARM_EL_IL)
334 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
335 | (crn << 10) | (rt << 5) | (crm << 1) | isread;
336 }
337
338 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
339 int rt, int rt2, int isread,
340 bool is_16bit)
341 {
342 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
343 | (is_16bit ? 0 : ARM_EL_IL)
344 | (cv << 24) | (cond << 20) | (opc1 << 16)
345 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
346 }
347
348 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
349 int rt, int rt2, int isread,
350 bool is_16bit)
351 {
352 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
353 | (is_16bit ? 0 : ARM_EL_IL)
354 | (cv << 24) | (cond << 20) | (opc1 << 16)
355 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
356 }
357
358 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit)
359 {
360 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
361 | (is_16bit ? 0 : ARM_EL_IL)
362 | (cv << 24) | (cond << 20);
363 }
364
365 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
366 {
367 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
368 | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc;
369 }
370
371 static inline uint32_t syn_data_abort_no_iss(int same_el,
372 int ea, int cm, int s1ptw,
373 int wnr, int fsc)
374 {
375 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
376 | ARM_EL_IL
377 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
378 }
379
380 static inline uint32_t syn_data_abort_with_iss(int same_el,
381 int sas, int sse, int srt,
382 int sf, int ar,
383 int ea, int cm, int s1ptw,
384 int wnr, int fsc,
385 bool is_16bit)
386 {
387 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
388 | (is_16bit ? 0 : ARM_EL_IL)
389 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16)
390 | (sf << 15) | (ar << 14)
391 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
392 }
393
394 static inline uint32_t syn_swstep(int same_el, int isv, int ex)
395 {
396 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
397 | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22;
398 }
399
400 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
401 {
402 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
403 | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22;
404 }
405
406 static inline uint32_t syn_breakpoint(int same_el)
407 {
408 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
409 | ARM_EL_IL | 0x22;
410 }
411
412 static inline uint32_t syn_wfx(int cv, int cond, int ti)
413 {
414 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) |
415 (cv << 24) | (cond << 20) | ti;
416 }
417
418 /* Update a QEMU watchpoint based on the information the guest has set in the
419 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
420 */
421 void hw_watchpoint_update(ARMCPU *cpu, int n);
422 /* Update the QEMU watchpoints for every guest watchpoint. This does a
423 * complete delete-and-reinstate of the QEMU watchpoint list and so is
424 * suitable for use after migration or on reset.
425 */
426 void hw_watchpoint_update_all(ARMCPU *cpu);
427 /* Update a QEMU breakpoint based on the information the guest has set in the
428 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
429 */
430 void hw_breakpoint_update(ARMCPU *cpu, int n);
431 /* Update the QEMU breakpoints for every guest breakpoint. This does a
432 * complete delete-and-reinstate of the QEMU breakpoint list and so is
433 * suitable for use after migration or on reset.
434 */
435 void hw_breakpoint_update_all(ARMCPU *cpu);
436
437 /* Callback function for checking if a watchpoint should trigger. */
438 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
439
440 /* Callback function for when a watchpoint or breakpoint triggers. */
441 void arm_debug_excp_handler(CPUState *cs);
442
443 #ifdef CONFIG_USER_ONLY
444 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
445 {
446 return false;
447 }
448 #else
449 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
450 bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
451 /* Actually handle a PSCI call */
452 void arm_handle_psci_call(ARMCPU *cpu);
453 #endif
454
455 /**
456 * ARMMMUFaultInfo: Information describing an ARM MMU Fault
457 * @s2addr: Address that caused a fault at stage 2
458 * @stage2: True if we faulted at stage 2
459 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
460 */
461 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
462 struct ARMMMUFaultInfo {
463 target_ulong s2addr;
464 bool stage2;
465 bool s1ptw;
466 };
467
468 /* Do a page table walk and add page to TLB if possible */
469 bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx,
470 uint32_t *fsr, ARMMMUFaultInfo *fi);
471
472 /* Return true if the stage 1 translation regime is using LPAE format page
473 * tables */
474 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
475
476 /* Raise a data fault alignment exception for the specified virtual address */
477 void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
478 MMUAccessType access_type,
479 int mmu_idx, uintptr_t retaddr);
480
481 /* Call the EL change hook if one has been registered */
482 static inline void arm_call_el_change_hook(ARMCPU *cpu)
483 {
484 if (cpu->el_change_hook) {
485 cpu->el_change_hook(cpu, cpu->el_change_hook_opaque);
486 }
487 }
488
489 #endif