migration: increase max-bandwidth to 128 MiB/s (1 Gib/s)
[qemu.git] / target / arm / internals.h
1 /*
2 * QEMU ARM CPU -- internal functions and types
3 *
4 * Copyright (c) 2014 Linaro Ltd
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 *
20 * This header defines functions, types, etc which need to be shared
21 * between different source files within target/arm/ but which are
22 * private to it and not required by the rest of QEMU.
23 */
24
25 #ifndef TARGET_ARM_INTERNALS_H
26 #define TARGET_ARM_INTERNALS_H
27
28 #include "hw/registerfields.h"
29
30 /* register banks for CPU modes */
31 #define BANK_USRSYS 0
32 #define BANK_SVC 1
33 #define BANK_ABT 2
34 #define BANK_UND 3
35 #define BANK_IRQ 4
36 #define BANK_FIQ 5
37 #define BANK_HYP 6
38 #define BANK_MON 7
39
40 static inline bool excp_is_internal(int excp)
41 {
42 /* Return true if this exception number represents a QEMU-internal
43 * exception that will not be passed to the guest.
44 */
45 return excp == EXCP_INTERRUPT
46 || excp == EXCP_HLT
47 || excp == EXCP_DEBUG
48 || excp == EXCP_HALTED
49 || excp == EXCP_EXCEPTION_EXIT
50 || excp == EXCP_KERNEL_TRAP
51 || excp == EXCP_SEMIHOST;
52 }
53
54 /* Scale factor for generic timers, ie number of ns per tick.
55 * This gives a 62.5MHz timer.
56 */
57 #define GTIMER_SCALE 16
58
59 /* Bit definitions for the v7M CONTROL register */
60 FIELD(V7M_CONTROL, NPRIV, 0, 1)
61 FIELD(V7M_CONTROL, SPSEL, 1, 1)
62 FIELD(V7M_CONTROL, FPCA, 2, 1)
63 FIELD(V7M_CONTROL, SFPA, 3, 1)
64
65 /* Bit definitions for v7M exception return payload */
66 FIELD(V7M_EXCRET, ES, 0, 1)
67 FIELD(V7M_EXCRET, RES0, 1, 1)
68 FIELD(V7M_EXCRET, SPSEL, 2, 1)
69 FIELD(V7M_EXCRET, MODE, 3, 1)
70 FIELD(V7M_EXCRET, FTYPE, 4, 1)
71 FIELD(V7M_EXCRET, DCRS, 5, 1)
72 FIELD(V7M_EXCRET, S, 6, 1)
73 FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
74
75 /* Minimum value which is a magic number for exception return */
76 #define EXC_RETURN_MIN_MAGIC 0xff000000
77 /* Minimum number which is a magic number for function or exception return
78 * when using v8M security extension
79 */
80 #define FNC_RETURN_MIN_MAGIC 0xfefffffe
81
82 /* We use a few fake FSR values for internal purposes in M profile.
83 * M profile cores don't have A/R format FSRs, but currently our
84 * get_phys_addr() code assumes A/R profile and reports failures via
85 * an A/R format FSR value. We then translate that into the proper
86 * M profile exception and FSR status bit in arm_v7m_cpu_do_interrupt().
87 * Mostly the FSR values we use for this are those defined for v7PMSA,
88 * since we share some of that codepath. A few kinds of fault are
89 * only for M profile and have no A/R equivalent, though, so we have
90 * to pick a value from the reserved range (which we never otherwise
91 * generate) to use for these.
92 * These values will never be visible to the guest.
93 */
94 #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */
95 #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */
96
97 /**
98 * raise_exception: Raise the specified exception.
99 * Raise a guest exception with the specified value, syndrome register
100 * and target exception level. This should be called from helper functions,
101 * and never returns because we will longjump back up to the CPU main loop.
102 */
103 void QEMU_NORETURN raise_exception(CPUARMState *env, uint32_t excp,
104 uint32_t syndrome, uint32_t target_el);
105
106 /*
107 * Similarly, but also use unwinding to restore cpu state.
108 */
109 void QEMU_NORETURN raise_exception_ra(CPUARMState *env, uint32_t excp,
110 uint32_t syndrome, uint32_t target_el,
111 uintptr_t ra);
112
113 /*
114 * For AArch64, map a given EL to an index in the banked_spsr array.
115 * Note that this mapping and the AArch32 mapping defined in bank_number()
116 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally
117 * mandated mapping between each other.
118 */
119 static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
120 {
121 static const unsigned int map[4] = {
122 [1] = BANK_SVC, /* EL1. */
123 [2] = BANK_HYP, /* EL2. */
124 [3] = BANK_MON, /* EL3. */
125 };
126 assert(el >= 1 && el <= 3);
127 return map[el];
128 }
129
130 /* Map CPU modes onto saved register banks. */
131 static inline int bank_number(int mode)
132 {
133 switch (mode) {
134 case ARM_CPU_MODE_USR:
135 case ARM_CPU_MODE_SYS:
136 return BANK_USRSYS;
137 case ARM_CPU_MODE_SVC:
138 return BANK_SVC;
139 case ARM_CPU_MODE_ABT:
140 return BANK_ABT;
141 case ARM_CPU_MODE_UND:
142 return BANK_UND;
143 case ARM_CPU_MODE_IRQ:
144 return BANK_IRQ;
145 case ARM_CPU_MODE_FIQ:
146 return BANK_FIQ;
147 case ARM_CPU_MODE_HYP:
148 return BANK_HYP;
149 case ARM_CPU_MODE_MON:
150 return BANK_MON;
151 }
152 g_assert_not_reached();
153 }
154
155 /**
156 * r14_bank_number: Map CPU mode onto register bank for r14
157 *
158 * Given an AArch32 CPU mode, return the index into the saved register
159 * banks to use for the R14 (LR) in that mode. This is the same as
160 * bank_number(), except for the special case of Hyp mode, where
161 * R14 is shared with USR and SYS, unlike its R13 and SPSR.
162 * This should be used as the index into env->banked_r14[], and
163 * bank_number() used for the index into env->banked_r13[] and
164 * env->banked_spsr[].
165 */
166 static inline int r14_bank_number(int mode)
167 {
168 return (mode == ARM_CPU_MODE_HYP) ? BANK_USRSYS : bank_number(mode);
169 }
170
171 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
172 void arm_translate_init(void);
173
174 enum arm_fprounding {
175 FPROUNDING_TIEEVEN,
176 FPROUNDING_POSINF,
177 FPROUNDING_NEGINF,
178 FPROUNDING_ZERO,
179 FPROUNDING_TIEAWAY,
180 FPROUNDING_ODD
181 };
182
183 int arm_rmode_to_sf(int rmode);
184
185 static inline void aarch64_save_sp(CPUARMState *env, int el)
186 {
187 if (env->pstate & PSTATE_SP) {
188 env->sp_el[el] = env->xregs[31];
189 } else {
190 env->sp_el[0] = env->xregs[31];
191 }
192 }
193
194 static inline void aarch64_restore_sp(CPUARMState *env, int el)
195 {
196 if (env->pstate & PSTATE_SP) {
197 env->xregs[31] = env->sp_el[el];
198 } else {
199 env->xregs[31] = env->sp_el[0];
200 }
201 }
202
203 static inline void update_spsel(CPUARMState *env, uint32_t imm)
204 {
205 unsigned int cur_el = arm_current_el(env);
206 /* Update PSTATE SPSel bit; this requires us to update the
207 * working stack pointer in xregs[31].
208 */
209 if (!((imm ^ env->pstate) & PSTATE_SP)) {
210 return;
211 }
212 aarch64_save_sp(env, cur_el);
213 env->pstate = deposit32(env->pstate, 0, 1, imm);
214
215 /* We rely on illegal updates to SPsel from EL0 to get trapped
216 * at translation time.
217 */
218 assert(cur_el >= 1 && cur_el <= 3);
219 aarch64_restore_sp(env, cur_el);
220 }
221
222 /*
223 * arm_pamax
224 * @cpu: ARMCPU
225 *
226 * Returns the implementation defined bit-width of physical addresses.
227 * The ARMv8 reference manuals refer to this as PAMax().
228 */
229 static inline unsigned int arm_pamax(ARMCPU *cpu)
230 {
231 static const unsigned int pamax_map[] = {
232 [0] = 32,
233 [1] = 36,
234 [2] = 40,
235 [3] = 42,
236 [4] = 44,
237 [5] = 48,
238 };
239 unsigned int parange =
240 FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
241
242 /* id_aa64mmfr0 is a read-only register so values outside of the
243 * supported mappings can be considered an implementation error. */
244 assert(parange < ARRAY_SIZE(pamax_map));
245 return pamax_map[parange];
246 }
247
248 /* Return true if extended addresses are enabled.
249 * This is always the case if our translation regime is 64 bit,
250 * but depends on TTBCR.EAE for 32 bit.
251 */
252 static inline bool extended_addresses_enabled(CPUARMState *env)
253 {
254 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
255 return arm_el_is_aa64(env, 1) ||
256 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
257 }
258
259 /* Valid Syndrome Register EC field values */
260 enum arm_exception_class {
261 EC_UNCATEGORIZED = 0x00,
262 EC_WFX_TRAP = 0x01,
263 EC_CP15RTTRAP = 0x03,
264 EC_CP15RRTTRAP = 0x04,
265 EC_CP14RTTRAP = 0x05,
266 EC_CP14DTTRAP = 0x06,
267 EC_ADVSIMDFPACCESSTRAP = 0x07,
268 EC_FPIDTRAP = 0x08,
269 EC_PACTRAP = 0x09,
270 EC_CP14RRTTRAP = 0x0c,
271 EC_BTITRAP = 0x0d,
272 EC_ILLEGALSTATE = 0x0e,
273 EC_AA32_SVC = 0x11,
274 EC_AA32_HVC = 0x12,
275 EC_AA32_SMC = 0x13,
276 EC_AA64_SVC = 0x15,
277 EC_AA64_HVC = 0x16,
278 EC_AA64_SMC = 0x17,
279 EC_SYSTEMREGISTERTRAP = 0x18,
280 EC_SVEACCESSTRAP = 0x19,
281 EC_INSNABORT = 0x20,
282 EC_INSNABORT_SAME_EL = 0x21,
283 EC_PCALIGNMENT = 0x22,
284 EC_DATAABORT = 0x24,
285 EC_DATAABORT_SAME_EL = 0x25,
286 EC_SPALIGNMENT = 0x26,
287 EC_AA32_FPTRAP = 0x28,
288 EC_AA64_FPTRAP = 0x2c,
289 EC_SERROR = 0x2f,
290 EC_BREAKPOINT = 0x30,
291 EC_BREAKPOINT_SAME_EL = 0x31,
292 EC_SOFTWARESTEP = 0x32,
293 EC_SOFTWARESTEP_SAME_EL = 0x33,
294 EC_WATCHPOINT = 0x34,
295 EC_WATCHPOINT_SAME_EL = 0x35,
296 EC_AA32_BKPT = 0x38,
297 EC_VECTORCATCH = 0x3a,
298 EC_AA64_BKPT = 0x3c,
299 };
300
301 #define ARM_EL_EC_SHIFT 26
302 #define ARM_EL_IL_SHIFT 25
303 #define ARM_EL_ISV_SHIFT 24
304 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
305 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)
306
307 static inline uint32_t syn_get_ec(uint32_t syn)
308 {
309 return syn >> ARM_EL_EC_SHIFT;
310 }
311
312 /* Utility functions for constructing various kinds of syndrome value.
313 * Note that in general we follow the AArch64 syndrome values; in a
314 * few cases the value in HSR for exceptions taken to AArch32 Hyp
315 * mode differs slightly, and we fix this up when populating HSR in
316 * arm_cpu_do_interrupt_aarch32_hyp().
317 * The exception is FP/SIMD access traps -- these report extra information
318 * when taking an exception to AArch32. For those we include the extra coproc
319 * and TA fields, and mask them out when taking the exception to AArch64.
320 */
321 static inline uint32_t syn_uncategorized(void)
322 {
323 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
324 }
325
326 static inline uint32_t syn_aa64_svc(uint32_t imm16)
327 {
328 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
329 }
330
331 static inline uint32_t syn_aa64_hvc(uint32_t imm16)
332 {
333 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
334 }
335
336 static inline uint32_t syn_aa64_smc(uint32_t imm16)
337 {
338 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
339 }
340
341 static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)
342 {
343 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
344 | (is_16bit ? 0 : ARM_EL_IL);
345 }
346
347 static inline uint32_t syn_aa32_hvc(uint32_t imm16)
348 {
349 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
350 }
351
352 static inline uint32_t syn_aa32_smc(void)
353 {
354 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;
355 }
356
357 static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
358 {
359 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
360 }
361
362 static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)
363 {
364 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
365 | (is_16bit ? 0 : ARM_EL_IL);
366 }
367
368 static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
369 int crn, int crm, int rt,
370 int isread)
371 {
372 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
373 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
374 | (crm << 1) | isread;
375 }
376
377 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
378 int crn, int crm, int rt, int isread,
379 bool is_16bit)
380 {
381 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
382 | (is_16bit ? 0 : ARM_EL_IL)
383 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
384 | (crn << 10) | (rt << 5) | (crm << 1) | isread;
385 }
386
387 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
388 int crn, int crm, int rt, int isread,
389 bool is_16bit)
390 {
391 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
392 | (is_16bit ? 0 : ARM_EL_IL)
393 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
394 | (crn << 10) | (rt << 5) | (crm << 1) | isread;
395 }
396
397 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
398 int rt, int rt2, int isread,
399 bool is_16bit)
400 {
401 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
402 | (is_16bit ? 0 : ARM_EL_IL)
403 | (cv << 24) | (cond << 20) | (opc1 << 16)
404 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
405 }
406
407 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
408 int rt, int rt2, int isread,
409 bool is_16bit)
410 {
411 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
412 | (is_16bit ? 0 : ARM_EL_IL)
413 | (cv << 24) | (cond << 20) | (opc1 << 16)
414 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
415 }
416
417 static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit)
418 {
419 /* AArch32 FP trap or any AArch64 FP/SIMD trap: TA == 0 coproc == 0xa */
420 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
421 | (is_16bit ? 0 : ARM_EL_IL)
422 | (cv << 24) | (cond << 20) | 0xa;
423 }
424
425 static inline uint32_t syn_simd_access_trap(int cv, int cond, bool is_16bit)
426 {
427 /* AArch32 SIMD trap: TA == 1 coproc == 0 */
428 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
429 | (is_16bit ? 0 : ARM_EL_IL)
430 | (cv << 24) | (cond << 20) | (1 << 5);
431 }
432
433 static inline uint32_t syn_sve_access_trap(void)
434 {
435 return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT;
436 }
437
438 static inline uint32_t syn_pactrap(void)
439 {
440 return EC_PACTRAP << ARM_EL_EC_SHIFT;
441 }
442
443 static inline uint32_t syn_btitrap(int btype)
444 {
445 return (EC_BTITRAP << ARM_EL_EC_SHIFT) | btype;
446 }
447
448 static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
449 {
450 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
451 | ARM_EL_IL | (ea << 9) | (s1ptw << 7) | fsc;
452 }
453
454 static inline uint32_t syn_data_abort_no_iss(int same_el, int fnv,
455 int ea, int cm, int s1ptw,
456 int wnr, int fsc)
457 {
458 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
459 | ARM_EL_IL
460 | (fnv << 10) | (ea << 9) | (cm << 8) | (s1ptw << 7)
461 | (wnr << 6) | fsc;
462 }
463
464 static inline uint32_t syn_data_abort_with_iss(int same_el,
465 int sas, int sse, int srt,
466 int sf, int ar,
467 int ea, int cm, int s1ptw,
468 int wnr, int fsc,
469 bool is_16bit)
470 {
471 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
472 | (is_16bit ? 0 : ARM_EL_IL)
473 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16)
474 | (sf << 15) | (ar << 14)
475 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
476 }
477
478 static inline uint32_t syn_swstep(int same_el, int isv, int ex)
479 {
480 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
481 | ARM_EL_IL | (isv << 24) | (ex << 6) | 0x22;
482 }
483
484 static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
485 {
486 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
487 | ARM_EL_IL | (cm << 8) | (wnr << 6) | 0x22;
488 }
489
490 static inline uint32_t syn_breakpoint(int same_el)
491 {
492 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
493 | ARM_EL_IL | 0x22;
494 }
495
496 static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit)
497 {
498 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) |
499 (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) |
500 (cv << 24) | (cond << 20) | ti;
501 }
502
503 /* Update a QEMU watchpoint based on the information the guest has set in the
504 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
505 */
506 void hw_watchpoint_update(ARMCPU *cpu, int n);
507 /* Update the QEMU watchpoints for every guest watchpoint. This does a
508 * complete delete-and-reinstate of the QEMU watchpoint list and so is
509 * suitable for use after migration or on reset.
510 */
511 void hw_watchpoint_update_all(ARMCPU *cpu);
512 /* Update a QEMU breakpoint based on the information the guest has set in the
513 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
514 */
515 void hw_breakpoint_update(ARMCPU *cpu, int n);
516 /* Update the QEMU breakpoints for every guest breakpoint. This does a
517 * complete delete-and-reinstate of the QEMU breakpoint list and so is
518 * suitable for use after migration or on reset.
519 */
520 void hw_breakpoint_update_all(ARMCPU *cpu);
521
522 /* Callback function for checking if a watchpoint should trigger. */
523 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
524
525 /* Adjust addresses (in BE32 mode) before testing against watchpoint
526 * addresses.
527 */
528 vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len);
529
530 /* Callback function for when a watchpoint or breakpoint triggers. */
531 void arm_debug_excp_handler(CPUState *cs);
532
533 #if defined(CONFIG_USER_ONLY) || !defined(CONFIG_TCG)
534 static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
535 {
536 return false;
537 }
538 static inline void arm_handle_psci_call(ARMCPU *cpu)
539 {
540 g_assert_not_reached();
541 }
542 #else
543 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
544 bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
545 /* Actually handle a PSCI call */
546 void arm_handle_psci_call(ARMCPU *cpu);
547 #endif
548
549 /**
550 * arm_clear_exclusive: clear the exclusive monitor
551 * @env: CPU env
552 * Clear the CPU's exclusive monitor, like the guest CLREX instruction.
553 */
554 static inline void arm_clear_exclusive(CPUARMState *env)
555 {
556 env->exclusive_addr = -1;
557 }
558
559 /**
560 * ARMFaultType: type of an ARM MMU fault
561 * This corresponds to the v8A pseudocode's Fault enumeration,
562 * with extensions for QEMU internal conditions.
563 */
564 typedef enum ARMFaultType {
565 ARMFault_None,
566 ARMFault_AccessFlag,
567 ARMFault_Alignment,
568 ARMFault_Background,
569 ARMFault_Domain,
570 ARMFault_Permission,
571 ARMFault_Translation,
572 ARMFault_AddressSize,
573 ARMFault_SyncExternal,
574 ARMFault_SyncExternalOnWalk,
575 ARMFault_SyncParity,
576 ARMFault_SyncParityOnWalk,
577 ARMFault_AsyncParity,
578 ARMFault_AsyncExternal,
579 ARMFault_Debug,
580 ARMFault_TLBConflict,
581 ARMFault_Lockdown,
582 ARMFault_Exclusive,
583 ARMFault_ICacheMaint,
584 ARMFault_QEMU_NSCExec, /* v8M: NS executing in S&NSC memory */
585 ARMFault_QEMU_SFault, /* v8M: SecureFault INVTRAN, INVEP or AUVIOL */
586 } ARMFaultType;
587
588 /**
589 * ARMMMUFaultInfo: Information describing an ARM MMU Fault
590 * @type: Type of fault
591 * @level: Table walk level (for translation, access flag and permission faults)
592 * @domain: Domain of the fault address (for non-LPAE CPUs only)
593 * @s2addr: Address that caused a fault at stage 2
594 * @stage2: True if we faulted at stage 2
595 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
596 * @ea: True if we should set the EA (external abort type) bit in syndrome
597 */
598 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
599 struct ARMMMUFaultInfo {
600 ARMFaultType type;
601 target_ulong s2addr;
602 int level;
603 int domain;
604 bool stage2;
605 bool s1ptw;
606 bool ea;
607 };
608
609 /**
610 * arm_fi_to_sfsc: Convert fault info struct to short-format FSC
611 * Compare pseudocode EncodeSDFSC(), though unlike that function
612 * we set up a whole FSR-format code including domain field and
613 * putting the high bit of the FSC into bit 10.
614 */
615 static inline uint32_t arm_fi_to_sfsc(ARMMMUFaultInfo *fi)
616 {
617 uint32_t fsc;
618
619 switch (fi->type) {
620 case ARMFault_None:
621 return 0;
622 case ARMFault_AccessFlag:
623 fsc = fi->level == 1 ? 0x3 : 0x6;
624 break;
625 case ARMFault_Alignment:
626 fsc = 0x1;
627 break;
628 case ARMFault_Permission:
629 fsc = fi->level == 1 ? 0xd : 0xf;
630 break;
631 case ARMFault_Domain:
632 fsc = fi->level == 1 ? 0x9 : 0xb;
633 break;
634 case ARMFault_Translation:
635 fsc = fi->level == 1 ? 0x5 : 0x7;
636 break;
637 case ARMFault_SyncExternal:
638 fsc = 0x8 | (fi->ea << 12);
639 break;
640 case ARMFault_SyncExternalOnWalk:
641 fsc = fi->level == 1 ? 0xc : 0xe;
642 fsc |= (fi->ea << 12);
643 break;
644 case ARMFault_SyncParity:
645 fsc = 0x409;
646 break;
647 case ARMFault_SyncParityOnWalk:
648 fsc = fi->level == 1 ? 0x40c : 0x40e;
649 break;
650 case ARMFault_AsyncParity:
651 fsc = 0x408;
652 break;
653 case ARMFault_AsyncExternal:
654 fsc = 0x406 | (fi->ea << 12);
655 break;
656 case ARMFault_Debug:
657 fsc = 0x2;
658 break;
659 case ARMFault_TLBConflict:
660 fsc = 0x400;
661 break;
662 case ARMFault_Lockdown:
663 fsc = 0x404;
664 break;
665 case ARMFault_Exclusive:
666 fsc = 0x405;
667 break;
668 case ARMFault_ICacheMaint:
669 fsc = 0x4;
670 break;
671 case ARMFault_Background:
672 fsc = 0x0;
673 break;
674 case ARMFault_QEMU_NSCExec:
675 fsc = M_FAKE_FSR_NSC_EXEC;
676 break;
677 case ARMFault_QEMU_SFault:
678 fsc = M_FAKE_FSR_SFAULT;
679 break;
680 default:
681 /* Other faults can't occur in a context that requires a
682 * short-format status code.
683 */
684 g_assert_not_reached();
685 }
686
687 fsc |= (fi->domain << 4);
688 return fsc;
689 }
690
691 /**
692 * arm_fi_to_lfsc: Convert fault info struct to long-format FSC
693 * Compare pseudocode EncodeLDFSC(), though unlike that function
694 * we fill in also the LPAE bit 9 of a DFSR format.
695 */
696 static inline uint32_t arm_fi_to_lfsc(ARMMMUFaultInfo *fi)
697 {
698 uint32_t fsc;
699
700 switch (fi->type) {
701 case ARMFault_None:
702 return 0;
703 case ARMFault_AddressSize:
704 fsc = fi->level & 3;
705 break;
706 case ARMFault_AccessFlag:
707 fsc = (fi->level & 3) | (0x2 << 2);
708 break;
709 case ARMFault_Permission:
710 fsc = (fi->level & 3) | (0x3 << 2);
711 break;
712 case ARMFault_Translation:
713 fsc = (fi->level & 3) | (0x1 << 2);
714 break;
715 case ARMFault_SyncExternal:
716 fsc = 0x10 | (fi->ea << 12);
717 break;
718 case ARMFault_SyncExternalOnWalk:
719 fsc = (fi->level & 3) | (0x5 << 2) | (fi->ea << 12);
720 break;
721 case ARMFault_SyncParity:
722 fsc = 0x18;
723 break;
724 case ARMFault_SyncParityOnWalk:
725 fsc = (fi->level & 3) | (0x7 << 2);
726 break;
727 case ARMFault_AsyncParity:
728 fsc = 0x19;
729 break;
730 case ARMFault_AsyncExternal:
731 fsc = 0x11 | (fi->ea << 12);
732 break;
733 case ARMFault_Alignment:
734 fsc = 0x21;
735 break;
736 case ARMFault_Debug:
737 fsc = 0x22;
738 break;
739 case ARMFault_TLBConflict:
740 fsc = 0x30;
741 break;
742 case ARMFault_Lockdown:
743 fsc = 0x34;
744 break;
745 case ARMFault_Exclusive:
746 fsc = 0x35;
747 break;
748 default:
749 /* Other faults can't occur in a context that requires a
750 * long-format status code.
751 */
752 g_assert_not_reached();
753 }
754
755 fsc |= 1 << 9;
756 return fsc;
757 }
758
759 static inline bool arm_extabort_type(MemTxResult result)
760 {
761 /* The EA bit in syndromes and fault status registers is an
762 * IMPDEF classification of external aborts. ARM implementations
763 * usually use this to indicate AXI bus Decode error (0) or
764 * Slave error (1); in QEMU we follow that.
765 */
766 return result != MEMTX_DECODE_ERROR;
767 }
768
769 bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
770 MMUAccessType access_type, int mmu_idx,
771 bool probe, uintptr_t retaddr);
772
773 static inline int arm_to_core_mmu_idx(ARMMMUIdx mmu_idx)
774 {
775 return mmu_idx & ARM_MMU_IDX_COREIDX_MASK;
776 }
777
778 static inline ARMMMUIdx core_to_arm_mmu_idx(CPUARMState *env, int mmu_idx)
779 {
780 if (arm_feature(env, ARM_FEATURE_M)) {
781 return mmu_idx | ARM_MMU_IDX_M;
782 } else {
783 return mmu_idx | ARM_MMU_IDX_A;
784 }
785 }
786
787 static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_idx)
788 {
789 /* AArch64 is always a-profile. */
790 return mmu_idx | ARM_MMU_IDX_A;
791 }
792
793 int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx);
794
795 /*
796 * Return the MMU index for a v7M CPU with all relevant information
797 * manually specified.
798 */
799 ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
800 bool secstate, bool priv, bool negpri);
801
802 /*
803 * Return the MMU index for a v7M CPU in the specified security and
804 * privilege state.
805 */
806 ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
807 bool secstate, bool priv);
808
809 /* Return the MMU index for a v7M CPU in the specified security state */
810 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
811
812 /* Return true if the stage 1 translation regime is using LPAE format page
813 * tables */
814 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
815
816 /* Raise a data fault alignment exception for the specified virtual address */
817 void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,
818 MMUAccessType access_type,
819 int mmu_idx, uintptr_t retaddr);
820
821 /* arm_cpu_do_transaction_failed: handle a memory system error response
822 * (eg "no device/memory present at address") by raising an external abort
823 * exception
824 */
825 void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
826 vaddr addr, unsigned size,
827 MMUAccessType access_type,
828 int mmu_idx, MemTxAttrs attrs,
829 MemTxResult response, uintptr_t retaddr);
830
831 /* Call any registered EL change hooks */
832 static inline void arm_call_pre_el_change_hook(ARMCPU *cpu)
833 {
834 ARMELChangeHook *hook, *next;
835 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
836 hook->hook(cpu, hook->opaque);
837 }
838 }
839 static inline void arm_call_el_change_hook(ARMCPU *cpu)
840 {
841 ARMELChangeHook *hook, *next;
842 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
843 hook->hook(cpu, hook->opaque);
844 }
845 }
846
847 /* Return true if this address translation regime has two ranges. */
848 static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx)
849 {
850 switch (mmu_idx) {
851 case ARMMMUIdx_Stage1_E0:
852 case ARMMMUIdx_Stage1_E1:
853 case ARMMMUIdx_Stage1_E1_PAN:
854 case ARMMMUIdx_E10_0:
855 case ARMMMUIdx_E10_1:
856 case ARMMMUIdx_E10_1_PAN:
857 case ARMMMUIdx_E20_0:
858 case ARMMMUIdx_E20_2:
859 case ARMMMUIdx_E20_2_PAN:
860 case ARMMMUIdx_SE10_0:
861 case ARMMMUIdx_SE10_1:
862 case ARMMMUIdx_SE10_1_PAN:
863 return true;
864 default:
865 return false;
866 }
867 }
868
869 /* Return true if this address translation regime is secure */
870 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
871 {
872 switch (mmu_idx) {
873 case ARMMMUIdx_E10_0:
874 case ARMMMUIdx_E10_1:
875 case ARMMMUIdx_E10_1_PAN:
876 case ARMMMUIdx_E20_0:
877 case ARMMMUIdx_E20_2:
878 case ARMMMUIdx_E20_2_PAN:
879 case ARMMMUIdx_Stage1_E0:
880 case ARMMMUIdx_Stage1_E1:
881 case ARMMMUIdx_Stage1_E1_PAN:
882 case ARMMMUIdx_E2:
883 case ARMMMUIdx_Stage2:
884 case ARMMMUIdx_MPrivNegPri:
885 case ARMMMUIdx_MUserNegPri:
886 case ARMMMUIdx_MPriv:
887 case ARMMMUIdx_MUser:
888 return false;
889 case ARMMMUIdx_SE3:
890 case ARMMMUIdx_SE10_0:
891 case ARMMMUIdx_SE10_1:
892 case ARMMMUIdx_SE10_1_PAN:
893 case ARMMMUIdx_MSPrivNegPri:
894 case ARMMMUIdx_MSUserNegPri:
895 case ARMMMUIdx_MSPriv:
896 case ARMMMUIdx_MSUser:
897 return true;
898 default:
899 g_assert_not_reached();
900 }
901 }
902
903 static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx)
904 {
905 switch (mmu_idx) {
906 case ARMMMUIdx_Stage1_E1_PAN:
907 case ARMMMUIdx_E10_1_PAN:
908 case ARMMMUIdx_E20_2_PAN:
909 case ARMMMUIdx_SE10_1_PAN:
910 return true;
911 default:
912 return false;
913 }
914 }
915
916 /* Return the exception level which controls this address translation regime */
917 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
918 {
919 switch (mmu_idx) {
920 case ARMMMUIdx_E20_0:
921 case ARMMMUIdx_E20_2:
922 case ARMMMUIdx_E20_2_PAN:
923 case ARMMMUIdx_Stage2:
924 case ARMMMUIdx_E2:
925 return 2;
926 case ARMMMUIdx_SE3:
927 return 3;
928 case ARMMMUIdx_SE10_0:
929 return arm_el_is_aa64(env, 3) ? 1 : 3;
930 case ARMMMUIdx_SE10_1:
931 case ARMMMUIdx_SE10_1_PAN:
932 case ARMMMUIdx_Stage1_E0:
933 case ARMMMUIdx_Stage1_E1:
934 case ARMMMUIdx_Stage1_E1_PAN:
935 case ARMMMUIdx_E10_0:
936 case ARMMMUIdx_E10_1:
937 case ARMMMUIdx_E10_1_PAN:
938 case ARMMMUIdx_MPrivNegPri:
939 case ARMMMUIdx_MUserNegPri:
940 case ARMMMUIdx_MPriv:
941 case ARMMMUIdx_MUser:
942 case ARMMMUIdx_MSPrivNegPri:
943 case ARMMMUIdx_MSUserNegPri:
944 case ARMMMUIdx_MSPriv:
945 case ARMMMUIdx_MSUser:
946 return 1;
947 default:
948 g_assert_not_reached();
949 }
950 }
951
952 /* Return the TCR controlling this translation regime */
953 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
954 {
955 if (mmu_idx == ARMMMUIdx_Stage2) {
956 return &env->cp15.vtcr_el2;
957 }
958 return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
959 }
960
961 /* Return the FSR value for a debug exception (watchpoint, hardware
962 * breakpoint or BKPT insn) targeting the specified exception level.
963 */
964 static inline uint32_t arm_debug_exception_fsr(CPUARMState *env)
965 {
966 ARMMMUFaultInfo fi = { .type = ARMFault_Debug };
967 int target_el = arm_debug_target_el(env);
968 bool using_lpae = false;
969
970 if (target_el == 2 || arm_el_is_aa64(env, target_el)) {
971 using_lpae = true;
972 } else {
973 if (arm_feature(env, ARM_FEATURE_LPAE) &&
974 (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) {
975 using_lpae = true;
976 }
977 }
978
979 if (using_lpae) {
980 return arm_fi_to_lfsc(&fi);
981 } else {
982 return arm_fi_to_sfsc(&fi);
983 }
984 }
985
986 /**
987 * arm_num_brps: Return number of implemented breakpoints.
988 * Note that the ID register BRPS field is "number of bps - 1",
989 * and we return the actual number of breakpoints.
990 */
991 static inline int arm_num_brps(ARMCPU *cpu)
992 {
993 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
994 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1;
995 } else {
996 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1;
997 }
998 }
999
1000 /**
1001 * arm_num_wrps: Return number of implemented watchpoints.
1002 * Note that the ID register WRPS field is "number of wps - 1",
1003 * and we return the actual number of watchpoints.
1004 */
1005 static inline int arm_num_wrps(ARMCPU *cpu)
1006 {
1007 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1008 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1;
1009 } else {
1010 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1;
1011 }
1012 }
1013
1014 /**
1015 * arm_num_ctx_cmps: Return number of implemented context comparators.
1016 * Note that the ID register CTX_CMPS field is "number of cmps - 1",
1017 * and we return the actual number of comparators.
1018 */
1019 static inline int arm_num_ctx_cmps(ARMCPU *cpu)
1020 {
1021 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
1022 return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1;
1023 } else {
1024 return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1;
1025 }
1026 }
1027
1028 /**
1029 * v7m_using_psp: Return true if using process stack pointer
1030 * Return true if the CPU is currently using the process stack
1031 * pointer, or false if it is using the main stack pointer.
1032 */
1033 static inline bool v7m_using_psp(CPUARMState *env)
1034 {
1035 /* Handler mode always uses the main stack; for thread mode
1036 * the CONTROL.SPSEL bit determines the answer.
1037 * Note that in v7M it is not possible to be in Handler mode with
1038 * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both.
1039 */
1040 return !arm_v7m_is_handler_mode(env) &&
1041 env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK;
1042 }
1043
1044 /**
1045 * v7m_sp_limit: Return SP limit for current CPU state
1046 * Return the SP limit value for the current CPU security state
1047 * and stack pointer.
1048 */
1049 static inline uint32_t v7m_sp_limit(CPUARMState *env)
1050 {
1051 if (v7m_using_psp(env)) {
1052 return env->v7m.psplim[env->v7m.secure];
1053 } else {
1054 return env->v7m.msplim[env->v7m.secure];
1055 }
1056 }
1057
1058 /**
1059 * v7m_cpacr_pass:
1060 * Return true if the v7M CPACR permits access to the FPU for the specified
1061 * security state and privilege level.
1062 */
1063 static inline bool v7m_cpacr_pass(CPUARMState *env,
1064 bool is_secure, bool is_priv)
1065 {
1066 switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) {
1067 case 0:
1068 case 2: /* UNPREDICTABLE: we treat like 0 */
1069 return false;
1070 case 1:
1071 return is_priv;
1072 case 3:
1073 return true;
1074 default:
1075 g_assert_not_reached();
1076 }
1077 }
1078
1079 /**
1080 * aarch32_mode_name(): Return name of the AArch32 CPU mode
1081 * @psr: Program Status Register indicating CPU mode
1082 *
1083 * Returns, for debug logging purposes, a printable representation
1084 * of the AArch32 CPU mode ("svc", "usr", etc) as indicated by
1085 * the low bits of the specified PSR.
1086 */
1087 static inline const char *aarch32_mode_name(uint32_t psr)
1088 {
1089 static const char cpu_mode_names[16][4] = {
1090 "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
1091 "???", "???", "hyp", "und", "???", "???", "???", "sys"
1092 };
1093
1094 return cpu_mode_names[psr & 0xf];
1095 }
1096
1097 /**
1098 * arm_cpu_update_virq: Update CPU_INTERRUPT_VIRQ bit in cs->interrupt_request
1099 *
1100 * Update the CPU_INTERRUPT_VIRQ bit in cs->interrupt_request, following
1101 * a change to either the input VIRQ line from the GIC or the HCR_EL2.VI bit.
1102 * Must be called with the iothread lock held.
1103 */
1104 void arm_cpu_update_virq(ARMCPU *cpu);
1105
1106 /**
1107 * arm_cpu_update_vfiq: Update CPU_INTERRUPT_VFIQ bit in cs->interrupt_request
1108 *
1109 * Update the CPU_INTERRUPT_VFIQ bit in cs->interrupt_request, following
1110 * a change to either the input VFIQ line from the GIC or the HCR_EL2.VF bit.
1111 * Must be called with the iothread lock held.
1112 */
1113 void arm_cpu_update_vfiq(ARMCPU *cpu);
1114
1115 /**
1116 * arm_mmu_idx_el:
1117 * @env: The cpu environment
1118 * @el: The EL to use.
1119 *
1120 * Return the full ARMMMUIdx for the translation regime for EL.
1121 */
1122 ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el);
1123
1124 /**
1125 * arm_mmu_idx:
1126 * @env: The cpu environment
1127 *
1128 * Return the full ARMMMUIdx for the current translation regime.
1129 */
1130 ARMMMUIdx arm_mmu_idx(CPUARMState *env);
1131
1132 /**
1133 * arm_stage1_mmu_idx:
1134 * @env: The cpu environment
1135 *
1136 * Return the ARMMMUIdx for the stage1 traversal for the current regime.
1137 */
1138 #ifdef CONFIG_USER_ONLY
1139 static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
1140 {
1141 return ARMMMUIdx_Stage1_E0;
1142 }
1143 #else
1144 ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env);
1145 #endif
1146
1147 /**
1148 * arm_mmu_idx_is_stage1_of_2:
1149 * @mmu_idx: The ARMMMUIdx to test
1150 *
1151 * Return true if @mmu_idx is a NOTLB mmu_idx that is the
1152 * first stage of a two stage regime.
1153 */
1154 static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx)
1155 {
1156 switch (mmu_idx) {
1157 case ARMMMUIdx_Stage1_E0:
1158 case ARMMMUIdx_Stage1_E1:
1159 case ARMMMUIdx_Stage1_E1_PAN:
1160 return true;
1161 default:
1162 return false;
1163 }
1164 }
1165
1166 static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
1167 const ARMISARegisters *id)
1168 {
1169 uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV;
1170
1171 if ((features >> ARM_FEATURE_V4T) & 1) {
1172 valid |= CPSR_T;
1173 }
1174 if ((features >> ARM_FEATURE_V5) & 1) {
1175 valid |= CPSR_Q; /* V5TE in reality*/
1176 }
1177 if ((features >> ARM_FEATURE_V6) & 1) {
1178 valid |= CPSR_E | CPSR_GE;
1179 }
1180 if ((features >> ARM_FEATURE_THUMB2) & 1) {
1181 valid |= CPSR_IT;
1182 }
1183 if (isar_feature_aa32_jazelle(id)) {
1184 valid |= CPSR_J;
1185 }
1186 if (isar_feature_aa32_pan(id)) {
1187 valid |= CPSR_PAN;
1188 }
1189
1190 return valid;
1191 }
1192
1193 static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
1194 {
1195 uint32_t valid;
1196
1197 valid = PSTATE_M | PSTATE_DAIF | PSTATE_IL | PSTATE_SS | PSTATE_NZCV;
1198 if (isar_feature_aa64_bti(id)) {
1199 valid |= PSTATE_BTYPE;
1200 }
1201 if (isar_feature_aa64_pan(id)) {
1202 valid |= PSTATE_PAN;
1203 }
1204 if (isar_feature_aa64_uao(id)) {
1205 valid |= PSTATE_UAO;
1206 }
1207 if (isar_feature_aa64_mte(id)) {
1208 valid |= PSTATE_TCO;
1209 }
1210
1211 return valid;
1212 }
1213
1214 /*
1215 * Parameters of a given virtual address, as extracted from the
1216 * translation control register (TCR) for a given regime.
1217 */
1218 typedef struct ARMVAParameters {
1219 unsigned tsz : 8;
1220 unsigned select : 1;
1221 bool tbi : 1;
1222 bool epd : 1;
1223 bool hpd : 1;
1224 bool using16k : 1;
1225 bool using64k : 1;
1226 } ARMVAParameters;
1227
1228 ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
1229 ARMMMUIdx mmu_idx, bool data);
1230
1231 static inline int exception_target_el(CPUARMState *env)
1232 {
1233 int target_el = MAX(1, arm_current_el(env));
1234
1235 /*
1236 * No such thing as secure EL1 if EL3 is aarch32,
1237 * so update the target EL to EL3 in this case.
1238 */
1239 if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) {
1240 target_el = 3;
1241 }
1242
1243 return target_el;
1244 }
1245
1246 /* Determine if allocation tags are available. */
1247 static inline bool allocation_tag_access_enabled(CPUARMState *env, int el,
1248 uint64_t sctlr)
1249 {
1250 if (el < 3
1251 && arm_feature(env, ARM_FEATURE_EL3)
1252 && !(env->cp15.scr_el3 & SCR_ATA)) {
1253 return false;
1254 }
1255 if (el < 2
1256 && arm_feature(env, ARM_FEATURE_EL2)
1257 && !(arm_hcr_el2_eff(env) & HCR_ATA)) {
1258 return false;
1259 }
1260 sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA);
1261 return sctlr != 0;
1262 }
1263
1264 #ifndef CONFIG_USER_ONLY
1265
1266 /* Security attributes for an address, as returned by v8m_security_lookup. */
1267 typedef struct V8M_SAttributes {
1268 bool subpage; /* true if these attrs don't cover the whole TARGET_PAGE */
1269 bool ns;
1270 bool nsc;
1271 uint8_t sregion;
1272 bool srvalid;
1273 uint8_t iregion;
1274 bool irvalid;
1275 } V8M_SAttributes;
1276
1277 void v8m_security_lookup(CPUARMState *env, uint32_t address,
1278 MMUAccessType access_type, ARMMMUIdx mmu_idx,
1279 V8M_SAttributes *sattrs);
1280
1281 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
1282 MMUAccessType access_type, ARMMMUIdx mmu_idx,
1283 hwaddr *phys_ptr, MemTxAttrs *txattrs,
1284 int *prot, bool *is_subpage,
1285 ARMMMUFaultInfo *fi, uint32_t *mregion);
1286
1287 /* Cacheability and shareability attributes for a memory access */
1288 typedef struct ARMCacheAttrs {
1289 unsigned int attrs:8; /* as in the MAIR register encoding */
1290 unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */
1291 } ARMCacheAttrs;
1292
1293 bool get_phys_addr(CPUARMState *env, target_ulong address,
1294 MMUAccessType access_type, ARMMMUIdx mmu_idx,
1295 hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
1296 target_ulong *page_size,
1297 ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
1298 __attribute__((nonnull));
1299
1300 void arm_log_exception(int idx);
1301
1302 #endif /* !CONFIG_USER_ONLY */
1303
1304 /*
1305 * The log2 of the words in the tag block, for GMID_EL1.BS.
1306 * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
1307 */
1308 #define GMID_EL1_BS 6
1309
1310 /* We associate one allocation tag per 16 bytes, the minimum. */
1311 #define LOG2_TAG_GRANULE 4
1312 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE)
1313
1314 /*
1315 * The SVE simd_data field, for memory ops, contains either
1316 * rd (5 bits) or a shift count (2 bits).
1317 */
1318 #define SVE_MTEDESC_SHIFT 5
1319
1320 /* Bits within a descriptor passed to the helper_mte_check* functions. */
1321 FIELD(MTEDESC, MIDX, 0, 4)
1322 FIELD(MTEDESC, TBI, 4, 2)
1323 FIELD(MTEDESC, TCMA, 6, 2)
1324 FIELD(MTEDESC, WRITE, 8, 1)
1325 FIELD(MTEDESC, ESIZE, 9, 5)
1326 FIELD(MTEDESC, TSIZE, 14, 10) /* mte_checkN only */
1327
1328 bool mte_probe1(CPUARMState *env, uint32_t desc, uint64_t ptr);
1329 uint64_t mte_check1(CPUARMState *env, uint32_t desc,
1330 uint64_t ptr, uintptr_t ra);
1331 uint64_t mte_checkN(CPUARMState *env, uint32_t desc,
1332 uint64_t ptr, uintptr_t ra);
1333
1334 static inline int allocation_tag_from_addr(uint64_t ptr)
1335 {
1336 return extract64(ptr, 56, 4);
1337 }
1338
1339 static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag)
1340 {
1341 return deposit64(ptr, 56, 4, rtag);
1342 }
1343
1344 /* Return true if tbi bits mean that the access is checked. */
1345 static inline bool tbi_check(uint32_t desc, int bit55)
1346 {
1347 return (desc >> (R_MTEDESC_TBI_SHIFT + bit55)) & 1;
1348 }
1349
1350 /* Return true if tcma bits mean that the access is unchecked. */
1351 static inline bool tcma_check(uint32_t desc, int bit55, int ptr_tag)
1352 {
1353 /*
1354 * We had extracted bit55 and ptr_tag for other reasons, so fold
1355 * (ptr<59:55> == 00000 || ptr<59:55> == 11111) into a single test.
1356 */
1357 bool match = ((ptr_tag + bit55) & 0xf) == 0;
1358 bool tcma = (desc >> (R_MTEDESC_TCMA_SHIFT + bit55)) & 1;
1359 return tcma && match;
1360 }
1361
1362 /*
1363 * For TBI, ideally, we would do nothing. Proper behaviour on fault is
1364 * for the tag to be present in the FAR_ELx register. But for user-only
1365 * mode, we do not have a TLB with which to implement this, so we must
1366 * remove the top byte.
1367 */
1368 static inline uint64_t useronly_clean_ptr(uint64_t ptr)
1369 {
1370 /* TBI is known to be enabled. */
1371 #ifdef CONFIG_USER_ONLY
1372 ptr = sextract64(ptr, 0, 56);
1373 #endif
1374 return ptr;
1375 }
1376
1377 static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc, uint64_t ptr)
1378 {
1379 #ifdef CONFIG_USER_ONLY
1380 int64_t clean_ptr = sextract64(ptr, 0, 56);
1381 if (tbi_check(desc, clean_ptr < 0)) {
1382 ptr = clean_ptr;
1383 }
1384 #endif
1385 return ptr;
1386 }
1387
1388 #endif