meson: target
[qemu.git] / target / arm / translate-a64.h
1 /*
2 * AArch64 translation, common definitions.
3 *
4 * This library is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU Lesser General Public
6 * License as published by the Free Software Foundation; either
7 * version 2 of the License, or (at your option) any later version.
8 *
9 * This library is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * Lesser General Public License for more details.
13 *
14 * You should have received a copy of the GNU Lesser General Public
15 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #ifndef TARGET_ARM_TRANSLATE_A64_H
19 #define TARGET_ARM_TRANSLATE_A64_H
20
21 void unallocated_encoding(DisasContext *s);
22
23 #define unsupported_encoding(s, insn) \
24 do { \
25 qemu_log_mask(LOG_UNIMP, \
26 "%s:%d: unsupported instruction encoding 0x%08x " \
27 "at pc=%016" PRIx64 "\n", \
28 __FILE__, __LINE__, insn, s->pc_curr); \
29 unallocated_encoding(s); \
30 } while (0)
31
32 TCGv_i64 new_tmp_a64(DisasContext *s);
33 TCGv_i64 new_tmp_a64_local(DisasContext *s);
34 TCGv_i64 new_tmp_a64_zero(DisasContext *s);
35 TCGv_i64 cpu_reg(DisasContext *s, int reg);
36 TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
37 TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf);
38 TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf);
39 void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v);
40 TCGv_ptr get_fpstatus_ptr(bool);
41 bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
42 unsigned int imms, unsigned int immr);
43 bool sve_access_check(DisasContext *s);
44 TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr);
45 TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write,
46 bool tag_checked, int log2_size);
47 TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr, bool is_write,
48 bool tag_checked, int count, int log2_esize);
49
50 /* We should have at some point before trying to access an FP register
51 * done the necessary access check, so assert that
52 * (a) we did the check and
53 * (b) we didn't then just plough ahead anyway if it failed.
54 * Print the instruction pattern in the abort message so we can figure
55 * out what we need to fix if a user encounters this problem in the wild.
56 */
57 static inline void assert_fp_access_checked(DisasContext *s)
58 {
59 #ifdef CONFIG_DEBUG_TCG
60 if (unlikely(!s->fp_access_checked || s->fp_excp_el)) {
61 fprintf(stderr, "target-arm: FP access check missing for "
62 "instruction 0x%08x\n", s->insn);
63 abort();
64 }
65 #endif
66 }
67
68 /* Return the offset into CPUARMState of an element of specified
69 * size, 'element' places in from the least significant end of
70 * the FP/vector register Qn.
71 */
72 static inline int vec_reg_offset(DisasContext *s, int regno,
73 int element, MemOp size)
74 {
75 int element_size = 1 << size;
76 int offs = element * element_size;
77 #ifdef HOST_WORDS_BIGENDIAN
78 /* This is complicated slightly because vfp.zregs[n].d[0] is
79 * still the lowest and vfp.zregs[n].d[15] the highest of the
80 * 256 byte vector, even on big endian systems.
81 *
82 * Calculate the offset assuming fully little-endian,
83 * then XOR to account for the order of the 8-byte units.
84 *
85 * For 16 byte elements, the two 8 byte halves will not form a
86 * host int128 if the host is bigendian, since they're in the
87 * wrong order. However the only 16 byte operation we have is
88 * a move, so we can ignore this for the moment. More complicated
89 * operations will have to special case loading and storing from
90 * the zregs array.
91 */
92 if (element_size < 8) {
93 offs ^= 8 - element_size;
94 }
95 #endif
96 offs += offsetof(CPUARMState, vfp.zregs[regno]);
97 assert_fp_access_checked(s);
98 return offs;
99 }
100
101 /* Return the offset info CPUARMState of the "whole" vector register Qn. */
102 static inline int vec_full_reg_offset(DisasContext *s, int regno)
103 {
104 assert_fp_access_checked(s);
105 return offsetof(CPUARMState, vfp.zregs[regno]);
106 }
107
108 /* Return a newly allocated pointer to the vector register. */
109 static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno)
110 {
111 TCGv_ptr ret = tcg_temp_new_ptr();
112 tcg_gen_addi_ptr(ret, cpu_env, vec_full_reg_offset(s, regno));
113 return ret;
114 }
115
116 /* Return the byte size of the "whole" vector register, VL / 8. */
117 static inline int vec_full_reg_size(DisasContext *s)
118 {
119 return s->sve_len;
120 }
121
122 bool disas_sve(DisasContext *, uint32_t);
123
124 void gen_gvec_rax1(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
125 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
126
127 #endif /* TARGET_ARM_TRANSLATE_A64_H */