meson: target
[qemu.git] / target / arm / translate.h
1 #ifndef TARGET_ARM_TRANSLATE_H
2 #define TARGET_ARM_TRANSLATE_H
3
4 #include "exec/translator.h"
5 #include "internals.h"
6
7
8 /* internal defines */
9 typedef struct DisasContext {
10 DisasContextBase base;
11 const ARMISARegisters *isar;
12
13 /* The address of the current instruction being translated. */
14 target_ulong pc_curr;
15 target_ulong page_start;
16 uint32_t insn;
17 /* Nonzero if this instruction has been conditionally skipped. */
18 int condjmp;
19 /* The label that will be jumped to when the instruction is skipped. */
20 TCGLabel *condlabel;
21 /* Thumb-2 conditional execution bits. */
22 int condexec_mask;
23 int condexec_cond;
24 int thumb;
25 int sctlr_b;
26 MemOp be_data;
27 #if !defined(CONFIG_USER_ONLY)
28 int user;
29 #endif
30 ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
31 uint8_t tbii; /* TBI1|TBI0 for insns */
32 uint8_t tbid; /* TBI1|TBI0 for data */
33 uint8_t tcma; /* TCMA1|TCMA0 for MTE */
34 bool ns; /* Use non-secure CPREG bank on access */
35 int fp_excp_el; /* FP exception EL or 0 if enabled */
36 int sve_excp_el; /* SVE exception EL or 0 if enabled */
37 int sve_len; /* SVE vector length in bytes */
38 /* Flag indicating that exceptions from secure mode are routed to EL3. */
39 bool secure_routed_to_el3;
40 bool vfp_enabled; /* FP enabled via FPSCR.EN */
41 int vec_len;
42 int vec_stride;
43 bool v7m_handler_mode;
44 bool v8m_secure; /* true if v8M and we're in Secure mode */
45 bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */
46 bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */
47 bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */
48 bool v7m_lspact; /* FPCCR.LSPACT set */
49 /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
50 * so that top level loop can generate correct syndrome information.
51 */
52 uint32_t svc_imm;
53 int aarch64;
54 int current_el;
55 /* Debug target exception level for single-step exceptions */
56 int debug_target_el;
57 GHashTable *cp_regs;
58 uint64_t features; /* CPU features bits */
59 /* Because unallocated encodings generate different exception syndrome
60 * information from traps due to FP being disabled, we can't do a single
61 * "is fp access disabled" check at a high level in the decode tree.
62 * To help in catching bugs where the access check was forgotten in some
63 * code path, we set this flag when the access check is done, and assert
64 * that it is set at the point where we actually touch the FP regs.
65 */
66 bool fp_access_checked;
67 /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
68 * single-step support).
69 */
70 bool ss_active;
71 bool pstate_ss;
72 /* True if the insn just emitted was a load-exclusive instruction
73 * (necessary for syndrome information for single step exceptions),
74 * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
75 */
76 bool is_ldex;
77 /* True if AccType_UNPRIV should be used for LDTR et al */
78 bool unpriv;
79 /* True if v8.3-PAuth is active. */
80 bool pauth_active;
81 /* True if v8.5-MTE access to tags is enabled. */
82 bool ata;
83 /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv. */
84 bool mte_active[2];
85 /* True with v8.5-BTI and SCTLR_ELx.BT* set. */
86 bool bt;
87 /* True if any CP15 access is trapped by HSTR_EL2 */
88 bool hstr_active;
89 /*
90 * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
91 * < 0, set by the current instruction.
92 */
93 int8_t btype;
94 /* A copy of cpu->dcz_blocksize. */
95 uint8_t dcz_blocksize;
96 /* True if this page is guarded. */
97 bool guarded_page;
98 /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
99 int c15_cpar;
100 /* TCG op of the current insn_start. */
101 TCGOp *insn_start;
102 #define TMP_A64_MAX 16
103 int tmp_a64_count;
104 TCGv_i64 tmp_a64[TMP_A64_MAX];
105 } DisasContext;
106
107 typedef struct DisasCompare {
108 TCGCond cond;
109 TCGv_i32 value;
110 bool value_global;
111 } DisasCompare;
112
113 /* Share the TCG temporaries common between 32 and 64 bit modes. */
114 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
115 extern TCGv_i64 cpu_exclusive_addr;
116 extern TCGv_i64 cpu_exclusive_val;
117
118 static inline int arm_dc_feature(DisasContext *dc, int feature)
119 {
120 return (dc->features & (1ULL << feature)) != 0;
121 }
122
123 static inline int get_mem_index(DisasContext *s)
124 {
125 return arm_to_core_mmu_idx(s->mmu_idx);
126 }
127
128 /* Function used to determine the target exception EL when otherwise not known
129 * or default.
130 */
131 static inline int default_exception_el(DisasContext *s)
132 {
133 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
134 * there is no secure EL1, so we route exceptions to EL3. Otherwise,
135 * exceptions can only be routed to ELs above 1, so we target the higher of
136 * 1 or the current EL.
137 */
138 return (s->mmu_idx == ARMMMUIdx_SE10_0 && s->secure_routed_to_el3)
139 ? 3 : MAX(1, s->current_el);
140 }
141
142 static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
143 {
144 /* We don't need to save all of the syndrome so we mask and shift
145 * out unneeded bits to help the sleb128 encoder do a better job.
146 */
147 syn &= ARM_INSN_START_WORD2_MASK;
148 syn >>= ARM_INSN_START_WORD2_SHIFT;
149
150 /* We check and clear insn_start_idx to catch multiple updates. */
151 assert(s->insn_start != NULL);
152 tcg_set_insn_start_param(s->insn_start, 2, syn);
153 s->insn_start = NULL;
154 }
155
156 /* is_jmp field values */
157 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
158 /* CPU state was modified dynamically; exit to main loop for interrupts. */
159 #define DISAS_UPDATE_EXIT DISAS_TARGET_1
160 /* These instructions trap after executing, so the A32/T32 decoder must
161 * defer them until after the conditional execution state has been updated.
162 * WFI also needs special handling when single-stepping.
163 */
164 #define DISAS_WFI DISAS_TARGET_2
165 #define DISAS_SWI DISAS_TARGET_3
166 /* WFE */
167 #define DISAS_WFE DISAS_TARGET_4
168 #define DISAS_HVC DISAS_TARGET_5
169 #define DISAS_SMC DISAS_TARGET_6
170 #define DISAS_YIELD DISAS_TARGET_7
171 /* M profile branch which might be an exception return (and so needs
172 * custom end-of-TB code)
173 */
174 #define DISAS_BX_EXCRET DISAS_TARGET_8
175 /*
176 * For instructions which want an immediate exit to the main loop, as opposed
177 * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this
178 * doesn't write the PC on exiting the translation loop so you need to ensure
179 * something (gen_a64_set_pc_im or runtime helper) has done so before we reach
180 * return from cpu_tb_exec.
181 */
182 #define DISAS_EXIT DISAS_TARGET_9
183 /* CPU state was modified dynamically; no need to exit, but do not chain. */
184 #define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10
185
186 #ifdef TARGET_AARCH64
187 void a64_translate_init(void);
188 void gen_a64_set_pc_im(uint64_t val);
189 extern const TranslatorOps aarch64_translator_ops;
190 #else
191 static inline void a64_translate_init(void)
192 {
193 }
194
195 static inline void gen_a64_set_pc_im(uint64_t val)
196 {
197 }
198 #endif
199
200 void arm_test_cc(DisasCompare *cmp, int cc);
201 void arm_free_cc(DisasCompare *cmp);
202 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
203 void arm_gen_test_cc(int cc, TCGLabel *label);
204
205 /* Return state of Alternate Half-precision flag, caller frees result */
206 static inline TCGv_i32 get_ahp_flag(void)
207 {
208 TCGv_i32 ret = tcg_temp_new_i32();
209
210 tcg_gen_ld_i32(ret, cpu_env,
211 offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
212 tcg_gen_extract_i32(ret, ret, 26, 1);
213
214 return ret;
215 }
216
217 /* Set bits within PSTATE. */
218 static inline void set_pstate_bits(uint32_t bits)
219 {
220 TCGv_i32 p = tcg_temp_new_i32();
221
222 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
223
224 tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
225 tcg_gen_ori_i32(p, p, bits);
226 tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
227 tcg_temp_free_i32(p);
228 }
229
230 /* Clear bits within PSTATE. */
231 static inline void clear_pstate_bits(uint32_t bits)
232 {
233 TCGv_i32 p = tcg_temp_new_i32();
234
235 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
236
237 tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
238 tcg_gen_andi_i32(p, p, ~bits);
239 tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
240 tcg_temp_free_i32(p);
241 }
242
243 /* If the singlestep state is Active-not-pending, advance to Active-pending. */
244 static inline void gen_ss_advance(DisasContext *s)
245 {
246 if (s->ss_active) {
247 s->pstate_ss = 0;
248 clear_pstate_bits(PSTATE_SS);
249 }
250 }
251
252 static inline void gen_exception(int excp, uint32_t syndrome,
253 uint32_t target_el)
254 {
255 TCGv_i32 tcg_excp = tcg_const_i32(excp);
256 TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
257 TCGv_i32 tcg_el = tcg_const_i32(target_el);
258
259 gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
260 tcg_syn, tcg_el);
261
262 tcg_temp_free_i32(tcg_el);
263 tcg_temp_free_i32(tcg_syn);
264 tcg_temp_free_i32(tcg_excp);
265 }
266
267 /* Generate an architectural singlestep exception */
268 static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
269 {
270 bool same_el = (s->debug_target_el == s->current_el);
271
272 /*
273 * If singlestep is targeting a lower EL than the current one,
274 * then s->ss_active must be false and we can never get here.
275 */
276 assert(s->debug_target_el >= s->current_el);
277
278 gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el);
279 }
280
281 /*
282 * Given a VFP floating point constant encoded into an 8 bit immediate in an
283 * instruction, expand it to the actual constant value of the specified
284 * size, as per the VFPExpandImm() pseudocode in the Arm ARM.
285 */
286 uint64_t vfp_expand_imm(int size, uint8_t imm8);
287
288 /* Vector operations shared between ARM and AArch64. */
289 void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
290 uint32_t opr_sz, uint32_t max_sz);
291 void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
292 uint32_t opr_sz, uint32_t max_sz);
293 void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
294 uint32_t opr_sz, uint32_t max_sz);
295 void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
296 uint32_t opr_sz, uint32_t max_sz);
297 void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
298 uint32_t opr_sz, uint32_t max_sz);
299
300 void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
301 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
302 void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
303 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
304
305 void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
306 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
307 void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
308 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
309 void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
310 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
311
312 void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
313 void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
314 void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
315 void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
316 void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
317
318 void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
319 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
320 void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
321 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
322 void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
323 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
324 void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
325 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
326
327 void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
328 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
329 void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
330 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
331
332 void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
333 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
334 void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
335 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
336 void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
337 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
338 void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
339 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
340
341 void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
342 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
343 void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
344 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
345
346 void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
347 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
348 void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
349 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
350
351 void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
352 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
353 void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
354 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
355
356 void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
357 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
358 void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
359 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
360
361 /*
362 * Forward to the isar_feature_* tests given a DisasContext pointer.
363 */
364 #define dc_isar_feature(name, ctx) \
365 ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
366
367 /* Note that the gvec expanders operate on offsets + sizes. */
368 typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
369 typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
370 uint32_t, uint32_t);
371 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
372 uint32_t, uint32_t, uint32_t);
373 typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
374 uint32_t, uint32_t, uint32_t);
375
376 /* Function prototype for gen_ functions for calling Neon helpers */
377 typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32);
378 typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
379 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
380 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
381 typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
382 typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
383 typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
384 typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
385 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
386 typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
387 typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr);
388 typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
389 typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
390 typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
391 typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
392 typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
393 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
394 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
395
396 #endif /* TARGET_ARM_TRANSLATE_H */