target/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMUL
[qemu.git] / target / arm / vec_helper.c
1 /*
2 * ARM AdvSIMD / SVE Vector Operations
3 *
4 * Copyright (c) 2018 Linaro
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/helper-proto.h"
23 #include "tcg/tcg-gvec-desc.h"
24 #include "fpu/softfloat.h"
25 #include "vec_internal.h"
26
27 /* Note that vector data is stored in host-endian 64-bit chunks,
28 so addressing units smaller than that needs a host-endian fixup. */
29 #ifdef HOST_WORDS_BIGENDIAN
30 #define H1(x) ((x) ^ 7)
31 #define H2(x) ((x) ^ 3)
32 #define H4(x) ((x) ^ 1)
33 #else
34 #define H1(x) (x)
35 #define H2(x) (x)
36 #define H4(x) (x)
37 #endif
38
39 /* Signed saturating rounding doubling multiply-accumulate high half, 16-bit */
40 static int16_t do_sqrdmlah_h(int16_t src1, int16_t src2, int16_t src3,
41 bool neg, bool round, uint32_t *sat)
42 {
43 /*
44 * Simplify:
45 * = ((a3 << 16) + ((e1 * e2) << 1) + (1 << 15)) >> 16
46 * = ((a3 << 15) + (e1 * e2) + (1 << 14)) >> 15
47 */
48 int32_t ret = (int32_t)src1 * src2;
49 if (neg) {
50 ret = -ret;
51 }
52 ret += ((int32_t)src3 << 15) + (round << 14);
53 ret >>= 15;
54
55 if (ret != (int16_t)ret) {
56 *sat = 1;
57 ret = (ret < 0 ? INT16_MIN : INT16_MAX);
58 }
59 return ret;
60 }
61
62 uint32_t HELPER(neon_qrdmlah_s16)(CPUARMState *env, uint32_t src1,
63 uint32_t src2, uint32_t src3)
64 {
65 uint32_t *sat = &env->vfp.qc[0];
66 uint16_t e1 = do_sqrdmlah_h(src1, src2, src3, false, true, sat);
67 uint16_t e2 = do_sqrdmlah_h(src1 >> 16, src2 >> 16, src3 >> 16,
68 false, true, sat);
69 return deposit32(e1, 16, 16, e2);
70 }
71
72 void HELPER(gvec_qrdmlah_s16)(void *vd, void *vn, void *vm,
73 void *vq, uint32_t desc)
74 {
75 uintptr_t opr_sz = simd_oprsz(desc);
76 int16_t *d = vd;
77 int16_t *n = vn;
78 int16_t *m = vm;
79 uintptr_t i;
80
81 for (i = 0; i < opr_sz / 2; ++i) {
82 d[i] = do_sqrdmlah_h(n[i], m[i], d[i], false, true, vq);
83 }
84 clear_tail(d, opr_sz, simd_maxsz(desc));
85 }
86
87 uint32_t HELPER(neon_qrdmlsh_s16)(CPUARMState *env, uint32_t src1,
88 uint32_t src2, uint32_t src3)
89 {
90 uint32_t *sat = &env->vfp.qc[0];
91 uint16_t e1 = do_sqrdmlah_h(src1, src2, src3, true, true, sat);
92 uint16_t e2 = do_sqrdmlah_h(src1 >> 16, src2 >> 16, src3 >> 16,
93 true, true, sat);
94 return deposit32(e1, 16, 16, e2);
95 }
96
97 void HELPER(gvec_qrdmlsh_s16)(void *vd, void *vn, void *vm,
98 void *vq, uint32_t desc)
99 {
100 uintptr_t opr_sz = simd_oprsz(desc);
101 int16_t *d = vd;
102 int16_t *n = vn;
103 int16_t *m = vm;
104 uintptr_t i;
105
106 for (i = 0; i < opr_sz / 2; ++i) {
107 d[i] = do_sqrdmlah_h(n[i], m[i], d[i], true, true, vq);
108 }
109 clear_tail(d, opr_sz, simd_maxsz(desc));
110 }
111
112 void HELPER(neon_sqdmulh_h)(void *vd, void *vn, void *vm,
113 void *vq, uint32_t desc)
114 {
115 intptr_t i, opr_sz = simd_oprsz(desc);
116 int16_t *d = vd, *n = vn, *m = vm;
117
118 for (i = 0; i < opr_sz / 2; ++i) {
119 d[i] = do_sqrdmlah_h(n[i], m[i], 0, false, false, vq);
120 }
121 clear_tail(d, opr_sz, simd_maxsz(desc));
122 }
123
124 void HELPER(neon_sqrdmulh_h)(void *vd, void *vn, void *vm,
125 void *vq, uint32_t desc)
126 {
127 intptr_t i, opr_sz = simd_oprsz(desc);
128 int16_t *d = vd, *n = vn, *m = vm;
129
130 for (i = 0; i < opr_sz / 2; ++i) {
131 d[i] = do_sqrdmlah_h(n[i], m[i], 0, false, true, vq);
132 }
133 clear_tail(d, opr_sz, simd_maxsz(desc));
134 }
135
136 /* Signed saturating rounding doubling multiply-accumulate high half, 32-bit */
137 static int32_t do_sqrdmlah_s(int32_t src1, int32_t src2, int32_t src3,
138 bool neg, bool round, uint32_t *sat)
139 {
140 /* Simplify similarly to int_qrdmlah_s16 above. */
141 int64_t ret = (int64_t)src1 * src2;
142 if (neg) {
143 ret = -ret;
144 }
145 ret += ((int64_t)src3 << 31) + (round << 30);
146 ret >>= 31;
147
148 if (ret != (int32_t)ret) {
149 *sat = 1;
150 ret = (ret < 0 ? INT32_MIN : INT32_MAX);
151 }
152 return ret;
153 }
154
155 uint32_t HELPER(neon_qrdmlah_s32)(CPUARMState *env, int32_t src1,
156 int32_t src2, int32_t src3)
157 {
158 uint32_t *sat = &env->vfp.qc[0];
159 return do_sqrdmlah_s(src1, src2, src3, false, true, sat);
160 }
161
162 void HELPER(gvec_qrdmlah_s32)(void *vd, void *vn, void *vm,
163 void *vq, uint32_t desc)
164 {
165 uintptr_t opr_sz = simd_oprsz(desc);
166 int32_t *d = vd;
167 int32_t *n = vn;
168 int32_t *m = vm;
169 uintptr_t i;
170
171 for (i = 0; i < opr_sz / 4; ++i) {
172 d[i] = do_sqrdmlah_s(n[i], m[i], d[i], false, true, vq);
173 }
174 clear_tail(d, opr_sz, simd_maxsz(desc));
175 }
176
177 uint32_t HELPER(neon_qrdmlsh_s32)(CPUARMState *env, int32_t src1,
178 int32_t src2, int32_t src3)
179 {
180 uint32_t *sat = &env->vfp.qc[0];
181 return do_sqrdmlah_s(src1, src2, src3, true, true, sat);
182 }
183
184 void HELPER(gvec_qrdmlsh_s32)(void *vd, void *vn, void *vm,
185 void *vq, uint32_t desc)
186 {
187 uintptr_t opr_sz = simd_oprsz(desc);
188 int32_t *d = vd;
189 int32_t *n = vn;
190 int32_t *m = vm;
191 uintptr_t i;
192
193 for (i = 0; i < opr_sz / 4; ++i) {
194 d[i] = do_sqrdmlah_s(n[i], m[i], d[i], true, true, vq);
195 }
196 clear_tail(d, opr_sz, simd_maxsz(desc));
197 }
198
199 void HELPER(neon_sqdmulh_s)(void *vd, void *vn, void *vm,
200 void *vq, uint32_t desc)
201 {
202 intptr_t i, opr_sz = simd_oprsz(desc);
203 int32_t *d = vd, *n = vn, *m = vm;
204
205 for (i = 0; i < opr_sz / 4; ++i) {
206 d[i] = do_sqrdmlah_s(n[i], m[i], 0, false, false, vq);
207 }
208 clear_tail(d, opr_sz, simd_maxsz(desc));
209 }
210
211 void HELPER(neon_sqrdmulh_s)(void *vd, void *vn, void *vm,
212 void *vq, uint32_t desc)
213 {
214 intptr_t i, opr_sz = simd_oprsz(desc);
215 int32_t *d = vd, *n = vn, *m = vm;
216
217 for (i = 0; i < opr_sz / 4; ++i) {
218 d[i] = do_sqrdmlah_s(n[i], m[i], 0, false, true, vq);
219 }
220 clear_tail(d, opr_sz, simd_maxsz(desc));
221 }
222
223 /* Integer 8 and 16-bit dot-product.
224 *
225 * Note that for the loops herein, host endianness does not matter
226 * with respect to the ordering of data within the 64-bit lanes.
227 * All elements are treated equally, no matter where they are.
228 */
229
230 void HELPER(gvec_sdot_b)(void *vd, void *vn, void *vm, uint32_t desc)
231 {
232 intptr_t i, opr_sz = simd_oprsz(desc);
233 uint32_t *d = vd;
234 int8_t *n = vn, *m = vm;
235
236 for (i = 0; i < opr_sz / 4; ++i) {
237 d[i] += n[i * 4 + 0] * m[i * 4 + 0]
238 + n[i * 4 + 1] * m[i * 4 + 1]
239 + n[i * 4 + 2] * m[i * 4 + 2]
240 + n[i * 4 + 3] * m[i * 4 + 3];
241 }
242 clear_tail(d, opr_sz, simd_maxsz(desc));
243 }
244
245 void HELPER(gvec_udot_b)(void *vd, void *vn, void *vm, uint32_t desc)
246 {
247 intptr_t i, opr_sz = simd_oprsz(desc);
248 uint32_t *d = vd;
249 uint8_t *n = vn, *m = vm;
250
251 for (i = 0; i < opr_sz / 4; ++i) {
252 d[i] += n[i * 4 + 0] * m[i * 4 + 0]
253 + n[i * 4 + 1] * m[i * 4 + 1]
254 + n[i * 4 + 2] * m[i * 4 + 2]
255 + n[i * 4 + 3] * m[i * 4 + 3];
256 }
257 clear_tail(d, opr_sz, simd_maxsz(desc));
258 }
259
260 void HELPER(gvec_sdot_h)(void *vd, void *vn, void *vm, uint32_t desc)
261 {
262 intptr_t i, opr_sz = simd_oprsz(desc);
263 uint64_t *d = vd;
264 int16_t *n = vn, *m = vm;
265
266 for (i = 0; i < opr_sz / 8; ++i) {
267 d[i] += (int64_t)n[i * 4 + 0] * m[i * 4 + 0]
268 + (int64_t)n[i * 4 + 1] * m[i * 4 + 1]
269 + (int64_t)n[i * 4 + 2] * m[i * 4 + 2]
270 + (int64_t)n[i * 4 + 3] * m[i * 4 + 3];
271 }
272 clear_tail(d, opr_sz, simd_maxsz(desc));
273 }
274
275 void HELPER(gvec_udot_h)(void *vd, void *vn, void *vm, uint32_t desc)
276 {
277 intptr_t i, opr_sz = simd_oprsz(desc);
278 uint64_t *d = vd;
279 uint16_t *n = vn, *m = vm;
280
281 for (i = 0; i < opr_sz / 8; ++i) {
282 d[i] += (uint64_t)n[i * 4 + 0] * m[i * 4 + 0]
283 + (uint64_t)n[i * 4 + 1] * m[i * 4 + 1]
284 + (uint64_t)n[i * 4 + 2] * m[i * 4 + 2]
285 + (uint64_t)n[i * 4 + 3] * m[i * 4 + 3];
286 }
287 clear_tail(d, opr_sz, simd_maxsz(desc));
288 }
289
290 void HELPER(gvec_sdot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc)
291 {
292 intptr_t i, segend, opr_sz = simd_oprsz(desc), opr_sz_4 = opr_sz / 4;
293 intptr_t index = simd_data(desc);
294 uint32_t *d = vd;
295 int8_t *n = vn;
296 int8_t *m_indexed = (int8_t *)vm + index * 4;
297
298 /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.
299 * Otherwise opr_sz is a multiple of 16.
300 */
301 segend = MIN(4, opr_sz_4);
302 i = 0;
303 do {
304 int8_t m0 = m_indexed[i * 4 + 0];
305 int8_t m1 = m_indexed[i * 4 + 1];
306 int8_t m2 = m_indexed[i * 4 + 2];
307 int8_t m3 = m_indexed[i * 4 + 3];
308
309 do {
310 d[i] += n[i * 4 + 0] * m0
311 + n[i * 4 + 1] * m1
312 + n[i * 4 + 2] * m2
313 + n[i * 4 + 3] * m3;
314 } while (++i < segend);
315 segend = i + 4;
316 } while (i < opr_sz_4);
317
318 clear_tail(d, opr_sz, simd_maxsz(desc));
319 }
320
321 void HELPER(gvec_udot_idx_b)(void *vd, void *vn, void *vm, uint32_t desc)
322 {
323 intptr_t i, segend, opr_sz = simd_oprsz(desc), opr_sz_4 = opr_sz / 4;
324 intptr_t index = simd_data(desc);
325 uint32_t *d = vd;
326 uint8_t *n = vn;
327 uint8_t *m_indexed = (uint8_t *)vm + index * 4;
328
329 /* Notice the special case of opr_sz == 8, from aa64/aa32 advsimd.
330 * Otherwise opr_sz is a multiple of 16.
331 */
332 segend = MIN(4, opr_sz_4);
333 i = 0;
334 do {
335 uint8_t m0 = m_indexed[i * 4 + 0];
336 uint8_t m1 = m_indexed[i * 4 + 1];
337 uint8_t m2 = m_indexed[i * 4 + 2];
338 uint8_t m3 = m_indexed[i * 4 + 3];
339
340 do {
341 d[i] += n[i * 4 + 0] * m0
342 + n[i * 4 + 1] * m1
343 + n[i * 4 + 2] * m2
344 + n[i * 4 + 3] * m3;
345 } while (++i < segend);
346 segend = i + 4;
347 } while (i < opr_sz_4);
348
349 clear_tail(d, opr_sz, simd_maxsz(desc));
350 }
351
352 void HELPER(gvec_sdot_idx_h)(void *vd, void *vn, void *vm, uint32_t desc)
353 {
354 intptr_t i, opr_sz = simd_oprsz(desc), opr_sz_8 = opr_sz / 8;
355 intptr_t index = simd_data(desc);
356 uint64_t *d = vd;
357 int16_t *n = vn;
358 int16_t *m_indexed = (int16_t *)vm + index * 4;
359
360 /* This is supported by SVE only, so opr_sz is always a multiple of 16.
361 * Process the entire segment all at once, writing back the results
362 * only after we've consumed all of the inputs.
363 */
364 for (i = 0; i < opr_sz_8 ; i += 2) {
365 uint64_t d0, d1;
366
367 d0 = n[i * 4 + 0] * (int64_t)m_indexed[i * 4 + 0];
368 d0 += n[i * 4 + 1] * (int64_t)m_indexed[i * 4 + 1];
369 d0 += n[i * 4 + 2] * (int64_t)m_indexed[i * 4 + 2];
370 d0 += n[i * 4 + 3] * (int64_t)m_indexed[i * 4 + 3];
371 d1 = n[i * 4 + 4] * (int64_t)m_indexed[i * 4 + 0];
372 d1 += n[i * 4 + 5] * (int64_t)m_indexed[i * 4 + 1];
373 d1 += n[i * 4 + 6] * (int64_t)m_indexed[i * 4 + 2];
374 d1 += n[i * 4 + 7] * (int64_t)m_indexed[i * 4 + 3];
375
376 d[i + 0] += d0;
377 d[i + 1] += d1;
378 }
379
380 clear_tail(d, opr_sz, simd_maxsz(desc));
381 }
382
383 void HELPER(gvec_udot_idx_h)(void *vd, void *vn, void *vm, uint32_t desc)
384 {
385 intptr_t i, opr_sz = simd_oprsz(desc), opr_sz_8 = opr_sz / 8;
386 intptr_t index = simd_data(desc);
387 uint64_t *d = vd;
388 uint16_t *n = vn;
389 uint16_t *m_indexed = (uint16_t *)vm + index * 4;
390
391 /* This is supported by SVE only, so opr_sz is always a multiple of 16.
392 * Process the entire segment all at once, writing back the results
393 * only after we've consumed all of the inputs.
394 */
395 for (i = 0; i < opr_sz_8 ; i += 2) {
396 uint64_t d0, d1;
397
398 d0 = n[i * 4 + 0] * (uint64_t)m_indexed[i * 4 + 0];
399 d0 += n[i * 4 + 1] * (uint64_t)m_indexed[i * 4 + 1];
400 d0 += n[i * 4 + 2] * (uint64_t)m_indexed[i * 4 + 2];
401 d0 += n[i * 4 + 3] * (uint64_t)m_indexed[i * 4 + 3];
402 d1 = n[i * 4 + 4] * (uint64_t)m_indexed[i * 4 + 0];
403 d1 += n[i * 4 + 5] * (uint64_t)m_indexed[i * 4 + 1];
404 d1 += n[i * 4 + 6] * (uint64_t)m_indexed[i * 4 + 2];
405 d1 += n[i * 4 + 7] * (uint64_t)m_indexed[i * 4 + 3];
406
407 d[i + 0] += d0;
408 d[i + 1] += d1;
409 }
410
411 clear_tail(d, opr_sz, simd_maxsz(desc));
412 }
413
414 void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm,
415 void *vfpst, uint32_t desc)
416 {
417 uintptr_t opr_sz = simd_oprsz(desc);
418 float16 *d = vd;
419 float16 *n = vn;
420 float16 *m = vm;
421 float_status *fpst = vfpst;
422 uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
423 uint32_t neg_imag = neg_real ^ 1;
424 uintptr_t i;
425
426 /* Shift boolean to the sign bit so we can xor to negate. */
427 neg_real <<= 15;
428 neg_imag <<= 15;
429
430 for (i = 0; i < opr_sz / 2; i += 2) {
431 float16 e0 = n[H2(i)];
432 float16 e1 = m[H2(i + 1)] ^ neg_imag;
433 float16 e2 = n[H2(i + 1)];
434 float16 e3 = m[H2(i)] ^ neg_real;
435
436 d[H2(i)] = float16_add(e0, e1, fpst);
437 d[H2(i + 1)] = float16_add(e2, e3, fpst);
438 }
439 clear_tail(d, opr_sz, simd_maxsz(desc));
440 }
441
442 void HELPER(gvec_fcadds)(void *vd, void *vn, void *vm,
443 void *vfpst, uint32_t desc)
444 {
445 uintptr_t opr_sz = simd_oprsz(desc);
446 float32 *d = vd;
447 float32 *n = vn;
448 float32 *m = vm;
449 float_status *fpst = vfpst;
450 uint32_t neg_real = extract32(desc, SIMD_DATA_SHIFT, 1);
451 uint32_t neg_imag = neg_real ^ 1;
452 uintptr_t i;
453
454 /* Shift boolean to the sign bit so we can xor to negate. */
455 neg_real <<= 31;
456 neg_imag <<= 31;
457
458 for (i = 0; i < opr_sz / 4; i += 2) {
459 float32 e0 = n[H4(i)];
460 float32 e1 = m[H4(i + 1)] ^ neg_imag;
461 float32 e2 = n[H4(i + 1)];
462 float32 e3 = m[H4(i)] ^ neg_real;
463
464 d[H4(i)] = float32_add(e0, e1, fpst);
465 d[H4(i + 1)] = float32_add(e2, e3, fpst);
466 }
467 clear_tail(d, opr_sz, simd_maxsz(desc));
468 }
469
470 void HELPER(gvec_fcaddd)(void *vd, void *vn, void *vm,
471 void *vfpst, uint32_t desc)
472 {
473 uintptr_t opr_sz = simd_oprsz(desc);
474 float64 *d = vd;
475 float64 *n = vn;
476 float64 *m = vm;
477 float_status *fpst = vfpst;
478 uint64_t neg_real = extract64(desc, SIMD_DATA_SHIFT, 1);
479 uint64_t neg_imag = neg_real ^ 1;
480 uintptr_t i;
481
482 /* Shift boolean to the sign bit so we can xor to negate. */
483 neg_real <<= 63;
484 neg_imag <<= 63;
485
486 for (i = 0; i < opr_sz / 8; i += 2) {
487 float64 e0 = n[i];
488 float64 e1 = m[i + 1] ^ neg_imag;
489 float64 e2 = n[i + 1];
490 float64 e3 = m[i] ^ neg_real;
491
492 d[i] = float64_add(e0, e1, fpst);
493 d[i + 1] = float64_add(e2, e3, fpst);
494 }
495 clear_tail(d, opr_sz, simd_maxsz(desc));
496 }
497
498 void HELPER(gvec_fcmlah)(void *vd, void *vn, void *vm,
499 void *vfpst, uint32_t desc)
500 {
501 uintptr_t opr_sz = simd_oprsz(desc);
502 float16 *d = vd;
503 float16 *n = vn;
504 float16 *m = vm;
505 float_status *fpst = vfpst;
506 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
507 uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
508 uint32_t neg_real = flip ^ neg_imag;
509 uintptr_t i;
510
511 /* Shift boolean to the sign bit so we can xor to negate. */
512 neg_real <<= 15;
513 neg_imag <<= 15;
514
515 for (i = 0; i < opr_sz / 2; i += 2) {
516 float16 e2 = n[H2(i + flip)];
517 float16 e1 = m[H2(i + flip)] ^ neg_real;
518 float16 e4 = e2;
519 float16 e3 = m[H2(i + 1 - flip)] ^ neg_imag;
520
521 d[H2(i)] = float16_muladd(e2, e1, d[H2(i)], 0, fpst);
522 d[H2(i + 1)] = float16_muladd(e4, e3, d[H2(i + 1)], 0, fpst);
523 }
524 clear_tail(d, opr_sz, simd_maxsz(desc));
525 }
526
527 void HELPER(gvec_fcmlah_idx)(void *vd, void *vn, void *vm,
528 void *vfpst, uint32_t desc)
529 {
530 uintptr_t opr_sz = simd_oprsz(desc);
531 float16 *d = vd;
532 float16 *n = vn;
533 float16 *m = vm;
534 float_status *fpst = vfpst;
535 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
536 uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
537 intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2);
538 uint32_t neg_real = flip ^ neg_imag;
539 intptr_t elements = opr_sz / sizeof(float16);
540 intptr_t eltspersegment = 16 / sizeof(float16);
541 intptr_t i, j;
542
543 /* Shift boolean to the sign bit so we can xor to negate. */
544 neg_real <<= 15;
545 neg_imag <<= 15;
546
547 for (i = 0; i < elements; i += eltspersegment) {
548 float16 mr = m[H2(i + 2 * index + 0)];
549 float16 mi = m[H2(i + 2 * index + 1)];
550 float16 e1 = neg_real ^ (flip ? mi : mr);
551 float16 e3 = neg_imag ^ (flip ? mr : mi);
552
553 for (j = i; j < i + eltspersegment; j += 2) {
554 float16 e2 = n[H2(j + flip)];
555 float16 e4 = e2;
556
557 d[H2(j)] = float16_muladd(e2, e1, d[H2(j)], 0, fpst);
558 d[H2(j + 1)] = float16_muladd(e4, e3, d[H2(j + 1)], 0, fpst);
559 }
560 }
561 clear_tail(d, opr_sz, simd_maxsz(desc));
562 }
563
564 void HELPER(gvec_fcmlas)(void *vd, void *vn, void *vm,
565 void *vfpst, uint32_t desc)
566 {
567 uintptr_t opr_sz = simd_oprsz(desc);
568 float32 *d = vd;
569 float32 *n = vn;
570 float32 *m = vm;
571 float_status *fpst = vfpst;
572 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
573 uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
574 uint32_t neg_real = flip ^ neg_imag;
575 uintptr_t i;
576
577 /* Shift boolean to the sign bit so we can xor to negate. */
578 neg_real <<= 31;
579 neg_imag <<= 31;
580
581 for (i = 0; i < opr_sz / 4; i += 2) {
582 float32 e2 = n[H4(i + flip)];
583 float32 e1 = m[H4(i + flip)] ^ neg_real;
584 float32 e4 = e2;
585 float32 e3 = m[H4(i + 1 - flip)] ^ neg_imag;
586
587 d[H4(i)] = float32_muladd(e2, e1, d[H4(i)], 0, fpst);
588 d[H4(i + 1)] = float32_muladd(e4, e3, d[H4(i + 1)], 0, fpst);
589 }
590 clear_tail(d, opr_sz, simd_maxsz(desc));
591 }
592
593 void HELPER(gvec_fcmlas_idx)(void *vd, void *vn, void *vm,
594 void *vfpst, uint32_t desc)
595 {
596 uintptr_t opr_sz = simd_oprsz(desc);
597 float32 *d = vd;
598 float32 *n = vn;
599 float32 *m = vm;
600 float_status *fpst = vfpst;
601 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
602 uint32_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
603 intptr_t index = extract32(desc, SIMD_DATA_SHIFT + 2, 2);
604 uint32_t neg_real = flip ^ neg_imag;
605 intptr_t elements = opr_sz / sizeof(float32);
606 intptr_t eltspersegment = 16 / sizeof(float32);
607 intptr_t i, j;
608
609 /* Shift boolean to the sign bit so we can xor to negate. */
610 neg_real <<= 31;
611 neg_imag <<= 31;
612
613 for (i = 0; i < elements; i += eltspersegment) {
614 float32 mr = m[H4(i + 2 * index + 0)];
615 float32 mi = m[H4(i + 2 * index + 1)];
616 float32 e1 = neg_real ^ (flip ? mi : mr);
617 float32 e3 = neg_imag ^ (flip ? mr : mi);
618
619 for (j = i; j < i + eltspersegment; j += 2) {
620 float32 e2 = n[H4(j + flip)];
621 float32 e4 = e2;
622
623 d[H4(j)] = float32_muladd(e2, e1, d[H4(j)], 0, fpst);
624 d[H4(j + 1)] = float32_muladd(e4, e3, d[H4(j + 1)], 0, fpst);
625 }
626 }
627 clear_tail(d, opr_sz, simd_maxsz(desc));
628 }
629
630 void HELPER(gvec_fcmlad)(void *vd, void *vn, void *vm,
631 void *vfpst, uint32_t desc)
632 {
633 uintptr_t opr_sz = simd_oprsz(desc);
634 float64 *d = vd;
635 float64 *n = vn;
636 float64 *m = vm;
637 float_status *fpst = vfpst;
638 intptr_t flip = extract32(desc, SIMD_DATA_SHIFT, 1);
639 uint64_t neg_imag = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
640 uint64_t neg_real = flip ^ neg_imag;
641 uintptr_t i;
642
643 /* Shift boolean to the sign bit so we can xor to negate. */
644 neg_real <<= 63;
645 neg_imag <<= 63;
646
647 for (i = 0; i < opr_sz / 8; i += 2) {
648 float64 e2 = n[i + flip];
649 float64 e1 = m[i + flip] ^ neg_real;
650 float64 e4 = e2;
651 float64 e3 = m[i + 1 - flip] ^ neg_imag;
652
653 d[i] = float64_muladd(e2, e1, d[i], 0, fpst);
654 d[i + 1] = float64_muladd(e4, e3, d[i + 1], 0, fpst);
655 }
656 clear_tail(d, opr_sz, simd_maxsz(desc));
657 }
658
659 #define DO_2OP(NAME, FUNC, TYPE) \
660 void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \
661 { \
662 intptr_t i, oprsz = simd_oprsz(desc); \
663 TYPE *d = vd, *n = vn; \
664 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
665 d[i] = FUNC(n[i], stat); \
666 } \
667 clear_tail(d, oprsz, simd_maxsz(desc)); \
668 }
669
670 DO_2OP(gvec_frecpe_h, helper_recpe_f16, float16)
671 DO_2OP(gvec_frecpe_s, helper_recpe_f32, float32)
672 DO_2OP(gvec_frecpe_d, helper_recpe_f64, float64)
673
674 DO_2OP(gvec_frsqrte_h, helper_rsqrte_f16, float16)
675 DO_2OP(gvec_frsqrte_s, helper_rsqrte_f32, float32)
676 DO_2OP(gvec_frsqrte_d, helper_rsqrte_f64, float64)
677
678 #undef DO_2OP
679
680 /* Floating-point trigonometric starting value.
681 * See the ARM ARM pseudocode function FPTrigSMul.
682 */
683 static float16 float16_ftsmul(float16 op1, uint16_t op2, float_status *stat)
684 {
685 float16 result = float16_mul(op1, op1, stat);
686 if (!float16_is_any_nan(result)) {
687 result = float16_set_sign(result, op2 & 1);
688 }
689 return result;
690 }
691
692 static float32 float32_ftsmul(float32 op1, uint32_t op2, float_status *stat)
693 {
694 float32 result = float32_mul(op1, op1, stat);
695 if (!float32_is_any_nan(result)) {
696 result = float32_set_sign(result, op2 & 1);
697 }
698 return result;
699 }
700
701 static float64 float64_ftsmul(float64 op1, uint64_t op2, float_status *stat)
702 {
703 float64 result = float64_mul(op1, op1, stat);
704 if (!float64_is_any_nan(result)) {
705 result = float64_set_sign(result, op2 & 1);
706 }
707 return result;
708 }
709
710 static float16 float16_abd(float16 op1, float16 op2, float_status *stat)
711 {
712 return float16_abs(float16_sub(op1, op2, stat));
713 }
714
715 static float32 float32_abd(float32 op1, float32 op2, float_status *stat)
716 {
717 return float32_abs(float32_sub(op1, op2, stat));
718 }
719
720 #define DO_3OP(NAME, FUNC, TYPE) \
721 void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
722 { \
723 intptr_t i, oprsz = simd_oprsz(desc); \
724 TYPE *d = vd, *n = vn, *m = vm; \
725 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
726 d[i] = FUNC(n[i], m[i], stat); \
727 } \
728 clear_tail(d, oprsz, simd_maxsz(desc)); \
729 }
730
731 DO_3OP(gvec_fadd_h, float16_add, float16)
732 DO_3OP(gvec_fadd_s, float32_add, float32)
733 DO_3OP(gvec_fadd_d, float64_add, float64)
734
735 DO_3OP(gvec_fsub_h, float16_sub, float16)
736 DO_3OP(gvec_fsub_s, float32_sub, float32)
737 DO_3OP(gvec_fsub_d, float64_sub, float64)
738
739 DO_3OP(gvec_fmul_h, float16_mul, float16)
740 DO_3OP(gvec_fmul_s, float32_mul, float32)
741 DO_3OP(gvec_fmul_d, float64_mul, float64)
742
743 DO_3OP(gvec_ftsmul_h, float16_ftsmul, float16)
744 DO_3OP(gvec_ftsmul_s, float32_ftsmul, float32)
745 DO_3OP(gvec_ftsmul_d, float64_ftsmul, float64)
746
747 DO_3OP(gvec_fabd_h, float16_abd, float16)
748 DO_3OP(gvec_fabd_s, float32_abd, float32)
749
750 #ifdef TARGET_AARCH64
751
752 DO_3OP(gvec_recps_h, helper_recpsf_f16, float16)
753 DO_3OP(gvec_recps_s, helper_recpsf_f32, float32)
754 DO_3OP(gvec_recps_d, helper_recpsf_f64, float64)
755
756 DO_3OP(gvec_rsqrts_h, helper_rsqrtsf_f16, float16)
757 DO_3OP(gvec_rsqrts_s, helper_rsqrtsf_f32, float32)
758 DO_3OP(gvec_rsqrts_d, helper_rsqrtsf_f64, float64)
759
760 #endif
761 #undef DO_3OP
762
763 /* For the indexed ops, SVE applies the index per 128-bit vector segment.
764 * For AdvSIMD, there is of course only one such vector segment.
765 */
766
767 #define DO_MUL_IDX(NAME, TYPE, H) \
768 void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
769 { \
770 intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
771 intptr_t idx = simd_data(desc); \
772 TYPE *d = vd, *n = vn, *m = vm; \
773 for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
774 TYPE mm = m[H(i + idx)]; \
775 for (j = 0; j < segment; j++) { \
776 d[i + j] = n[i + j] * mm; \
777 } \
778 } \
779 clear_tail(d, oprsz, simd_maxsz(desc)); \
780 }
781
782 DO_MUL_IDX(gvec_mul_idx_h, uint16_t, H2)
783 DO_MUL_IDX(gvec_mul_idx_s, uint32_t, H4)
784 DO_MUL_IDX(gvec_mul_idx_d, uint64_t, )
785
786 #undef DO_MUL_IDX
787
788 #define DO_MLA_IDX(NAME, TYPE, OP, H) \
789 void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, uint32_t desc) \
790 { \
791 intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
792 intptr_t idx = simd_data(desc); \
793 TYPE *d = vd, *n = vn, *m = vm, *a = va; \
794 for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
795 TYPE mm = m[H(i + idx)]; \
796 for (j = 0; j < segment; j++) { \
797 d[i + j] = a[i + j] OP n[i + j] * mm; \
798 } \
799 } \
800 clear_tail(d, oprsz, simd_maxsz(desc)); \
801 }
802
803 DO_MLA_IDX(gvec_mla_idx_h, uint16_t, +, H2)
804 DO_MLA_IDX(gvec_mla_idx_s, uint32_t, +, H4)
805 DO_MLA_IDX(gvec_mla_idx_d, uint64_t, +, )
806
807 DO_MLA_IDX(gvec_mls_idx_h, uint16_t, -, H2)
808 DO_MLA_IDX(gvec_mls_idx_s, uint32_t, -, H4)
809 DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, )
810
811 #undef DO_MLA_IDX
812
813 #define DO_FMUL_IDX(NAME, TYPE, H) \
814 void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \
815 { \
816 intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
817 intptr_t idx = simd_data(desc); \
818 TYPE *d = vd, *n = vn, *m = vm; \
819 for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
820 TYPE mm = m[H(i + idx)]; \
821 for (j = 0; j < segment; j++) { \
822 d[i + j] = TYPE##_mul(n[i + j], mm, stat); \
823 } \
824 } \
825 clear_tail(d, oprsz, simd_maxsz(desc)); \
826 }
827
828 DO_FMUL_IDX(gvec_fmul_idx_h, float16, H2)
829 DO_FMUL_IDX(gvec_fmul_idx_s, float32, H4)
830 DO_FMUL_IDX(gvec_fmul_idx_d, float64, )
831
832 #undef DO_FMUL_IDX
833
834 #define DO_FMLA_IDX(NAME, TYPE, H) \
835 void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, \
836 void *stat, uint32_t desc) \
837 { \
838 intptr_t i, j, oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
839 TYPE op1_neg = extract32(desc, SIMD_DATA_SHIFT, 1); \
840 intptr_t idx = desc >> (SIMD_DATA_SHIFT + 1); \
841 TYPE *d = vd, *n = vn, *m = vm, *a = va; \
842 op1_neg <<= (8 * sizeof(TYPE) - 1); \
843 for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
844 TYPE mm = m[H(i + idx)]; \
845 for (j = 0; j < segment; j++) { \
846 d[i + j] = TYPE##_muladd(n[i + j] ^ op1_neg, \
847 mm, a[i + j], 0, stat); \
848 } \
849 } \
850 clear_tail(d, oprsz, simd_maxsz(desc)); \
851 }
852
853 DO_FMLA_IDX(gvec_fmla_idx_h, float16, H2)
854 DO_FMLA_IDX(gvec_fmla_idx_s, float32, H4)
855 DO_FMLA_IDX(gvec_fmla_idx_d, float64, )
856
857 #undef DO_FMLA_IDX
858
859 #define DO_SAT(NAME, WTYPE, TYPEN, TYPEM, OP, MIN, MAX) \
860 void HELPER(NAME)(void *vd, void *vq, void *vn, void *vm, uint32_t desc) \
861 { \
862 intptr_t i, oprsz = simd_oprsz(desc); \
863 TYPEN *d = vd, *n = vn; TYPEM *m = vm; \
864 bool q = false; \
865 for (i = 0; i < oprsz / sizeof(TYPEN); i++) { \
866 WTYPE dd = (WTYPE)n[i] OP m[i]; \
867 if (dd < MIN) { \
868 dd = MIN; \
869 q = true; \
870 } else if (dd > MAX) { \
871 dd = MAX; \
872 q = true; \
873 } \
874 d[i] = dd; \
875 } \
876 if (q) { \
877 uint32_t *qc = vq; \
878 qc[0] = 1; \
879 } \
880 clear_tail(d, oprsz, simd_maxsz(desc)); \
881 }
882
883 DO_SAT(gvec_uqadd_b, int, uint8_t, uint8_t, +, 0, UINT8_MAX)
884 DO_SAT(gvec_uqadd_h, int, uint16_t, uint16_t, +, 0, UINT16_MAX)
885 DO_SAT(gvec_uqadd_s, int64_t, uint32_t, uint32_t, +, 0, UINT32_MAX)
886
887 DO_SAT(gvec_sqadd_b, int, int8_t, int8_t, +, INT8_MIN, INT8_MAX)
888 DO_SAT(gvec_sqadd_h, int, int16_t, int16_t, +, INT16_MIN, INT16_MAX)
889 DO_SAT(gvec_sqadd_s, int64_t, int32_t, int32_t, +, INT32_MIN, INT32_MAX)
890
891 DO_SAT(gvec_uqsub_b, int, uint8_t, uint8_t, -, 0, UINT8_MAX)
892 DO_SAT(gvec_uqsub_h, int, uint16_t, uint16_t, -, 0, UINT16_MAX)
893 DO_SAT(gvec_uqsub_s, int64_t, uint32_t, uint32_t, -, 0, UINT32_MAX)
894
895 DO_SAT(gvec_sqsub_b, int, int8_t, int8_t, -, INT8_MIN, INT8_MAX)
896 DO_SAT(gvec_sqsub_h, int, int16_t, int16_t, -, INT16_MIN, INT16_MAX)
897 DO_SAT(gvec_sqsub_s, int64_t, int32_t, int32_t, -, INT32_MIN, INT32_MAX)
898
899 #undef DO_SAT
900
901 void HELPER(gvec_uqadd_d)(void *vd, void *vq, void *vn,
902 void *vm, uint32_t desc)
903 {
904 intptr_t i, oprsz = simd_oprsz(desc);
905 uint64_t *d = vd, *n = vn, *m = vm;
906 bool q = false;
907
908 for (i = 0; i < oprsz / 8; i++) {
909 uint64_t nn = n[i], mm = m[i], dd = nn + mm;
910 if (dd < nn) {
911 dd = UINT64_MAX;
912 q = true;
913 }
914 d[i] = dd;
915 }
916 if (q) {
917 uint32_t *qc = vq;
918 qc[0] = 1;
919 }
920 clear_tail(d, oprsz, simd_maxsz(desc));
921 }
922
923 void HELPER(gvec_uqsub_d)(void *vd, void *vq, void *vn,
924 void *vm, uint32_t desc)
925 {
926 intptr_t i, oprsz = simd_oprsz(desc);
927 uint64_t *d = vd, *n = vn, *m = vm;
928 bool q = false;
929
930 for (i = 0; i < oprsz / 8; i++) {
931 uint64_t nn = n[i], mm = m[i], dd = nn - mm;
932 if (nn < mm) {
933 dd = 0;
934 q = true;
935 }
936 d[i] = dd;
937 }
938 if (q) {
939 uint32_t *qc = vq;
940 qc[0] = 1;
941 }
942 clear_tail(d, oprsz, simd_maxsz(desc));
943 }
944
945 void HELPER(gvec_sqadd_d)(void *vd, void *vq, void *vn,
946 void *vm, uint32_t desc)
947 {
948 intptr_t i, oprsz = simd_oprsz(desc);
949 int64_t *d = vd, *n = vn, *m = vm;
950 bool q = false;
951
952 for (i = 0; i < oprsz / 8; i++) {
953 int64_t nn = n[i], mm = m[i], dd = nn + mm;
954 if (((dd ^ nn) & ~(nn ^ mm)) & INT64_MIN) {
955 dd = (nn >> 63) ^ ~INT64_MIN;
956 q = true;
957 }
958 d[i] = dd;
959 }
960 if (q) {
961 uint32_t *qc = vq;
962 qc[0] = 1;
963 }
964 clear_tail(d, oprsz, simd_maxsz(desc));
965 }
966
967 void HELPER(gvec_sqsub_d)(void *vd, void *vq, void *vn,
968 void *vm, uint32_t desc)
969 {
970 intptr_t i, oprsz = simd_oprsz(desc);
971 int64_t *d = vd, *n = vn, *m = vm;
972 bool q = false;
973
974 for (i = 0; i < oprsz / 8; i++) {
975 int64_t nn = n[i], mm = m[i], dd = nn - mm;
976 if (((dd ^ nn) & (nn ^ mm)) & INT64_MIN) {
977 dd = (nn >> 63) ^ ~INT64_MIN;
978 q = true;
979 }
980 d[i] = dd;
981 }
982 if (q) {
983 uint32_t *qc = vq;
984 qc[0] = 1;
985 }
986 clear_tail(d, oprsz, simd_maxsz(desc));
987 }
988
989
990 #define DO_SRA(NAME, TYPE) \
991 void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
992 { \
993 intptr_t i, oprsz = simd_oprsz(desc); \
994 int shift = simd_data(desc); \
995 TYPE *d = vd, *n = vn; \
996 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
997 d[i] += n[i] >> shift; \
998 } \
999 clear_tail(d, oprsz, simd_maxsz(desc)); \
1000 }
1001
1002 DO_SRA(gvec_ssra_b, int8_t)
1003 DO_SRA(gvec_ssra_h, int16_t)
1004 DO_SRA(gvec_ssra_s, int32_t)
1005 DO_SRA(gvec_ssra_d, int64_t)
1006
1007 DO_SRA(gvec_usra_b, uint8_t)
1008 DO_SRA(gvec_usra_h, uint16_t)
1009 DO_SRA(gvec_usra_s, uint32_t)
1010 DO_SRA(gvec_usra_d, uint64_t)
1011
1012 #undef DO_SRA
1013
1014 #define DO_RSHR(NAME, TYPE) \
1015 void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
1016 { \
1017 intptr_t i, oprsz = simd_oprsz(desc); \
1018 int shift = simd_data(desc); \
1019 TYPE *d = vd, *n = vn; \
1020 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
1021 TYPE tmp = n[i] >> (shift - 1); \
1022 d[i] = (tmp >> 1) + (tmp & 1); \
1023 } \
1024 clear_tail(d, oprsz, simd_maxsz(desc)); \
1025 }
1026
1027 DO_RSHR(gvec_srshr_b, int8_t)
1028 DO_RSHR(gvec_srshr_h, int16_t)
1029 DO_RSHR(gvec_srshr_s, int32_t)
1030 DO_RSHR(gvec_srshr_d, int64_t)
1031
1032 DO_RSHR(gvec_urshr_b, uint8_t)
1033 DO_RSHR(gvec_urshr_h, uint16_t)
1034 DO_RSHR(gvec_urshr_s, uint32_t)
1035 DO_RSHR(gvec_urshr_d, uint64_t)
1036
1037 #undef DO_RSHR
1038
1039 #define DO_RSRA(NAME, TYPE) \
1040 void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
1041 { \
1042 intptr_t i, oprsz = simd_oprsz(desc); \
1043 int shift = simd_data(desc); \
1044 TYPE *d = vd, *n = vn; \
1045 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
1046 TYPE tmp = n[i] >> (shift - 1); \
1047 d[i] += (tmp >> 1) + (tmp & 1); \
1048 } \
1049 clear_tail(d, oprsz, simd_maxsz(desc)); \
1050 }
1051
1052 DO_RSRA(gvec_srsra_b, int8_t)
1053 DO_RSRA(gvec_srsra_h, int16_t)
1054 DO_RSRA(gvec_srsra_s, int32_t)
1055 DO_RSRA(gvec_srsra_d, int64_t)
1056
1057 DO_RSRA(gvec_ursra_b, uint8_t)
1058 DO_RSRA(gvec_ursra_h, uint16_t)
1059 DO_RSRA(gvec_ursra_s, uint32_t)
1060 DO_RSRA(gvec_ursra_d, uint64_t)
1061
1062 #undef DO_RSRA
1063
1064 #define DO_SRI(NAME, TYPE) \
1065 void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
1066 { \
1067 intptr_t i, oprsz = simd_oprsz(desc); \
1068 int shift = simd_data(desc); \
1069 TYPE *d = vd, *n = vn; \
1070 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
1071 d[i] = deposit64(d[i], 0, sizeof(TYPE) * 8 - shift, n[i] >> shift); \
1072 } \
1073 clear_tail(d, oprsz, simd_maxsz(desc)); \
1074 }
1075
1076 DO_SRI(gvec_sri_b, uint8_t)
1077 DO_SRI(gvec_sri_h, uint16_t)
1078 DO_SRI(gvec_sri_s, uint32_t)
1079 DO_SRI(gvec_sri_d, uint64_t)
1080
1081 #undef DO_SRI
1082
1083 #define DO_SLI(NAME, TYPE) \
1084 void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
1085 { \
1086 intptr_t i, oprsz = simd_oprsz(desc); \
1087 int shift = simd_data(desc); \
1088 TYPE *d = vd, *n = vn; \
1089 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
1090 d[i] = deposit64(d[i], shift, sizeof(TYPE) * 8 - shift, n[i]); \
1091 } \
1092 clear_tail(d, oprsz, simd_maxsz(desc)); \
1093 }
1094
1095 DO_SLI(gvec_sli_b, uint8_t)
1096 DO_SLI(gvec_sli_h, uint16_t)
1097 DO_SLI(gvec_sli_s, uint32_t)
1098 DO_SLI(gvec_sli_d, uint64_t)
1099
1100 #undef DO_SLI
1101
1102 /*
1103 * Convert float16 to float32, raising no exceptions and
1104 * preserving exceptional values, including SNaN.
1105 * This is effectively an unpack+repack operation.
1106 */
1107 static float32 float16_to_float32_by_bits(uint32_t f16, bool fz16)
1108 {
1109 const int f16_bias = 15;
1110 const int f32_bias = 127;
1111 uint32_t sign = extract32(f16, 15, 1);
1112 uint32_t exp = extract32(f16, 10, 5);
1113 uint32_t frac = extract32(f16, 0, 10);
1114
1115 if (exp == 0x1f) {
1116 /* Inf or NaN */
1117 exp = 0xff;
1118 } else if (exp == 0) {
1119 /* Zero or denormal. */
1120 if (frac != 0) {
1121 if (fz16) {
1122 frac = 0;
1123 } else {
1124 /*
1125 * Denormal; these are all normal float32.
1126 * Shift the fraction so that the msb is at bit 11,
1127 * then remove bit 11 as the implicit bit of the
1128 * normalized float32. Note that we still go through
1129 * the shift for normal numbers below, to put the
1130 * float32 fraction at the right place.
1131 */
1132 int shift = clz32(frac) - 21;
1133 frac = (frac << shift) & 0x3ff;
1134 exp = f32_bias - f16_bias - shift + 1;
1135 }
1136 }
1137 } else {
1138 /* Normal number; adjust the bias. */
1139 exp += f32_bias - f16_bias;
1140 }
1141 sign <<= 31;
1142 exp <<= 23;
1143 frac <<= 23 - 10;
1144
1145 return sign | exp | frac;
1146 }
1147
1148 static uint64_t load4_f16(uint64_t *ptr, int is_q, int is_2)
1149 {
1150 /*
1151 * Branchless load of u32[0], u64[0], u32[1], or u64[1].
1152 * Load the 2nd qword iff is_q & is_2.
1153 * Shift to the 2nd dword iff !is_q & is_2.
1154 * For !is_q & !is_2, the upper bits of the result are garbage.
1155 */
1156 return ptr[is_q & is_2] >> ((is_2 & ~is_q) << 5);
1157 }
1158
1159 /*
1160 * Note that FMLAL requires oprsz == 8 or oprsz == 16,
1161 * as there is not yet SVE versions that might use blocking.
1162 */
1163
1164 static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst,
1165 uint32_t desc, bool fz16)
1166 {
1167 intptr_t i, oprsz = simd_oprsz(desc);
1168 int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
1169 int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
1170 int is_q = oprsz == 16;
1171 uint64_t n_4, m_4;
1172
1173 /* Pre-load all of the f16 data, avoiding overlap issues. */
1174 n_4 = load4_f16(vn, is_q, is_2);
1175 m_4 = load4_f16(vm, is_q, is_2);
1176
1177 /* Negate all inputs for FMLSL at once. */
1178 if (is_s) {
1179 n_4 ^= 0x8000800080008000ull;
1180 }
1181
1182 for (i = 0; i < oprsz / 4; i++) {
1183 float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16);
1184 float32 m_1 = float16_to_float32_by_bits(m_4 >> (i * 16), fz16);
1185 d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
1186 }
1187 clear_tail(d, oprsz, simd_maxsz(desc));
1188 }
1189
1190 void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm,
1191 void *venv, uint32_t desc)
1192 {
1193 CPUARMState *env = venv;
1194 do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc,
1195 get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
1196 }
1197
1198 void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
1199 void *venv, uint32_t desc)
1200 {
1201 CPUARMState *env = venv;
1202 do_fmlal(vd, vn, vm, &env->vfp.fp_status, desc,
1203 get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
1204 }
1205
1206 static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fpst,
1207 uint32_t desc, bool fz16)
1208 {
1209 intptr_t i, oprsz = simd_oprsz(desc);
1210 int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
1211 int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
1212 int index = extract32(desc, SIMD_DATA_SHIFT + 2, 3);
1213 int is_q = oprsz == 16;
1214 uint64_t n_4;
1215 float32 m_1;
1216
1217 /* Pre-load all of the f16 data, avoiding overlap issues. */
1218 n_4 = load4_f16(vn, is_q, is_2);
1219
1220 /* Negate all inputs for FMLSL at once. */
1221 if (is_s) {
1222 n_4 ^= 0x8000800080008000ull;
1223 }
1224
1225 m_1 = float16_to_float32_by_bits(((float16 *)vm)[H2(index)], fz16);
1226
1227 for (i = 0; i < oprsz / 4; i++) {
1228 float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16);
1229 d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
1230 }
1231 clear_tail(d, oprsz, simd_maxsz(desc));
1232 }
1233
1234 void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm,
1235 void *venv, uint32_t desc)
1236 {
1237 CPUARMState *env = venv;
1238 do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc,
1239 get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
1240 }
1241
1242 void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
1243 void *venv, uint32_t desc)
1244 {
1245 CPUARMState *env = venv;
1246 do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc,
1247 get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
1248 }
1249
1250 void HELPER(gvec_sshl_b)(void *vd, void *vn, void *vm, uint32_t desc)
1251 {
1252 intptr_t i, opr_sz = simd_oprsz(desc);
1253 int8_t *d = vd, *n = vn, *m = vm;
1254
1255 for (i = 0; i < opr_sz; ++i) {
1256 int8_t mm = m[i];
1257 int8_t nn = n[i];
1258 int8_t res = 0;
1259 if (mm >= 0) {
1260 if (mm < 8) {
1261 res = nn << mm;
1262 }
1263 } else {
1264 res = nn >> (mm > -8 ? -mm : 7);
1265 }
1266 d[i] = res;
1267 }
1268 clear_tail(d, opr_sz, simd_maxsz(desc));
1269 }
1270
1271 void HELPER(gvec_sshl_h)(void *vd, void *vn, void *vm, uint32_t desc)
1272 {
1273 intptr_t i, opr_sz = simd_oprsz(desc);
1274 int16_t *d = vd, *n = vn, *m = vm;
1275
1276 for (i = 0; i < opr_sz / 2; ++i) {
1277 int8_t mm = m[i]; /* only 8 bits of shift are significant */
1278 int16_t nn = n[i];
1279 int16_t res = 0;
1280 if (mm >= 0) {
1281 if (mm < 16) {
1282 res = nn << mm;
1283 }
1284 } else {
1285 res = nn >> (mm > -16 ? -mm : 15);
1286 }
1287 d[i] = res;
1288 }
1289 clear_tail(d, opr_sz, simd_maxsz(desc));
1290 }
1291
1292 void HELPER(gvec_ushl_b)(void *vd, void *vn, void *vm, uint32_t desc)
1293 {
1294 intptr_t i, opr_sz = simd_oprsz(desc);
1295 uint8_t *d = vd, *n = vn, *m = vm;
1296
1297 for (i = 0; i < opr_sz; ++i) {
1298 int8_t mm = m[i];
1299 uint8_t nn = n[i];
1300 uint8_t res = 0;
1301 if (mm >= 0) {
1302 if (mm < 8) {
1303 res = nn << mm;
1304 }
1305 } else {
1306 if (mm > -8) {
1307 res = nn >> -mm;
1308 }
1309 }
1310 d[i] = res;
1311 }
1312 clear_tail(d, opr_sz, simd_maxsz(desc));
1313 }
1314
1315 void HELPER(gvec_ushl_h)(void *vd, void *vn, void *vm, uint32_t desc)
1316 {
1317 intptr_t i, opr_sz = simd_oprsz(desc);
1318 uint16_t *d = vd, *n = vn, *m = vm;
1319
1320 for (i = 0; i < opr_sz / 2; ++i) {
1321 int8_t mm = m[i]; /* only 8 bits of shift are significant */
1322 uint16_t nn = n[i];
1323 uint16_t res = 0;
1324 if (mm >= 0) {
1325 if (mm < 16) {
1326 res = nn << mm;
1327 }
1328 } else {
1329 if (mm > -16) {
1330 res = nn >> -mm;
1331 }
1332 }
1333 d[i] = res;
1334 }
1335 clear_tail(d, opr_sz, simd_maxsz(desc));
1336 }
1337
1338 /*
1339 * 8x8->8 polynomial multiply.
1340 *
1341 * Polynomial multiplication is like integer multiplication except the
1342 * partial products are XORed, not added.
1343 *
1344 * TODO: expose this as a generic vector operation, as it is a common
1345 * crypto building block.
1346 */
1347 void HELPER(gvec_pmul_b)(void *vd, void *vn, void *vm, uint32_t desc)
1348 {
1349 intptr_t i, j, opr_sz = simd_oprsz(desc);
1350 uint64_t *d = vd, *n = vn, *m = vm;
1351
1352 for (i = 0; i < opr_sz / 8; ++i) {
1353 uint64_t nn = n[i];
1354 uint64_t mm = m[i];
1355 uint64_t rr = 0;
1356
1357 for (j = 0; j < 8; ++j) {
1358 uint64_t mask = (nn & 0x0101010101010101ull) * 0xff;
1359 rr ^= mm & mask;
1360 mm = (mm << 1) & 0xfefefefefefefefeull;
1361 nn >>= 1;
1362 }
1363 d[i] = rr;
1364 }
1365 clear_tail(d, opr_sz, simd_maxsz(desc));
1366 }
1367
1368 /*
1369 * 64x64->128 polynomial multiply.
1370 * Because of the lanes are not accessed in strict columns,
1371 * this probably cannot be turned into a generic helper.
1372 */
1373 void HELPER(gvec_pmull_q)(void *vd, void *vn, void *vm, uint32_t desc)
1374 {
1375 intptr_t i, j, opr_sz = simd_oprsz(desc);
1376 intptr_t hi = simd_data(desc);
1377 uint64_t *d = vd, *n = vn, *m = vm;
1378
1379 for (i = 0; i < opr_sz / 8; i += 2) {
1380 uint64_t nn = n[i + hi];
1381 uint64_t mm = m[i + hi];
1382 uint64_t rhi = 0;
1383 uint64_t rlo = 0;
1384
1385 /* Bit 0 can only influence the low 64-bit result. */
1386 if (nn & 1) {
1387 rlo = mm;
1388 }
1389
1390 for (j = 1; j < 64; ++j) {
1391 uint64_t mask = -((nn >> j) & 1);
1392 rlo ^= (mm << j) & mask;
1393 rhi ^= (mm >> (64 - j)) & mask;
1394 }
1395 d[i] = rlo;
1396 d[i + 1] = rhi;
1397 }
1398 clear_tail(d, opr_sz, simd_maxsz(desc));
1399 }
1400
1401 /*
1402 * 8x8->16 polynomial multiply.
1403 *
1404 * The byte inputs are expanded to (or extracted from) half-words.
1405 * Note that neon and sve2 get the inputs from different positions.
1406 * This allows 4 bytes to be processed in parallel with uint64_t.
1407 */
1408
1409 static uint64_t expand_byte_to_half(uint64_t x)
1410 {
1411 return (x & 0x000000ff)
1412 | ((x & 0x0000ff00) << 8)
1413 | ((x & 0x00ff0000) << 16)
1414 | ((x & 0xff000000) << 24);
1415 }
1416
1417 static uint64_t pmull_h(uint64_t op1, uint64_t op2)
1418 {
1419 uint64_t result = 0;
1420 int i;
1421
1422 for (i = 0; i < 8; ++i) {
1423 uint64_t mask = (op1 & 0x0001000100010001ull) * 0xffff;
1424 result ^= op2 & mask;
1425 op1 >>= 1;
1426 op2 <<= 1;
1427 }
1428 return result;
1429 }
1430
1431 void HELPER(neon_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc)
1432 {
1433 int hi = simd_data(desc);
1434 uint64_t *d = vd, *n = vn, *m = vm;
1435 uint64_t nn = n[hi], mm = m[hi];
1436
1437 d[0] = pmull_h(expand_byte_to_half(nn), expand_byte_to_half(mm));
1438 nn >>= 32;
1439 mm >>= 32;
1440 d[1] = pmull_h(expand_byte_to_half(nn), expand_byte_to_half(mm));
1441
1442 clear_tail(d, 16, simd_maxsz(desc));
1443 }
1444
1445 #ifdef TARGET_AARCH64
1446 void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc)
1447 {
1448 int shift = simd_data(desc) * 8;
1449 intptr_t i, opr_sz = simd_oprsz(desc);
1450 uint64_t *d = vd, *n = vn, *m = vm;
1451
1452 for (i = 0; i < opr_sz / 8; ++i) {
1453 uint64_t nn = (n[i] >> shift) & 0x00ff00ff00ff00ffull;
1454 uint64_t mm = (m[i] >> shift) & 0x00ff00ff00ff00ffull;
1455
1456 d[i] = pmull_h(nn, mm);
1457 }
1458 }
1459 #endif
1460
1461 #define DO_CMP0(NAME, TYPE, OP) \
1462 void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \
1463 { \
1464 intptr_t i, opr_sz = simd_oprsz(desc); \
1465 for (i = 0; i < opr_sz; i += sizeof(TYPE)) { \
1466 TYPE nn = *(TYPE *)(vn + i); \
1467 *(TYPE *)(vd + i) = -(nn OP 0); \
1468 } \
1469 clear_tail(vd, opr_sz, simd_maxsz(desc)); \
1470 }
1471
1472 DO_CMP0(gvec_ceq0_b, int8_t, ==)
1473 DO_CMP0(gvec_clt0_b, int8_t, <)
1474 DO_CMP0(gvec_cle0_b, int8_t, <=)
1475 DO_CMP0(gvec_cgt0_b, int8_t, >)
1476 DO_CMP0(gvec_cge0_b, int8_t, >=)
1477
1478 DO_CMP0(gvec_ceq0_h, int16_t, ==)
1479 DO_CMP0(gvec_clt0_h, int16_t, <)
1480 DO_CMP0(gvec_cle0_h, int16_t, <=)
1481 DO_CMP0(gvec_cgt0_h, int16_t, >)
1482 DO_CMP0(gvec_cge0_h, int16_t, >=)
1483
1484 #undef DO_CMP0
1485
1486 #define DO_ABD(NAME, TYPE) \
1487 void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
1488 { \
1489 intptr_t i, opr_sz = simd_oprsz(desc); \
1490 TYPE *d = vd, *n = vn, *m = vm; \
1491 \
1492 for (i = 0; i < opr_sz / sizeof(TYPE); ++i) { \
1493 d[i] = n[i] < m[i] ? m[i] - n[i] : n[i] - m[i]; \
1494 } \
1495 clear_tail(d, opr_sz, simd_maxsz(desc)); \
1496 }
1497
1498 DO_ABD(gvec_sabd_b, int8_t)
1499 DO_ABD(gvec_sabd_h, int16_t)
1500 DO_ABD(gvec_sabd_s, int32_t)
1501 DO_ABD(gvec_sabd_d, int64_t)
1502
1503 DO_ABD(gvec_uabd_b, uint8_t)
1504 DO_ABD(gvec_uabd_h, uint16_t)
1505 DO_ABD(gvec_uabd_s, uint32_t)
1506 DO_ABD(gvec_uabd_d, uint64_t)
1507
1508 #undef DO_ABD
1509
1510 #define DO_ABA(NAME, TYPE) \
1511 void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
1512 { \
1513 intptr_t i, opr_sz = simd_oprsz(desc); \
1514 TYPE *d = vd, *n = vn, *m = vm; \
1515 \
1516 for (i = 0; i < opr_sz / sizeof(TYPE); ++i) { \
1517 d[i] += n[i] < m[i] ? m[i] - n[i] : n[i] - m[i]; \
1518 } \
1519 clear_tail(d, opr_sz, simd_maxsz(desc)); \
1520 }
1521
1522 DO_ABA(gvec_saba_b, int8_t)
1523 DO_ABA(gvec_saba_h, int16_t)
1524 DO_ABA(gvec_saba_s, int32_t)
1525 DO_ABA(gvec_saba_d, int64_t)
1526
1527 DO_ABA(gvec_uaba_b, uint8_t)
1528 DO_ABA(gvec_uaba_h, uint16_t)
1529 DO_ABA(gvec_uaba_s, uint32_t)
1530 DO_ABA(gvec_uaba_d, uint64_t)
1531
1532 #undef DO_ABA