target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16
[qemu.git] / target / arm / vfp_helper.c
1 /*
2 * ARM VFP floating-point operations
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/helper-proto.h"
23 #include "internals.h"
24 #ifdef CONFIG_TCG
25 #include "qemu/log.h"
26 #include "fpu/softfloat.h"
27 #endif
28
29 /* VFP support. We follow the convention used for VFP instructions:
30 Single precision routines have a "s" suffix, double precision a
31 "d" suffix. */
32
33 #ifdef CONFIG_TCG
34
35 /* Convert host exception flags to vfp form. */
36 static inline int vfp_exceptbits_from_host(int host_bits)
37 {
38 int target_bits = 0;
39
40 if (host_bits & float_flag_invalid) {
41 target_bits |= 1;
42 }
43 if (host_bits & float_flag_divbyzero) {
44 target_bits |= 2;
45 }
46 if (host_bits & float_flag_overflow) {
47 target_bits |= 4;
48 }
49 if (host_bits & (float_flag_underflow | float_flag_output_denormal)) {
50 target_bits |= 8;
51 }
52 if (host_bits & float_flag_inexact) {
53 target_bits |= 0x10;
54 }
55 if (host_bits & float_flag_input_denormal) {
56 target_bits |= 0x80;
57 }
58 return target_bits;
59 }
60
61 /* Convert vfp exception flags to target form. */
62 static inline int vfp_exceptbits_to_host(int target_bits)
63 {
64 int host_bits = 0;
65
66 if (target_bits & 1) {
67 host_bits |= float_flag_invalid;
68 }
69 if (target_bits & 2) {
70 host_bits |= float_flag_divbyzero;
71 }
72 if (target_bits & 4) {
73 host_bits |= float_flag_overflow;
74 }
75 if (target_bits & 8) {
76 host_bits |= float_flag_underflow;
77 }
78 if (target_bits & 0x10) {
79 host_bits |= float_flag_inexact;
80 }
81 if (target_bits & 0x80) {
82 host_bits |= float_flag_input_denormal;
83 }
84 return host_bits;
85 }
86
87 static uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
88 {
89 uint32_t i;
90
91 i = get_float_exception_flags(&env->vfp.fp_status);
92 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
93 /* FZ16 does not generate an input denormal exception. */
94 i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
95 & ~float_flag_input_denormal);
96 i |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16)
97 & ~float_flag_input_denormal);
98 return vfp_exceptbits_from_host(i);
99 }
100
101 static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
102 {
103 int i;
104 uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];
105
106 changed ^= val;
107 if (changed & (3 << 22)) {
108 i = (val >> 22) & 3;
109 switch (i) {
110 case FPROUNDING_TIEEVEN:
111 i = float_round_nearest_even;
112 break;
113 case FPROUNDING_POSINF:
114 i = float_round_up;
115 break;
116 case FPROUNDING_NEGINF:
117 i = float_round_down;
118 break;
119 case FPROUNDING_ZERO:
120 i = float_round_to_zero;
121 break;
122 }
123 set_float_rounding_mode(i, &env->vfp.fp_status);
124 set_float_rounding_mode(i, &env->vfp.fp_status_f16);
125 }
126 if (changed & FPCR_FZ16) {
127 bool ftz_enabled = val & FPCR_FZ16;
128 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
129 set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
130 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
131 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
132 }
133 if (changed & FPCR_FZ) {
134 bool ftz_enabled = val & FPCR_FZ;
135 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
136 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
137 }
138 if (changed & FPCR_DN) {
139 bool dnan_enabled = val & FPCR_DN;
140 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
141 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
142 }
143
144 /*
145 * The exception flags are ORed together when we read fpscr so we
146 * only need to preserve the current state in one of our
147 * float_status values.
148 */
149 i = vfp_exceptbits_to_host(val);
150 set_float_exception_flags(i, &env->vfp.fp_status);
151 set_float_exception_flags(0, &env->vfp.fp_status_f16);
152 set_float_exception_flags(0, &env->vfp.standard_fp_status);
153 set_float_exception_flags(0, &env->vfp.standard_fp_status_f16);
154 }
155
156 #else
157
158 static uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
159 {
160 return 0;
161 }
162
163 static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
164 {
165 }
166
167 #endif
168
169 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
170 {
171 uint32_t i, fpscr;
172
173 fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
174 | (env->vfp.vec_len << 16)
175 | (env->vfp.vec_stride << 20);
176
177 fpscr |= vfp_get_fpscr_from_host(env);
178
179 i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
180 fpscr |= i ? FPCR_QC : 0;
181
182 return fpscr;
183 }
184
185 uint32_t vfp_get_fpscr(CPUARMState *env)
186 {
187 return HELPER(vfp_get_fpscr)(env);
188 }
189
190 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
191 {
192 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
193 if (!cpu_isar_feature(any_fp16, env_archcpu(env))) {
194 val &= ~FPCR_FZ16;
195 }
196
197 vfp_set_fpscr_to_host(env, val);
198
199 if (!arm_feature(env, ARM_FEATURE_M)) {
200 /*
201 * Short-vector length and stride; on M-profile these bits
202 * are used for different purposes.
203 * We can't make this conditional be "if MVFR0.FPShVec != 0",
204 * because in v7A no-short-vector-support cores still had to
205 * allow Stride/Len to be written with the only effect that
206 * some insns are required to UNDEF if the guest sets them.
207 *
208 * TODO: if M-profile MVE implemented, set LTPSIZE.
209 */
210 env->vfp.vec_len = extract32(val, 16, 3);
211 env->vfp.vec_stride = extract32(val, 20, 2);
212 }
213
214 if (arm_feature(env, ARM_FEATURE_NEON)) {
215 /*
216 * The bit we set within fpscr_q is arbitrary; the register as a
217 * whole being zero/non-zero is what counts.
218 * TODO: M-profile MVE also has a QC bit.
219 */
220 env->vfp.qc[0] = val & FPCR_QC;
221 env->vfp.qc[1] = 0;
222 env->vfp.qc[2] = 0;
223 env->vfp.qc[3] = 0;
224 }
225
226 /*
227 * We don't implement trapped exception handling, so the
228 * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
229 *
230 * The exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in
231 * fp_status; QC, Len and Stride are stored separately earlier.
232 * Clear out all of those and the RES0 bits: only NZCV, AHP, DN,
233 * FZ, RMode and FZ16 are kept in vfp.xregs[FPSCR].
234 */
235 env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
236 }
237
238 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
239 {
240 HELPER(vfp_set_fpscr)(env, val);
241 }
242
243 #ifdef CONFIG_TCG
244
245 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
246
247 #define VFP_BINOP(name) \
248 dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, void *fpstp) \
249 { \
250 float_status *fpst = fpstp; \
251 return float16_ ## name(a, b, fpst); \
252 } \
253 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
254 { \
255 float_status *fpst = fpstp; \
256 return float32_ ## name(a, b, fpst); \
257 } \
258 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
259 { \
260 float_status *fpst = fpstp; \
261 return float64_ ## name(a, b, fpst); \
262 }
263 VFP_BINOP(add)
264 VFP_BINOP(sub)
265 VFP_BINOP(mul)
266 VFP_BINOP(div)
267 VFP_BINOP(min)
268 VFP_BINOP(max)
269 VFP_BINOP(minnum)
270 VFP_BINOP(maxnum)
271 #undef VFP_BINOP
272
273 dh_ctype_f16 VFP_HELPER(neg, h)(dh_ctype_f16 a)
274 {
275 return float16_chs(a);
276 }
277
278 float32 VFP_HELPER(neg, s)(float32 a)
279 {
280 return float32_chs(a);
281 }
282
283 float64 VFP_HELPER(neg, d)(float64 a)
284 {
285 return float64_chs(a);
286 }
287
288 dh_ctype_f16 VFP_HELPER(abs, h)(dh_ctype_f16 a)
289 {
290 return float16_abs(a);
291 }
292
293 float32 VFP_HELPER(abs, s)(float32 a)
294 {
295 return float32_abs(a);
296 }
297
298 float64 VFP_HELPER(abs, d)(float64 a)
299 {
300 return float64_abs(a);
301 }
302
303 dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, CPUARMState *env)
304 {
305 return float16_sqrt(a, &env->vfp.fp_status_f16);
306 }
307
308 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
309 {
310 return float32_sqrt(a, &env->vfp.fp_status);
311 }
312
313 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
314 {
315 return float64_sqrt(a, &env->vfp.fp_status);
316 }
317
318 static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp)
319 {
320 uint32_t flags;
321 switch (cmp) {
322 case float_relation_equal:
323 flags = 0x6;
324 break;
325 case float_relation_less:
326 flags = 0x8;
327 break;
328 case float_relation_greater:
329 flags = 0x2;
330 break;
331 case float_relation_unordered:
332 flags = 0x3;
333 break;
334 default:
335 g_assert_not_reached();
336 }
337 env->vfp.xregs[ARM_VFP_FPSCR] =
338 deposit32(env->vfp.xregs[ARM_VFP_FPSCR], 28, 4, flags);
339 }
340
341 /* XXX: check quiet/signaling case */
342 #define DO_VFP_cmp(P, FLOATTYPE, ARGTYPE, FPST) \
343 void VFP_HELPER(cmp, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
344 { \
345 softfloat_to_vfp_compare(env, \
346 FLOATTYPE ## _compare_quiet(a, b, &env->vfp.FPST)); \
347 } \
348 void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
349 { \
350 softfloat_to_vfp_compare(env, \
351 FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \
352 }
353 DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status_f16)
354 DO_VFP_cmp(s, float32, float32, fp_status)
355 DO_VFP_cmp(d, float64, float64, fp_status)
356 #undef DO_VFP_cmp
357
358 /* Integer to float and float to integer conversions */
359
360 #define CONV_ITOF(name, ftype, fsz, sign) \
361 ftype HELPER(name)(uint32_t x, void *fpstp) \
362 { \
363 float_status *fpst = fpstp; \
364 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
365 }
366
367 #define CONV_FTOI(name, ftype, fsz, sign, round) \
368 sign##int32_t HELPER(name)(ftype x, void *fpstp) \
369 { \
370 float_status *fpst = fpstp; \
371 if (float##fsz##_is_any_nan(x)) { \
372 float_raise(float_flag_invalid, fpst); \
373 return 0; \
374 } \
375 return float##fsz##_to_##sign##int32##round(x, fpst); \
376 }
377
378 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \
379 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
380 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
381 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
382
383 FLOAT_CONVS(si, h, uint32_t, 16, )
384 FLOAT_CONVS(si, s, float32, 32, )
385 FLOAT_CONVS(si, d, float64, 64, )
386 FLOAT_CONVS(ui, h, uint32_t, 16, u)
387 FLOAT_CONVS(ui, s, float32, 32, u)
388 FLOAT_CONVS(ui, d, float64, 64, u)
389
390 #undef CONV_ITOF
391 #undef CONV_FTOI
392 #undef FLOAT_CONVS
393
394 /* floating point conversion */
395 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
396 {
397 return float32_to_float64(x, &env->vfp.fp_status);
398 }
399
400 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
401 {
402 return float64_to_float32(x, &env->vfp.fp_status);
403 }
404
405 /*
406 * VFP3 fixed point conversion. The AArch32 versions of fix-to-float
407 * must always round-to-nearest; the AArch64 ones honour the FPSCR
408 * rounding mode. (For AArch32 Neon the standard-FPSCR is set to
409 * round-to-nearest so either helper will work.) AArch32 float-to-fix
410 * must round-to-zero.
411 */
412 #define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
413 ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
414 void *fpstp) \
415 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
416
417 #define VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \
418 ftype HELPER(vfp_##name##to##p##_round_to_nearest)(uint##isz##_t x, \
419 uint32_t shift, \
420 void *fpstp) \
421 { \
422 ftype ret; \
423 float_status *fpst = fpstp; \
424 FloatRoundMode oldmode = fpst->float_rounding_mode; \
425 fpst->float_rounding_mode = float_round_nearest_even; \
426 ret = itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); \
427 fpst->float_rounding_mode = oldmode; \
428 return ret; \
429 }
430
431 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \
432 uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \
433 void *fpst) \
434 { \
435 if (unlikely(float##fsz##_is_any_nan(x))) { \
436 float_raise(float_flag_invalid, fpst); \
437 return 0; \
438 } \
439 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \
440 }
441
442 #define VFP_CONV_FIX(name, p, fsz, ftype, isz, itype) \
443 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
444 VFP_CONV_FIX_FLOAT_ROUND(name, p, fsz, ftype, isz, itype) \
445 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
446 float_round_to_zero, _round_to_zero) \
447 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
448 get_float_rounding_mode(fpst), )
449
450 #define VFP_CONV_FIX_A64(name, p, fsz, ftype, isz, itype) \
451 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
452 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
453 get_float_rounding_mode(fpst), )
454
455 VFP_CONV_FIX(sh, d, 64, float64, 64, int16)
456 VFP_CONV_FIX(sl, d, 64, float64, 64, int32)
457 VFP_CONV_FIX_A64(sq, d, 64, float64, 64, int64)
458 VFP_CONV_FIX(uh, d, 64, float64, 64, uint16)
459 VFP_CONV_FIX(ul, d, 64, float64, 64, uint32)
460 VFP_CONV_FIX_A64(uq, d, 64, float64, 64, uint64)
461 VFP_CONV_FIX(sh, s, 32, float32, 32, int16)
462 VFP_CONV_FIX(sl, s, 32, float32, 32, int32)
463 VFP_CONV_FIX_A64(sq, s, 32, float32, 64, int64)
464 VFP_CONV_FIX(uh, s, 32, float32, 32, uint16)
465 VFP_CONV_FIX(ul, s, 32, float32, 32, uint32)
466 VFP_CONV_FIX_A64(uq, s, 32, float32, 64, uint64)
467 VFP_CONV_FIX(sh, h, 16, dh_ctype_f16, 32, int16)
468 VFP_CONV_FIX(sl, h, 16, dh_ctype_f16, 32, int32)
469 VFP_CONV_FIX_A64(sq, h, 16, dh_ctype_f16, 64, int64)
470 VFP_CONV_FIX(uh, h, 16, dh_ctype_f16, 32, uint16)
471 VFP_CONV_FIX(ul, h, 16, dh_ctype_f16, 32, uint32)
472 VFP_CONV_FIX_A64(uq, h, 16, dh_ctype_f16, 64, uint64)
473
474 #undef VFP_CONV_FIX
475 #undef VFP_CONV_FIX_FLOAT
476 #undef VFP_CONV_FLOAT_FIX_ROUND
477 #undef VFP_CONV_FIX_A64
478
479 /* Set the current fp rounding mode and return the old one.
480 * The argument is a softfloat float_round_ value.
481 */
482 uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
483 {
484 float_status *fp_status = fpstp;
485
486 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
487 set_float_rounding_mode(rmode, fp_status);
488
489 return prev_rmode;
490 }
491
492 /* Half precision conversions. */
493 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
494 {
495 /* Squash FZ16 to 0 for the duration of conversion. In this case,
496 * it would affect flushing input denormals.
497 */
498 float_status *fpst = fpstp;
499 bool save = get_flush_inputs_to_zero(fpst);
500 set_flush_inputs_to_zero(false, fpst);
501 float32 r = float16_to_float32(a, !ahp_mode, fpst);
502 set_flush_inputs_to_zero(save, fpst);
503 return r;
504 }
505
506 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
507 {
508 /* Squash FZ16 to 0 for the duration of conversion. In this case,
509 * it would affect flushing output denormals.
510 */
511 float_status *fpst = fpstp;
512 bool save = get_flush_to_zero(fpst);
513 set_flush_to_zero(false, fpst);
514 float16 r = float32_to_float16(a, !ahp_mode, fpst);
515 set_flush_to_zero(save, fpst);
516 return r;
517 }
518
519 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
520 {
521 /* Squash FZ16 to 0 for the duration of conversion. In this case,
522 * it would affect flushing input denormals.
523 */
524 float_status *fpst = fpstp;
525 bool save = get_flush_inputs_to_zero(fpst);
526 set_flush_inputs_to_zero(false, fpst);
527 float64 r = float16_to_float64(a, !ahp_mode, fpst);
528 set_flush_inputs_to_zero(save, fpst);
529 return r;
530 }
531
532 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
533 {
534 /* Squash FZ16 to 0 for the duration of conversion. In this case,
535 * it would affect flushing output denormals.
536 */
537 float_status *fpst = fpstp;
538 bool save = get_flush_to_zero(fpst);
539 set_flush_to_zero(false, fpst);
540 float16 r = float64_to_float16(a, !ahp_mode, fpst);
541 set_flush_to_zero(save, fpst);
542 return r;
543 }
544
545 /* NEON helpers. */
546
547 /* Constants 256 and 512 are used in some helpers; we avoid relying on
548 * int->float conversions at run-time. */
549 #define float64_256 make_float64(0x4070000000000000LL)
550 #define float64_512 make_float64(0x4080000000000000LL)
551 #define float16_maxnorm make_float16(0x7bff)
552 #define float32_maxnorm make_float32(0x7f7fffff)
553 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
554
555 /* Reciprocal functions
556 *
557 * The algorithm that must be used to calculate the estimate
558 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
559 */
560
561 /* See RecipEstimate()
562 *
563 * input is a 9 bit fixed point number
564 * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
565 * result range 256 .. 511 for a number from 1.0 to 511/256.
566 */
567
568 static int recip_estimate(int input)
569 {
570 int a, b, r;
571 assert(256 <= input && input < 512);
572 a = (input * 2) + 1;
573 b = (1 << 19) / a;
574 r = (b + 1) >> 1;
575 assert(256 <= r && r < 512);
576 return r;
577 }
578
579 /*
580 * Common wrapper to call recip_estimate
581 *
582 * The parameters are exponent and 64 bit fraction (without implicit
583 * bit) where the binary point is nominally at bit 52. Returns a
584 * float64 which can then be rounded to the appropriate size by the
585 * callee.
586 */
587
588 static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac)
589 {
590 uint32_t scaled, estimate;
591 uint64_t result_frac;
592 int result_exp;
593
594 /* Handle sub-normals */
595 if (*exp == 0) {
596 if (extract64(frac, 51, 1) == 0) {
597 *exp = -1;
598 frac <<= 2;
599 } else {
600 frac <<= 1;
601 }
602 }
603
604 /* scaled = UInt('1':fraction<51:44>) */
605 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
606 estimate = recip_estimate(scaled);
607
608 result_exp = exp_off - *exp;
609 result_frac = deposit64(0, 44, 8, estimate);
610 if (result_exp == 0) {
611 result_frac = deposit64(result_frac >> 1, 51, 1, 1);
612 } else if (result_exp == -1) {
613 result_frac = deposit64(result_frac >> 2, 50, 2, 1);
614 result_exp = 0;
615 }
616
617 *exp = result_exp;
618
619 return result_frac;
620 }
621
622 static bool round_to_inf(float_status *fpst, bool sign_bit)
623 {
624 switch (fpst->float_rounding_mode) {
625 case float_round_nearest_even: /* Round to Nearest */
626 return true;
627 case float_round_up: /* Round to +Inf */
628 return !sign_bit;
629 case float_round_down: /* Round to -Inf */
630 return sign_bit;
631 case float_round_to_zero: /* Round to Zero */
632 return false;
633 default:
634 g_assert_not_reached();
635 }
636 }
637
638 uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
639 {
640 float_status *fpst = fpstp;
641 float16 f16 = float16_squash_input_denormal(input, fpst);
642 uint32_t f16_val = float16_val(f16);
643 uint32_t f16_sign = float16_is_neg(f16);
644 int f16_exp = extract32(f16_val, 10, 5);
645 uint32_t f16_frac = extract32(f16_val, 0, 10);
646 uint64_t f64_frac;
647
648 if (float16_is_any_nan(f16)) {
649 float16 nan = f16;
650 if (float16_is_signaling_nan(f16, fpst)) {
651 float_raise(float_flag_invalid, fpst);
652 nan = float16_silence_nan(f16, fpst);
653 }
654 if (fpst->default_nan_mode) {
655 nan = float16_default_nan(fpst);
656 }
657 return nan;
658 } else if (float16_is_infinity(f16)) {
659 return float16_set_sign(float16_zero, float16_is_neg(f16));
660 } else if (float16_is_zero(f16)) {
661 float_raise(float_flag_divbyzero, fpst);
662 return float16_set_sign(float16_infinity, float16_is_neg(f16));
663 } else if (float16_abs(f16) < (1 << 8)) {
664 /* Abs(value) < 2.0^-16 */
665 float_raise(float_flag_overflow | float_flag_inexact, fpst);
666 if (round_to_inf(fpst, f16_sign)) {
667 return float16_set_sign(float16_infinity, f16_sign);
668 } else {
669 return float16_set_sign(float16_maxnorm, f16_sign);
670 }
671 } else if (f16_exp >= 29 && fpst->flush_to_zero) {
672 float_raise(float_flag_underflow, fpst);
673 return float16_set_sign(float16_zero, float16_is_neg(f16));
674 }
675
676 f64_frac = call_recip_estimate(&f16_exp, 29,
677 ((uint64_t) f16_frac) << (52 - 10));
678
679 /* result = sign : result_exp<4:0> : fraction<51:42> */
680 f16_val = deposit32(0, 15, 1, f16_sign);
681 f16_val = deposit32(f16_val, 10, 5, f16_exp);
682 f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10));
683 return make_float16(f16_val);
684 }
685
686 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
687 {
688 float_status *fpst = fpstp;
689 float32 f32 = float32_squash_input_denormal(input, fpst);
690 uint32_t f32_val = float32_val(f32);
691 bool f32_sign = float32_is_neg(f32);
692 int f32_exp = extract32(f32_val, 23, 8);
693 uint32_t f32_frac = extract32(f32_val, 0, 23);
694 uint64_t f64_frac;
695
696 if (float32_is_any_nan(f32)) {
697 float32 nan = f32;
698 if (float32_is_signaling_nan(f32, fpst)) {
699 float_raise(float_flag_invalid, fpst);
700 nan = float32_silence_nan(f32, fpst);
701 }
702 if (fpst->default_nan_mode) {
703 nan = float32_default_nan(fpst);
704 }
705 return nan;
706 } else if (float32_is_infinity(f32)) {
707 return float32_set_sign(float32_zero, float32_is_neg(f32));
708 } else if (float32_is_zero(f32)) {
709 float_raise(float_flag_divbyzero, fpst);
710 return float32_set_sign(float32_infinity, float32_is_neg(f32));
711 } else if (float32_abs(f32) < (1ULL << 21)) {
712 /* Abs(value) < 2.0^-128 */
713 float_raise(float_flag_overflow | float_flag_inexact, fpst);
714 if (round_to_inf(fpst, f32_sign)) {
715 return float32_set_sign(float32_infinity, f32_sign);
716 } else {
717 return float32_set_sign(float32_maxnorm, f32_sign);
718 }
719 } else if (f32_exp >= 253 && fpst->flush_to_zero) {
720 float_raise(float_flag_underflow, fpst);
721 return float32_set_sign(float32_zero, float32_is_neg(f32));
722 }
723
724 f64_frac = call_recip_estimate(&f32_exp, 253,
725 ((uint64_t) f32_frac) << (52 - 23));
726
727 /* result = sign : result_exp<7:0> : fraction<51:29> */
728 f32_val = deposit32(0, 31, 1, f32_sign);
729 f32_val = deposit32(f32_val, 23, 8, f32_exp);
730 f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23));
731 return make_float32(f32_val);
732 }
733
734 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
735 {
736 float_status *fpst = fpstp;
737 float64 f64 = float64_squash_input_denormal(input, fpst);
738 uint64_t f64_val = float64_val(f64);
739 bool f64_sign = float64_is_neg(f64);
740 int f64_exp = extract64(f64_val, 52, 11);
741 uint64_t f64_frac = extract64(f64_val, 0, 52);
742
743 /* Deal with any special cases */
744 if (float64_is_any_nan(f64)) {
745 float64 nan = f64;
746 if (float64_is_signaling_nan(f64, fpst)) {
747 float_raise(float_flag_invalid, fpst);
748 nan = float64_silence_nan(f64, fpst);
749 }
750 if (fpst->default_nan_mode) {
751 nan = float64_default_nan(fpst);
752 }
753 return nan;
754 } else if (float64_is_infinity(f64)) {
755 return float64_set_sign(float64_zero, float64_is_neg(f64));
756 } else if (float64_is_zero(f64)) {
757 float_raise(float_flag_divbyzero, fpst);
758 return float64_set_sign(float64_infinity, float64_is_neg(f64));
759 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
760 /* Abs(value) < 2.0^-1024 */
761 float_raise(float_flag_overflow | float_flag_inexact, fpst);
762 if (round_to_inf(fpst, f64_sign)) {
763 return float64_set_sign(float64_infinity, f64_sign);
764 } else {
765 return float64_set_sign(float64_maxnorm, f64_sign);
766 }
767 } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
768 float_raise(float_flag_underflow, fpst);
769 return float64_set_sign(float64_zero, float64_is_neg(f64));
770 }
771
772 f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac);
773
774 /* result = sign : result_exp<10:0> : fraction<51:0>; */
775 f64_val = deposit64(0, 63, 1, f64_sign);
776 f64_val = deposit64(f64_val, 52, 11, f64_exp);
777 f64_val = deposit64(f64_val, 0, 52, f64_frac);
778 return make_float64(f64_val);
779 }
780
781 /* The algorithm that must be used to calculate the estimate
782 * is specified by the ARM ARM.
783 */
784
785 static int do_recip_sqrt_estimate(int a)
786 {
787 int b, estimate;
788
789 assert(128 <= a && a < 512);
790 if (a < 256) {
791 a = a * 2 + 1;
792 } else {
793 a = (a >> 1) << 1;
794 a = (a + 1) * 2;
795 }
796 b = 512;
797 while (a * (b + 1) * (b + 1) < (1 << 28)) {
798 b += 1;
799 }
800 estimate = (b + 1) / 2;
801 assert(256 <= estimate && estimate < 512);
802
803 return estimate;
804 }
805
806
807 static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
808 {
809 int estimate;
810 uint32_t scaled;
811
812 if (*exp == 0) {
813 while (extract64(frac, 51, 1) == 0) {
814 frac = frac << 1;
815 *exp -= 1;
816 }
817 frac = extract64(frac, 0, 51) << 1;
818 }
819
820 if (*exp & 1) {
821 /* scaled = UInt('01':fraction<51:45>) */
822 scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7));
823 } else {
824 /* scaled = UInt('1':fraction<51:44>) */
825 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
826 }
827 estimate = do_recip_sqrt_estimate(scaled);
828
829 *exp = (exp_off - *exp) / 2;
830 return extract64(estimate, 0, 8) << 44;
831 }
832
833 uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
834 {
835 float_status *s = fpstp;
836 float16 f16 = float16_squash_input_denormal(input, s);
837 uint16_t val = float16_val(f16);
838 bool f16_sign = float16_is_neg(f16);
839 int f16_exp = extract32(val, 10, 5);
840 uint16_t f16_frac = extract32(val, 0, 10);
841 uint64_t f64_frac;
842
843 if (float16_is_any_nan(f16)) {
844 float16 nan = f16;
845 if (float16_is_signaling_nan(f16, s)) {
846 float_raise(float_flag_invalid, s);
847 nan = float16_silence_nan(f16, s);
848 }
849 if (s->default_nan_mode) {
850 nan = float16_default_nan(s);
851 }
852 return nan;
853 } else if (float16_is_zero(f16)) {
854 float_raise(float_flag_divbyzero, s);
855 return float16_set_sign(float16_infinity, f16_sign);
856 } else if (f16_sign) {
857 float_raise(float_flag_invalid, s);
858 return float16_default_nan(s);
859 } else if (float16_is_infinity(f16)) {
860 return float16_zero;
861 }
862
863 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
864 * preserving the parity of the exponent. */
865
866 f64_frac = ((uint64_t) f16_frac) << (52 - 10);
867
868 f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac);
869
870 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
871 val = deposit32(0, 15, 1, f16_sign);
872 val = deposit32(val, 10, 5, f16_exp);
873 val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8));
874 return make_float16(val);
875 }
876
877 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
878 {
879 float_status *s = fpstp;
880 float32 f32 = float32_squash_input_denormal(input, s);
881 uint32_t val = float32_val(f32);
882 uint32_t f32_sign = float32_is_neg(f32);
883 int f32_exp = extract32(val, 23, 8);
884 uint32_t f32_frac = extract32(val, 0, 23);
885 uint64_t f64_frac;
886
887 if (float32_is_any_nan(f32)) {
888 float32 nan = f32;
889 if (float32_is_signaling_nan(f32, s)) {
890 float_raise(float_flag_invalid, s);
891 nan = float32_silence_nan(f32, s);
892 }
893 if (s->default_nan_mode) {
894 nan = float32_default_nan(s);
895 }
896 return nan;
897 } else if (float32_is_zero(f32)) {
898 float_raise(float_flag_divbyzero, s);
899 return float32_set_sign(float32_infinity, float32_is_neg(f32));
900 } else if (float32_is_neg(f32)) {
901 float_raise(float_flag_invalid, s);
902 return float32_default_nan(s);
903 } else if (float32_is_infinity(f32)) {
904 return float32_zero;
905 }
906
907 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
908 * preserving the parity of the exponent. */
909
910 f64_frac = ((uint64_t) f32_frac) << 29;
911
912 f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac);
913
914 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
915 val = deposit32(0, 31, 1, f32_sign);
916 val = deposit32(val, 23, 8, f32_exp);
917 val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8));
918 return make_float32(val);
919 }
920
921 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
922 {
923 float_status *s = fpstp;
924 float64 f64 = float64_squash_input_denormal(input, s);
925 uint64_t val = float64_val(f64);
926 bool f64_sign = float64_is_neg(f64);
927 int f64_exp = extract64(val, 52, 11);
928 uint64_t f64_frac = extract64(val, 0, 52);
929
930 if (float64_is_any_nan(f64)) {
931 float64 nan = f64;
932 if (float64_is_signaling_nan(f64, s)) {
933 float_raise(float_flag_invalid, s);
934 nan = float64_silence_nan(f64, s);
935 }
936 if (s->default_nan_mode) {
937 nan = float64_default_nan(s);
938 }
939 return nan;
940 } else if (float64_is_zero(f64)) {
941 float_raise(float_flag_divbyzero, s);
942 return float64_set_sign(float64_infinity, float64_is_neg(f64));
943 } else if (float64_is_neg(f64)) {
944 float_raise(float_flag_invalid, s);
945 return float64_default_nan(s);
946 } else if (float64_is_infinity(f64)) {
947 return float64_zero;
948 }
949
950 f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac);
951
952 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
953 val = deposit64(0, 61, 1, f64_sign);
954 val = deposit64(val, 52, 11, f64_exp);
955 val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8));
956 return make_float64(val);
957 }
958
959 uint32_t HELPER(recpe_u32)(uint32_t a)
960 {
961 int input, estimate;
962
963 if ((a & 0x80000000) == 0) {
964 return 0xffffffff;
965 }
966
967 input = extract32(a, 23, 9);
968 estimate = recip_estimate(input);
969
970 return deposit32(0, (32 - 9), 9, estimate);
971 }
972
973 uint32_t HELPER(rsqrte_u32)(uint32_t a)
974 {
975 int estimate;
976
977 if ((a & 0xc0000000) == 0) {
978 return 0xffffffff;
979 }
980
981 estimate = do_recip_sqrt_estimate(extract32(a, 23, 9));
982
983 return deposit32(0, 23, 9, estimate);
984 }
985
986 /* VFPv4 fused multiply-accumulate */
987 dh_ctype_f16 VFP_HELPER(muladd, h)(dh_ctype_f16 a, dh_ctype_f16 b,
988 dh_ctype_f16 c, void *fpstp)
989 {
990 float_status *fpst = fpstp;
991 return float16_muladd(a, b, c, 0, fpst);
992 }
993
994 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
995 {
996 float_status *fpst = fpstp;
997 return float32_muladd(a, b, c, 0, fpst);
998 }
999
1000 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
1001 {
1002 float_status *fpst = fpstp;
1003 return float64_muladd(a, b, c, 0, fpst);
1004 }
1005
1006 /* ARMv8 round to integral */
1007 dh_ctype_f16 HELPER(rinth_exact)(dh_ctype_f16 x, void *fp_status)
1008 {
1009 return float16_round_to_int(x, fp_status);
1010 }
1011
1012 float32 HELPER(rints_exact)(float32 x, void *fp_status)
1013 {
1014 return float32_round_to_int(x, fp_status);
1015 }
1016
1017 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
1018 {
1019 return float64_round_to_int(x, fp_status);
1020 }
1021
1022 dh_ctype_f16 HELPER(rinth)(dh_ctype_f16 x, void *fp_status)
1023 {
1024 int old_flags = get_float_exception_flags(fp_status), new_flags;
1025 float16 ret;
1026
1027 ret = float16_round_to_int(x, fp_status);
1028
1029 /* Suppress any inexact exceptions the conversion produced */
1030 if (!(old_flags & float_flag_inexact)) {
1031 new_flags = get_float_exception_flags(fp_status);
1032 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
1033 }
1034
1035 return ret;
1036 }
1037
1038 float32 HELPER(rints)(float32 x, void *fp_status)
1039 {
1040 int old_flags = get_float_exception_flags(fp_status), new_flags;
1041 float32 ret;
1042
1043 ret = float32_round_to_int(x, fp_status);
1044
1045 /* Suppress any inexact exceptions the conversion produced */
1046 if (!(old_flags & float_flag_inexact)) {
1047 new_flags = get_float_exception_flags(fp_status);
1048 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
1049 }
1050
1051 return ret;
1052 }
1053
1054 float64 HELPER(rintd)(float64 x, void *fp_status)
1055 {
1056 int old_flags = get_float_exception_flags(fp_status), new_flags;
1057 float64 ret;
1058
1059 ret = float64_round_to_int(x, fp_status);
1060
1061 new_flags = get_float_exception_flags(fp_status);
1062
1063 /* Suppress any inexact exceptions the conversion produced */
1064 if (!(old_flags & float_flag_inexact)) {
1065 new_flags = get_float_exception_flags(fp_status);
1066 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
1067 }
1068
1069 return ret;
1070 }
1071
1072 /* Convert ARM rounding mode to softfloat */
1073 int arm_rmode_to_sf(int rmode)
1074 {
1075 switch (rmode) {
1076 case FPROUNDING_TIEAWAY:
1077 rmode = float_round_ties_away;
1078 break;
1079 case FPROUNDING_ODD:
1080 /* FIXME: add support for TIEAWAY and ODD */
1081 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
1082 rmode);
1083 /* fall through for now */
1084 case FPROUNDING_TIEEVEN:
1085 default:
1086 rmode = float_round_nearest_even;
1087 break;
1088 case FPROUNDING_POSINF:
1089 rmode = float_round_up;
1090 break;
1091 case FPROUNDING_NEGINF:
1092 rmode = float_round_down;
1093 break;
1094 case FPROUNDING_ZERO:
1095 rmode = float_round_to_zero;
1096 break;
1097 }
1098 return rmode;
1099 }
1100
1101 /*
1102 * Implement float64 to int32_t conversion without saturation;
1103 * the result is supplied modulo 2^32.
1104 */
1105 uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus)
1106 {
1107 float_status *status = vstatus;
1108 uint32_t exp, sign;
1109 uint64_t frac;
1110 uint32_t inexact = 1; /* !Z */
1111
1112 sign = extract64(value, 63, 1);
1113 exp = extract64(value, 52, 11);
1114 frac = extract64(value, 0, 52);
1115
1116 if (exp == 0) {
1117 /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */
1118 inexact = sign;
1119 if (frac != 0) {
1120 if (status->flush_inputs_to_zero) {
1121 float_raise(float_flag_input_denormal, status);
1122 } else {
1123 float_raise(float_flag_inexact, status);
1124 inexact = 1;
1125 }
1126 }
1127 frac = 0;
1128 } else if (exp == 0x7ff) {
1129 /* This operation raises Invalid for both NaN and overflow (Inf). */
1130 float_raise(float_flag_invalid, status);
1131 frac = 0;
1132 } else {
1133 int true_exp = exp - 1023;
1134 int shift = true_exp - 52;
1135
1136 /* Restore implicit bit. */
1137 frac |= 1ull << 52;
1138
1139 /* Shift the fraction into place. */
1140 if (shift >= 0) {
1141 /* The number is so large we must shift the fraction left. */
1142 if (shift >= 64) {
1143 /* The fraction is shifted out entirely. */
1144 frac = 0;
1145 } else {
1146 frac <<= shift;
1147 }
1148 } else if (shift > -64) {
1149 /* Normal case -- shift right and notice if bits shift out. */
1150 inexact = (frac << (64 + shift)) != 0;
1151 frac >>= -shift;
1152 } else {
1153 /* The fraction is shifted out entirely. */
1154 frac = 0;
1155 }
1156
1157 /* Notice overflow or inexact exceptions. */
1158 if (true_exp > 31 || frac > (sign ? 0x80000000ull : 0x7fffffff)) {
1159 /* Overflow, for which this operation raises invalid. */
1160 float_raise(float_flag_invalid, status);
1161 inexact = 1;
1162 } else if (inexact) {
1163 float_raise(float_flag_inexact, status);
1164 }
1165
1166 /* Honor the sign. */
1167 if (sign) {
1168 frac = -frac;
1169 }
1170 }
1171
1172 /* Pack the result and the env->ZF representation of Z together. */
1173 return deposit64(frac, 32, 32, inexact);
1174 }
1175
1176 uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env)
1177 {
1178 uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status);
1179 uint32_t result = pair;
1180 uint32_t z = (pair >> 32) == 0;
1181
1182 /* Store Z, clear NCV, in FPSCR.NZCV. */
1183 env->vfp.xregs[ARM_VFP_FPSCR]
1184 = (env->vfp.xregs[ARM_VFP_FPSCR] & ~CPSR_NZCV) | (z * CPSR_Z);
1185
1186 return result;
1187 }
1188
1189 /* Round a float32 to an integer that fits in int32_t or int64_t. */
1190 static float32 frint_s(float32 f, float_status *fpst, int intsize)
1191 {
1192 int old_flags = get_float_exception_flags(fpst);
1193 uint32_t exp = extract32(f, 23, 8);
1194
1195 if (unlikely(exp == 0xff)) {
1196 /* NaN or Inf. */
1197 goto overflow;
1198 }
1199
1200 /* Round and re-extract the exponent. */
1201 f = float32_round_to_int(f, fpst);
1202 exp = extract32(f, 23, 8);
1203
1204 /* Validate the range of the result. */
1205 if (exp < 126 + intsize) {
1206 /* abs(F) <= INT{N}_MAX */
1207 return f;
1208 }
1209 if (exp == 126 + intsize) {
1210 uint32_t sign = extract32(f, 31, 1);
1211 uint32_t frac = extract32(f, 0, 23);
1212 if (sign && frac == 0) {
1213 /* F == INT{N}_MIN */
1214 return f;
1215 }
1216 }
1217
1218 overflow:
1219 /*
1220 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1221 * inexact exception float32_round_to_int may have raised.
1222 */
1223 set_float_exception_flags(old_flags | float_flag_invalid, fpst);
1224 return (0x100u + 126u + intsize) << 23;
1225 }
1226
1227 float32 HELPER(frint32_s)(float32 f, void *fpst)
1228 {
1229 return frint_s(f, fpst, 32);
1230 }
1231
1232 float32 HELPER(frint64_s)(float32 f, void *fpst)
1233 {
1234 return frint_s(f, fpst, 64);
1235 }
1236
1237 /* Round a float64 to an integer that fits in int32_t or int64_t. */
1238 static float64 frint_d(float64 f, float_status *fpst, int intsize)
1239 {
1240 int old_flags = get_float_exception_flags(fpst);
1241 uint32_t exp = extract64(f, 52, 11);
1242
1243 if (unlikely(exp == 0x7ff)) {
1244 /* NaN or Inf. */
1245 goto overflow;
1246 }
1247
1248 /* Round and re-extract the exponent. */
1249 f = float64_round_to_int(f, fpst);
1250 exp = extract64(f, 52, 11);
1251
1252 /* Validate the range of the result. */
1253 if (exp < 1022 + intsize) {
1254 /* abs(F) <= INT{N}_MAX */
1255 return f;
1256 }
1257 if (exp == 1022 + intsize) {
1258 uint64_t sign = extract64(f, 63, 1);
1259 uint64_t frac = extract64(f, 0, 52);
1260 if (sign && frac == 0) {
1261 /* F == INT{N}_MIN */
1262 return f;
1263 }
1264 }
1265
1266 overflow:
1267 /*
1268 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1269 * inexact exception float64_round_to_int may have raised.
1270 */
1271 set_float_exception_flags(old_flags | float_flag_invalid, fpst);
1272 return (uint64_t)(0x800 + 1022 + intsize) << 52;
1273 }
1274
1275 float64 HELPER(frint32_d)(float64 f, void *fpst)
1276 {
1277 return frint_d(f, fpst, 32);
1278 }
1279
1280 float64 HELPER(frint64_d)(float64 f, void *fpst)
1281 {
1282 return frint_d(f, fpst, 64);
1283 }
1284
1285 void HELPER(check_hcr_el2_trap)(CPUARMState *env, uint32_t rt, uint32_t reg)
1286 {
1287 uint32_t syndrome;
1288
1289 switch (reg) {
1290 case ARM_VFP_MVFR0:
1291 case ARM_VFP_MVFR1:
1292 case ARM_VFP_MVFR2:
1293 if (!(arm_hcr_el2_eff(env) & HCR_TID3)) {
1294 return;
1295 }
1296 break;
1297 case ARM_VFP_FPSID:
1298 if (!(arm_hcr_el2_eff(env) & HCR_TID0)) {
1299 return;
1300 }
1301 break;
1302 default:
1303 g_assert_not_reached();
1304 }
1305
1306 syndrome = ((EC_FPIDTRAP << ARM_EL_EC_SHIFT)
1307 | ARM_EL_IL
1308 | (1 << 24) | (0xe << 20) | (7 << 14)
1309 | (reg << 10) | (rt << 5) | 1);
1310
1311 raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);
1312 }
1313
1314 #endif