target/arm: Make VFP_CONV_FIX macros take separate float type and float size
[qemu.git] / target / arm / vfp_helper.c
1 /*
2 * ARM VFP floating-point operations
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/helper-proto.h"
23 #include "internals.h"
24 #ifdef CONFIG_TCG
25 #include "qemu/log.h"
26 #include "fpu/softfloat.h"
27 #endif
28
29 /* VFP support. We follow the convention used for VFP instructions:
30 Single precision routines have a "s" suffix, double precision a
31 "d" suffix. */
32
33 #ifdef CONFIG_TCG
34
35 /* Convert host exception flags to vfp form. */
36 static inline int vfp_exceptbits_from_host(int host_bits)
37 {
38 int target_bits = 0;
39
40 if (host_bits & float_flag_invalid) {
41 target_bits |= 1;
42 }
43 if (host_bits & float_flag_divbyzero) {
44 target_bits |= 2;
45 }
46 if (host_bits & float_flag_overflow) {
47 target_bits |= 4;
48 }
49 if (host_bits & (float_flag_underflow | float_flag_output_denormal)) {
50 target_bits |= 8;
51 }
52 if (host_bits & float_flag_inexact) {
53 target_bits |= 0x10;
54 }
55 if (host_bits & float_flag_input_denormal) {
56 target_bits |= 0x80;
57 }
58 return target_bits;
59 }
60
61 /* Convert vfp exception flags to target form. */
62 static inline int vfp_exceptbits_to_host(int target_bits)
63 {
64 int host_bits = 0;
65
66 if (target_bits & 1) {
67 host_bits |= float_flag_invalid;
68 }
69 if (target_bits & 2) {
70 host_bits |= float_flag_divbyzero;
71 }
72 if (target_bits & 4) {
73 host_bits |= float_flag_overflow;
74 }
75 if (target_bits & 8) {
76 host_bits |= float_flag_underflow;
77 }
78 if (target_bits & 0x10) {
79 host_bits |= float_flag_inexact;
80 }
81 if (target_bits & 0x80) {
82 host_bits |= float_flag_input_denormal;
83 }
84 return host_bits;
85 }
86
87 static uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
88 {
89 uint32_t i;
90
91 i = get_float_exception_flags(&env->vfp.fp_status);
92 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
93 /* FZ16 does not generate an input denormal exception. */
94 i |= (get_float_exception_flags(&env->vfp.fp_status_f16)
95 & ~float_flag_input_denormal);
96 i |= (get_float_exception_flags(&env->vfp.standard_fp_status_f16)
97 & ~float_flag_input_denormal);
98 return vfp_exceptbits_from_host(i);
99 }
100
101 static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
102 {
103 int i;
104 uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR];
105
106 changed ^= val;
107 if (changed & (3 << 22)) {
108 i = (val >> 22) & 3;
109 switch (i) {
110 case FPROUNDING_TIEEVEN:
111 i = float_round_nearest_even;
112 break;
113 case FPROUNDING_POSINF:
114 i = float_round_up;
115 break;
116 case FPROUNDING_NEGINF:
117 i = float_round_down;
118 break;
119 case FPROUNDING_ZERO:
120 i = float_round_to_zero;
121 break;
122 }
123 set_float_rounding_mode(i, &env->vfp.fp_status);
124 set_float_rounding_mode(i, &env->vfp.fp_status_f16);
125 }
126 if (changed & FPCR_FZ16) {
127 bool ftz_enabled = val & FPCR_FZ16;
128 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
129 set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
130 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16);
131 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16);
132 }
133 if (changed & FPCR_FZ) {
134 bool ftz_enabled = val & FPCR_FZ;
135 set_flush_to_zero(ftz_enabled, &env->vfp.fp_status);
136 set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status);
137 }
138 if (changed & FPCR_DN) {
139 bool dnan_enabled = val & FPCR_DN;
140 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status);
141 set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16);
142 }
143
144 /*
145 * The exception flags are ORed together when we read fpscr so we
146 * only need to preserve the current state in one of our
147 * float_status values.
148 */
149 i = vfp_exceptbits_to_host(val);
150 set_float_exception_flags(i, &env->vfp.fp_status);
151 set_float_exception_flags(0, &env->vfp.fp_status_f16);
152 set_float_exception_flags(0, &env->vfp.standard_fp_status);
153 set_float_exception_flags(0, &env->vfp.standard_fp_status_f16);
154 }
155
156 #else
157
158 static uint32_t vfp_get_fpscr_from_host(CPUARMState *env)
159 {
160 return 0;
161 }
162
163 static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val)
164 {
165 }
166
167 #endif
168
169 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
170 {
171 uint32_t i, fpscr;
172
173 fpscr = env->vfp.xregs[ARM_VFP_FPSCR]
174 | (env->vfp.vec_len << 16)
175 | (env->vfp.vec_stride << 20);
176
177 fpscr |= vfp_get_fpscr_from_host(env);
178
179 i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3];
180 fpscr |= i ? FPCR_QC : 0;
181
182 return fpscr;
183 }
184
185 uint32_t vfp_get_fpscr(CPUARMState *env)
186 {
187 return HELPER(vfp_get_fpscr)(env);
188 }
189
190 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
191 {
192 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
193 if (!cpu_isar_feature(any_fp16, env_archcpu(env))) {
194 val &= ~FPCR_FZ16;
195 }
196
197 if (arm_feature(env, ARM_FEATURE_M)) {
198 /*
199 * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
200 * and also for the trapped-exception-handling bits IxE.
201 */
202 val &= 0xf7c0009f;
203 }
204
205 vfp_set_fpscr_to_host(env, val);
206
207 /*
208 * We don't implement trapped exception handling, so the
209 * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
210 *
211 * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
212 * (which are stored in fp_status), and the other RES0 bits
213 * in between, then we clear all of the low 16 bits.
214 */
215 env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000;
216 env->vfp.vec_len = (val >> 16) & 7;
217 env->vfp.vec_stride = (val >> 20) & 3;
218
219 /*
220 * The bit we set within fpscr_q is arbitrary; the register as a
221 * whole being zero/non-zero is what counts.
222 */
223 env->vfp.qc[0] = val & FPCR_QC;
224 env->vfp.qc[1] = 0;
225 env->vfp.qc[2] = 0;
226 env->vfp.qc[3] = 0;
227 }
228
229 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
230 {
231 HELPER(vfp_set_fpscr)(env, val);
232 }
233
234 #ifdef CONFIG_TCG
235
236 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
237
238 #define VFP_BINOP(name) \
239 dh_ctype_f16 VFP_HELPER(name, h)(dh_ctype_f16 a, dh_ctype_f16 b, void *fpstp) \
240 { \
241 float_status *fpst = fpstp; \
242 return float16_ ## name(a, b, fpst); \
243 } \
244 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
245 { \
246 float_status *fpst = fpstp; \
247 return float32_ ## name(a, b, fpst); \
248 } \
249 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
250 { \
251 float_status *fpst = fpstp; \
252 return float64_ ## name(a, b, fpst); \
253 }
254 VFP_BINOP(add)
255 VFP_BINOP(sub)
256 VFP_BINOP(mul)
257 VFP_BINOP(div)
258 VFP_BINOP(min)
259 VFP_BINOP(max)
260 VFP_BINOP(minnum)
261 VFP_BINOP(maxnum)
262 #undef VFP_BINOP
263
264 dh_ctype_f16 VFP_HELPER(neg, h)(dh_ctype_f16 a)
265 {
266 return float16_chs(a);
267 }
268
269 float32 VFP_HELPER(neg, s)(float32 a)
270 {
271 return float32_chs(a);
272 }
273
274 float64 VFP_HELPER(neg, d)(float64 a)
275 {
276 return float64_chs(a);
277 }
278
279 dh_ctype_f16 VFP_HELPER(abs, h)(dh_ctype_f16 a)
280 {
281 return float16_abs(a);
282 }
283
284 float32 VFP_HELPER(abs, s)(float32 a)
285 {
286 return float32_abs(a);
287 }
288
289 float64 VFP_HELPER(abs, d)(float64 a)
290 {
291 return float64_abs(a);
292 }
293
294 dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, CPUARMState *env)
295 {
296 return float16_sqrt(a, &env->vfp.fp_status_f16);
297 }
298
299 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
300 {
301 return float32_sqrt(a, &env->vfp.fp_status);
302 }
303
304 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
305 {
306 return float64_sqrt(a, &env->vfp.fp_status);
307 }
308
309 static void softfloat_to_vfp_compare(CPUARMState *env, FloatRelation cmp)
310 {
311 uint32_t flags;
312 switch (cmp) {
313 case float_relation_equal:
314 flags = 0x6;
315 break;
316 case float_relation_less:
317 flags = 0x8;
318 break;
319 case float_relation_greater:
320 flags = 0x2;
321 break;
322 case float_relation_unordered:
323 flags = 0x3;
324 break;
325 default:
326 g_assert_not_reached();
327 }
328 env->vfp.xregs[ARM_VFP_FPSCR] =
329 deposit32(env->vfp.xregs[ARM_VFP_FPSCR], 28, 4, flags);
330 }
331
332 /* XXX: check quiet/signaling case */
333 #define DO_VFP_cmp(P, FLOATTYPE, ARGTYPE, FPST) \
334 void VFP_HELPER(cmp, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
335 { \
336 softfloat_to_vfp_compare(env, \
337 FLOATTYPE ## _compare_quiet(a, b, &env->vfp.FPST)); \
338 } \
339 void VFP_HELPER(cmpe, P)(ARGTYPE a, ARGTYPE b, CPUARMState *env) \
340 { \
341 softfloat_to_vfp_compare(env, \
342 FLOATTYPE ## _compare(a, b, &env->vfp.FPST)); \
343 }
344 DO_VFP_cmp(h, float16, dh_ctype_f16, fp_status_f16)
345 DO_VFP_cmp(s, float32, float32, fp_status)
346 DO_VFP_cmp(d, float64, float64, fp_status)
347 #undef DO_VFP_cmp
348
349 /* Integer to float and float to integer conversions */
350
351 #define CONV_ITOF(name, ftype, fsz, sign) \
352 ftype HELPER(name)(uint32_t x, void *fpstp) \
353 { \
354 float_status *fpst = fpstp; \
355 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
356 }
357
358 #define CONV_FTOI(name, ftype, fsz, sign, round) \
359 sign##int32_t HELPER(name)(ftype x, void *fpstp) \
360 { \
361 float_status *fpst = fpstp; \
362 if (float##fsz##_is_any_nan(x)) { \
363 float_raise(float_flag_invalid, fpst); \
364 return 0; \
365 } \
366 return float##fsz##_to_##sign##int32##round(x, fpst); \
367 }
368
369 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \
370 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
371 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
372 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
373
374 FLOAT_CONVS(si, h, uint32_t, 16, )
375 FLOAT_CONVS(si, s, float32, 32, )
376 FLOAT_CONVS(si, d, float64, 64, )
377 FLOAT_CONVS(ui, h, uint32_t, 16, u)
378 FLOAT_CONVS(ui, s, float32, 32, u)
379 FLOAT_CONVS(ui, d, float64, 64, u)
380
381 #undef CONV_ITOF
382 #undef CONV_FTOI
383 #undef FLOAT_CONVS
384
385 /* floating point conversion */
386 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
387 {
388 return float32_to_float64(x, &env->vfp.fp_status);
389 }
390
391 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
392 {
393 return float64_to_float32(x, &env->vfp.fp_status);
394 }
395
396 /* VFP3 fixed point conversion. */
397 #define VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
398 ftype HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
399 void *fpstp) \
400 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
401
402 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, ROUND, suff) \
403 uint##isz##_t HELPER(vfp_to##name##p##suff)(ftype x, uint32_t shift, \
404 void *fpst) \
405 { \
406 if (unlikely(float##fsz##_is_any_nan(x))) { \
407 float_raise(float_flag_invalid, fpst); \
408 return 0; \
409 } \
410 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \
411 }
412
413 #define VFP_CONV_FIX(name, p, fsz, ftype, isz, itype) \
414 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
415 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
416 float_round_to_zero, _round_to_zero) \
417 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
418 get_float_rounding_mode(fpst), )
419
420 #define VFP_CONV_FIX_A64(name, p, fsz, ftype, isz, itype) \
421 VFP_CONV_FIX_FLOAT(name, p, fsz, ftype, isz, itype) \
422 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, ftype, isz, itype, \
423 get_float_rounding_mode(fpst), )
424
425 VFP_CONV_FIX(sh, d, 64, float64, 64, int16)
426 VFP_CONV_FIX(sl, d, 64, float64, 64, int32)
427 VFP_CONV_FIX_A64(sq, d, 64, float64, 64, int64)
428 VFP_CONV_FIX(uh, d, 64, float64, 64, uint16)
429 VFP_CONV_FIX(ul, d, 64, float64, 64, uint32)
430 VFP_CONV_FIX_A64(uq, d, 64, float64, 64, uint64)
431 VFP_CONV_FIX(sh, s, 32, float32, 32, int16)
432 VFP_CONV_FIX(sl, s, 32, float32, 32, int32)
433 VFP_CONV_FIX_A64(sq, s, 32, float32, 64, int64)
434 VFP_CONV_FIX(uh, s, 32, float32, 32, uint16)
435 VFP_CONV_FIX(ul, s, 32, float32, 32, uint32)
436 VFP_CONV_FIX_A64(uq, s, 32, float32, 64, uint64)
437
438 #undef VFP_CONV_FIX
439 #undef VFP_CONV_FIX_FLOAT
440 #undef VFP_CONV_FLOAT_FIX_ROUND
441 #undef VFP_CONV_FIX_A64
442
443 uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
444 {
445 return int32_to_float16_scalbn(x, -shift, fpst);
446 }
447
448 uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
449 {
450 return uint32_to_float16_scalbn(x, -shift, fpst);
451 }
452
453 uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
454 {
455 return int64_to_float16_scalbn(x, -shift, fpst);
456 }
457
458 uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
459 {
460 return uint64_to_float16_scalbn(x, -shift, fpst);
461 }
462
463 uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)
464 {
465 if (unlikely(float16_is_any_nan(x))) {
466 float_raise(float_flag_invalid, fpst);
467 return 0;
468 }
469 return float16_to_int16_scalbn(x, get_float_rounding_mode(fpst),
470 shift, fpst);
471 }
472
473 uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)
474 {
475 if (unlikely(float16_is_any_nan(x))) {
476 float_raise(float_flag_invalid, fpst);
477 return 0;
478 }
479 return float16_to_uint16_scalbn(x, get_float_rounding_mode(fpst),
480 shift, fpst);
481 }
482
483 uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)
484 {
485 if (unlikely(float16_is_any_nan(x))) {
486 float_raise(float_flag_invalid, fpst);
487 return 0;
488 }
489 return float16_to_int32_scalbn(x, get_float_rounding_mode(fpst),
490 shift, fpst);
491 }
492
493 uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)
494 {
495 if (unlikely(float16_is_any_nan(x))) {
496 float_raise(float_flag_invalid, fpst);
497 return 0;
498 }
499 return float16_to_uint32_scalbn(x, get_float_rounding_mode(fpst),
500 shift, fpst);
501 }
502
503 uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)
504 {
505 if (unlikely(float16_is_any_nan(x))) {
506 float_raise(float_flag_invalid, fpst);
507 return 0;
508 }
509 return float16_to_int64_scalbn(x, get_float_rounding_mode(fpst),
510 shift, fpst);
511 }
512
513 uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
514 {
515 if (unlikely(float16_is_any_nan(x))) {
516 float_raise(float_flag_invalid, fpst);
517 return 0;
518 }
519 return float16_to_uint64_scalbn(x, get_float_rounding_mode(fpst),
520 shift, fpst);
521 }
522
523 /* Set the current fp rounding mode and return the old one.
524 * The argument is a softfloat float_round_ value.
525 */
526 uint32_t HELPER(set_rmode)(uint32_t rmode, void *fpstp)
527 {
528 float_status *fp_status = fpstp;
529
530 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
531 set_float_rounding_mode(rmode, fp_status);
532
533 return prev_rmode;
534 }
535
536 /* Set the current fp rounding mode in the standard fp status and return
537 * the old one. This is for NEON instructions that need to change the
538 * rounding mode but wish to use the standard FPSCR values for everything
539 * else. Always set the rounding mode back to the correct value after
540 * modifying it.
541 * The argument is a softfloat float_round_ value.
542 */
543 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
544 {
545 float_status *fp_status = &env->vfp.standard_fp_status;
546
547 uint32_t prev_rmode = get_float_rounding_mode(fp_status);
548 set_float_rounding_mode(rmode, fp_status);
549
550 return prev_rmode;
551 }
552
553 /* Half precision conversions. */
554 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
555 {
556 /* Squash FZ16 to 0 for the duration of conversion. In this case,
557 * it would affect flushing input denormals.
558 */
559 float_status *fpst = fpstp;
560 bool save = get_flush_inputs_to_zero(fpst);
561 set_flush_inputs_to_zero(false, fpst);
562 float32 r = float16_to_float32(a, !ahp_mode, fpst);
563 set_flush_inputs_to_zero(save, fpst);
564 return r;
565 }
566
567 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
568 {
569 /* Squash FZ16 to 0 for the duration of conversion. In this case,
570 * it would affect flushing output denormals.
571 */
572 float_status *fpst = fpstp;
573 bool save = get_flush_to_zero(fpst);
574 set_flush_to_zero(false, fpst);
575 float16 r = float32_to_float16(a, !ahp_mode, fpst);
576 set_flush_to_zero(save, fpst);
577 return r;
578 }
579
580 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
581 {
582 /* Squash FZ16 to 0 for the duration of conversion. In this case,
583 * it would affect flushing input denormals.
584 */
585 float_status *fpst = fpstp;
586 bool save = get_flush_inputs_to_zero(fpst);
587 set_flush_inputs_to_zero(false, fpst);
588 float64 r = float16_to_float64(a, !ahp_mode, fpst);
589 set_flush_inputs_to_zero(save, fpst);
590 return r;
591 }
592
593 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
594 {
595 /* Squash FZ16 to 0 for the duration of conversion. In this case,
596 * it would affect flushing output denormals.
597 */
598 float_status *fpst = fpstp;
599 bool save = get_flush_to_zero(fpst);
600 set_flush_to_zero(false, fpst);
601 float16 r = float64_to_float16(a, !ahp_mode, fpst);
602 set_flush_to_zero(save, fpst);
603 return r;
604 }
605
606 float32 HELPER(recps_f32)(CPUARMState *env, float32 a, float32 b)
607 {
608 float_status *s = &env->vfp.standard_fp_status;
609 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
610 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
611 if (!(float32_is_zero(a) || float32_is_zero(b))) {
612 float_raise(float_flag_input_denormal, s);
613 }
614 return float32_two;
615 }
616 return float32_sub(float32_two, float32_mul(a, b, s), s);
617 }
618
619 float32 HELPER(rsqrts_f32)(CPUARMState *env, float32 a, float32 b)
620 {
621 float_status *s = &env->vfp.standard_fp_status;
622 float32 product;
623 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
624 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
625 if (!(float32_is_zero(a) || float32_is_zero(b))) {
626 float_raise(float_flag_input_denormal, s);
627 }
628 return float32_one_point_five;
629 }
630 product = float32_mul(a, b, s);
631 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
632 }
633
634 /* NEON helpers. */
635
636 /* Constants 256 and 512 are used in some helpers; we avoid relying on
637 * int->float conversions at run-time. */
638 #define float64_256 make_float64(0x4070000000000000LL)
639 #define float64_512 make_float64(0x4080000000000000LL)
640 #define float16_maxnorm make_float16(0x7bff)
641 #define float32_maxnorm make_float32(0x7f7fffff)
642 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
643
644 /* Reciprocal functions
645 *
646 * The algorithm that must be used to calculate the estimate
647 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
648 */
649
650 /* See RecipEstimate()
651 *
652 * input is a 9 bit fixed point number
653 * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
654 * result range 256 .. 511 for a number from 1.0 to 511/256.
655 */
656
657 static int recip_estimate(int input)
658 {
659 int a, b, r;
660 assert(256 <= input && input < 512);
661 a = (input * 2) + 1;
662 b = (1 << 19) / a;
663 r = (b + 1) >> 1;
664 assert(256 <= r && r < 512);
665 return r;
666 }
667
668 /*
669 * Common wrapper to call recip_estimate
670 *
671 * The parameters are exponent and 64 bit fraction (without implicit
672 * bit) where the binary point is nominally at bit 52. Returns a
673 * float64 which can then be rounded to the appropriate size by the
674 * callee.
675 */
676
677 static uint64_t call_recip_estimate(int *exp, int exp_off, uint64_t frac)
678 {
679 uint32_t scaled, estimate;
680 uint64_t result_frac;
681 int result_exp;
682
683 /* Handle sub-normals */
684 if (*exp == 0) {
685 if (extract64(frac, 51, 1) == 0) {
686 *exp = -1;
687 frac <<= 2;
688 } else {
689 frac <<= 1;
690 }
691 }
692
693 /* scaled = UInt('1':fraction<51:44>) */
694 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
695 estimate = recip_estimate(scaled);
696
697 result_exp = exp_off - *exp;
698 result_frac = deposit64(0, 44, 8, estimate);
699 if (result_exp == 0) {
700 result_frac = deposit64(result_frac >> 1, 51, 1, 1);
701 } else if (result_exp == -1) {
702 result_frac = deposit64(result_frac >> 2, 50, 2, 1);
703 result_exp = 0;
704 }
705
706 *exp = result_exp;
707
708 return result_frac;
709 }
710
711 static bool round_to_inf(float_status *fpst, bool sign_bit)
712 {
713 switch (fpst->float_rounding_mode) {
714 case float_round_nearest_even: /* Round to Nearest */
715 return true;
716 case float_round_up: /* Round to +Inf */
717 return !sign_bit;
718 case float_round_down: /* Round to -Inf */
719 return sign_bit;
720 case float_round_to_zero: /* Round to Zero */
721 return false;
722 default:
723 g_assert_not_reached();
724 }
725 }
726
727 uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
728 {
729 float_status *fpst = fpstp;
730 float16 f16 = float16_squash_input_denormal(input, fpst);
731 uint32_t f16_val = float16_val(f16);
732 uint32_t f16_sign = float16_is_neg(f16);
733 int f16_exp = extract32(f16_val, 10, 5);
734 uint32_t f16_frac = extract32(f16_val, 0, 10);
735 uint64_t f64_frac;
736
737 if (float16_is_any_nan(f16)) {
738 float16 nan = f16;
739 if (float16_is_signaling_nan(f16, fpst)) {
740 float_raise(float_flag_invalid, fpst);
741 nan = float16_silence_nan(f16, fpst);
742 }
743 if (fpst->default_nan_mode) {
744 nan = float16_default_nan(fpst);
745 }
746 return nan;
747 } else if (float16_is_infinity(f16)) {
748 return float16_set_sign(float16_zero, float16_is_neg(f16));
749 } else if (float16_is_zero(f16)) {
750 float_raise(float_flag_divbyzero, fpst);
751 return float16_set_sign(float16_infinity, float16_is_neg(f16));
752 } else if (float16_abs(f16) < (1 << 8)) {
753 /* Abs(value) < 2.0^-16 */
754 float_raise(float_flag_overflow | float_flag_inexact, fpst);
755 if (round_to_inf(fpst, f16_sign)) {
756 return float16_set_sign(float16_infinity, f16_sign);
757 } else {
758 return float16_set_sign(float16_maxnorm, f16_sign);
759 }
760 } else if (f16_exp >= 29 && fpst->flush_to_zero) {
761 float_raise(float_flag_underflow, fpst);
762 return float16_set_sign(float16_zero, float16_is_neg(f16));
763 }
764
765 f64_frac = call_recip_estimate(&f16_exp, 29,
766 ((uint64_t) f16_frac) << (52 - 10));
767
768 /* result = sign : result_exp<4:0> : fraction<51:42> */
769 f16_val = deposit32(0, 15, 1, f16_sign);
770 f16_val = deposit32(f16_val, 10, 5, f16_exp);
771 f16_val = deposit32(f16_val, 0, 10, extract64(f64_frac, 52 - 10, 10));
772 return make_float16(f16_val);
773 }
774
775 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
776 {
777 float_status *fpst = fpstp;
778 float32 f32 = float32_squash_input_denormal(input, fpst);
779 uint32_t f32_val = float32_val(f32);
780 bool f32_sign = float32_is_neg(f32);
781 int f32_exp = extract32(f32_val, 23, 8);
782 uint32_t f32_frac = extract32(f32_val, 0, 23);
783 uint64_t f64_frac;
784
785 if (float32_is_any_nan(f32)) {
786 float32 nan = f32;
787 if (float32_is_signaling_nan(f32, fpst)) {
788 float_raise(float_flag_invalid, fpst);
789 nan = float32_silence_nan(f32, fpst);
790 }
791 if (fpst->default_nan_mode) {
792 nan = float32_default_nan(fpst);
793 }
794 return nan;
795 } else if (float32_is_infinity(f32)) {
796 return float32_set_sign(float32_zero, float32_is_neg(f32));
797 } else if (float32_is_zero(f32)) {
798 float_raise(float_flag_divbyzero, fpst);
799 return float32_set_sign(float32_infinity, float32_is_neg(f32));
800 } else if (float32_abs(f32) < (1ULL << 21)) {
801 /* Abs(value) < 2.0^-128 */
802 float_raise(float_flag_overflow | float_flag_inexact, fpst);
803 if (round_to_inf(fpst, f32_sign)) {
804 return float32_set_sign(float32_infinity, f32_sign);
805 } else {
806 return float32_set_sign(float32_maxnorm, f32_sign);
807 }
808 } else if (f32_exp >= 253 && fpst->flush_to_zero) {
809 float_raise(float_flag_underflow, fpst);
810 return float32_set_sign(float32_zero, float32_is_neg(f32));
811 }
812
813 f64_frac = call_recip_estimate(&f32_exp, 253,
814 ((uint64_t) f32_frac) << (52 - 23));
815
816 /* result = sign : result_exp<7:0> : fraction<51:29> */
817 f32_val = deposit32(0, 31, 1, f32_sign);
818 f32_val = deposit32(f32_val, 23, 8, f32_exp);
819 f32_val = deposit32(f32_val, 0, 23, extract64(f64_frac, 52 - 23, 23));
820 return make_float32(f32_val);
821 }
822
823 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
824 {
825 float_status *fpst = fpstp;
826 float64 f64 = float64_squash_input_denormal(input, fpst);
827 uint64_t f64_val = float64_val(f64);
828 bool f64_sign = float64_is_neg(f64);
829 int f64_exp = extract64(f64_val, 52, 11);
830 uint64_t f64_frac = extract64(f64_val, 0, 52);
831
832 /* Deal with any special cases */
833 if (float64_is_any_nan(f64)) {
834 float64 nan = f64;
835 if (float64_is_signaling_nan(f64, fpst)) {
836 float_raise(float_flag_invalid, fpst);
837 nan = float64_silence_nan(f64, fpst);
838 }
839 if (fpst->default_nan_mode) {
840 nan = float64_default_nan(fpst);
841 }
842 return nan;
843 } else if (float64_is_infinity(f64)) {
844 return float64_set_sign(float64_zero, float64_is_neg(f64));
845 } else if (float64_is_zero(f64)) {
846 float_raise(float_flag_divbyzero, fpst);
847 return float64_set_sign(float64_infinity, float64_is_neg(f64));
848 } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
849 /* Abs(value) < 2.0^-1024 */
850 float_raise(float_flag_overflow | float_flag_inexact, fpst);
851 if (round_to_inf(fpst, f64_sign)) {
852 return float64_set_sign(float64_infinity, f64_sign);
853 } else {
854 return float64_set_sign(float64_maxnorm, f64_sign);
855 }
856 } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
857 float_raise(float_flag_underflow, fpst);
858 return float64_set_sign(float64_zero, float64_is_neg(f64));
859 }
860
861 f64_frac = call_recip_estimate(&f64_exp, 2045, f64_frac);
862
863 /* result = sign : result_exp<10:0> : fraction<51:0>; */
864 f64_val = deposit64(0, 63, 1, f64_sign);
865 f64_val = deposit64(f64_val, 52, 11, f64_exp);
866 f64_val = deposit64(f64_val, 0, 52, f64_frac);
867 return make_float64(f64_val);
868 }
869
870 /* The algorithm that must be used to calculate the estimate
871 * is specified by the ARM ARM.
872 */
873
874 static int do_recip_sqrt_estimate(int a)
875 {
876 int b, estimate;
877
878 assert(128 <= a && a < 512);
879 if (a < 256) {
880 a = a * 2 + 1;
881 } else {
882 a = (a >> 1) << 1;
883 a = (a + 1) * 2;
884 }
885 b = 512;
886 while (a * (b + 1) * (b + 1) < (1 << 28)) {
887 b += 1;
888 }
889 estimate = (b + 1) / 2;
890 assert(256 <= estimate && estimate < 512);
891
892 return estimate;
893 }
894
895
896 static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
897 {
898 int estimate;
899 uint32_t scaled;
900
901 if (*exp == 0) {
902 while (extract64(frac, 51, 1) == 0) {
903 frac = frac << 1;
904 *exp -= 1;
905 }
906 frac = extract64(frac, 0, 51) << 1;
907 }
908
909 if (*exp & 1) {
910 /* scaled = UInt('01':fraction<51:45>) */
911 scaled = deposit32(1 << 7, 0, 7, extract64(frac, 45, 7));
912 } else {
913 /* scaled = UInt('1':fraction<51:44>) */
914 scaled = deposit32(1 << 8, 0, 8, extract64(frac, 44, 8));
915 }
916 estimate = do_recip_sqrt_estimate(scaled);
917
918 *exp = (exp_off - *exp) / 2;
919 return extract64(estimate, 0, 8) << 44;
920 }
921
922 uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
923 {
924 float_status *s = fpstp;
925 float16 f16 = float16_squash_input_denormal(input, s);
926 uint16_t val = float16_val(f16);
927 bool f16_sign = float16_is_neg(f16);
928 int f16_exp = extract32(val, 10, 5);
929 uint16_t f16_frac = extract32(val, 0, 10);
930 uint64_t f64_frac;
931
932 if (float16_is_any_nan(f16)) {
933 float16 nan = f16;
934 if (float16_is_signaling_nan(f16, s)) {
935 float_raise(float_flag_invalid, s);
936 nan = float16_silence_nan(f16, s);
937 }
938 if (s->default_nan_mode) {
939 nan = float16_default_nan(s);
940 }
941 return nan;
942 } else if (float16_is_zero(f16)) {
943 float_raise(float_flag_divbyzero, s);
944 return float16_set_sign(float16_infinity, f16_sign);
945 } else if (f16_sign) {
946 float_raise(float_flag_invalid, s);
947 return float16_default_nan(s);
948 } else if (float16_is_infinity(f16)) {
949 return float16_zero;
950 }
951
952 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
953 * preserving the parity of the exponent. */
954
955 f64_frac = ((uint64_t) f16_frac) << (52 - 10);
956
957 f64_frac = recip_sqrt_estimate(&f16_exp, 44, f64_frac);
958
959 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
960 val = deposit32(0, 15, 1, f16_sign);
961 val = deposit32(val, 10, 5, f16_exp);
962 val = deposit32(val, 2, 8, extract64(f64_frac, 52 - 8, 8));
963 return make_float16(val);
964 }
965
966 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
967 {
968 float_status *s = fpstp;
969 float32 f32 = float32_squash_input_denormal(input, s);
970 uint32_t val = float32_val(f32);
971 uint32_t f32_sign = float32_is_neg(f32);
972 int f32_exp = extract32(val, 23, 8);
973 uint32_t f32_frac = extract32(val, 0, 23);
974 uint64_t f64_frac;
975
976 if (float32_is_any_nan(f32)) {
977 float32 nan = f32;
978 if (float32_is_signaling_nan(f32, s)) {
979 float_raise(float_flag_invalid, s);
980 nan = float32_silence_nan(f32, s);
981 }
982 if (s->default_nan_mode) {
983 nan = float32_default_nan(s);
984 }
985 return nan;
986 } else if (float32_is_zero(f32)) {
987 float_raise(float_flag_divbyzero, s);
988 return float32_set_sign(float32_infinity, float32_is_neg(f32));
989 } else if (float32_is_neg(f32)) {
990 float_raise(float_flag_invalid, s);
991 return float32_default_nan(s);
992 } else if (float32_is_infinity(f32)) {
993 return float32_zero;
994 }
995
996 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
997 * preserving the parity of the exponent. */
998
999 f64_frac = ((uint64_t) f32_frac) << 29;
1000
1001 f64_frac = recip_sqrt_estimate(&f32_exp, 380, f64_frac);
1002
1003 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
1004 val = deposit32(0, 31, 1, f32_sign);
1005 val = deposit32(val, 23, 8, f32_exp);
1006 val = deposit32(val, 15, 8, extract64(f64_frac, 52 - 8, 8));
1007 return make_float32(val);
1008 }
1009
1010 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
1011 {
1012 float_status *s = fpstp;
1013 float64 f64 = float64_squash_input_denormal(input, s);
1014 uint64_t val = float64_val(f64);
1015 bool f64_sign = float64_is_neg(f64);
1016 int f64_exp = extract64(val, 52, 11);
1017 uint64_t f64_frac = extract64(val, 0, 52);
1018
1019 if (float64_is_any_nan(f64)) {
1020 float64 nan = f64;
1021 if (float64_is_signaling_nan(f64, s)) {
1022 float_raise(float_flag_invalid, s);
1023 nan = float64_silence_nan(f64, s);
1024 }
1025 if (s->default_nan_mode) {
1026 nan = float64_default_nan(s);
1027 }
1028 return nan;
1029 } else if (float64_is_zero(f64)) {
1030 float_raise(float_flag_divbyzero, s);
1031 return float64_set_sign(float64_infinity, float64_is_neg(f64));
1032 } else if (float64_is_neg(f64)) {
1033 float_raise(float_flag_invalid, s);
1034 return float64_default_nan(s);
1035 } else if (float64_is_infinity(f64)) {
1036 return float64_zero;
1037 }
1038
1039 f64_frac = recip_sqrt_estimate(&f64_exp, 3068, f64_frac);
1040
1041 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
1042 val = deposit64(0, 61, 1, f64_sign);
1043 val = deposit64(val, 52, 11, f64_exp);
1044 val = deposit64(val, 44, 8, extract64(f64_frac, 52 - 8, 8));
1045 return make_float64(val);
1046 }
1047
1048 uint32_t HELPER(recpe_u32)(uint32_t a)
1049 {
1050 int input, estimate;
1051
1052 if ((a & 0x80000000) == 0) {
1053 return 0xffffffff;
1054 }
1055
1056 input = extract32(a, 23, 9);
1057 estimate = recip_estimate(input);
1058
1059 return deposit32(0, (32 - 9), 9, estimate);
1060 }
1061
1062 uint32_t HELPER(rsqrte_u32)(uint32_t a)
1063 {
1064 int estimate;
1065
1066 if ((a & 0xc0000000) == 0) {
1067 return 0xffffffff;
1068 }
1069
1070 estimate = do_recip_sqrt_estimate(extract32(a, 23, 9));
1071
1072 return deposit32(0, 23, 9, estimate);
1073 }
1074
1075 /* VFPv4 fused multiply-accumulate */
1076 dh_ctype_f16 VFP_HELPER(muladd, h)(dh_ctype_f16 a, dh_ctype_f16 b,
1077 dh_ctype_f16 c, void *fpstp)
1078 {
1079 float_status *fpst = fpstp;
1080 return float16_muladd(a, b, c, 0, fpst);
1081 }
1082
1083 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
1084 {
1085 float_status *fpst = fpstp;
1086 return float32_muladd(a, b, c, 0, fpst);
1087 }
1088
1089 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
1090 {
1091 float_status *fpst = fpstp;
1092 return float64_muladd(a, b, c, 0, fpst);
1093 }
1094
1095 /* ARMv8 round to integral */
1096 float32 HELPER(rints_exact)(float32 x, void *fp_status)
1097 {
1098 return float32_round_to_int(x, fp_status);
1099 }
1100
1101 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
1102 {
1103 return float64_round_to_int(x, fp_status);
1104 }
1105
1106 float32 HELPER(rints)(float32 x, void *fp_status)
1107 {
1108 int old_flags = get_float_exception_flags(fp_status), new_flags;
1109 float32 ret;
1110
1111 ret = float32_round_to_int(x, fp_status);
1112
1113 /* Suppress any inexact exceptions the conversion produced */
1114 if (!(old_flags & float_flag_inexact)) {
1115 new_flags = get_float_exception_flags(fp_status);
1116 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
1117 }
1118
1119 return ret;
1120 }
1121
1122 float64 HELPER(rintd)(float64 x, void *fp_status)
1123 {
1124 int old_flags = get_float_exception_flags(fp_status), new_flags;
1125 float64 ret;
1126
1127 ret = float64_round_to_int(x, fp_status);
1128
1129 new_flags = get_float_exception_flags(fp_status);
1130
1131 /* Suppress any inexact exceptions the conversion produced */
1132 if (!(old_flags & float_flag_inexact)) {
1133 new_flags = get_float_exception_flags(fp_status);
1134 set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
1135 }
1136
1137 return ret;
1138 }
1139
1140 /* Convert ARM rounding mode to softfloat */
1141 int arm_rmode_to_sf(int rmode)
1142 {
1143 switch (rmode) {
1144 case FPROUNDING_TIEAWAY:
1145 rmode = float_round_ties_away;
1146 break;
1147 case FPROUNDING_ODD:
1148 /* FIXME: add support for TIEAWAY and ODD */
1149 qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
1150 rmode);
1151 /* fall through for now */
1152 case FPROUNDING_TIEEVEN:
1153 default:
1154 rmode = float_round_nearest_even;
1155 break;
1156 case FPROUNDING_POSINF:
1157 rmode = float_round_up;
1158 break;
1159 case FPROUNDING_NEGINF:
1160 rmode = float_round_down;
1161 break;
1162 case FPROUNDING_ZERO:
1163 rmode = float_round_to_zero;
1164 break;
1165 }
1166 return rmode;
1167 }
1168
1169 /*
1170 * Implement float64 to int32_t conversion without saturation;
1171 * the result is supplied modulo 2^32.
1172 */
1173 uint64_t HELPER(fjcvtzs)(float64 value, void *vstatus)
1174 {
1175 float_status *status = vstatus;
1176 uint32_t exp, sign;
1177 uint64_t frac;
1178 uint32_t inexact = 1; /* !Z */
1179
1180 sign = extract64(value, 63, 1);
1181 exp = extract64(value, 52, 11);
1182 frac = extract64(value, 0, 52);
1183
1184 if (exp == 0) {
1185 /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */
1186 inexact = sign;
1187 if (frac != 0) {
1188 if (status->flush_inputs_to_zero) {
1189 float_raise(float_flag_input_denormal, status);
1190 } else {
1191 float_raise(float_flag_inexact, status);
1192 inexact = 1;
1193 }
1194 }
1195 frac = 0;
1196 } else if (exp == 0x7ff) {
1197 /* This operation raises Invalid for both NaN and overflow (Inf). */
1198 float_raise(float_flag_invalid, status);
1199 frac = 0;
1200 } else {
1201 int true_exp = exp - 1023;
1202 int shift = true_exp - 52;
1203
1204 /* Restore implicit bit. */
1205 frac |= 1ull << 52;
1206
1207 /* Shift the fraction into place. */
1208 if (shift >= 0) {
1209 /* The number is so large we must shift the fraction left. */
1210 if (shift >= 64) {
1211 /* The fraction is shifted out entirely. */
1212 frac = 0;
1213 } else {
1214 frac <<= shift;
1215 }
1216 } else if (shift > -64) {
1217 /* Normal case -- shift right and notice if bits shift out. */
1218 inexact = (frac << (64 + shift)) != 0;
1219 frac >>= -shift;
1220 } else {
1221 /* The fraction is shifted out entirely. */
1222 frac = 0;
1223 }
1224
1225 /* Notice overflow or inexact exceptions. */
1226 if (true_exp > 31 || frac > (sign ? 0x80000000ull : 0x7fffffff)) {
1227 /* Overflow, for which this operation raises invalid. */
1228 float_raise(float_flag_invalid, status);
1229 inexact = 1;
1230 } else if (inexact) {
1231 float_raise(float_flag_inexact, status);
1232 }
1233
1234 /* Honor the sign. */
1235 if (sign) {
1236 frac = -frac;
1237 }
1238 }
1239
1240 /* Pack the result and the env->ZF representation of Z together. */
1241 return deposit64(frac, 32, 32, inexact);
1242 }
1243
1244 uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env)
1245 {
1246 uint64_t pair = HELPER(fjcvtzs)(value, &env->vfp.fp_status);
1247 uint32_t result = pair;
1248 uint32_t z = (pair >> 32) == 0;
1249
1250 /* Store Z, clear NCV, in FPSCR.NZCV. */
1251 env->vfp.xregs[ARM_VFP_FPSCR]
1252 = (env->vfp.xregs[ARM_VFP_FPSCR] & ~CPSR_NZCV) | (z * CPSR_Z);
1253
1254 return result;
1255 }
1256
1257 /* Round a float32 to an integer that fits in int32_t or int64_t. */
1258 static float32 frint_s(float32 f, float_status *fpst, int intsize)
1259 {
1260 int old_flags = get_float_exception_flags(fpst);
1261 uint32_t exp = extract32(f, 23, 8);
1262
1263 if (unlikely(exp == 0xff)) {
1264 /* NaN or Inf. */
1265 goto overflow;
1266 }
1267
1268 /* Round and re-extract the exponent. */
1269 f = float32_round_to_int(f, fpst);
1270 exp = extract32(f, 23, 8);
1271
1272 /* Validate the range of the result. */
1273 if (exp < 126 + intsize) {
1274 /* abs(F) <= INT{N}_MAX */
1275 return f;
1276 }
1277 if (exp == 126 + intsize) {
1278 uint32_t sign = extract32(f, 31, 1);
1279 uint32_t frac = extract32(f, 0, 23);
1280 if (sign && frac == 0) {
1281 /* F == INT{N}_MIN */
1282 return f;
1283 }
1284 }
1285
1286 overflow:
1287 /*
1288 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1289 * inexact exception float32_round_to_int may have raised.
1290 */
1291 set_float_exception_flags(old_flags | float_flag_invalid, fpst);
1292 return (0x100u + 126u + intsize) << 23;
1293 }
1294
1295 float32 HELPER(frint32_s)(float32 f, void *fpst)
1296 {
1297 return frint_s(f, fpst, 32);
1298 }
1299
1300 float32 HELPER(frint64_s)(float32 f, void *fpst)
1301 {
1302 return frint_s(f, fpst, 64);
1303 }
1304
1305 /* Round a float64 to an integer that fits in int32_t or int64_t. */
1306 static float64 frint_d(float64 f, float_status *fpst, int intsize)
1307 {
1308 int old_flags = get_float_exception_flags(fpst);
1309 uint32_t exp = extract64(f, 52, 11);
1310
1311 if (unlikely(exp == 0x7ff)) {
1312 /* NaN or Inf. */
1313 goto overflow;
1314 }
1315
1316 /* Round and re-extract the exponent. */
1317 f = float64_round_to_int(f, fpst);
1318 exp = extract64(f, 52, 11);
1319
1320 /* Validate the range of the result. */
1321 if (exp < 1022 + intsize) {
1322 /* abs(F) <= INT{N}_MAX */
1323 return f;
1324 }
1325 if (exp == 1022 + intsize) {
1326 uint64_t sign = extract64(f, 63, 1);
1327 uint64_t frac = extract64(f, 0, 52);
1328 if (sign && frac == 0) {
1329 /* F == INT{N}_MIN */
1330 return f;
1331 }
1332 }
1333
1334 overflow:
1335 /*
1336 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1337 * inexact exception float64_round_to_int may have raised.
1338 */
1339 set_float_exception_flags(old_flags | float_flag_invalid, fpst);
1340 return (uint64_t)(0x800 + 1022 + intsize) << 52;
1341 }
1342
1343 float64 HELPER(frint32_d)(float64 f, void *fpst)
1344 {
1345 return frint_d(f, fpst, 32);
1346 }
1347
1348 float64 HELPER(frint64_d)(float64 f, void *fpst)
1349 {
1350 return frint_d(f, fpst, 64);
1351 }
1352
1353 void HELPER(check_hcr_el2_trap)(CPUARMState *env, uint32_t rt, uint32_t reg)
1354 {
1355 uint32_t syndrome;
1356
1357 switch (reg) {
1358 case ARM_VFP_MVFR0:
1359 case ARM_VFP_MVFR1:
1360 case ARM_VFP_MVFR2:
1361 if (!(arm_hcr_el2_eff(env) & HCR_TID3)) {
1362 return;
1363 }
1364 break;
1365 case ARM_VFP_FPSID:
1366 if (!(arm_hcr_el2_eff(env) & HCR_TID0)) {
1367 return;
1368 }
1369 break;
1370 default:
1371 g_assert_not_reached();
1372 }
1373
1374 syndrome = ((EC_FPIDTRAP << ARM_EL_EC_SHIFT)
1375 | ARM_EL_IL
1376 | (1 << 24) | (0xe << 20) | (7 << 14)
1377 | (reg << 10) | (rt << 5) | 1);
1378
1379 raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);
1380 }
1381
1382 #endif