meson: target
[qemu.git] / target / avr / helper.c
1 /*
2 * QEMU AVR CPU helpers
3 *
4 * Copyright (c) 2016-2020 Michael Rolnik
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "exec/exec-all.h"
24 #include "exec/address-spaces.h"
25 #include "exec/helper-proto.h"
26
27 bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
28 {
29 bool ret = false;
30 CPUClass *cc = CPU_GET_CLASS(cs);
31 AVRCPU *cpu = AVR_CPU(cs);
32 CPUAVRState *env = &cpu->env;
33
34 if (interrupt_request & CPU_INTERRUPT_RESET) {
35 if (cpu_interrupts_enabled(env)) {
36 cs->exception_index = EXCP_RESET;
37 cc->do_interrupt(cs);
38
39 cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
40
41 ret = true;
42 }
43 }
44 if (interrupt_request & CPU_INTERRUPT_HARD) {
45 if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
46 int index = ctz32(env->intsrc);
47 cs->exception_index = EXCP_INT(index);
48 cc->do_interrupt(cs);
49
50 env->intsrc &= env->intsrc - 1; /* clear the interrupt */
51 cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
52
53 ret = true;
54 }
55 }
56 return ret;
57 }
58
59 void avr_cpu_do_interrupt(CPUState *cs)
60 {
61 AVRCPU *cpu = AVR_CPU(cs);
62 CPUAVRState *env = &cpu->env;
63
64 uint32_t ret = env->pc_w;
65 int vector = 0;
66 int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1;
67 int base = 0;
68
69 if (cs->exception_index == EXCP_RESET) {
70 vector = 0;
71 } else if (env->intsrc != 0) {
72 vector = ctz32(env->intsrc) + 1;
73 }
74
75 if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
76 cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
77 cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
78 cpu_stb_data(env, env->sp--, (ret & 0xff0000) >> 16);
79 } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) {
80 cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
81 cpu_stb_data(env, env->sp--, (ret & 0x00ff00) >> 8);
82 } else {
83 cpu_stb_data(env, env->sp--, (ret & 0x0000ff));
84 }
85
86 env->pc_w = base + vector * size;
87 env->sregI = 0; /* clear Global Interrupt Flag */
88
89 cs->exception_index = -1;
90 }
91
92 int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uint8_t *buf,
93 int len, bool is_write)
94 {
95 return cpu_memory_rw_debug(cs, addr, buf, len, is_write);
96 }
97
98 hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
99 {
100 return addr; /* I assume 1:1 address correspondance */
101 }
102
103 bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
104 MMUAccessType access_type, int mmu_idx,
105 bool probe, uintptr_t retaddr)
106 {
107 int prot = 0;
108 MemTxAttrs attrs = {};
109 uint32_t paddr;
110
111 address &= TARGET_PAGE_MASK;
112
113 if (mmu_idx == MMU_CODE_IDX) {
114 /* access to code in flash */
115 paddr = OFFSET_CODE + address;
116 prot = PAGE_READ | PAGE_EXEC;
117 if (paddr + TARGET_PAGE_SIZE > OFFSET_DATA) {
118 error_report("execution left flash memory");
119 abort();
120 }
121 } else if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
122 /*
123 * access to CPU registers, exit and rebuilt this TB to use full access
124 * incase it touches specially handled registers like SREG or SP
125 */
126 AVRCPU *cpu = AVR_CPU(cs);
127 CPUAVRState *env = &cpu->env;
128 env->fullacc = 1;
129 cpu_loop_exit_restore(cs, retaddr);
130 } else {
131 /* access to memory. nothing special */
132 paddr = OFFSET_DATA + address;
133 prot = PAGE_READ | PAGE_WRITE;
134 }
135
136 tlb_set_page_with_attrs(cs, address, paddr, attrs, prot,
137 mmu_idx, TARGET_PAGE_SIZE);
138
139 return true;
140 }
141
142 /*
143 * helpers
144 */
145
146 void helper_sleep(CPUAVRState *env)
147 {
148 CPUState *cs = env_cpu(env);
149
150 cs->exception_index = EXCP_HLT;
151 cpu_loop_exit(cs);
152 }
153
154 void helper_unsupported(CPUAVRState *env)
155 {
156 CPUState *cs = env_cpu(env);
157
158 /*
159 * I count not find what happens on the real platform, so
160 * it's EXCP_DEBUG for meanwhile
161 */
162 cs->exception_index = EXCP_DEBUG;
163 if (qemu_loglevel_mask(LOG_UNIMP)) {
164 qemu_log("UNSUPPORTED\n");
165 cpu_dump_state(cs, stderr, 0);
166 }
167 cpu_loop_exit(cs);
168 }
169
170 void helper_debug(CPUAVRState *env)
171 {
172 CPUState *cs = env_cpu(env);
173
174 cs->exception_index = EXCP_DEBUG;
175 cpu_loop_exit(cs);
176 }
177
178 void helper_break(CPUAVRState *env)
179 {
180 CPUState *cs = env_cpu(env);
181
182 cs->exception_index = EXCP_DEBUG;
183 cpu_loop_exit(cs);
184 }
185
186 void helper_wdr(CPUAVRState *env)
187 {
188 CPUState *cs = env_cpu(env);
189
190 /* WD is not implemented yet, placeholder */
191 cs->exception_index = EXCP_DEBUG;
192 cpu_loop_exit(cs);
193 }
194
195 /*
196 * This function implements IN instruction
197 *
198 * It does the following
199 * a. if an IO register belongs to CPU, its value is read and returned
200 * b. otherwise io address is translated to mem address and physical memory
201 * is read.
202 * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
203 *
204 */
205 target_ulong helper_inb(CPUAVRState *env, uint32_t port)
206 {
207 target_ulong data = 0;
208
209 switch (port) {
210 case 0x38: /* RAMPD */
211 data = 0xff & (env->rampD >> 16);
212 break;
213 case 0x39: /* RAMPX */
214 data = 0xff & (env->rampX >> 16);
215 break;
216 case 0x3a: /* RAMPY */
217 data = 0xff & (env->rampY >> 16);
218 break;
219 case 0x3b: /* RAMPZ */
220 data = 0xff & (env->rampZ >> 16);
221 break;
222 case 0x3c: /* EIND */
223 data = 0xff & (env->eind >> 16);
224 break;
225 case 0x3d: /* SPL */
226 data = env->sp & 0x00ff;
227 break;
228 case 0x3e: /* SPH */
229 data = env->sp >> 8;
230 break;
231 case 0x3f: /* SREG */
232 data = cpu_get_sreg(env);
233 break;
234 default:
235 /* not a special register, pass to normal memory access */
236 data = address_space_ldub(&address_space_memory,
237 OFFSET_IO_REGISTERS + port,
238 MEMTXATTRS_UNSPECIFIED, NULL);
239 }
240
241 return data;
242 }
243
244 /*
245 * This function implements OUT instruction
246 *
247 * It does the following
248 * a. if an IO register belongs to CPU, its value is written into the register
249 * b. otherwise io address is translated to mem address and physical memory
250 * is written.
251 * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
252 *
253 */
254 void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data)
255 {
256 data &= 0x000000ff;
257
258 switch (port) {
259 case 0x38: /* RAMPD */
260 if (avr_feature(env, AVR_FEATURE_RAMPD)) {
261 env->rampD = (data & 0xff) << 16;
262 }
263 break;
264 case 0x39: /* RAMPX */
265 if (avr_feature(env, AVR_FEATURE_RAMPX)) {
266 env->rampX = (data & 0xff) << 16;
267 }
268 break;
269 case 0x3a: /* RAMPY */
270 if (avr_feature(env, AVR_FEATURE_RAMPY)) {
271 env->rampY = (data & 0xff) << 16;
272 }
273 break;
274 case 0x3b: /* RAMPZ */
275 if (avr_feature(env, AVR_FEATURE_RAMPZ)) {
276 env->rampZ = (data & 0xff) << 16;
277 }
278 break;
279 case 0x3c: /* EIDN */
280 env->eind = (data & 0xff) << 16;
281 break;
282 case 0x3d: /* SPL */
283 env->sp = (env->sp & 0xff00) | (data);
284 break;
285 case 0x3e: /* SPH */
286 if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) {
287 env->sp = (env->sp & 0x00ff) | (data << 8);
288 }
289 break;
290 case 0x3f: /* SREG */
291 cpu_set_sreg(env, data);
292 break;
293 default:
294 /* not a special register, pass to normal memory access */
295 address_space_stb(&address_space_memory, OFFSET_IO_REGISTERS + port,
296 data, MEMTXATTRS_UNSPECIFIED, NULL);
297 }
298 }
299
300 /*
301 * this function implements LD instruction when there is a posibility to read
302 * from a CPU register
303 */
304 target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr)
305 {
306 uint8_t data;
307
308 env->fullacc = false;
309
310 if (addr < NUMBER_OF_CPU_REGISTERS) {
311 /* CPU registers */
312 data = env->r[addr];
313 } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
314 /* IO registers */
315 data = helper_inb(env, addr - NUMBER_OF_CPU_REGISTERS);
316 } else {
317 /* memory */
318 data = address_space_ldub(&address_space_memory, OFFSET_DATA + addr,
319 MEMTXATTRS_UNSPECIFIED, NULL);
320 }
321 return data;
322 }
323
324 /*
325 * this function implements ST instruction when there is a posibility to write
326 * into a CPU register
327 */
328 void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr)
329 {
330 env->fullacc = false;
331
332 /* Following logic assumes this: */
333 assert(OFFSET_CPU_REGISTERS == OFFSET_DATA);
334 assert(OFFSET_IO_REGISTERS == OFFSET_CPU_REGISTERS +
335 NUMBER_OF_CPU_REGISTERS);
336
337 if (addr < NUMBER_OF_CPU_REGISTERS) {
338 /* CPU registers */
339 env->r[addr] = data;
340 } else if (addr < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
341 /* IO registers */
342 helper_outb(env, addr - NUMBER_OF_CPU_REGISTERS, data);
343 } else {
344 /* memory */
345 address_space_stb(&address_space_memory, OFFSET_DATA + addr, data,
346 MEMTXATTRS_UNSPECIFIED, NULL);
347 }
348 }