Merge tag 'pull-request-2022-09-28' of https://gitlab.com/thuth/qemu into staging
[qemu.git] / target / cris / cpu.h
1 /*
2 * CRIS virtual CPU header
3 *
4 * Copyright (c) 2007 AXIS Communications AB
5 * Written by Edgar E. Iglesias
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #ifndef CRIS_CPU_H
22 #define CRIS_CPU_H
23
24 #include "cpu-qom.h"
25 #include "exec/cpu-defs.h"
26
27 #define EXCP_NMI 1
28 #define EXCP_GURU 2
29 #define EXCP_BUSFAULT 3
30 #define EXCP_IRQ 4
31 #define EXCP_BREAK 5
32
33 /* CRIS-specific interrupt pending bits. */
34 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
35
36 /* CRUS CPU device objects interrupt lines. */
37 /* PIC passes the vector for the IRQ as the value of it sends over qemu_irq */
38 #define CRIS_CPU_IRQ 0
39 #define CRIS_CPU_NMI 1
40
41 /* Register aliases. R0 - R15 */
42 #define R_FP 8
43 #define R_SP 14
44 #define R_ACR 15
45
46 /* Support regs, P0 - P15 */
47 #define PR_BZ 0
48 #define PR_VR 1
49 #define PR_PID 2
50 #define PR_SRS 3
51 #define PR_WZ 4
52 #define PR_EXS 5
53 #define PR_EDA 6
54 #define PR_PREFIX 6 /* On CRISv10 P6 is reserved, we use it as prefix. */
55 #define PR_MOF 7
56 #define PR_DZ 8
57 #define PR_EBP 9
58 #define PR_ERP 10
59 #define PR_SRP 11
60 #define PR_NRP 12
61 #define PR_CCS 13
62 #define PR_USP 14
63 #define PRV10_BRP 14
64 #define PR_SPC 15
65
66 /* CPU flags. */
67 #define Q_FLAG 0x80000000
68 #define M_FLAG_V32 0x40000000
69 #define PFIX_FLAG 0x800 /* CRISv10 Only. */
70 #define F_FLAG_V10 0x400
71 #define P_FLAG_V10 0x200
72 #define S_FLAG 0x200
73 #define R_FLAG 0x100
74 #define P_FLAG 0x80
75 #define M_FLAG_V10 0x80
76 #define U_FLAG 0x40
77 #define I_FLAG 0x20
78 #define X_FLAG 0x10
79 #define N_FLAG 0x08
80 #define Z_FLAG 0x04
81 #define V_FLAG 0x02
82 #define C_FLAG 0x01
83 #define ALU_FLAGS 0x1F
84
85 /* Condition codes. */
86 #define CC_CC 0
87 #define CC_CS 1
88 #define CC_NE 2
89 #define CC_EQ 3
90 #define CC_VC 4
91 #define CC_VS 5
92 #define CC_PL 6
93 #define CC_MI 7
94 #define CC_LS 8
95 #define CC_HI 9
96 #define CC_GE 10
97 #define CC_LT 11
98 #define CC_GT 12
99 #define CC_LE 13
100 #define CC_A 14
101 #define CC_P 15
102
103 typedef struct {
104 uint32_t hi;
105 uint32_t lo;
106 } TLBSet;
107
108 typedef struct CPUArchState {
109 uint32_t regs[16];
110 /* P0 - P15 are referred to as special registers in the docs. */
111 uint32_t pregs[16];
112
113 /* Pseudo register for the PC. Not directly accessible on CRIS. */
114 uint32_t pc;
115
116 /* Pseudo register for the kernel stack. */
117 uint32_t ksp;
118
119 /* Branch. */
120 int dslot;
121 int btaken;
122 uint32_t btarget;
123
124 /* Condition flag tracking. */
125 uint32_t cc_op;
126 uint32_t cc_mask;
127 uint32_t cc_dest;
128 uint32_t cc_src;
129 uint32_t cc_result;
130 /* size of the operation, 1 = byte, 2 = word, 4 = dword. */
131 int cc_size;
132 /* X flag at the time of cc snapshot. */
133 int cc_x;
134
135 /* CRIS has certain insns that lockout interrupts. */
136 int locked_irq;
137 int interrupt_vector;
138 int fault_vector;
139 int trap_vector;
140
141 /* FIXME: add a check in the translator to avoid writing to support
142 register sets beyond the 4th. The ISA allows up to 256! but in
143 practice there is no core that implements more than 4.
144
145 Support function registers are used to control units close to the
146 core. Accesses do not pass down the normal hierarchy.
147 */
148 uint32_t sregs[4][16];
149
150 /* Linear feedback shift reg in the mmu. Used to provide pseudo
151 randomness for the 'hint' the mmu gives to sw for choosing valid
152 sets on TLB refills. */
153 uint32_t mmu_rand_lfsr;
154
155 /*
156 * We just store the stores to the tlbset here for later evaluation
157 * when the hw needs access to them.
158 *
159 * One for I and another for D.
160 */
161 TLBSet tlbsets[2][4][16];
162
163 /* Fields up to this point are cleared by a CPU reset */
164 struct {} end_reset_fields;
165
166 /* Members from load_info on are preserved across resets. */
167 void *load_info;
168 } CPUCRISState;
169
170 /**
171 * CRISCPU:
172 * @env: #CPUCRISState
173 *
174 * A CRIS CPU.
175 */
176 struct ArchCPU {
177 /*< private >*/
178 CPUState parent_obj;
179 /*< public >*/
180
181 CPUNegativeOffsetState neg;
182 CPUCRISState env;
183 };
184
185
186 #ifndef CONFIG_USER_ONLY
187 extern const VMStateDescription vmstate_cris_cpu;
188
189 void cris_cpu_do_interrupt(CPUState *cpu);
190 void crisv10_cpu_do_interrupt(CPUState *cpu);
191 bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req);
192
193 bool cris_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
194 MMUAccessType access_type, int mmu_idx,
195 bool probe, uintptr_t retaddr);
196 #endif
197
198 void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags);
199
200 hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
201
202 int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
203 int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
204 int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
205
206 void cris_initialize_tcg(void);
207 void cris_initialize_crisv10_tcg(void);
208
209 /* Instead of computing the condition codes after each CRIS instruction,
210 * QEMU just stores one operand (called CC_SRC), the result
211 * (called CC_DEST) and the type of operation (called CC_OP). When the
212 * condition codes are needed, the condition codes can be calculated
213 * using this information. Condition codes are not generated if they
214 * are only needed for conditional branches.
215 */
216 enum {
217 CC_OP_DYNAMIC, /* Use env->cc_op */
218 CC_OP_FLAGS,
219 CC_OP_CMP,
220 CC_OP_MOVE,
221 CC_OP_ADD,
222 CC_OP_ADDC,
223 CC_OP_MCP,
224 CC_OP_ADDU,
225 CC_OP_SUB,
226 CC_OP_SUBU,
227 CC_OP_NEG,
228 CC_OP_BTST,
229 CC_OP_MULS,
230 CC_OP_MULU,
231 CC_OP_DSTEP,
232 CC_OP_MSTEP,
233 CC_OP_BOUND,
234
235 CC_OP_OR,
236 CC_OP_AND,
237 CC_OP_XOR,
238 CC_OP_LSL,
239 CC_OP_LSR,
240 CC_OP_ASR,
241 CC_OP_LZ
242 };
243
244 /* CRIS uses 8k pages. */
245 #define MMAP_SHIFT TARGET_PAGE_BITS
246
247 #define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU
248 #define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX)
249 #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU
250
251 /* MMU modes definitions */
252 #define MMU_USER_IDX 1
253 static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
254 {
255 return !!(env->pregs[PR_CCS] & U_FLAG);
256 }
257
258 /* Support function regs. */
259 #define SFR_RW_GC_CFG 0][0
260 #define SFR_RW_MM_CFG env->pregs[PR_SRS]][0
261 #define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
262 #define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
263 #define SFR_R_MM_CAUSE env->pregs[PR_SRS]][3
264 #define SFR_RW_MM_TLB_SEL env->pregs[PR_SRS]][4
265 #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5
266 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6
267
268 #include "exec/cpu-all.h"
269
270 static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
271 target_ulong *cs_base, uint32_t *flags)
272 {
273 *pc = env->pc;
274 *cs_base = 0;
275 *flags = env->dslot |
276 (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
277 | X_FLAG | PFIX_FLAG));
278 }
279
280 #define cpu_list cris_cpu_list
281 void cris_cpu_list(void);
282
283 #endif