Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging
[qemu.git] / target / hppa / cpu.c
1 /*
2 * QEMU HPPA CPU
3 *
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu/qemu-print.h"
24 #include "cpu.h"
25 #include "qemu/module.h"
26 #include "exec/exec-all.h"
27 #include "fpu/softfloat.h"
28
29
30 static void hppa_cpu_set_pc(CPUState *cs, vaddr value)
31 {
32 HPPACPU *cpu = HPPA_CPU(cs);
33
34 cpu->env.iaoq_f = value;
35 cpu->env.iaoq_b = value + 4;
36 }
37
38 static void hppa_cpu_synchronize_from_tb(CPUState *cs,
39 const TranslationBlock *tb)
40 {
41 HPPACPU *cpu = HPPA_CPU(cs);
42
43 #ifdef CONFIG_USER_ONLY
44 cpu->env.iaoq_f = tb->pc;
45 cpu->env.iaoq_b = tb->cs_base;
46 #else
47 /* Recover the IAOQ values from the GVA + PRIV. */
48 uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3;
49 target_ulong cs_base = tb->cs_base;
50 target_ulong iasq_f = cs_base & ~0xffffffffull;
51 int32_t diff = cs_base;
52
53 cpu->env.iasq_f = iasq_f;
54 cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv;
55 if (diff) {
56 cpu->env.iaoq_b = cpu->env.iaoq_f + diff;
57 }
58 #endif
59
60 cpu->env.psw_n = (tb->flags & PSW_N) != 0;
61 }
62
63 static bool hppa_cpu_has_work(CPUState *cs)
64 {
65 return cs->interrupt_request & CPU_INTERRUPT_HARD;
66 }
67
68 static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
69 {
70 info->mach = bfd_mach_hppa20;
71 info->print_insn = print_insn_hppa;
72 }
73
74 #ifndef CONFIG_USER_ONLY
75 static void QEMU_NORETURN
76 hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
77 MMUAccessType access_type, int mmu_idx,
78 uintptr_t retaddr)
79 {
80 HPPACPU *cpu = HPPA_CPU(cs);
81 CPUHPPAState *env = &cpu->env;
82
83 cs->exception_index = EXCP_UNALIGN;
84 if (env->psw & PSW_Q) {
85 /* ??? Needs tweaking for hppa64. */
86 env->cr[CR_IOR] = addr;
87 env->cr[CR_ISR] = addr >> 32;
88 }
89
90 cpu_loop_exit_restore(cs, retaddr);
91 }
92 #endif /* CONFIG_USER_ONLY */
93
94 static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
95 {
96 CPUState *cs = CPU(dev);
97 HPPACPUClass *acc = HPPA_CPU_GET_CLASS(dev);
98 Error *local_err = NULL;
99
100 cpu_exec_realizefn(cs, &local_err);
101 if (local_err != NULL) {
102 error_propagate(errp, local_err);
103 return;
104 }
105
106 qemu_init_vcpu(cs);
107 acc->parent_realize(dev, errp);
108
109 #ifndef CONFIG_USER_ONLY
110 {
111 HPPACPU *cpu = HPPA_CPU(cs);
112 cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
113 hppa_cpu_alarm_timer, cpu);
114 }
115 #endif
116 }
117
118 static void hppa_cpu_initfn(Object *obj)
119 {
120 CPUState *cs = CPU(obj);
121 HPPACPU *cpu = HPPA_CPU(obj);
122 CPUHPPAState *env = &cpu->env;
123
124 cpu_set_cpustate_pointers(cpu);
125 cs->exception_index = -1;
126 cpu_hppa_loaded_fr0(env);
127 cpu_hppa_put_psw(env, PSW_W);
128 }
129
130 static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
131 {
132 return object_class_by_name(TYPE_HPPA_CPU);
133 }
134
135 #ifndef CONFIG_USER_ONLY
136 #include "hw/core/sysemu-cpu-ops.h"
137
138 static const struct SysemuCPUOps hppa_sysemu_ops = {
139 .get_phys_page_debug = hppa_cpu_get_phys_page_debug,
140 };
141 #endif
142
143 #include "hw/core/tcg-cpu-ops.h"
144
145 static const struct TCGCPUOps hppa_tcg_ops = {
146 .initialize = hppa_translate_init,
147 .synchronize_from_tb = hppa_cpu_synchronize_from_tb,
148
149 #ifndef CONFIG_USER_ONLY
150 .tlb_fill = hppa_cpu_tlb_fill,
151 .cpu_exec_interrupt = hppa_cpu_exec_interrupt,
152 .do_interrupt = hppa_cpu_do_interrupt,
153 .do_unaligned_access = hppa_cpu_do_unaligned_access,
154 #endif /* !CONFIG_USER_ONLY */
155 };
156
157 static void hppa_cpu_class_init(ObjectClass *oc, void *data)
158 {
159 DeviceClass *dc = DEVICE_CLASS(oc);
160 CPUClass *cc = CPU_CLASS(oc);
161 HPPACPUClass *acc = HPPA_CPU_CLASS(oc);
162
163 device_class_set_parent_realize(dc, hppa_cpu_realizefn,
164 &acc->parent_realize);
165
166 cc->class_by_name = hppa_cpu_class_by_name;
167 cc->has_work = hppa_cpu_has_work;
168 cc->dump_state = hppa_cpu_dump_state;
169 cc->set_pc = hppa_cpu_set_pc;
170 cc->gdb_read_register = hppa_cpu_gdb_read_register;
171 cc->gdb_write_register = hppa_cpu_gdb_write_register;
172 #ifndef CONFIG_USER_ONLY
173 dc->vmsd = &vmstate_hppa_cpu;
174 cc->sysemu_ops = &hppa_sysemu_ops;
175 #endif
176 cc->disas_set_info = hppa_cpu_disas_set_info;
177 cc->gdb_num_core_regs = 128;
178 cc->tcg_ops = &hppa_tcg_ops;
179 }
180
181 static const TypeInfo hppa_cpu_type_info = {
182 .name = TYPE_HPPA_CPU,
183 .parent = TYPE_CPU,
184 .instance_size = sizeof(HPPACPU),
185 .instance_init = hppa_cpu_initfn,
186 .abstract = false,
187 .class_size = sizeof(HPPACPUClass),
188 .class_init = hppa_cpu_class_init,
189 };
190
191 static void hppa_cpu_register_types(void)
192 {
193 type_register_static(&hppa_cpu_type_info);
194 }
195
196 type_init(hppa_cpu_register_types)