target/i386/cpu: Fix memleak in x86_cpu_class_check_missing_features
[qemu.git] / target / i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/bitops.h"
24 #include "qemu/qemu-print.h"
25
26 #include "cpu.h"
27 #include "exec/exec-all.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/reset.h"
30 #include "sysemu/hvf.h"
31 #include "sysemu/cpus.h"
32 #include "sysemu/xen.h"
33 #include "kvm_i386.h"
34 #include "sev_i386.h"
35
36 #include "qemu/error-report.h"
37 #include "qemu/module.h"
38 #include "qemu/option.h"
39 #include "qemu/config-file.h"
40 #include "qapi/error.h"
41 #include "qapi/qapi-visit-machine.h"
42 #include "qapi/qapi-visit-run-state.h"
43 #include "qapi/qmp/qdict.h"
44 #include "qapi/qmp/qerror.h"
45 #include "qapi/visitor.h"
46 #include "qom/qom-qobject.h"
47 #include "sysemu/arch_init.h"
48 #include "qapi/qapi-commands-machine-target.h"
49
50 #include "standard-headers/asm-x86/kvm_para.h"
51
52 #include "sysemu/sysemu.h"
53 #include "sysemu/tcg.h"
54 #include "hw/qdev-properties.h"
55 #include "hw/i386/topology.h"
56 #ifndef CONFIG_USER_ONLY
57 #include "exec/address-spaces.h"
58 #include "hw/i386/apic_internal.h"
59 #include "hw/boards.h"
60 #endif
61
62 #include "disas/capstone.h"
63
64 /* Helpers for building CPUID[2] descriptors: */
65
66 struct CPUID2CacheDescriptorInfo {
67 enum CacheType type;
68 int level;
69 int size;
70 int line_size;
71 int associativity;
72 };
73
74 /*
75 * Known CPUID 2 cache descriptors.
76 * From Intel SDM Volume 2A, CPUID instruction
77 */
78 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
79 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
80 .associativity = 4, .line_size = 32, },
81 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
82 .associativity = 4, .line_size = 32, },
83 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
84 .associativity = 4, .line_size = 64, },
85 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
86 .associativity = 2, .line_size = 32, },
87 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
88 .associativity = 4, .line_size = 32, },
89 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
90 .associativity = 4, .line_size = 64, },
91 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
92 .associativity = 6, .line_size = 64, },
93 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
94 .associativity = 2, .line_size = 64, },
95 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
96 .associativity = 8, .line_size = 64, },
97 /* lines per sector is not supported cpuid2_cache_descriptor(),
98 * so descriptors 0x22, 0x23 are not included
99 */
100 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
101 .associativity = 16, .line_size = 64, },
102 /* lines per sector is not supported cpuid2_cache_descriptor(),
103 * so descriptors 0x25, 0x20 are not included
104 */
105 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
106 .associativity = 8, .line_size = 64, },
107 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
108 .associativity = 8, .line_size = 64, },
109 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
110 .associativity = 4, .line_size = 32, },
111 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
112 .associativity = 4, .line_size = 32, },
113 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
114 .associativity = 4, .line_size = 32, },
115 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
116 .associativity = 4, .line_size = 32, },
117 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
118 .associativity = 4, .line_size = 32, },
119 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
120 .associativity = 4, .line_size = 64, },
121 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
122 .associativity = 8, .line_size = 64, },
123 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
124 .associativity = 12, .line_size = 64, },
125 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
126 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
127 .associativity = 12, .line_size = 64, },
128 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
129 .associativity = 16, .line_size = 64, },
130 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
131 .associativity = 12, .line_size = 64, },
132 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
133 .associativity = 16, .line_size = 64, },
134 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
135 .associativity = 24, .line_size = 64, },
136 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
137 .associativity = 8, .line_size = 64, },
138 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
139 .associativity = 4, .line_size = 64, },
140 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
141 .associativity = 4, .line_size = 64, },
142 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
143 .associativity = 4, .line_size = 64, },
144 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
145 .associativity = 4, .line_size = 64, },
146 /* lines per sector is not supported cpuid2_cache_descriptor(),
147 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
148 */
149 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
150 .associativity = 8, .line_size = 64, },
151 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
152 .associativity = 2, .line_size = 64, },
153 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
154 .associativity = 8, .line_size = 64, },
155 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
156 .associativity = 8, .line_size = 32, },
157 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
158 .associativity = 8, .line_size = 32, },
159 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
160 .associativity = 8, .line_size = 32, },
161 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
162 .associativity = 8, .line_size = 32, },
163 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
164 .associativity = 4, .line_size = 64, },
165 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
166 .associativity = 8, .line_size = 64, },
167 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
168 .associativity = 4, .line_size = 64, },
169 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
170 .associativity = 4, .line_size = 64, },
171 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
172 .associativity = 4, .line_size = 64, },
173 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
174 .associativity = 8, .line_size = 64, },
175 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
176 .associativity = 8, .line_size = 64, },
177 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
178 .associativity = 8, .line_size = 64, },
179 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
180 .associativity = 12, .line_size = 64, },
181 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
182 .associativity = 12, .line_size = 64, },
183 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
184 .associativity = 12, .line_size = 64, },
185 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
186 .associativity = 16, .line_size = 64, },
187 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
188 .associativity = 16, .line_size = 64, },
189 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
190 .associativity = 16, .line_size = 64, },
191 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
192 .associativity = 24, .line_size = 64, },
193 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
194 .associativity = 24, .line_size = 64, },
195 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
196 .associativity = 24, .line_size = 64, },
197 };
198
199 /*
200 * "CPUID leaf 2 does not report cache descriptor information,
201 * use CPUID leaf 4 to query cache parameters"
202 */
203 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
204
205 /*
206 * Return a CPUID 2 cache descriptor for a given cache.
207 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
208 */
209 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
210 {
211 int i;
212
213 assert(cache->size > 0);
214 assert(cache->level > 0);
215 assert(cache->line_size > 0);
216 assert(cache->associativity > 0);
217 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
218 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
219 if (d->level == cache->level && d->type == cache->type &&
220 d->size == cache->size && d->line_size == cache->line_size &&
221 d->associativity == cache->associativity) {
222 return i;
223 }
224 }
225
226 return CACHE_DESCRIPTOR_UNAVAILABLE;
227 }
228
229 /* CPUID Leaf 4 constants: */
230
231 /* EAX: */
232 #define CACHE_TYPE_D 1
233 #define CACHE_TYPE_I 2
234 #define CACHE_TYPE_UNIFIED 3
235
236 #define CACHE_LEVEL(l) (l << 5)
237
238 #define CACHE_SELF_INIT_LEVEL (1 << 8)
239
240 /* EDX: */
241 #define CACHE_NO_INVD_SHARING (1 << 0)
242 #define CACHE_INCLUSIVE (1 << 1)
243 #define CACHE_COMPLEX_IDX (1 << 2)
244
245 /* Encode CacheType for CPUID[4].EAX */
246 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
247 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
248 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
249 0 /* Invalid value */)
250
251
252 /* Encode cache info for CPUID[4] */
253 static void encode_cache_cpuid4(CPUCacheInfo *cache,
254 int num_apic_ids, int num_cores,
255 uint32_t *eax, uint32_t *ebx,
256 uint32_t *ecx, uint32_t *edx)
257 {
258 assert(cache->size == cache->line_size * cache->associativity *
259 cache->partitions * cache->sets);
260
261 assert(num_apic_ids > 0);
262 *eax = CACHE_TYPE(cache->type) |
263 CACHE_LEVEL(cache->level) |
264 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
265 ((num_cores - 1) << 26) |
266 ((num_apic_ids - 1) << 14);
267
268 assert(cache->line_size > 0);
269 assert(cache->partitions > 0);
270 assert(cache->associativity > 0);
271 /* We don't implement fully-associative caches */
272 assert(cache->associativity < cache->sets);
273 *ebx = (cache->line_size - 1) |
274 ((cache->partitions - 1) << 12) |
275 ((cache->associativity - 1) << 22);
276
277 assert(cache->sets > 0);
278 *ecx = cache->sets - 1;
279
280 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
281 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
282 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
283 }
284
285 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
286 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
287 {
288 assert(cache->size % 1024 == 0);
289 assert(cache->lines_per_tag > 0);
290 assert(cache->associativity > 0);
291 assert(cache->line_size > 0);
292 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
293 (cache->lines_per_tag << 8) | (cache->line_size);
294 }
295
296 #define ASSOC_FULL 0xFF
297
298 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
299 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
300 a == 2 ? 0x2 : \
301 a == 4 ? 0x4 : \
302 a == 8 ? 0x6 : \
303 a == 16 ? 0x8 : \
304 a == 32 ? 0xA : \
305 a == 48 ? 0xB : \
306 a == 64 ? 0xC : \
307 a == 96 ? 0xD : \
308 a == 128 ? 0xE : \
309 a == ASSOC_FULL ? 0xF : \
310 0 /* invalid value */)
311
312 /*
313 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
314 * @l3 can be NULL.
315 */
316 static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
317 CPUCacheInfo *l3,
318 uint32_t *ecx, uint32_t *edx)
319 {
320 assert(l2->size % 1024 == 0);
321 assert(l2->associativity > 0);
322 assert(l2->lines_per_tag > 0);
323 assert(l2->line_size > 0);
324 *ecx = ((l2->size / 1024) << 16) |
325 (AMD_ENC_ASSOC(l2->associativity) << 12) |
326 (l2->lines_per_tag << 8) | (l2->line_size);
327
328 if (l3) {
329 assert(l3->size % (512 * 1024) == 0);
330 assert(l3->associativity > 0);
331 assert(l3->lines_per_tag > 0);
332 assert(l3->line_size > 0);
333 *edx = ((l3->size / (512 * 1024)) << 18) |
334 (AMD_ENC_ASSOC(l3->associativity) << 12) |
335 (l3->lines_per_tag << 8) | (l3->line_size);
336 } else {
337 *edx = 0;
338 }
339 }
340
341 /*
342 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
343 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
344 * Define the constants to build the cpu topology. Right now, TOPOEXT
345 * feature is enabled only on EPYC. So, these constants are based on
346 * EPYC supported configurations. We may need to handle the cases if
347 * these values change in future.
348 */
349 /* Maximum core complexes in a node */
350 #define MAX_CCX 2
351 /* Maximum cores in a core complex */
352 #define MAX_CORES_IN_CCX 4
353 /* Maximum cores in a node */
354 #define MAX_CORES_IN_NODE 8
355 /* Maximum nodes in a socket */
356 #define MAX_NODES_PER_SOCKET 4
357
358 /*
359 * Figure out the number of nodes required to build this config.
360 * Max cores in a node is 8
361 */
362 static int nodes_in_socket(int nr_cores)
363 {
364 int nodes;
365
366 nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
367
368 /* Hardware does not support config with 3 nodes, return 4 in that case */
369 return (nodes == 3) ? 4 : nodes;
370 }
371
372 /*
373 * Decide the number of cores in a core complex with the given nr_cores using
374 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
375 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
376 * L3 cache is shared across all cores in a core complex. So, this will also
377 * tell us how many cores are sharing the L3 cache.
378 */
379 static int cores_in_core_complex(int nr_cores)
380 {
381 int nodes;
382
383 /* Check if we can fit all the cores in one core complex */
384 if (nr_cores <= MAX_CORES_IN_CCX) {
385 return nr_cores;
386 }
387 /* Get the number of nodes required to build this config */
388 nodes = nodes_in_socket(nr_cores);
389
390 /*
391 * Divide the cores accros all the core complexes
392 * Return rounded up value
393 */
394 return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
395 }
396
397 /* Encode cache info for CPUID[8000001D] */
398 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
399 uint32_t *eax, uint32_t *ebx,
400 uint32_t *ecx, uint32_t *edx)
401 {
402 uint32_t l3_cores;
403 assert(cache->size == cache->line_size * cache->associativity *
404 cache->partitions * cache->sets);
405
406 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
407 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
408
409 /* L3 is shared among multiple cores */
410 if (cache->level == 3) {
411 l3_cores = cores_in_core_complex(cs->nr_cores);
412 *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
413 } else {
414 *eax |= ((cs->nr_threads - 1) << 14);
415 }
416
417 assert(cache->line_size > 0);
418 assert(cache->partitions > 0);
419 assert(cache->associativity > 0);
420 /* We don't implement fully-associative caches */
421 assert(cache->associativity < cache->sets);
422 *ebx = (cache->line_size - 1) |
423 ((cache->partitions - 1) << 12) |
424 ((cache->associativity - 1) << 22);
425
426 assert(cache->sets > 0);
427 *ecx = cache->sets - 1;
428
429 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
430 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
431 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
432 }
433
434 /* Data structure to hold the configuration info for a given core index */
435 struct core_topology {
436 /* core complex id of the current core index */
437 int ccx_id;
438 /*
439 * Adjusted core index for this core in the topology
440 * This can be 0,1,2,3 with max 4 cores in a core complex
441 */
442 int core_id;
443 /* Node id for this core index */
444 int node_id;
445 /* Number of nodes in this config */
446 int num_nodes;
447 };
448
449 /*
450 * Build the configuration closely match the EPYC hardware. Using the EPYC
451 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
452 * right now. This could change in future.
453 * nr_cores : Total number of cores in the config
454 * core_id : Core index of the current CPU
455 * topo : Data structure to hold all the config info for this core index
456 */
457 static void build_core_topology(int nr_cores, int core_id,
458 struct core_topology *topo)
459 {
460 int nodes, cores_in_ccx;
461
462 /* First get the number of nodes required */
463 nodes = nodes_in_socket(nr_cores);
464
465 cores_in_ccx = cores_in_core_complex(nr_cores);
466
467 topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
468 topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
469 topo->core_id = core_id % cores_in_ccx;
470 topo->num_nodes = nodes;
471 }
472
473 /* Encode cache info for CPUID[8000001E] */
474 static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
475 uint32_t *eax, uint32_t *ebx,
476 uint32_t *ecx, uint32_t *edx)
477 {
478 struct core_topology topo = {0};
479 unsigned long nodes;
480 int shift;
481
482 build_core_topology(cs->nr_cores, cpu->core_id, &topo);
483 *eax = cpu->apic_id;
484 /*
485 * CPUID_Fn8000001E_EBX
486 * 31:16 Reserved
487 * 15:8 Threads per core (The number of threads per core is
488 * Threads per core + 1)
489 * 7:0 Core id (see bit decoding below)
490 * SMT:
491 * 4:3 node id
492 * 2 Core complex id
493 * 1:0 Core id
494 * Non SMT:
495 * 5:4 node id
496 * 3 Core complex id
497 * 1:0 Core id
498 */
499 if (cs->nr_threads - 1) {
500 *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
501 (topo.ccx_id << 2) | topo.core_id;
502 } else {
503 *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
504 }
505 /*
506 * CPUID_Fn8000001E_ECX
507 * 31:11 Reserved
508 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
509 * 7:0 Node id (see bit decoding below)
510 * 2 Socket id
511 * 1:0 Node id
512 */
513 if (topo.num_nodes <= 4) {
514 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
515 topo.node_id;
516 } else {
517 /*
518 * Node id fix up. Actual hardware supports up to 4 nodes. But with
519 * more than 32 cores, we may end up with more than 4 nodes.
520 * Node id is a combination of socket id and node id. Only requirement
521 * here is that this number should be unique accross the system.
522 * Shift the socket id to accommodate more nodes. We dont expect both
523 * socket id and node id to be big number at the same time. This is not
524 * an ideal config but we need to to support it. Max nodes we can have
525 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
526 * 5 bits for nodes. Find the left most set bit to represent the total
527 * number of nodes. find_last_bit returns last set bit(0 based). Left
528 * shift(+1) the socket id to represent all the nodes.
529 */
530 nodes = topo.num_nodes - 1;
531 shift = find_last_bit(&nodes, 8);
532 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
533 topo.node_id;
534 }
535 *edx = 0;
536 }
537
538 /*
539 * Definitions of the hardcoded cache entries we expose:
540 * These are legacy cache values. If there is a need to change any
541 * of these values please use builtin_x86_defs
542 */
543
544 /* L1 data cache: */
545 static CPUCacheInfo legacy_l1d_cache = {
546 .type = DATA_CACHE,
547 .level = 1,
548 .size = 32 * KiB,
549 .self_init = 1,
550 .line_size = 64,
551 .associativity = 8,
552 .sets = 64,
553 .partitions = 1,
554 .no_invd_sharing = true,
555 };
556
557 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
558 static CPUCacheInfo legacy_l1d_cache_amd = {
559 .type = DATA_CACHE,
560 .level = 1,
561 .size = 64 * KiB,
562 .self_init = 1,
563 .line_size = 64,
564 .associativity = 2,
565 .sets = 512,
566 .partitions = 1,
567 .lines_per_tag = 1,
568 .no_invd_sharing = true,
569 };
570
571 /* L1 instruction cache: */
572 static CPUCacheInfo legacy_l1i_cache = {
573 .type = INSTRUCTION_CACHE,
574 .level = 1,
575 .size = 32 * KiB,
576 .self_init = 1,
577 .line_size = 64,
578 .associativity = 8,
579 .sets = 64,
580 .partitions = 1,
581 .no_invd_sharing = true,
582 };
583
584 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
585 static CPUCacheInfo legacy_l1i_cache_amd = {
586 .type = INSTRUCTION_CACHE,
587 .level = 1,
588 .size = 64 * KiB,
589 .self_init = 1,
590 .line_size = 64,
591 .associativity = 2,
592 .sets = 512,
593 .partitions = 1,
594 .lines_per_tag = 1,
595 .no_invd_sharing = true,
596 };
597
598 /* Level 2 unified cache: */
599 static CPUCacheInfo legacy_l2_cache = {
600 .type = UNIFIED_CACHE,
601 .level = 2,
602 .size = 4 * MiB,
603 .self_init = 1,
604 .line_size = 64,
605 .associativity = 16,
606 .sets = 4096,
607 .partitions = 1,
608 .no_invd_sharing = true,
609 };
610
611 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
612 static CPUCacheInfo legacy_l2_cache_cpuid2 = {
613 .type = UNIFIED_CACHE,
614 .level = 2,
615 .size = 2 * MiB,
616 .line_size = 64,
617 .associativity = 8,
618 };
619
620
621 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
622 static CPUCacheInfo legacy_l2_cache_amd = {
623 .type = UNIFIED_CACHE,
624 .level = 2,
625 .size = 512 * KiB,
626 .line_size = 64,
627 .lines_per_tag = 1,
628 .associativity = 16,
629 .sets = 512,
630 .partitions = 1,
631 };
632
633 /* Level 3 unified cache: */
634 static CPUCacheInfo legacy_l3_cache = {
635 .type = UNIFIED_CACHE,
636 .level = 3,
637 .size = 16 * MiB,
638 .line_size = 64,
639 .associativity = 16,
640 .sets = 16384,
641 .partitions = 1,
642 .lines_per_tag = 1,
643 .self_init = true,
644 .inclusive = true,
645 .complex_indexing = true,
646 };
647
648 /* TLB definitions: */
649
650 #define L1_DTLB_2M_ASSOC 1
651 #define L1_DTLB_2M_ENTRIES 255
652 #define L1_DTLB_4K_ASSOC 1
653 #define L1_DTLB_4K_ENTRIES 255
654
655 #define L1_ITLB_2M_ASSOC 1
656 #define L1_ITLB_2M_ENTRIES 255
657 #define L1_ITLB_4K_ASSOC 1
658 #define L1_ITLB_4K_ENTRIES 255
659
660 #define L2_DTLB_2M_ASSOC 0 /* disabled */
661 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
662 #define L2_DTLB_4K_ASSOC 4
663 #define L2_DTLB_4K_ENTRIES 512
664
665 #define L2_ITLB_2M_ASSOC 0 /* disabled */
666 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
667 #define L2_ITLB_4K_ASSOC 4
668 #define L2_ITLB_4K_ENTRIES 512
669
670 /* CPUID Leaf 0x14 constants: */
671 #define INTEL_PT_MAX_SUBLEAF 0x1
672 /*
673 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
674 * MSR can be accessed;
675 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
676 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
677 * of Intel PT MSRs across warm reset;
678 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
679 */
680 #define INTEL_PT_MINIMAL_EBX 0xf
681 /*
682 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
683 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
684 * accessed;
685 * bit[01]: ToPA tables can hold any number of output entries, up to the
686 * maximum allowed by the MaskOrTableOffset field of
687 * IA32_RTIT_OUTPUT_MASK_PTRS;
688 * bit[02]: Support Single-Range Output scheme;
689 */
690 #define INTEL_PT_MINIMAL_ECX 0x7
691 /* generated packets which contain IP payloads have LIP values */
692 #define INTEL_PT_IP_LIP (1 << 31)
693 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
694 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
695 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
696 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
697 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
698
699 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
700 uint32_t vendor2, uint32_t vendor3)
701 {
702 int i;
703 for (i = 0; i < 4; i++) {
704 dst[i] = vendor1 >> (8 * i);
705 dst[i + 4] = vendor2 >> (8 * i);
706 dst[i + 8] = vendor3 >> (8 * i);
707 }
708 dst[CPUID_VENDOR_SZ] = '\0';
709 }
710
711 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
712 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
713 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
714 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
715 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
716 CPUID_PSE36 | CPUID_FXSR)
717 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
718 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
719 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
720 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
721 CPUID_PAE | CPUID_SEP | CPUID_APIC)
722
723 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
724 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
725 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
726 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
727 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
728 /* partly implemented:
729 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
730 /* missing:
731 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
732 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
733 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
734 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
735 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
736 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
737 CPUID_EXT_RDRAND)
738 /* missing:
739 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
740 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
741 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
742 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
743 CPUID_EXT_F16C */
744
745 #ifdef TARGET_X86_64
746 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
747 #else
748 #define TCG_EXT2_X86_64_FEATURES 0
749 #endif
750
751 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
752 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
753 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
754 TCG_EXT2_X86_64_FEATURES)
755 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
756 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
757 #define TCG_EXT4_FEATURES 0
758 #define TCG_SVM_FEATURES CPUID_SVM_NPT
759 #define TCG_KVM_FEATURES 0
760 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
761 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
762 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
763 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
764 CPUID_7_0_EBX_ERMS)
765 /* missing:
766 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
767 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
768 CPUID_7_0_EBX_RDSEED */
769 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
770 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
771 CPUID_7_0_ECX_LA57)
772 #define TCG_7_0_EDX_FEATURES 0
773 #define TCG_7_1_EAX_FEATURES 0
774 #define TCG_APM_FEATURES 0
775 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
776 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
777 /* missing:
778 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
779
780 typedef enum FeatureWordType {
781 CPUID_FEATURE_WORD,
782 MSR_FEATURE_WORD,
783 } FeatureWordType;
784
785 typedef struct FeatureWordInfo {
786 FeatureWordType type;
787 /* feature flags names are taken from "Intel Processor Identification and
788 * the CPUID Instruction" and AMD's "CPUID Specification".
789 * In cases of disagreement between feature naming conventions,
790 * aliases may be added.
791 */
792 const char *feat_names[64];
793 union {
794 /* If type==CPUID_FEATURE_WORD */
795 struct {
796 uint32_t eax; /* Input EAX for CPUID */
797 bool needs_ecx; /* CPUID instruction uses ECX as input */
798 uint32_t ecx; /* Input ECX value for CPUID */
799 int reg; /* output register (R_* constant) */
800 } cpuid;
801 /* If type==MSR_FEATURE_WORD */
802 struct {
803 uint32_t index;
804 } msr;
805 };
806 uint64_t tcg_features; /* Feature flags supported by TCG */
807 uint64_t unmigratable_flags; /* Feature flags known to be unmigratable */
808 uint64_t migratable_flags; /* Feature flags known to be migratable */
809 /* Features that shouldn't be auto-enabled by "-cpu host" */
810 uint64_t no_autoenable_flags;
811 } FeatureWordInfo;
812
813 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
814 [FEAT_1_EDX] = {
815 .type = CPUID_FEATURE_WORD,
816 .feat_names = {
817 "fpu", "vme", "de", "pse",
818 "tsc", "msr", "pae", "mce",
819 "cx8", "apic", NULL, "sep",
820 "mtrr", "pge", "mca", "cmov",
821 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
822 NULL, "ds" /* Intel dts */, "acpi", "mmx",
823 "fxsr", "sse", "sse2", "ss",
824 "ht" /* Intel htt */, "tm", "ia64", "pbe",
825 },
826 .cpuid = {.eax = 1, .reg = R_EDX, },
827 .tcg_features = TCG_FEATURES,
828 },
829 [FEAT_1_ECX] = {
830 .type = CPUID_FEATURE_WORD,
831 .feat_names = {
832 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
833 "ds-cpl", "vmx", "smx", "est",
834 "tm2", "ssse3", "cid", NULL,
835 "fma", "cx16", "xtpr", "pdcm",
836 NULL, "pcid", "dca", "sse4.1",
837 "sse4.2", "x2apic", "movbe", "popcnt",
838 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
839 "avx", "f16c", "rdrand", "hypervisor",
840 },
841 .cpuid = { .eax = 1, .reg = R_ECX, },
842 .tcg_features = TCG_EXT_FEATURES,
843 },
844 /* Feature names that are already defined on feature_name[] but
845 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
846 * names on feat_names below. They are copied automatically
847 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
848 */
849 [FEAT_8000_0001_EDX] = {
850 .type = CPUID_FEATURE_WORD,
851 .feat_names = {
852 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
853 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
854 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
855 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
856 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
857 "nx", NULL, "mmxext", NULL /* mmx */,
858 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
859 NULL, "lm", "3dnowext", "3dnow",
860 },
861 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
862 .tcg_features = TCG_EXT2_FEATURES,
863 },
864 [FEAT_8000_0001_ECX] = {
865 .type = CPUID_FEATURE_WORD,
866 .feat_names = {
867 "lahf-lm", "cmp-legacy", "svm", "extapic",
868 "cr8legacy", "abm", "sse4a", "misalignsse",
869 "3dnowprefetch", "osvw", "ibs", "xop",
870 "skinit", "wdt", NULL, "lwp",
871 "fma4", "tce", NULL, "nodeid-msr",
872 NULL, "tbm", "topoext", "perfctr-core",
873 "perfctr-nb", NULL, NULL, NULL,
874 NULL, NULL, NULL, NULL,
875 },
876 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
877 .tcg_features = TCG_EXT3_FEATURES,
878 /*
879 * TOPOEXT is always allowed but can't be enabled blindly by
880 * "-cpu host", as it requires consistent cache topology info
881 * to be provided so it doesn't confuse guests.
882 */
883 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
884 },
885 [FEAT_C000_0001_EDX] = {
886 .type = CPUID_FEATURE_WORD,
887 .feat_names = {
888 NULL, NULL, "xstore", "xstore-en",
889 NULL, NULL, "xcrypt", "xcrypt-en",
890 "ace2", "ace2-en", "phe", "phe-en",
891 "pmm", "pmm-en", NULL, NULL,
892 NULL, NULL, NULL, NULL,
893 NULL, NULL, NULL, NULL,
894 NULL, NULL, NULL, NULL,
895 NULL, NULL, NULL, NULL,
896 },
897 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
898 .tcg_features = TCG_EXT4_FEATURES,
899 },
900 [FEAT_KVM] = {
901 .type = CPUID_FEATURE_WORD,
902 .feat_names = {
903 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
904 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
905 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
906 "kvm-poll-control", "kvm-pv-sched-yield", NULL, NULL,
907 NULL, NULL, NULL, NULL,
908 NULL, NULL, NULL, NULL,
909 "kvmclock-stable-bit", NULL, NULL, NULL,
910 NULL, NULL, NULL, NULL,
911 },
912 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
913 .tcg_features = TCG_KVM_FEATURES,
914 },
915 [FEAT_KVM_HINTS] = {
916 .type = CPUID_FEATURE_WORD,
917 .feat_names = {
918 "kvm-hint-dedicated", NULL, NULL, NULL,
919 NULL, NULL, NULL, NULL,
920 NULL, NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 NULL, NULL, NULL, NULL,
924 NULL, NULL, NULL, NULL,
925 NULL, NULL, NULL, NULL,
926 },
927 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
928 .tcg_features = TCG_KVM_FEATURES,
929 /*
930 * KVM hints aren't auto-enabled by -cpu host, they need to be
931 * explicitly enabled in the command-line.
932 */
933 .no_autoenable_flags = ~0U,
934 },
935 /*
936 * .feat_names are commented out for Hyper-V enlightenments because we
937 * don't want to have two different ways for enabling them on QEMU command
938 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
939 * enabling several feature bits simultaneously, exposing these bits
940 * individually may just confuse guests.
941 */
942 [FEAT_HYPERV_EAX] = {
943 .type = CPUID_FEATURE_WORD,
944 .feat_names = {
945 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
946 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
947 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
948 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
949 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
950 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
951 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
952 NULL, NULL,
953 NULL, NULL, NULL, NULL,
954 NULL, NULL, NULL, NULL,
955 NULL, NULL, NULL, NULL,
956 NULL, NULL, NULL, NULL,
957 },
958 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
959 },
960 [FEAT_HYPERV_EBX] = {
961 .type = CPUID_FEATURE_WORD,
962 .feat_names = {
963 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
964 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
965 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
966 NULL /* hv_create_port */, NULL /* hv_connect_port */,
967 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
968 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
969 NULL, NULL,
970 NULL, NULL, NULL, NULL,
971 NULL, NULL, NULL, NULL,
972 NULL, NULL, NULL, NULL,
973 NULL, NULL, NULL, NULL,
974 },
975 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
976 },
977 [FEAT_HYPERV_EDX] = {
978 .type = CPUID_FEATURE_WORD,
979 .feat_names = {
980 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
981 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
982 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
983 NULL, NULL,
984 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
985 NULL, NULL, NULL, NULL,
986 NULL, NULL, NULL, NULL,
987 NULL, NULL, NULL, NULL,
988 NULL, NULL, NULL, NULL,
989 NULL, NULL, NULL, NULL,
990 },
991 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
992 },
993 [FEAT_HV_RECOMM_EAX] = {
994 .type = CPUID_FEATURE_WORD,
995 .feat_names = {
996 NULL /* hv_recommend_pv_as_switch */,
997 NULL /* hv_recommend_pv_tlbflush_local */,
998 NULL /* hv_recommend_pv_tlbflush_remote */,
999 NULL /* hv_recommend_msr_apic_access */,
1000 NULL /* hv_recommend_msr_reset */,
1001 NULL /* hv_recommend_relaxed_timing */,
1002 NULL /* hv_recommend_dma_remapping */,
1003 NULL /* hv_recommend_int_remapping */,
1004 NULL /* hv_recommend_x2apic_msrs */,
1005 NULL /* hv_recommend_autoeoi_deprecation */,
1006 NULL /* hv_recommend_pv_ipi */,
1007 NULL /* hv_recommend_ex_hypercalls */,
1008 NULL /* hv_hypervisor_is_nested */,
1009 NULL /* hv_recommend_int_mbec */,
1010 NULL /* hv_recommend_evmcs */,
1011 NULL,
1012 NULL, NULL, NULL, NULL,
1013 NULL, NULL, NULL, NULL,
1014 NULL, NULL, NULL, NULL,
1015 NULL, NULL, NULL, NULL,
1016 },
1017 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
1018 },
1019 [FEAT_HV_NESTED_EAX] = {
1020 .type = CPUID_FEATURE_WORD,
1021 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
1022 },
1023 [FEAT_SVM] = {
1024 .type = CPUID_FEATURE_WORD,
1025 .feat_names = {
1026 "npt", "lbrv", "svm-lock", "nrip-save",
1027 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1028 NULL, NULL, "pause-filter", NULL,
1029 "pfthreshold", NULL, NULL, NULL,
1030 NULL, NULL, NULL, NULL,
1031 NULL, NULL, NULL, NULL,
1032 NULL, NULL, NULL, NULL,
1033 NULL, NULL, NULL, NULL,
1034 },
1035 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
1036 .tcg_features = TCG_SVM_FEATURES,
1037 },
1038 [FEAT_7_0_EBX] = {
1039 .type = CPUID_FEATURE_WORD,
1040 .feat_names = {
1041 "fsgsbase", "tsc-adjust", NULL, "bmi1",
1042 "hle", "avx2", NULL, "smep",
1043 "bmi2", "erms", "invpcid", "rtm",
1044 NULL, NULL, "mpx", NULL,
1045 "avx512f", "avx512dq", "rdseed", "adx",
1046 "smap", "avx512ifma", "pcommit", "clflushopt",
1047 "clwb", "intel-pt", "avx512pf", "avx512er",
1048 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
1049 },
1050 .cpuid = {
1051 .eax = 7,
1052 .needs_ecx = true, .ecx = 0,
1053 .reg = R_EBX,
1054 },
1055 .tcg_features = TCG_7_0_EBX_FEATURES,
1056 },
1057 [FEAT_7_0_ECX] = {
1058 .type = CPUID_FEATURE_WORD,
1059 .feat_names = {
1060 NULL, "avx512vbmi", "umip", "pku",
1061 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
1062 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1063 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
1064 "la57", NULL, NULL, NULL,
1065 NULL, NULL, "rdpid", NULL,
1066 NULL, "cldemote", NULL, "movdiri",
1067 "movdir64b", NULL, NULL, NULL,
1068 },
1069 .cpuid = {
1070 .eax = 7,
1071 .needs_ecx = true, .ecx = 0,
1072 .reg = R_ECX,
1073 },
1074 .tcg_features = TCG_7_0_ECX_FEATURES,
1075 },
1076 [FEAT_7_0_EDX] = {
1077 .type = CPUID_FEATURE_WORD,
1078 .feat_names = {
1079 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1080 "fsrm", NULL, NULL, NULL,
1081 "avx512-vp2intersect", NULL, "md-clear", NULL,
1082 NULL, NULL, "serialize", NULL,
1083 "tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
1084 NULL, NULL, NULL, NULL,
1085 NULL, NULL, "spec-ctrl", "stibp",
1086 NULL, "arch-capabilities", "core-capability", "ssbd",
1087 },
1088 .cpuid = {
1089 .eax = 7,
1090 .needs_ecx = true, .ecx = 0,
1091 .reg = R_EDX,
1092 },
1093 .tcg_features = TCG_7_0_EDX_FEATURES,
1094 },
1095 [FEAT_7_1_EAX] = {
1096 .type = CPUID_FEATURE_WORD,
1097 .feat_names = {
1098 NULL, NULL, NULL, NULL,
1099 NULL, "avx512-bf16", NULL, NULL,
1100 NULL, NULL, NULL, NULL,
1101 NULL, NULL, NULL, NULL,
1102 NULL, NULL, NULL, NULL,
1103 NULL, NULL, NULL, NULL,
1104 NULL, NULL, NULL, NULL,
1105 NULL, NULL, NULL, NULL,
1106 },
1107 .cpuid = {
1108 .eax = 7,
1109 .needs_ecx = true, .ecx = 1,
1110 .reg = R_EAX,
1111 },
1112 .tcg_features = TCG_7_1_EAX_FEATURES,
1113 },
1114 [FEAT_8000_0007_EDX] = {
1115 .type = CPUID_FEATURE_WORD,
1116 .feat_names = {
1117 NULL, NULL, NULL, NULL,
1118 NULL, NULL, NULL, NULL,
1119 "invtsc", NULL, NULL, NULL,
1120 NULL, NULL, NULL, NULL,
1121 NULL, NULL, NULL, NULL,
1122 NULL, NULL, NULL, NULL,
1123 NULL, NULL, NULL, NULL,
1124 NULL, NULL, NULL, NULL,
1125 },
1126 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
1127 .tcg_features = TCG_APM_FEATURES,
1128 .unmigratable_flags = CPUID_APM_INVTSC,
1129 },
1130 [FEAT_8000_0008_EBX] = {
1131 .type = CPUID_FEATURE_WORD,
1132 .feat_names = {
1133 "clzero", NULL, "xsaveerptr", NULL,
1134 NULL, NULL, NULL, NULL,
1135 NULL, "wbnoinvd", NULL, NULL,
1136 "ibpb", NULL, NULL, "amd-stibp",
1137 NULL, NULL, NULL, NULL,
1138 NULL, NULL, NULL, NULL,
1139 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1140 NULL, NULL, NULL, NULL,
1141 },
1142 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1143 .tcg_features = 0,
1144 .unmigratable_flags = 0,
1145 },
1146 [FEAT_XSAVE] = {
1147 .type = CPUID_FEATURE_WORD,
1148 .feat_names = {
1149 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1150 NULL, NULL, NULL, NULL,
1151 NULL, NULL, NULL, NULL,
1152 NULL, NULL, NULL, NULL,
1153 NULL, NULL, NULL, NULL,
1154 NULL, NULL, NULL, NULL,
1155 NULL, NULL, NULL, NULL,
1156 NULL, NULL, NULL, NULL,
1157 },
1158 .cpuid = {
1159 .eax = 0xd,
1160 .needs_ecx = true, .ecx = 1,
1161 .reg = R_EAX,
1162 },
1163 .tcg_features = TCG_XSAVE_FEATURES,
1164 },
1165 [FEAT_6_EAX] = {
1166 .type = CPUID_FEATURE_WORD,
1167 .feat_names = {
1168 NULL, NULL, "arat", NULL,
1169 NULL, NULL, NULL, NULL,
1170 NULL, NULL, NULL, NULL,
1171 NULL, NULL, NULL, NULL,
1172 NULL, NULL, NULL, NULL,
1173 NULL, NULL, NULL, NULL,
1174 NULL, NULL, NULL, NULL,
1175 NULL, NULL, NULL, NULL,
1176 },
1177 .cpuid = { .eax = 6, .reg = R_EAX, },
1178 .tcg_features = TCG_6_EAX_FEATURES,
1179 },
1180 [FEAT_XSAVE_COMP_LO] = {
1181 .type = CPUID_FEATURE_WORD,
1182 .cpuid = {
1183 .eax = 0xD,
1184 .needs_ecx = true, .ecx = 0,
1185 .reg = R_EAX,
1186 },
1187 .tcg_features = ~0U,
1188 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1189 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1190 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1191 XSTATE_PKRU_MASK,
1192 },
1193 [FEAT_XSAVE_COMP_HI] = {
1194 .type = CPUID_FEATURE_WORD,
1195 .cpuid = {
1196 .eax = 0xD,
1197 .needs_ecx = true, .ecx = 0,
1198 .reg = R_EDX,
1199 },
1200 .tcg_features = ~0U,
1201 },
1202 /*Below are MSR exposed features*/
1203 [FEAT_ARCH_CAPABILITIES] = {
1204 .type = MSR_FEATURE_WORD,
1205 .feat_names = {
1206 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1207 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
1208 "taa-no", NULL, NULL, NULL,
1209 NULL, NULL, NULL, NULL,
1210 NULL, NULL, NULL, NULL,
1211 NULL, NULL, NULL, NULL,
1212 NULL, NULL, NULL, NULL,
1213 NULL, NULL, NULL, NULL,
1214 },
1215 .msr = {
1216 .index = MSR_IA32_ARCH_CAPABILITIES,
1217 },
1218 },
1219 [FEAT_CORE_CAPABILITY] = {
1220 .type = MSR_FEATURE_WORD,
1221 .feat_names = {
1222 NULL, NULL, NULL, NULL,
1223 NULL, "split-lock-detect", NULL, NULL,
1224 NULL, NULL, NULL, NULL,
1225 NULL, NULL, NULL, NULL,
1226 NULL, NULL, NULL, NULL,
1227 NULL, NULL, NULL, NULL,
1228 NULL, NULL, NULL, NULL,
1229 NULL, NULL, NULL, NULL,
1230 },
1231 .msr = {
1232 .index = MSR_IA32_CORE_CAPABILITY,
1233 },
1234 },
1235 [FEAT_PERF_CAPABILITIES] = {
1236 .type = MSR_FEATURE_WORD,
1237 .feat_names = {
1238 NULL, NULL, NULL, NULL,
1239 NULL, NULL, NULL, NULL,
1240 NULL, NULL, NULL, NULL,
1241 NULL, "full-width-write", NULL, NULL,
1242 NULL, NULL, NULL, NULL,
1243 NULL, NULL, NULL, NULL,
1244 NULL, NULL, NULL, NULL,
1245 NULL, NULL, NULL, NULL,
1246 },
1247 .msr = {
1248 .index = MSR_IA32_PERF_CAPABILITIES,
1249 },
1250 },
1251
1252 [FEAT_VMX_PROCBASED_CTLS] = {
1253 .type = MSR_FEATURE_WORD,
1254 .feat_names = {
1255 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1256 NULL, NULL, NULL, "vmx-hlt-exit",
1257 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1258 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1259 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1260 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1261 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1262 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1263 },
1264 .msr = {
1265 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1266 }
1267 },
1268
1269 [FEAT_VMX_SECONDARY_CTLS] = {
1270 .type = MSR_FEATURE_WORD,
1271 .feat_names = {
1272 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1273 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1274 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1275 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1276 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1277 "vmx-xsaves", NULL, NULL, NULL,
1278 NULL, NULL, NULL, NULL,
1279 NULL, NULL, NULL, NULL,
1280 },
1281 .msr = {
1282 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1283 }
1284 },
1285
1286 [FEAT_VMX_PINBASED_CTLS] = {
1287 .type = MSR_FEATURE_WORD,
1288 .feat_names = {
1289 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1290 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1291 NULL, NULL, NULL, NULL,
1292 NULL, NULL, NULL, NULL,
1293 NULL, NULL, NULL, NULL,
1294 NULL, NULL, NULL, NULL,
1295 NULL, NULL, NULL, NULL,
1296 NULL, NULL, NULL, NULL,
1297 },
1298 .msr = {
1299 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1300 }
1301 },
1302
1303 [FEAT_VMX_EXIT_CTLS] = {
1304 .type = MSR_FEATURE_WORD,
1305 /*
1306 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1307 * the LM CPUID bit.
1308 */
1309 .feat_names = {
1310 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1311 NULL, NULL, NULL, NULL,
1312 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1313 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1314 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1315 "vmx-exit-save-efer", "vmx-exit-load-efer",
1316 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1317 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
1318 NULL, NULL, NULL, NULL,
1319 },
1320 .msr = {
1321 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1322 }
1323 },
1324
1325 [FEAT_VMX_ENTRY_CTLS] = {
1326 .type = MSR_FEATURE_WORD,
1327 .feat_names = {
1328 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1329 NULL, NULL, NULL, NULL,
1330 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1331 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1332 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
1333 NULL, NULL, NULL, NULL,
1334 NULL, NULL, NULL, NULL,
1335 NULL, NULL, NULL, NULL,
1336 },
1337 .msr = {
1338 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1339 }
1340 },
1341
1342 [FEAT_VMX_MISC] = {
1343 .type = MSR_FEATURE_WORD,
1344 .feat_names = {
1345 NULL, NULL, NULL, NULL,
1346 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1347 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1348 NULL, NULL, NULL, NULL,
1349 NULL, NULL, NULL, NULL,
1350 NULL, NULL, NULL, NULL,
1351 NULL, NULL, NULL, NULL,
1352 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1353 },
1354 .msr = {
1355 .index = MSR_IA32_VMX_MISC,
1356 }
1357 },
1358
1359 [FEAT_VMX_EPT_VPID_CAPS] = {
1360 .type = MSR_FEATURE_WORD,
1361 .feat_names = {
1362 "vmx-ept-execonly", NULL, NULL, NULL,
1363 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1364 NULL, NULL, NULL, NULL,
1365 NULL, NULL, NULL, NULL,
1366 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1367 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1368 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1369 NULL, NULL, NULL, NULL,
1370 "vmx-invvpid", NULL, NULL, NULL,
1371 NULL, NULL, NULL, NULL,
1372 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1373 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1374 NULL, NULL, NULL, NULL,
1375 NULL, NULL, NULL, NULL,
1376 NULL, NULL, NULL, NULL,
1377 NULL, NULL, NULL, NULL,
1378 NULL, NULL, NULL, NULL,
1379 },
1380 .msr = {
1381 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1382 }
1383 },
1384
1385 [FEAT_VMX_BASIC] = {
1386 .type = MSR_FEATURE_WORD,
1387 .feat_names = {
1388 [54] = "vmx-ins-outs",
1389 [55] = "vmx-true-ctls",
1390 },
1391 .msr = {
1392 .index = MSR_IA32_VMX_BASIC,
1393 },
1394 /* Just to be safe - we don't support setting the MSEG version field. */
1395 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1396 },
1397
1398 [FEAT_VMX_VMFUNC] = {
1399 .type = MSR_FEATURE_WORD,
1400 .feat_names = {
1401 [0] = "vmx-eptp-switching",
1402 },
1403 .msr = {
1404 .index = MSR_IA32_VMX_VMFUNC,
1405 }
1406 },
1407
1408 };
1409
1410 typedef struct FeatureMask {
1411 FeatureWord index;
1412 uint64_t mask;
1413 } FeatureMask;
1414
1415 typedef struct FeatureDep {
1416 FeatureMask from, to;
1417 } FeatureDep;
1418
1419 static FeatureDep feature_dependencies[] = {
1420 {
1421 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
1422 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
1423 },
1424 {
1425 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
1426 .to = { FEAT_CORE_CAPABILITY, ~0ull },
1427 },
1428 {
1429 .from = { FEAT_1_ECX, CPUID_EXT_PDCM },
1430 .to = { FEAT_PERF_CAPABILITIES, ~0ull },
1431 },
1432 {
1433 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1434 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1435 },
1436 {
1437 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1438 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1439 },
1440 {
1441 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1442 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1443 },
1444 {
1445 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1446 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1447 },
1448 {
1449 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1450 .to = { FEAT_VMX_MISC, ~0ull },
1451 },
1452 {
1453 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1454 .to = { FEAT_VMX_BASIC, ~0ull },
1455 },
1456 {
1457 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1458 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1459 },
1460 {
1461 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1462 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1463 },
1464 {
1465 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1466 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1467 },
1468 {
1469 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1470 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1471 },
1472 {
1473 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1474 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1475 },
1476 {
1477 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1478 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1479 },
1480 {
1481 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1482 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1483 },
1484 {
1485 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1486 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1487 },
1488 {
1489 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1490 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1491 },
1492 {
1493 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1494 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1495 },
1496 {
1497 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1498 .to = { FEAT_VMX_VMFUNC, ~0ull },
1499 },
1500 {
1501 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM },
1502 .to = { FEAT_SVM, ~0ull },
1503 },
1504 };
1505
1506 typedef struct X86RegisterInfo32 {
1507 /* Name of register */
1508 const char *name;
1509 /* QAPI enum value register */
1510 X86CPURegister32 qapi_enum;
1511 } X86RegisterInfo32;
1512
1513 #define REGISTER(reg) \
1514 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1515 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
1516 REGISTER(EAX),
1517 REGISTER(ECX),
1518 REGISTER(EDX),
1519 REGISTER(EBX),
1520 REGISTER(ESP),
1521 REGISTER(EBP),
1522 REGISTER(ESI),
1523 REGISTER(EDI),
1524 };
1525 #undef REGISTER
1526
1527 typedef struct ExtSaveArea {
1528 uint32_t feature, bits;
1529 uint32_t offset, size;
1530 } ExtSaveArea;
1531
1532 static const ExtSaveArea x86_ext_save_areas[] = {
1533 [XSTATE_FP_BIT] = {
1534 /* x87 FP state component is always enabled if XSAVE is supported */
1535 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1536 /* x87 state is in the legacy region of the XSAVE area */
1537 .offset = 0,
1538 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1539 },
1540 [XSTATE_SSE_BIT] = {
1541 /* SSE state component is always enabled if XSAVE is supported */
1542 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1543 /* SSE state is in the legacy region of the XSAVE area */
1544 .offset = 0,
1545 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1546 },
1547 [XSTATE_YMM_BIT] =
1548 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
1549 .offset = offsetof(X86XSaveArea, avx_state),
1550 .size = sizeof(XSaveAVX) },
1551 [XSTATE_BNDREGS_BIT] =
1552 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1553 .offset = offsetof(X86XSaveArea, bndreg_state),
1554 .size = sizeof(XSaveBNDREG) },
1555 [XSTATE_BNDCSR_BIT] =
1556 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1557 .offset = offsetof(X86XSaveArea, bndcsr_state),
1558 .size = sizeof(XSaveBNDCSR) },
1559 [XSTATE_OPMASK_BIT] =
1560 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1561 .offset = offsetof(X86XSaveArea, opmask_state),
1562 .size = sizeof(XSaveOpmask) },
1563 [XSTATE_ZMM_Hi256_BIT] =
1564 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1565 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1566 .size = sizeof(XSaveZMM_Hi256) },
1567 [XSTATE_Hi16_ZMM_BIT] =
1568 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1569 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1570 .size = sizeof(XSaveHi16_ZMM) },
1571 [XSTATE_PKRU_BIT] =
1572 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
1573 .offset = offsetof(X86XSaveArea, pkru_state),
1574 .size = sizeof(XSavePKRU) },
1575 };
1576
1577 static uint32_t xsave_area_size(uint64_t mask)
1578 {
1579 int i;
1580 uint64_t ret = 0;
1581
1582 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1583 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1584 if ((mask >> i) & 1) {
1585 ret = MAX(ret, esa->offset + esa->size);
1586 }
1587 }
1588 return ret;
1589 }
1590
1591 static inline bool accel_uses_host_cpuid(void)
1592 {
1593 return kvm_enabled() || hvf_enabled();
1594 }
1595
1596 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1597 {
1598 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1599 cpu->env.features[FEAT_XSAVE_COMP_LO];
1600 }
1601
1602 const char *get_register_name_32(unsigned int reg)
1603 {
1604 if (reg >= CPU_NB_REGS32) {
1605 return NULL;
1606 }
1607 return x86_reg_info_32[reg].name;
1608 }
1609
1610 /*
1611 * Returns the set of feature flags that are supported and migratable by
1612 * QEMU, for a given FeatureWord.
1613 */
1614 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
1615 {
1616 FeatureWordInfo *wi = &feature_word_info[w];
1617 uint64_t r = 0;
1618 int i;
1619
1620 for (i = 0; i < 64; i++) {
1621 uint64_t f = 1ULL << i;
1622
1623 /* If the feature name is known, it is implicitly considered migratable,
1624 * unless it is explicitly set in unmigratable_flags */
1625 if ((wi->migratable_flags & f) ||
1626 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1627 r |= f;
1628 }
1629 }
1630 return r;
1631 }
1632
1633 void host_cpuid(uint32_t function, uint32_t count,
1634 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
1635 {
1636 uint32_t vec[4];
1637
1638 #ifdef __x86_64__
1639 asm volatile("cpuid"
1640 : "=a"(vec[0]), "=b"(vec[1]),
1641 "=c"(vec[2]), "=d"(vec[3])
1642 : "0"(function), "c"(count) : "cc");
1643 #elif defined(__i386__)
1644 asm volatile("pusha \n\t"
1645 "cpuid \n\t"
1646 "mov %%eax, 0(%2) \n\t"
1647 "mov %%ebx, 4(%2) \n\t"
1648 "mov %%ecx, 8(%2) \n\t"
1649 "mov %%edx, 12(%2) \n\t"
1650 "popa"
1651 : : "a"(function), "c"(count), "S"(vec)
1652 : "memory", "cc");
1653 #else
1654 abort();
1655 #endif
1656
1657 if (eax)
1658 *eax = vec[0];
1659 if (ebx)
1660 *ebx = vec[1];
1661 if (ecx)
1662 *ecx = vec[2];
1663 if (edx)
1664 *edx = vec[3];
1665 }
1666
1667 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1668 {
1669 uint32_t eax, ebx, ecx, edx;
1670
1671 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1672 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1673
1674 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1675 if (family) {
1676 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1677 }
1678 if (model) {
1679 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1680 }
1681 if (stepping) {
1682 *stepping = eax & 0x0F;
1683 }
1684 }
1685
1686 /* CPU class name definitions: */
1687
1688 /* Return type name for a given CPU model name
1689 * Caller is responsible for freeing the returned string.
1690 */
1691 static char *x86_cpu_type_name(const char *model_name)
1692 {
1693 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1694 }
1695
1696 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1697 {
1698 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1699 return object_class_by_name(typename);
1700 }
1701
1702 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1703 {
1704 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1705 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1706 return g_strndup(class_name,
1707 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1708 }
1709
1710 typedef struct PropValue {
1711 const char *prop, *value;
1712 } PropValue;
1713
1714 typedef struct X86CPUVersionDefinition {
1715 X86CPUVersion version;
1716 const char *alias;
1717 const char *note;
1718 PropValue *props;
1719 } X86CPUVersionDefinition;
1720
1721 /* Base definition for a CPU model */
1722 typedef struct X86CPUDefinition {
1723 const char *name;
1724 uint32_t level;
1725 uint32_t xlevel;
1726 /* vendor is zero-terminated, 12 character ASCII string */
1727 char vendor[CPUID_VENDOR_SZ + 1];
1728 int family;
1729 int model;
1730 int stepping;
1731 FeatureWordArray features;
1732 const char *model_id;
1733 CPUCaches *cache_info;
1734 /*
1735 * Definitions for alternative versions of CPU model.
1736 * List is terminated by item with version == 0.
1737 * If NULL, version 1 will be registered automatically.
1738 */
1739 const X86CPUVersionDefinition *versions;
1740 } X86CPUDefinition;
1741
1742 /* Reference to a specific CPU model version */
1743 struct X86CPUModel {
1744 /* Base CPU definition */
1745 X86CPUDefinition *cpudef;
1746 /* CPU model version */
1747 X86CPUVersion version;
1748 const char *note;
1749 /*
1750 * If true, this is an alias CPU model.
1751 * This matters only for "-cpu help" and query-cpu-definitions
1752 */
1753 bool is_alias;
1754 };
1755
1756 /* Get full model name for CPU version */
1757 static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef,
1758 X86CPUVersion version)
1759 {
1760 assert(version > 0);
1761 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1762 }
1763
1764 static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def)
1765 {
1766 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1767 static const X86CPUVersionDefinition default_version_list[] = {
1768 { 1 },
1769 { /* end of list */ }
1770 };
1771
1772 return def->versions ?: default_version_list;
1773 }
1774
1775 static CPUCaches epyc_cache_info = {
1776 .l1d_cache = &(CPUCacheInfo) {
1777 .type = DATA_CACHE,
1778 .level = 1,
1779 .size = 32 * KiB,
1780 .line_size = 64,
1781 .associativity = 8,
1782 .partitions = 1,
1783 .sets = 64,
1784 .lines_per_tag = 1,
1785 .self_init = 1,
1786 .no_invd_sharing = true,
1787 },
1788 .l1i_cache = &(CPUCacheInfo) {
1789 .type = INSTRUCTION_CACHE,
1790 .level = 1,
1791 .size = 64 * KiB,
1792 .line_size = 64,
1793 .associativity = 4,
1794 .partitions = 1,
1795 .sets = 256,
1796 .lines_per_tag = 1,
1797 .self_init = 1,
1798 .no_invd_sharing = true,
1799 },
1800 .l2_cache = &(CPUCacheInfo) {
1801 .type = UNIFIED_CACHE,
1802 .level = 2,
1803 .size = 512 * KiB,
1804 .line_size = 64,
1805 .associativity = 8,
1806 .partitions = 1,
1807 .sets = 1024,
1808 .lines_per_tag = 1,
1809 },
1810 .l3_cache = &(CPUCacheInfo) {
1811 .type = UNIFIED_CACHE,
1812 .level = 3,
1813 .size = 8 * MiB,
1814 .line_size = 64,
1815 .associativity = 16,
1816 .partitions = 1,
1817 .sets = 8192,
1818 .lines_per_tag = 1,
1819 .self_init = true,
1820 .inclusive = true,
1821 .complex_indexing = true,
1822 },
1823 };
1824
1825 static CPUCaches epyc_rome_cache_info = {
1826 .l1d_cache = &(CPUCacheInfo) {
1827 .type = DATA_CACHE,
1828 .level = 1,
1829 .size = 32 * KiB,
1830 .line_size = 64,
1831 .associativity = 8,
1832 .partitions = 1,
1833 .sets = 64,
1834 .lines_per_tag = 1,
1835 .self_init = 1,
1836 .no_invd_sharing = true,
1837 },
1838 .l1i_cache = &(CPUCacheInfo) {
1839 .type = INSTRUCTION_CACHE,
1840 .level = 1,
1841 .size = 32 * KiB,
1842 .line_size = 64,
1843 .associativity = 8,
1844 .partitions = 1,
1845 .sets = 64,
1846 .lines_per_tag = 1,
1847 .self_init = 1,
1848 .no_invd_sharing = true,
1849 },
1850 .l2_cache = &(CPUCacheInfo) {
1851 .type = UNIFIED_CACHE,
1852 .level = 2,
1853 .size = 512 * KiB,
1854 .line_size = 64,
1855 .associativity = 8,
1856 .partitions = 1,
1857 .sets = 1024,
1858 .lines_per_tag = 1,
1859 },
1860 .l3_cache = &(CPUCacheInfo) {
1861 .type = UNIFIED_CACHE,
1862 .level = 3,
1863 .size = 16 * MiB,
1864 .line_size = 64,
1865 .associativity = 16,
1866 .partitions = 1,
1867 .sets = 16384,
1868 .lines_per_tag = 1,
1869 .self_init = true,
1870 .inclusive = true,
1871 .complex_indexing = true,
1872 },
1873 };
1874
1875 /* The following VMX features are not supported by KVM and are left out in the
1876 * CPU definitions:
1877 *
1878 * Dual-monitor support (all processors)
1879 * Entry to SMM
1880 * Deactivate dual-monitor treatment
1881 * Number of CR3-target values
1882 * Shutdown activity state
1883 * Wait-for-SIPI activity state
1884 * PAUSE-loop exiting (Westmere and newer)
1885 * EPT-violation #VE (Broadwell and newer)
1886 * Inject event with insn length=0 (Skylake and newer)
1887 * Conceal non-root operation from PT
1888 * Conceal VM exits from PT
1889 * Conceal VM entries from PT
1890 * Enable ENCLS exiting
1891 * Mode-based execute control (XS/XU)
1892 s TSC scaling (Skylake Server and newer)
1893 * GPA translation for PT (IceLake and newer)
1894 * User wait and pause
1895 * ENCLV exiting
1896 * Load IA32_RTIT_CTL
1897 * Clear IA32_RTIT_CTL
1898 * Advanced VM-exit information for EPT violations
1899 * Sub-page write permissions
1900 * PT in VMX operation
1901 */
1902
1903 static X86CPUDefinition builtin_x86_defs[] = {
1904 {
1905 .name = "qemu64",
1906 .level = 0xd,
1907 .vendor = CPUID_VENDOR_AMD,
1908 .family = 6,
1909 .model = 6,
1910 .stepping = 3,
1911 .features[FEAT_1_EDX] =
1912 PPRO_FEATURES |
1913 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1914 CPUID_PSE36,
1915 .features[FEAT_1_ECX] =
1916 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1917 .features[FEAT_8000_0001_EDX] =
1918 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1919 .features[FEAT_8000_0001_ECX] =
1920 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
1921 .xlevel = 0x8000000A,
1922 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1923 },
1924 {
1925 .name = "phenom",
1926 .level = 5,
1927 .vendor = CPUID_VENDOR_AMD,
1928 .family = 16,
1929 .model = 2,
1930 .stepping = 3,
1931 /* Missing: CPUID_HT */
1932 .features[FEAT_1_EDX] =
1933 PPRO_FEATURES |
1934 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1935 CPUID_PSE36 | CPUID_VME,
1936 .features[FEAT_1_ECX] =
1937 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
1938 CPUID_EXT_POPCNT,
1939 .features[FEAT_8000_0001_EDX] =
1940 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1941 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
1942 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
1943 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1944 CPUID_EXT3_CR8LEG,
1945 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1946 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1947 .features[FEAT_8000_0001_ECX] =
1948 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
1949 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
1950 /* Missing: CPUID_SVM_LBRV */
1951 .features[FEAT_SVM] =
1952 CPUID_SVM_NPT,
1953 .xlevel = 0x8000001A,
1954 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1955 },
1956 {
1957 .name = "core2duo",
1958 .level = 10,
1959 .vendor = CPUID_VENDOR_INTEL,
1960 .family = 6,
1961 .model = 15,
1962 .stepping = 11,
1963 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1964 .features[FEAT_1_EDX] =
1965 PPRO_FEATURES |
1966 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1967 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1968 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1969 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1970 .features[FEAT_1_ECX] =
1971 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1972 CPUID_EXT_CX16,
1973 .features[FEAT_8000_0001_EDX] =
1974 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1975 .features[FEAT_8000_0001_ECX] =
1976 CPUID_EXT3_LAHF_LM,
1977 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
1978 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1979 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1980 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1981 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1982 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
1983 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1984 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1985 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1986 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1987 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1988 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1989 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1990 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
1991 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
1992 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
1993 .features[FEAT_VMX_SECONDARY_CTLS] =
1994 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
1995 .xlevel = 0x80000008,
1996 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1997 },
1998 {
1999 .name = "kvm64",
2000 .level = 0xd,
2001 .vendor = CPUID_VENDOR_INTEL,
2002 .family = 15,
2003 .model = 6,
2004 .stepping = 1,
2005 /* Missing: CPUID_HT */
2006 .features[FEAT_1_EDX] =
2007 PPRO_FEATURES | CPUID_VME |
2008 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
2009 CPUID_PSE36,
2010 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
2011 .features[FEAT_1_ECX] =
2012 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
2013 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
2014 .features[FEAT_8000_0001_EDX] =
2015 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2016 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
2017 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
2018 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
2019 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
2020 .features[FEAT_8000_0001_ECX] =
2021 0,
2022 /* VMX features from Cedar Mill/Prescott */
2023 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2024 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2025 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2026 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2027 VMX_PIN_BASED_NMI_EXITING,
2028 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2029 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2030 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2031 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2032 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2033 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2034 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2035 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
2036 .xlevel = 0x80000008,
2037 .model_id = "Common KVM processor"
2038 },
2039 {
2040 .name = "qemu32",
2041 .level = 4,
2042 .vendor = CPUID_VENDOR_INTEL,
2043 .family = 6,
2044 .model = 6,
2045 .stepping = 3,
2046 .features[FEAT_1_EDX] =
2047 PPRO_FEATURES,
2048 .features[FEAT_1_ECX] =
2049 CPUID_EXT_SSE3,
2050 .xlevel = 0x80000004,
2051 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
2052 },
2053 {
2054 .name = "kvm32",
2055 .level = 5,
2056 .vendor = CPUID_VENDOR_INTEL,
2057 .family = 15,
2058 .model = 6,
2059 .stepping = 1,
2060 .features[FEAT_1_EDX] =
2061 PPRO_FEATURES | CPUID_VME |
2062 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
2063 .features[FEAT_1_ECX] =
2064 CPUID_EXT_SSE3,
2065 .features[FEAT_8000_0001_ECX] =
2066 0,
2067 /* VMX features from Yonah */
2068 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2069 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2070 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2071 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2072 VMX_PIN_BASED_NMI_EXITING,
2073 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2074 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2075 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2076 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2077 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2078 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2079 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
2080 .xlevel = 0x80000008,
2081 .model_id = "Common 32-bit KVM processor"
2082 },
2083 {
2084 .name = "coreduo",
2085 .level = 10,
2086 .vendor = CPUID_VENDOR_INTEL,
2087 .family = 6,
2088 .model = 14,
2089 .stepping = 8,
2090 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2091 .features[FEAT_1_EDX] =
2092 PPRO_FEATURES | CPUID_VME |
2093 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
2094 CPUID_SS,
2095 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
2096 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
2097 .features[FEAT_1_ECX] =
2098 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
2099 .features[FEAT_8000_0001_EDX] =
2100 CPUID_EXT2_NX,
2101 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2102 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2103 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2104 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2105 VMX_PIN_BASED_NMI_EXITING,
2106 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2107 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2108 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2109 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2110 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2111 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2112 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
2113 .xlevel = 0x80000008,
2114 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
2115 },
2116 {
2117 .name = "486",
2118 .level = 1,
2119 .vendor = CPUID_VENDOR_INTEL,
2120 .family = 4,
2121 .model = 8,
2122 .stepping = 0,
2123 .features[FEAT_1_EDX] =
2124 I486_FEATURES,
2125 .xlevel = 0,
2126 .model_id = "",
2127 },
2128 {
2129 .name = "pentium",
2130 .level = 1,
2131 .vendor = CPUID_VENDOR_INTEL,
2132 .family = 5,
2133 .model = 4,
2134 .stepping = 3,
2135 .features[FEAT_1_EDX] =
2136 PENTIUM_FEATURES,
2137 .xlevel = 0,
2138 .model_id = "",
2139 },
2140 {
2141 .name = "pentium2",
2142 .level = 2,
2143 .vendor = CPUID_VENDOR_INTEL,
2144 .family = 6,
2145 .model = 5,
2146 .stepping = 2,
2147 .features[FEAT_1_EDX] =
2148 PENTIUM2_FEATURES,
2149 .xlevel = 0,
2150 .model_id = "",
2151 },
2152 {
2153 .name = "pentium3",
2154 .level = 3,
2155 .vendor = CPUID_VENDOR_INTEL,
2156 .family = 6,
2157 .model = 7,
2158 .stepping = 3,
2159 .features[FEAT_1_EDX] =
2160 PENTIUM3_FEATURES,
2161 .xlevel = 0,
2162 .model_id = "",
2163 },
2164 {
2165 .name = "athlon",
2166 .level = 2,
2167 .vendor = CPUID_VENDOR_AMD,
2168 .family = 6,
2169 .model = 2,
2170 .stepping = 3,
2171 .features[FEAT_1_EDX] =
2172 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
2173 CPUID_MCA,
2174 .features[FEAT_8000_0001_EDX] =
2175 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
2176 .xlevel = 0x80000008,
2177 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
2178 },
2179 {
2180 .name = "n270",
2181 .level = 10,
2182 .vendor = CPUID_VENDOR_INTEL,
2183 .family = 6,
2184 .model = 28,
2185 .stepping = 2,
2186 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2187 .features[FEAT_1_EDX] =
2188 PPRO_FEATURES |
2189 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2190 CPUID_ACPI | CPUID_SS,
2191 /* Some CPUs got no CPUID_SEP */
2192 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2193 * CPUID_EXT_XTPR */
2194 .features[FEAT_1_ECX] =
2195 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
2196 CPUID_EXT_MOVBE,
2197 .features[FEAT_8000_0001_EDX] =
2198 CPUID_EXT2_NX,
2199 .features[FEAT_8000_0001_ECX] =
2200 CPUID_EXT3_LAHF_LM,
2201 .xlevel = 0x80000008,
2202 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2203 },
2204 {
2205 .name = "Conroe",
2206 .level = 10,
2207 .vendor = CPUID_VENDOR_INTEL,
2208 .family = 6,
2209 .model = 15,
2210 .stepping = 3,
2211 .features[FEAT_1_EDX] =
2212 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2213 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2214 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2215 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2216 CPUID_DE | CPUID_FP87,
2217 .features[FEAT_1_ECX] =
2218 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2219 .features[FEAT_8000_0001_EDX] =
2220 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2221 .features[FEAT_8000_0001_ECX] =
2222 CPUID_EXT3_LAHF_LM,
2223 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2224 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2225 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2226 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2227 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2228 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2229 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2230 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2231 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2232 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2233 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2234 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2235 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2236 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2237 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2238 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2239 .features[FEAT_VMX_SECONDARY_CTLS] =
2240 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
2241 .xlevel = 0x80000008,
2242 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2243 },
2244 {
2245 .name = "Penryn",
2246 .level = 10,
2247 .vendor = CPUID_VENDOR_INTEL,
2248 .family = 6,
2249 .model = 23,
2250 .stepping = 3,
2251 .features[FEAT_1_EDX] =
2252 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2253 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2254 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2255 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2256 CPUID_DE | CPUID_FP87,
2257 .features[FEAT_1_ECX] =
2258 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2259 CPUID_EXT_SSE3,
2260 .features[FEAT_8000_0001_EDX] =
2261 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2262 .features[FEAT_8000_0001_ECX] =
2263 CPUID_EXT3_LAHF_LM,
2264 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2265 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2266 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2267 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2268 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2269 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2270 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2271 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2272 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2273 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2274 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2275 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2276 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2277 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2278 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2279 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2280 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2281 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2282 .features[FEAT_VMX_SECONDARY_CTLS] =
2283 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2284 VMX_SECONDARY_EXEC_WBINVD_EXITING,
2285 .xlevel = 0x80000008,
2286 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2287 },
2288 {
2289 .name = "Nehalem",
2290 .level = 11,
2291 .vendor = CPUID_VENDOR_INTEL,
2292 .family = 6,
2293 .model = 26,
2294 .stepping = 3,
2295 .features[FEAT_1_EDX] =
2296 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2297 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2298 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2299 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2300 CPUID_DE | CPUID_FP87,
2301 .features[FEAT_1_ECX] =
2302 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2303 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2304 .features[FEAT_8000_0001_EDX] =
2305 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2306 .features[FEAT_8000_0001_ECX] =
2307 CPUID_EXT3_LAHF_LM,
2308 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2309 MSR_VMX_BASIC_TRUE_CTLS,
2310 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2311 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2312 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2313 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2314 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2315 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2316 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2317 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2318 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2319 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2320 .features[FEAT_VMX_EXIT_CTLS] =
2321 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2322 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2323 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2324 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2325 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2326 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2327 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2328 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2329 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2330 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2331 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2332 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2333 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2334 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2335 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2336 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2337 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2338 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2339 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2340 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2341 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2342 .features[FEAT_VMX_SECONDARY_CTLS] =
2343 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2344 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2345 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2346 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2347 VMX_SECONDARY_EXEC_ENABLE_VPID,
2348 .xlevel = 0x80000008,
2349 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
2350 .versions = (X86CPUVersionDefinition[]) {
2351 { .version = 1 },
2352 {
2353 .version = 2,
2354 .alias = "Nehalem-IBRS",
2355 .props = (PropValue[]) {
2356 { "spec-ctrl", "on" },
2357 { "model-id",
2358 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2359 { /* end of list */ }
2360 }
2361 },
2362 { /* end of list */ }
2363 }
2364 },
2365 {
2366 .name = "Westmere",
2367 .level = 11,
2368 .vendor = CPUID_VENDOR_INTEL,
2369 .family = 6,
2370 .model = 44,
2371 .stepping = 1,
2372 .features[FEAT_1_EDX] =
2373 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2374 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2375 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2376 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2377 CPUID_DE | CPUID_FP87,
2378 .features[FEAT_1_ECX] =
2379 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2380 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2381 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2382 .features[FEAT_8000_0001_EDX] =
2383 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2384 .features[FEAT_8000_0001_ECX] =
2385 CPUID_EXT3_LAHF_LM,
2386 .features[FEAT_6_EAX] =
2387 CPUID_6_EAX_ARAT,
2388 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2389 MSR_VMX_BASIC_TRUE_CTLS,
2390 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2391 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2392 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2393 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2394 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2395 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2396 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2397 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2398 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2399 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2400 .features[FEAT_VMX_EXIT_CTLS] =
2401 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2402 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2403 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2404 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2405 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2406 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2407 MSR_VMX_MISC_STORE_LMA,
2408 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2409 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2410 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2411 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2412 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2413 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2414 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2415 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2416 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2417 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2418 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2419 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2420 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2421 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2422 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2423 .features[FEAT_VMX_SECONDARY_CTLS] =
2424 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2425 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2426 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2427 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2428 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2429 .xlevel = 0x80000008,
2430 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
2431 .versions = (X86CPUVersionDefinition[]) {
2432 { .version = 1 },
2433 {
2434 .version = 2,
2435 .alias = "Westmere-IBRS",
2436 .props = (PropValue[]) {
2437 { "spec-ctrl", "on" },
2438 { "model-id",
2439 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2440 { /* end of list */ }
2441 }
2442 },
2443 { /* end of list */ }
2444 }
2445 },
2446 {
2447 .name = "SandyBridge",
2448 .level = 0xd,
2449 .vendor = CPUID_VENDOR_INTEL,
2450 .family = 6,
2451 .model = 42,
2452 .stepping = 1,
2453 .features[FEAT_1_EDX] =
2454 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2455 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2456 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2457 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2458 CPUID_DE | CPUID_FP87,
2459 .features[FEAT_1_ECX] =
2460 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2461 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2462 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2463 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2464 CPUID_EXT_SSE3,
2465 .features[FEAT_8000_0001_EDX] =
2466 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2467 CPUID_EXT2_SYSCALL,
2468 .features[FEAT_8000_0001_ECX] =
2469 CPUID_EXT3_LAHF_LM,
2470 .features[FEAT_XSAVE] =
2471 CPUID_XSAVE_XSAVEOPT,
2472 .features[FEAT_6_EAX] =
2473 CPUID_6_EAX_ARAT,
2474 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2475 MSR_VMX_BASIC_TRUE_CTLS,
2476 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2477 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2478 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2479 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2480 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2481 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2482 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2483 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2484 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2485 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2486 .features[FEAT_VMX_EXIT_CTLS] =
2487 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2488 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2489 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2490 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2491 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2492 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2493 MSR_VMX_MISC_STORE_LMA,
2494 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2495 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2496 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2497 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2498 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2499 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2500 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2501 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2502 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2503 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2504 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2505 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2506 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2507 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2508 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2509 .features[FEAT_VMX_SECONDARY_CTLS] =
2510 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2511 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2512 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2513 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2514 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2515 .xlevel = 0x80000008,
2516 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
2517 .versions = (X86CPUVersionDefinition[]) {
2518 { .version = 1 },
2519 {
2520 .version = 2,
2521 .alias = "SandyBridge-IBRS",
2522 .props = (PropValue[]) {
2523 { "spec-ctrl", "on" },
2524 { "model-id",
2525 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2526 { /* end of list */ }
2527 }
2528 },
2529 { /* end of list */ }
2530 }
2531 },
2532 {
2533 .name = "IvyBridge",
2534 .level = 0xd,
2535 .vendor = CPUID_VENDOR_INTEL,
2536 .family = 6,
2537 .model = 58,
2538 .stepping = 9,
2539 .features[FEAT_1_EDX] =
2540 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2541 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2542 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2543 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2544 CPUID_DE | CPUID_FP87,
2545 .features[FEAT_1_ECX] =
2546 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2547 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2548 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2549 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2550 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2551 .features[FEAT_7_0_EBX] =
2552 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2553 CPUID_7_0_EBX_ERMS,
2554 .features[FEAT_8000_0001_EDX] =
2555 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2556 CPUID_EXT2_SYSCALL,
2557 .features[FEAT_8000_0001_ECX] =
2558 CPUID_EXT3_LAHF_LM,
2559 .features[FEAT_XSAVE] =
2560 CPUID_XSAVE_XSAVEOPT,
2561 .features[FEAT_6_EAX] =
2562 CPUID_6_EAX_ARAT,
2563 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2564 MSR_VMX_BASIC_TRUE_CTLS,
2565 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2566 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2567 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2568 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2569 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2570 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2571 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2572 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2573 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2574 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2575 .features[FEAT_VMX_EXIT_CTLS] =
2576 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2577 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2578 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2579 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2580 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2581 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2582 MSR_VMX_MISC_STORE_LMA,
2583 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2584 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2585 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2586 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2587 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2588 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2589 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2590 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2591 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2592 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2593 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2594 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2595 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2596 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2597 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2598 .features[FEAT_VMX_SECONDARY_CTLS] =
2599 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2600 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2601 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2602 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2603 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2604 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2605 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2606 VMX_SECONDARY_EXEC_RDRAND_EXITING,
2607 .xlevel = 0x80000008,
2608 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
2609 .versions = (X86CPUVersionDefinition[]) {
2610 { .version = 1 },
2611 {
2612 .version = 2,
2613 .alias = "IvyBridge-IBRS",
2614 .props = (PropValue[]) {
2615 { "spec-ctrl", "on" },
2616 { "model-id",
2617 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2618 { /* end of list */ }
2619 }
2620 },
2621 { /* end of list */ }
2622 }
2623 },
2624 {
2625 .name = "Haswell",
2626 .level = 0xd,
2627 .vendor = CPUID_VENDOR_INTEL,
2628 .family = 6,
2629 .model = 60,
2630 .stepping = 4,
2631 .features[FEAT_1_EDX] =
2632 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2633 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2634 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2635 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2636 CPUID_DE | CPUID_FP87,
2637 .features[FEAT_1_ECX] =
2638 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2639 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2640 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2641 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2642 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2643 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2644 .features[FEAT_8000_0001_EDX] =
2645 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2646 CPUID_EXT2_SYSCALL,
2647 .features[FEAT_8000_0001_ECX] =
2648 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2649 .features[FEAT_7_0_EBX] =
2650 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2651 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2652 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2653 CPUID_7_0_EBX_RTM,
2654 .features[FEAT_XSAVE] =
2655 CPUID_XSAVE_XSAVEOPT,
2656 .features[FEAT_6_EAX] =
2657 CPUID_6_EAX_ARAT,
2658 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2659 MSR_VMX_BASIC_TRUE_CTLS,
2660 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2661 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2662 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2663 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2664 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2665 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2666 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2667 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2668 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2669 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2670 .features[FEAT_VMX_EXIT_CTLS] =
2671 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2672 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2673 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2674 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2675 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2676 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2677 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2678 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2679 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2680 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2681 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2682 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2683 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2684 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2685 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2686 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2687 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2688 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2689 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2690 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2691 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2692 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2693 .features[FEAT_VMX_SECONDARY_CTLS] =
2694 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2695 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2696 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2697 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2698 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2699 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2700 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2701 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2702 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2703 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2704 .xlevel = 0x80000008,
2705 .model_id = "Intel Core Processor (Haswell)",
2706 .versions = (X86CPUVersionDefinition[]) {
2707 { .version = 1 },
2708 {
2709 .version = 2,
2710 .alias = "Haswell-noTSX",
2711 .props = (PropValue[]) {
2712 { "hle", "off" },
2713 { "rtm", "off" },
2714 { "stepping", "1" },
2715 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2716 { /* end of list */ }
2717 },
2718 },
2719 {
2720 .version = 3,
2721 .alias = "Haswell-IBRS",
2722 .props = (PropValue[]) {
2723 /* Restore TSX features removed by -v2 above */
2724 { "hle", "on" },
2725 { "rtm", "on" },
2726 /*
2727 * Haswell and Haswell-IBRS had stepping=4 in
2728 * QEMU 4.0 and older
2729 */
2730 { "stepping", "4" },
2731 { "spec-ctrl", "on" },
2732 { "model-id",
2733 "Intel Core Processor (Haswell, IBRS)" },
2734 { /* end of list */ }
2735 }
2736 },
2737 {
2738 .version = 4,
2739 .alias = "Haswell-noTSX-IBRS",
2740 .props = (PropValue[]) {
2741 { "hle", "off" },
2742 { "rtm", "off" },
2743 /* spec-ctrl was already enabled by -v3 above */
2744 { "stepping", "1" },
2745 { "model-id",
2746 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2747 { /* end of list */ }
2748 }
2749 },
2750 { /* end of list */ }
2751 }
2752 },
2753 {
2754 .name = "Broadwell",
2755 .level = 0xd,
2756 .vendor = CPUID_VENDOR_INTEL,
2757 .family = 6,
2758 .model = 61,
2759 .stepping = 2,
2760 .features[FEAT_1_EDX] =
2761 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2762 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2763 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2764 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2765 CPUID_DE | CPUID_FP87,
2766 .features[FEAT_1_ECX] =
2767 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2768 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2769 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2770 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2771 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2772 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2773 .features[FEAT_8000_0001_EDX] =
2774 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2775 CPUID_EXT2_SYSCALL,
2776 .features[FEAT_8000_0001_ECX] =
2777 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2778 .features[FEAT_7_0_EBX] =
2779 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2780 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2781 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2782 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2783 CPUID_7_0_EBX_SMAP,
2784 .features[FEAT_XSAVE] =
2785 CPUID_XSAVE_XSAVEOPT,
2786 .features[FEAT_6_EAX] =
2787 CPUID_6_EAX_ARAT,
2788 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2789 MSR_VMX_BASIC_TRUE_CTLS,
2790 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2791 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2792 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2793 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2794 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2795 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2796 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2797 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2798 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2799 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2800 .features[FEAT_VMX_EXIT_CTLS] =
2801 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2802 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2803 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2804 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2805 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2806 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2807 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2808 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2809 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2810 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2811 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2812 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2813 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2814 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2815 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2816 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2817 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2818 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2819 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2820 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2821 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2822 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2823 .features[FEAT_VMX_SECONDARY_CTLS] =
2824 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2825 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2826 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2827 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2828 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2829 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2830 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2831 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2832 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2833 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2834 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2835 .xlevel = 0x80000008,
2836 .model_id = "Intel Core Processor (Broadwell)",
2837 .versions = (X86CPUVersionDefinition[]) {
2838 { .version = 1 },
2839 {
2840 .version = 2,
2841 .alias = "Broadwell-noTSX",
2842 .props = (PropValue[]) {
2843 { "hle", "off" },
2844 { "rtm", "off" },
2845 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2846 { /* end of list */ }
2847 },
2848 },
2849 {
2850 .version = 3,
2851 .alias = "Broadwell-IBRS",
2852 .props = (PropValue[]) {
2853 /* Restore TSX features removed by -v2 above */
2854 { "hle", "on" },
2855 { "rtm", "on" },
2856 { "spec-ctrl", "on" },
2857 { "model-id",
2858 "Intel Core Processor (Broadwell, IBRS)" },
2859 { /* end of list */ }
2860 }
2861 },
2862 {
2863 .version = 4,
2864 .alias = "Broadwell-noTSX-IBRS",
2865 .props = (PropValue[]) {
2866 { "hle", "off" },
2867 { "rtm", "off" },
2868 /* spec-ctrl was already enabled by -v3 above */
2869 { "model-id",
2870 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2871 { /* end of list */ }
2872 }
2873 },
2874 { /* end of list */ }
2875 }
2876 },
2877 {
2878 .name = "Skylake-Client",
2879 .level = 0xd,
2880 .vendor = CPUID_VENDOR_INTEL,
2881 .family = 6,
2882 .model = 94,
2883 .stepping = 3,
2884 .features[FEAT_1_EDX] =
2885 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2886 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2887 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2888 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2889 CPUID_DE | CPUID_FP87,
2890 .features[FEAT_1_ECX] =
2891 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2892 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2893 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2894 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2895 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2896 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2897 .features[FEAT_8000_0001_EDX] =
2898 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2899 CPUID_EXT2_SYSCALL,
2900 .features[FEAT_8000_0001_ECX] =
2901 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2902 .features[FEAT_7_0_EBX] =
2903 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2904 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2905 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2906 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2907 CPUID_7_0_EBX_SMAP,
2908 /* Missing: XSAVES (not supported by some Linux versions,
2909 * including v4.1 to v4.12).
2910 * KVM doesn't yet expose any XSAVES state save component,
2911 * and the only one defined in Skylake (processor tracing)
2912 * probably will block migration anyway.
2913 */
2914 .features[FEAT_XSAVE] =
2915 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2916 CPUID_XSAVE_XGETBV1,
2917 .features[FEAT_6_EAX] =
2918 CPUID_6_EAX_ARAT,
2919 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2920 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2921 MSR_VMX_BASIC_TRUE_CTLS,
2922 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2923 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2924 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2925 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2926 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2927 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2928 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2929 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2930 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2931 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2932 .features[FEAT_VMX_EXIT_CTLS] =
2933 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2934 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2935 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2936 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2937 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2938 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2939 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2940 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2941 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2942 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2943 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2944 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2945 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2946 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2947 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2948 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2949 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2950 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2951 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2952 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2953 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2954 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2955 .features[FEAT_VMX_SECONDARY_CTLS] =
2956 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2957 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2958 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2959 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2960 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2961 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2962 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2963 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2964 .xlevel = 0x80000008,
2965 .model_id = "Intel Core Processor (Skylake)",
2966 .versions = (X86CPUVersionDefinition[]) {
2967 { .version = 1 },
2968 {
2969 .version = 2,
2970 .alias = "Skylake-Client-IBRS",
2971 .props = (PropValue[]) {
2972 { "spec-ctrl", "on" },
2973 { "model-id",
2974 "Intel Core Processor (Skylake, IBRS)" },
2975 { /* end of list */ }
2976 }
2977 },
2978 {
2979 .version = 3,
2980 .alias = "Skylake-Client-noTSX-IBRS",
2981 .props = (PropValue[]) {
2982 { "hle", "off" },
2983 { "rtm", "off" },
2984 { "model-id",
2985 "Intel Core Processor (Skylake, IBRS, no TSX)" },
2986 { /* end of list */ }
2987 }
2988 },
2989 { /* end of list */ }
2990 }
2991 },
2992 {
2993 .name = "Skylake-Server",
2994 .level = 0xd,
2995 .vendor = CPUID_VENDOR_INTEL,
2996 .family = 6,
2997 .model = 85,
2998 .stepping = 4,
2999 .features[FEAT_1_EDX] =
3000 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3001 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3002 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3003 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3004 CPUID_DE | CPUID_FP87,
3005 .features[FEAT_1_ECX] =
3006 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3007 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3008 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3009 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3010 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3011 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3012 .features[FEAT_8000_0001_EDX] =
3013 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3014 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3015 .features[FEAT_8000_0001_ECX] =
3016 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3017 .features[FEAT_7_0_EBX] =
3018 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3019 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3020 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3021 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3022 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3023 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3024 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3025 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3026 .features[FEAT_7_0_ECX] =
3027 CPUID_7_0_ECX_PKU,
3028 /* Missing: XSAVES (not supported by some Linux versions,
3029 * including v4.1 to v4.12).
3030 * KVM doesn't yet expose any XSAVES state save component,
3031 * and the only one defined in Skylake (processor tracing)
3032 * probably will block migration anyway.
3033 */
3034 .features[FEAT_XSAVE] =
3035 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3036 CPUID_XSAVE_XGETBV1,
3037 .features[FEAT_6_EAX] =
3038 CPUID_6_EAX_ARAT,
3039 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3040 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3041 MSR_VMX_BASIC_TRUE_CTLS,
3042 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3043 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3044 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3045 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3046 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3047 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3048 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3049 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3050 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3051 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3052 .features[FEAT_VMX_EXIT_CTLS] =
3053 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3054 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3055 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3056 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3057 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3058 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3059 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3060 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3061 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3062 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3063 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3064 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3065 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3066 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3067 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3068 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3069 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3070 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3071 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3072 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3073 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3074 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3075 .features[FEAT_VMX_SECONDARY_CTLS] =
3076 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3077 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3078 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3079 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3080 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3081 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3082 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3083 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3084 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3085 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3086 .xlevel = 0x80000008,
3087 .model_id = "Intel Xeon Processor (Skylake)",
3088 .versions = (X86CPUVersionDefinition[]) {
3089 { .version = 1 },
3090 {
3091 .version = 2,
3092 .alias = "Skylake-Server-IBRS",
3093 .props = (PropValue[]) {
3094 /* clflushopt was not added to Skylake-Server-IBRS */
3095 /* TODO: add -v3 including clflushopt */
3096 { "clflushopt", "off" },
3097 { "spec-ctrl", "on" },
3098 { "model-id",
3099 "Intel Xeon Processor (Skylake, IBRS)" },
3100 { /* end of list */ }
3101 }
3102 },
3103 {
3104 .version = 3,
3105 .alias = "Skylake-Server-noTSX-IBRS",
3106 .props = (PropValue[]) {
3107 { "hle", "off" },
3108 { "rtm", "off" },
3109 { "model-id",
3110 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
3111 { /* end of list */ }
3112 }
3113 },
3114 {
3115 .version = 4,
3116 .props = (PropValue[]) {
3117 { "vmx-eptp-switching", "on" },
3118 { /* end of list */ }
3119 }
3120 },
3121 { /* end of list */ }
3122 }
3123 },
3124 {
3125 .name = "Cascadelake-Server",
3126 .level = 0xd,
3127 .vendor = CPUID_VENDOR_INTEL,
3128 .family = 6,
3129 .model = 85,
3130 .stepping = 6,
3131 .features[FEAT_1_EDX] =
3132 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3133 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3134 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3135 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3136 CPUID_DE | CPUID_FP87,
3137 .features[FEAT_1_ECX] =
3138 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3139 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3140 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3141 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3142 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3143 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3144 .features[FEAT_8000_0001_EDX] =
3145 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3146 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3147 .features[FEAT_8000_0001_ECX] =
3148 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3149 .features[FEAT_7_0_EBX] =
3150 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3151 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3152 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3153 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3154 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3155 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3156 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3157 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3158 .features[FEAT_7_0_ECX] =
3159 CPUID_7_0_ECX_PKU |
3160 CPUID_7_0_ECX_AVX512VNNI,
3161 .features[FEAT_7_0_EDX] =
3162 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3163 /* Missing: XSAVES (not supported by some Linux versions,
3164 * including v4.1 to v4.12).
3165 * KVM doesn't yet expose any XSAVES state save component,
3166 * and the only one defined in Skylake (processor tracing)
3167 * probably will block migration anyway.
3168 */
3169 .features[FEAT_XSAVE] =
3170 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3171 CPUID_XSAVE_XGETBV1,
3172 .features[FEAT_6_EAX] =
3173 CPUID_6_EAX_ARAT,
3174 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3175 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3176 MSR_VMX_BASIC_TRUE_CTLS,
3177 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3178 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3179 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3180 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3181 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3182 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3183 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3184 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3185 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3186 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3187 .features[FEAT_VMX_EXIT_CTLS] =
3188 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3189 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3190 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |