Merge tag 'ide-pull-request' of https://gitlab.com/jsnow/qemu into staging
[qemu.git] / target / i386 / cpu.c
1 /*
2 * i386 CPUID, CPU class, definitions, models
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/qemu-print.h"
24 #include "cpu.h"
25 #include "tcg/helper-tcg.h"
26 #include "sysemu/reset.h"
27 #include "sysemu/hvf.h"
28 #include "kvm/kvm_i386.h"
29 #include "sev_i386.h"
30 #include "qapi/qapi-visit-machine.h"
31 #include "qapi/qmp/qerror.h"
32 #include "qapi/qapi-commands-machine-target.h"
33 #include "standard-headers/asm-x86/kvm_para.h"
34 #include "hw/qdev-properties.h"
35 #include "hw/i386/topology.h"
36 #ifndef CONFIG_USER_ONLY
37 #include "exec/address-spaces.h"
38 #include "hw/boards.h"
39 #endif
40
41 #include "disas/capstone.h"
42 #include "cpu-internal.h"
43
44 /* Helpers for building CPUID[2] descriptors: */
45
46 struct CPUID2CacheDescriptorInfo {
47 enum CacheType type;
48 int level;
49 int size;
50 int line_size;
51 int associativity;
52 };
53
54 /*
55 * Known CPUID 2 cache descriptors.
56 * From Intel SDM Volume 2A, CPUID instruction
57 */
58 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
59 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
60 .associativity = 4, .line_size = 32, },
61 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
62 .associativity = 4, .line_size = 32, },
63 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
64 .associativity = 4, .line_size = 64, },
65 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
66 .associativity = 2, .line_size = 32, },
67 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
68 .associativity = 4, .line_size = 32, },
69 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
70 .associativity = 4, .line_size = 64, },
71 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
72 .associativity = 6, .line_size = 64, },
73 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
74 .associativity = 2, .line_size = 64, },
75 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
76 .associativity = 8, .line_size = 64, },
77 /* lines per sector is not supported cpuid2_cache_descriptor(),
78 * so descriptors 0x22, 0x23 are not included
79 */
80 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
81 .associativity = 16, .line_size = 64, },
82 /* lines per sector is not supported cpuid2_cache_descriptor(),
83 * so descriptors 0x25, 0x20 are not included
84 */
85 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
86 .associativity = 8, .line_size = 64, },
87 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
88 .associativity = 8, .line_size = 64, },
89 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
90 .associativity = 4, .line_size = 32, },
91 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
92 .associativity = 4, .line_size = 32, },
93 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
94 .associativity = 4, .line_size = 32, },
95 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
96 .associativity = 4, .line_size = 32, },
97 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
98 .associativity = 4, .line_size = 32, },
99 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
100 .associativity = 4, .line_size = 64, },
101 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
102 .associativity = 8, .line_size = 64, },
103 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
104 .associativity = 12, .line_size = 64, },
105 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
106 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
107 .associativity = 12, .line_size = 64, },
108 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
109 .associativity = 16, .line_size = 64, },
110 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
111 .associativity = 12, .line_size = 64, },
112 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
113 .associativity = 16, .line_size = 64, },
114 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
115 .associativity = 24, .line_size = 64, },
116 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
117 .associativity = 8, .line_size = 64, },
118 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
119 .associativity = 4, .line_size = 64, },
120 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
121 .associativity = 4, .line_size = 64, },
122 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
123 .associativity = 4, .line_size = 64, },
124 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
125 .associativity = 4, .line_size = 64, },
126 /* lines per sector is not supported cpuid2_cache_descriptor(),
127 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
128 */
129 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
130 .associativity = 8, .line_size = 64, },
131 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
132 .associativity = 2, .line_size = 64, },
133 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
134 .associativity = 8, .line_size = 64, },
135 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
136 .associativity = 8, .line_size = 32, },
137 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
138 .associativity = 8, .line_size = 32, },
139 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
140 .associativity = 8, .line_size = 32, },
141 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
142 .associativity = 8, .line_size = 32, },
143 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
144 .associativity = 4, .line_size = 64, },
145 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
146 .associativity = 8, .line_size = 64, },
147 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
148 .associativity = 4, .line_size = 64, },
149 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
150 .associativity = 4, .line_size = 64, },
151 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
152 .associativity = 4, .line_size = 64, },
153 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
154 .associativity = 8, .line_size = 64, },
155 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
156 .associativity = 8, .line_size = 64, },
157 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
158 .associativity = 8, .line_size = 64, },
159 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
160 .associativity = 12, .line_size = 64, },
161 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
162 .associativity = 12, .line_size = 64, },
163 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
164 .associativity = 12, .line_size = 64, },
165 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
166 .associativity = 16, .line_size = 64, },
167 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
168 .associativity = 16, .line_size = 64, },
169 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
170 .associativity = 16, .line_size = 64, },
171 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
172 .associativity = 24, .line_size = 64, },
173 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
174 .associativity = 24, .line_size = 64, },
175 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
176 .associativity = 24, .line_size = 64, },
177 };
178
179 /*
180 * "CPUID leaf 2 does not report cache descriptor information,
181 * use CPUID leaf 4 to query cache parameters"
182 */
183 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
184
185 /*
186 * Return a CPUID 2 cache descriptor for a given cache.
187 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
188 */
189 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
190 {
191 int i;
192
193 assert(cache->size > 0);
194 assert(cache->level > 0);
195 assert(cache->line_size > 0);
196 assert(cache->associativity > 0);
197 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
198 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
199 if (d->level == cache->level && d->type == cache->type &&
200 d->size == cache->size && d->line_size == cache->line_size &&
201 d->associativity == cache->associativity) {
202 return i;
203 }
204 }
205
206 return CACHE_DESCRIPTOR_UNAVAILABLE;
207 }
208
209 /* CPUID Leaf 4 constants: */
210
211 /* EAX: */
212 #define CACHE_TYPE_D 1
213 #define CACHE_TYPE_I 2
214 #define CACHE_TYPE_UNIFIED 3
215
216 #define CACHE_LEVEL(l) (l << 5)
217
218 #define CACHE_SELF_INIT_LEVEL (1 << 8)
219
220 /* EDX: */
221 #define CACHE_NO_INVD_SHARING (1 << 0)
222 #define CACHE_INCLUSIVE (1 << 1)
223 #define CACHE_COMPLEX_IDX (1 << 2)
224
225 /* Encode CacheType for CPUID[4].EAX */
226 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
227 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
228 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
229 0 /* Invalid value */)
230
231
232 /* Encode cache info for CPUID[4] */
233 static void encode_cache_cpuid4(CPUCacheInfo *cache,
234 int num_apic_ids, int num_cores,
235 uint32_t *eax, uint32_t *ebx,
236 uint32_t *ecx, uint32_t *edx)
237 {
238 assert(cache->size == cache->line_size * cache->associativity *
239 cache->partitions * cache->sets);
240
241 assert(num_apic_ids > 0);
242 *eax = CACHE_TYPE(cache->type) |
243 CACHE_LEVEL(cache->level) |
244 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
245 ((num_cores - 1) << 26) |
246 ((num_apic_ids - 1) << 14);
247
248 assert(cache->line_size > 0);
249 assert(cache->partitions > 0);
250 assert(cache->associativity > 0);
251 /* We don't implement fully-associative caches */
252 assert(cache->associativity < cache->sets);
253 *ebx = (cache->line_size - 1) |
254 ((cache->partitions - 1) << 12) |
255 ((cache->associativity - 1) << 22);
256
257 assert(cache->sets > 0);
258 *ecx = cache->sets - 1;
259
260 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
261 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
262 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
263 }
264
265 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
266 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
267 {
268 assert(cache->size % 1024 == 0);
269 assert(cache->lines_per_tag > 0);
270 assert(cache->associativity > 0);
271 assert(cache->line_size > 0);
272 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
273 (cache->lines_per_tag << 8) | (cache->line_size);
274 }
275
276 #define ASSOC_FULL 0xFF
277
278 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
279 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
280 a == 2 ? 0x2 : \
281 a == 4 ? 0x4 : \
282 a == 8 ? 0x6 : \
283 a == 16 ? 0x8 : \
284 a == 32 ? 0xA : \
285 a == 48 ? 0xB : \
286 a == 64 ? 0xC : \
287 a == 96 ? 0xD : \
288 a == 128 ? 0xE : \
289 a == ASSOC_FULL ? 0xF : \
290 0 /* invalid value */)
291
292 /*
293 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
294 * @l3 can be NULL.
295 */
296 static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
297 CPUCacheInfo *l3,
298 uint32_t *ecx, uint32_t *edx)
299 {
300 assert(l2->size % 1024 == 0);
301 assert(l2->associativity > 0);
302 assert(l2->lines_per_tag > 0);
303 assert(l2->line_size > 0);
304 *ecx = ((l2->size / 1024) << 16) |
305 (AMD_ENC_ASSOC(l2->associativity) << 12) |
306 (l2->lines_per_tag << 8) | (l2->line_size);
307
308 if (l3) {
309 assert(l3->size % (512 * 1024) == 0);
310 assert(l3->associativity > 0);
311 assert(l3->lines_per_tag > 0);
312 assert(l3->line_size > 0);
313 *edx = ((l3->size / (512 * 1024)) << 18) |
314 (AMD_ENC_ASSOC(l3->associativity) << 12) |
315 (l3->lines_per_tag << 8) | (l3->line_size);
316 } else {
317 *edx = 0;
318 }
319 }
320
321 /* Encode cache info for CPUID[8000001D] */
322 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
323 X86CPUTopoInfo *topo_info,
324 uint32_t *eax, uint32_t *ebx,
325 uint32_t *ecx, uint32_t *edx)
326 {
327 uint32_t l3_threads;
328 assert(cache->size == cache->line_size * cache->associativity *
329 cache->partitions * cache->sets);
330
331 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
332 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
333
334 /* L3 is shared among multiple cores */
335 if (cache->level == 3) {
336 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core;
337 *eax |= (l3_threads - 1) << 14;
338 } else {
339 *eax |= ((topo_info->threads_per_core - 1) << 14);
340 }
341
342 assert(cache->line_size > 0);
343 assert(cache->partitions > 0);
344 assert(cache->associativity > 0);
345 /* We don't implement fully-associative caches */
346 assert(cache->associativity < cache->sets);
347 *ebx = (cache->line_size - 1) |
348 ((cache->partitions - 1) << 12) |
349 ((cache->associativity - 1) << 22);
350
351 assert(cache->sets > 0);
352 *ecx = cache->sets - 1;
353
354 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
355 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
356 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
357 }
358
359 /* Encode cache info for CPUID[8000001E] */
360 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
361 uint32_t *eax, uint32_t *ebx,
362 uint32_t *ecx, uint32_t *edx)
363 {
364 X86CPUTopoIDs topo_ids;
365
366 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
367
368 *eax = cpu->apic_id;
369
370 /*
371 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
372 * Read-only. Reset: 0000_XXXXh.
373 * See Core::X86::Cpuid::ExtApicId.
374 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
375 * Bits Description
376 * 31:16 Reserved.
377 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
378 * The number of threads per core is ThreadsPerCore+1.
379 * 7:0 CoreId: core ID. Read-only. Reset: XXh.
380 *
381 * NOTE: CoreId is already part of apic_id. Just use it. We can
382 * use all the 8 bits to represent the core_id here.
383 */
384 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF);
385
386 /*
387 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
388 * Read-only. Reset: 0000_0XXXh.
389 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
390 * Bits Description
391 * 31:11 Reserved.
392 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
393 * ValidValues:
394 * Value Description
395 * 000b 1 node per processor.
396 * 001b 2 nodes per processor.
397 * 010b Reserved.
398 * 011b 4 nodes per processor.
399 * 111b-100b Reserved.
400 * 7:0 NodeId: Node ID. Read-only. Reset: XXh.
401 *
402 * NOTE: Hardware reserves 3 bits for number of nodes per processor.
403 * But users can create more nodes than the actual hardware can
404 * support. To genaralize we can use all the upper 8 bits for nodes.
405 * NodeId is combination of node and socket_id which is already decoded
406 * in apic_id. Just use it by shifting.
407 */
408 *ecx = ((topo_info->dies_per_pkg - 1) << 8) |
409 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
410
411 *edx = 0;
412 }
413
414 /*
415 * Definitions of the hardcoded cache entries we expose:
416 * These are legacy cache values. If there is a need to change any
417 * of these values please use builtin_x86_defs
418 */
419
420 /* L1 data cache: */
421 static CPUCacheInfo legacy_l1d_cache = {
422 .type = DATA_CACHE,
423 .level = 1,
424 .size = 32 * KiB,
425 .self_init = 1,
426 .line_size = 64,
427 .associativity = 8,
428 .sets = 64,
429 .partitions = 1,
430 .no_invd_sharing = true,
431 };
432
433 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
434 static CPUCacheInfo legacy_l1d_cache_amd = {
435 .type = DATA_CACHE,
436 .level = 1,
437 .size = 64 * KiB,
438 .self_init = 1,
439 .line_size = 64,
440 .associativity = 2,
441 .sets = 512,
442 .partitions = 1,
443 .lines_per_tag = 1,
444 .no_invd_sharing = true,
445 };
446
447 /* L1 instruction cache: */
448 static CPUCacheInfo legacy_l1i_cache = {
449 .type = INSTRUCTION_CACHE,
450 .level = 1,
451 .size = 32 * KiB,
452 .self_init = 1,
453 .line_size = 64,
454 .associativity = 8,
455 .sets = 64,
456 .partitions = 1,
457 .no_invd_sharing = true,
458 };
459
460 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
461 static CPUCacheInfo legacy_l1i_cache_amd = {
462 .type = INSTRUCTION_CACHE,
463 .level = 1,
464 .size = 64 * KiB,
465 .self_init = 1,
466 .line_size = 64,
467 .associativity = 2,
468 .sets = 512,
469 .partitions = 1,
470 .lines_per_tag = 1,
471 .no_invd_sharing = true,
472 };
473
474 /* Level 2 unified cache: */
475 static CPUCacheInfo legacy_l2_cache = {
476 .type = UNIFIED_CACHE,
477 .level = 2,
478 .size = 4 * MiB,
479 .self_init = 1,
480 .line_size = 64,
481 .associativity = 16,
482 .sets = 4096,
483 .partitions = 1,
484 .no_invd_sharing = true,
485 };
486
487 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
488 static CPUCacheInfo legacy_l2_cache_cpuid2 = {
489 .type = UNIFIED_CACHE,
490 .level = 2,
491 .size = 2 * MiB,
492 .line_size = 64,
493 .associativity = 8,
494 };
495
496
497 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
498 static CPUCacheInfo legacy_l2_cache_amd = {
499 .type = UNIFIED_CACHE,
500 .level = 2,
501 .size = 512 * KiB,
502 .line_size = 64,
503 .lines_per_tag = 1,
504 .associativity = 16,
505 .sets = 512,
506 .partitions = 1,
507 };
508
509 /* Level 3 unified cache: */
510 static CPUCacheInfo legacy_l3_cache = {
511 .type = UNIFIED_CACHE,
512 .level = 3,
513 .size = 16 * MiB,
514 .line_size = 64,
515 .associativity = 16,
516 .sets = 16384,
517 .partitions = 1,
518 .lines_per_tag = 1,
519 .self_init = true,
520 .inclusive = true,
521 .complex_indexing = true,
522 };
523
524 /* TLB definitions: */
525
526 #define L1_DTLB_2M_ASSOC 1
527 #define L1_DTLB_2M_ENTRIES 255
528 #define L1_DTLB_4K_ASSOC 1
529 #define L1_DTLB_4K_ENTRIES 255
530
531 #define L1_ITLB_2M_ASSOC 1
532 #define L1_ITLB_2M_ENTRIES 255
533 #define L1_ITLB_4K_ASSOC 1
534 #define L1_ITLB_4K_ENTRIES 255
535
536 #define L2_DTLB_2M_ASSOC 0 /* disabled */
537 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
538 #define L2_DTLB_4K_ASSOC 4
539 #define L2_DTLB_4K_ENTRIES 512
540
541 #define L2_ITLB_2M_ASSOC 0 /* disabled */
542 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
543 #define L2_ITLB_4K_ASSOC 4
544 #define L2_ITLB_4K_ENTRIES 512
545
546 /* CPUID Leaf 0x14 constants: */
547 #define INTEL_PT_MAX_SUBLEAF 0x1
548 /*
549 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
550 * MSR can be accessed;
551 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
552 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
553 * of Intel PT MSRs across warm reset;
554 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
555 */
556 #define INTEL_PT_MINIMAL_EBX 0xf
557 /*
558 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
559 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
560 * accessed;
561 * bit[01]: ToPA tables can hold any number of output entries, up to the
562 * maximum allowed by the MaskOrTableOffset field of
563 * IA32_RTIT_OUTPUT_MASK_PTRS;
564 * bit[02]: Support Single-Range Output scheme;
565 */
566 #define INTEL_PT_MINIMAL_ECX 0x7
567 /* generated packets which contain IP payloads have LIP values */
568 #define INTEL_PT_IP_LIP (1 << 31)
569 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
570 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
571 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
572 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
573 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
574
575 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
576 uint32_t vendor2, uint32_t vendor3)
577 {
578 int i;
579 for (i = 0; i < 4; i++) {
580 dst[i] = vendor1 >> (8 * i);
581 dst[i + 4] = vendor2 >> (8 * i);
582 dst[i + 8] = vendor3 >> (8 * i);
583 }
584 dst[CPUID_VENDOR_SZ] = '\0';
585 }
586
587 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
588 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
589 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
590 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
591 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
592 CPUID_PSE36 | CPUID_FXSR)
593 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
594 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
595 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
596 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
597 CPUID_PAE | CPUID_SEP | CPUID_APIC)
598
599 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
600 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
601 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
602 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
603 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
604 /* partly implemented:
605 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
606 /* missing:
607 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
608 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
609 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
610 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
611 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
612 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
613 CPUID_EXT_RDRAND)
614 /* missing:
615 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
616 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
617 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
618 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
619 CPUID_EXT_F16C */
620
621 #ifdef TARGET_X86_64
622 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
623 #else
624 #define TCG_EXT2_X86_64_FEATURES 0
625 #endif
626
627 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
628 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
629 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
630 TCG_EXT2_X86_64_FEATURES)
631 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
632 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
633 #define TCG_EXT4_FEATURES 0
634 #define TCG_SVM_FEATURES CPUID_SVM_NPT
635 #define TCG_KVM_FEATURES 0
636 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
637 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
638 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
639 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
640 CPUID_7_0_EBX_ERMS)
641 /* missing:
642 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
643 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
644 CPUID_7_0_EBX_RDSEED */
645 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
646 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
647 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS)
648 #define TCG_7_0_EDX_FEATURES 0
649 #define TCG_7_1_EAX_FEATURES 0
650 #define TCG_APM_FEATURES 0
651 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
652 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
653 /* missing:
654 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
655 #define TCG_14_0_ECX_FEATURES 0
656
657 FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
658 [FEAT_1_EDX] = {
659 .type = CPUID_FEATURE_WORD,
660 .feat_names = {
661 "fpu", "vme", "de", "pse",
662 "tsc", "msr", "pae", "mce",
663 "cx8", "apic", NULL, "sep",
664 "mtrr", "pge", "mca", "cmov",
665 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
666 NULL, "ds" /* Intel dts */, "acpi", "mmx",
667 "fxsr", "sse", "sse2", "ss",
668 "ht" /* Intel htt */, "tm", "ia64", "pbe",
669 },
670 .cpuid = {.eax = 1, .reg = R_EDX, },
671 .tcg_features = TCG_FEATURES,
672 },
673 [FEAT_1_ECX] = {
674 .type = CPUID_FEATURE_WORD,
675 .feat_names = {
676 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
677 "ds-cpl", "vmx", "smx", "est",
678 "tm2", "ssse3", "cid", NULL,
679 "fma", "cx16", "xtpr", "pdcm",
680 NULL, "pcid", "dca", "sse4.1",
681 "sse4.2", "x2apic", "movbe", "popcnt",
682 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
683 "avx", "f16c", "rdrand", "hypervisor",
684 },
685 .cpuid = { .eax = 1, .reg = R_ECX, },
686 .tcg_features = TCG_EXT_FEATURES,
687 },
688 /* Feature names that are already defined on feature_name[] but
689 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
690 * names on feat_names below. They are copied automatically
691 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
692 */
693 [FEAT_8000_0001_EDX] = {
694 .type = CPUID_FEATURE_WORD,
695 .feat_names = {
696 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
697 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
698 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
699 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
700 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
701 "nx", NULL, "mmxext", NULL /* mmx */,
702 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
703 NULL, "lm", "3dnowext", "3dnow",
704 },
705 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
706 .tcg_features = TCG_EXT2_FEATURES,
707 },
708 [FEAT_8000_0001_ECX] = {
709 .type = CPUID_FEATURE_WORD,
710 .feat_names = {
711 "lahf-lm", "cmp-legacy", "svm", "extapic",
712 "cr8legacy", "abm", "sse4a", "misalignsse",
713 "3dnowprefetch", "osvw", "ibs", "xop",
714 "skinit", "wdt", NULL, "lwp",
715 "fma4", "tce", NULL, "nodeid-msr",
716 NULL, "tbm", "topoext", "perfctr-core",
717 "perfctr-nb", NULL, NULL, NULL,
718 NULL, NULL, NULL, NULL,
719 },
720 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
721 .tcg_features = TCG_EXT3_FEATURES,
722 /*
723 * TOPOEXT is always allowed but can't be enabled blindly by
724 * "-cpu host", as it requires consistent cache topology info
725 * to be provided so it doesn't confuse guests.
726 */
727 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
728 },
729 [FEAT_C000_0001_EDX] = {
730 .type = CPUID_FEATURE_WORD,
731 .feat_names = {
732 NULL, NULL, "xstore", "xstore-en",
733 NULL, NULL, "xcrypt", "xcrypt-en",
734 "ace2", "ace2-en", "phe", "phe-en",
735 "pmm", "pmm-en", NULL, NULL,
736 NULL, NULL, NULL, NULL,
737 NULL, NULL, NULL, NULL,
738 NULL, NULL, NULL, NULL,
739 NULL, NULL, NULL, NULL,
740 },
741 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
742 .tcg_features = TCG_EXT4_FEATURES,
743 },
744 [FEAT_KVM] = {
745 .type = CPUID_FEATURE_WORD,
746 .feat_names = {
747 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
748 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
749 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
750 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
751 NULL, NULL, NULL, NULL,
752 NULL, NULL, NULL, NULL,
753 "kvmclock-stable-bit", NULL, NULL, NULL,
754 NULL, NULL, NULL, NULL,
755 },
756 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
757 .tcg_features = TCG_KVM_FEATURES,
758 },
759 [FEAT_KVM_HINTS] = {
760 .type = CPUID_FEATURE_WORD,
761 .feat_names = {
762 "kvm-hint-dedicated", NULL, NULL, NULL,
763 NULL, NULL, NULL, NULL,
764 NULL, NULL, NULL, NULL,
765 NULL, NULL, NULL, NULL,
766 NULL, NULL, NULL, NULL,
767 NULL, NULL, NULL, NULL,
768 NULL, NULL, NULL, NULL,
769 NULL, NULL, NULL, NULL,
770 },
771 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
772 .tcg_features = TCG_KVM_FEATURES,
773 /*
774 * KVM hints aren't auto-enabled by -cpu host, they need to be
775 * explicitly enabled in the command-line.
776 */
777 .no_autoenable_flags = ~0U,
778 },
779 [FEAT_SVM] = {
780 .type = CPUID_FEATURE_WORD,
781 .feat_names = {
782 "npt", "lbrv", "svm-lock", "nrip-save",
783 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
784 NULL, NULL, "pause-filter", NULL,
785 "pfthreshold", "avic", NULL, "v-vmsave-vmload",
786 "vgif", NULL, NULL, NULL,
787 NULL, NULL, NULL, NULL,
788 NULL, NULL, NULL, NULL,
789 "svme-addr-chk", NULL, NULL, NULL,
790 },
791 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
792 .tcg_features = TCG_SVM_FEATURES,
793 },
794 [FEAT_7_0_EBX] = {
795 .type = CPUID_FEATURE_WORD,
796 .feat_names = {
797 "fsgsbase", "tsc-adjust", NULL, "bmi1",
798 "hle", "avx2", NULL, "smep",
799 "bmi2", "erms", "invpcid", "rtm",
800 NULL, NULL, "mpx", NULL,
801 "avx512f", "avx512dq", "rdseed", "adx",
802 "smap", "avx512ifma", "pcommit", "clflushopt",
803 "clwb", "intel-pt", "avx512pf", "avx512er",
804 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
805 },
806 .cpuid = {
807 .eax = 7,
808 .needs_ecx = true, .ecx = 0,
809 .reg = R_EBX,
810 },
811 .tcg_features = TCG_7_0_EBX_FEATURES,
812 },
813 [FEAT_7_0_ECX] = {
814 .type = CPUID_FEATURE_WORD,
815 .feat_names = {
816 NULL, "avx512vbmi", "umip", "pku",
817 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
818 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
819 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
820 "la57", NULL, NULL, NULL,
821 NULL, NULL, "rdpid", NULL,
822 "bus-lock-detect", "cldemote", NULL, "movdiri",
823 "movdir64b", NULL, NULL, "pks",
824 },
825 .cpuid = {
826 .eax = 7,
827 .needs_ecx = true, .ecx = 0,
828 .reg = R_ECX,
829 },
830 .tcg_features = TCG_7_0_ECX_FEATURES,
831 },
832 [FEAT_7_0_EDX] = {
833 .type = CPUID_FEATURE_WORD,
834 .feat_names = {
835 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
836 "fsrm", NULL, NULL, NULL,
837 "avx512-vp2intersect", NULL, "md-clear", NULL,
838 NULL, NULL, "serialize", NULL,
839 "tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
840 NULL, NULL, NULL, "avx512-fp16",
841 NULL, NULL, "spec-ctrl", "stibp",
842 NULL, "arch-capabilities", "core-capability", "ssbd",
843 },
844 .cpuid = {
845 .eax = 7,
846 .needs_ecx = true, .ecx = 0,
847 .reg = R_EDX,
848 },
849 .tcg_features = TCG_7_0_EDX_FEATURES,
850 },
851 [FEAT_7_1_EAX] = {
852 .type = CPUID_FEATURE_WORD,
853 .feat_names = {
854 NULL, NULL, NULL, NULL,
855 "avx-vnni", "avx512-bf16", NULL, NULL,
856 NULL, NULL, NULL, NULL,
857 NULL, NULL, NULL, NULL,
858 NULL, NULL, NULL, NULL,
859 NULL, NULL, NULL, NULL,
860 NULL, NULL, NULL, NULL,
861 NULL, NULL, NULL, NULL,
862 },
863 .cpuid = {
864 .eax = 7,
865 .needs_ecx = true, .ecx = 1,
866 .reg = R_EAX,
867 },
868 .tcg_features = TCG_7_1_EAX_FEATURES,
869 },
870 [FEAT_8000_0007_EDX] = {
871 .type = CPUID_FEATURE_WORD,
872 .feat_names = {
873 NULL, NULL, NULL, NULL,
874 NULL, NULL, NULL, NULL,
875 "invtsc", NULL, NULL, NULL,
876 NULL, NULL, NULL, NULL,
877 NULL, NULL, NULL, NULL,
878 NULL, NULL, NULL, NULL,
879 NULL, NULL, NULL, NULL,
880 NULL, NULL, NULL, NULL,
881 },
882 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
883 .tcg_features = TCG_APM_FEATURES,
884 .unmigratable_flags = CPUID_APM_INVTSC,
885 },
886 [FEAT_8000_0008_EBX] = {
887 .type = CPUID_FEATURE_WORD,
888 .feat_names = {
889 "clzero", NULL, "xsaveerptr", NULL,
890 NULL, NULL, NULL, NULL,
891 NULL, "wbnoinvd", NULL, NULL,
892 "ibpb", NULL, "ibrs", "amd-stibp",
893 NULL, NULL, NULL, NULL,
894 NULL, NULL, NULL, NULL,
895 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
896 NULL, NULL, NULL, NULL,
897 },
898 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
899 .tcg_features = 0,
900 .unmigratable_flags = 0,
901 },
902 [FEAT_XSAVE] = {
903 .type = CPUID_FEATURE_WORD,
904 .feat_names = {
905 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
906 NULL, NULL, NULL, NULL,
907 NULL, NULL, NULL, NULL,
908 NULL, NULL, NULL, NULL,
909 NULL, NULL, NULL, NULL,
910 NULL, NULL, NULL, NULL,
911 NULL, NULL, NULL, NULL,
912 NULL, NULL, NULL, NULL,
913 },
914 .cpuid = {
915 .eax = 0xd,
916 .needs_ecx = true, .ecx = 1,
917 .reg = R_EAX,
918 },
919 .tcg_features = TCG_XSAVE_FEATURES,
920 },
921 [FEAT_6_EAX] = {
922 .type = CPUID_FEATURE_WORD,
923 .feat_names = {
924 NULL, NULL, "arat", NULL,
925 NULL, NULL, NULL, NULL,
926 NULL, NULL, NULL, NULL,
927 NULL, NULL, NULL, NULL,
928 NULL, NULL, NULL, NULL,
929 NULL, NULL, NULL, NULL,
930 NULL, NULL, NULL, NULL,
931 NULL, NULL, NULL, NULL,
932 },
933 .cpuid = { .eax = 6, .reg = R_EAX, },
934 .tcg_features = TCG_6_EAX_FEATURES,
935 },
936 [FEAT_XSAVE_COMP_LO] = {
937 .type = CPUID_FEATURE_WORD,
938 .cpuid = {
939 .eax = 0xD,
940 .needs_ecx = true, .ecx = 0,
941 .reg = R_EAX,
942 },
943 .tcg_features = ~0U,
944 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
945 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
946 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
947 XSTATE_PKRU_MASK,
948 },
949 [FEAT_XSAVE_COMP_HI] = {
950 .type = CPUID_FEATURE_WORD,
951 .cpuid = {
952 .eax = 0xD,
953 .needs_ecx = true, .ecx = 0,
954 .reg = R_EDX,
955 },
956 .tcg_features = ~0U,
957 },
958 /*Below are MSR exposed features*/
959 [FEAT_ARCH_CAPABILITIES] = {
960 .type = MSR_FEATURE_WORD,
961 .feat_names = {
962 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
963 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
964 "taa-no", NULL, NULL, NULL,
965 NULL, NULL, NULL, NULL,
966 NULL, NULL, NULL, NULL,
967 NULL, NULL, NULL, NULL,
968 NULL, NULL, NULL, NULL,
969 NULL, NULL, NULL, NULL,
970 },
971 .msr = {
972 .index = MSR_IA32_ARCH_CAPABILITIES,
973 },
974 },
975 [FEAT_CORE_CAPABILITY] = {
976 .type = MSR_FEATURE_WORD,
977 .feat_names = {
978 NULL, NULL, NULL, NULL,
979 NULL, "split-lock-detect", NULL, NULL,
980 NULL, NULL, NULL, NULL,
981 NULL, NULL, NULL, NULL,
982 NULL, NULL, NULL, NULL,
983 NULL, NULL, NULL, NULL,
984 NULL, NULL, NULL, NULL,
985 NULL, NULL, NULL, NULL,
986 },
987 .msr = {
988 .index = MSR_IA32_CORE_CAPABILITY,
989 },
990 },
991 [FEAT_PERF_CAPABILITIES] = {
992 .type = MSR_FEATURE_WORD,
993 .feat_names = {
994 NULL, NULL, NULL, NULL,
995 NULL, NULL, NULL, NULL,
996 NULL, NULL, NULL, NULL,
997 NULL, "full-width-write", NULL, NULL,
998 NULL, NULL, NULL, NULL,
999 NULL, NULL, NULL, NULL,
1000 NULL, NULL, NULL, NULL,
1001 NULL, NULL, NULL, NULL,
1002 },
1003 .msr = {
1004 .index = MSR_IA32_PERF_CAPABILITIES,
1005 },
1006 },
1007
1008 [FEAT_VMX_PROCBASED_CTLS] = {
1009 .type = MSR_FEATURE_WORD,
1010 .feat_names = {
1011 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1012 NULL, NULL, NULL, "vmx-hlt-exit",
1013 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1014 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1015 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1016 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1017 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1018 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1019 },
1020 .msr = {
1021 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1022 }
1023 },
1024
1025 [FEAT_VMX_SECONDARY_CTLS] = {
1026 .type = MSR_FEATURE_WORD,
1027 .feat_names = {
1028 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1029 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1030 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1031 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1032 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1033 "vmx-xsaves", NULL, NULL, NULL,
1034 NULL, NULL, NULL, NULL,
1035 NULL, NULL, NULL, NULL,
1036 },
1037 .msr = {
1038 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1039 }
1040 },
1041
1042 [FEAT_VMX_PINBASED_CTLS] = {
1043 .type = MSR_FEATURE_WORD,
1044 .feat_names = {
1045 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1046 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1047 NULL, NULL, NULL, NULL,
1048 NULL, NULL, NULL, NULL,
1049 NULL, NULL, NULL, NULL,
1050 NULL, NULL, NULL, NULL,
1051 NULL, NULL, NULL, NULL,
1052 NULL, NULL, NULL, NULL,
1053 },
1054 .msr = {
1055 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1056 }
1057 },
1058
1059 [FEAT_VMX_EXIT_CTLS] = {
1060 .type = MSR_FEATURE_WORD,
1061 /*
1062 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1063 * the LM CPUID bit.
1064 */
1065 .feat_names = {
1066 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1067 NULL, NULL, NULL, NULL,
1068 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1069 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1070 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1071 "vmx-exit-save-efer", "vmx-exit-load-efer",
1072 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1073 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
1074 NULL, "vmx-exit-load-pkrs", NULL, NULL,
1075 },
1076 .msr = {
1077 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1078 }
1079 },
1080
1081 [FEAT_VMX_ENTRY_CTLS] = {
1082 .type = MSR_FEATURE_WORD,
1083 .feat_names = {
1084 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1085 NULL, NULL, NULL, NULL,
1086 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1087 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1088 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
1089 NULL, NULL, "vmx-entry-load-pkrs", NULL,
1090 NULL, NULL, NULL, NULL,
1091 NULL, NULL, NULL, NULL,
1092 },
1093 .msr = {
1094 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1095 }
1096 },
1097
1098 [FEAT_VMX_MISC] = {
1099 .type = MSR_FEATURE_WORD,
1100 .feat_names = {
1101 NULL, NULL, NULL, NULL,
1102 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1103 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1104 NULL, NULL, NULL, NULL,
1105 NULL, NULL, NULL, NULL,
1106 NULL, NULL, NULL, NULL,
1107 NULL, NULL, NULL, NULL,
1108 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1109 },
1110 .msr = {
1111 .index = MSR_IA32_VMX_MISC,
1112 }
1113 },
1114
1115 [FEAT_VMX_EPT_VPID_CAPS] = {
1116 .type = MSR_FEATURE_WORD,
1117 .feat_names = {
1118 "vmx-ept-execonly", NULL, NULL, NULL,
1119 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1120 NULL, NULL, NULL, NULL,
1121 NULL, NULL, NULL, NULL,
1122 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1123 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1124 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1125 NULL, NULL, NULL, NULL,
1126 "vmx-invvpid", NULL, NULL, NULL,
1127 NULL, NULL, NULL, NULL,
1128 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1129 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1130 NULL, NULL, NULL, NULL,
1131 NULL, NULL, NULL, NULL,
1132 NULL, NULL, NULL, NULL,
1133 NULL, NULL, NULL, NULL,
1134 NULL, NULL, NULL, NULL,
1135 },
1136 .msr = {
1137 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1138 }
1139 },
1140
1141 [FEAT_VMX_BASIC] = {
1142 .type = MSR_FEATURE_WORD,
1143 .feat_names = {
1144 [54] = "vmx-ins-outs",
1145 [55] = "vmx-true-ctls",
1146 },
1147 .msr = {
1148 .index = MSR_IA32_VMX_BASIC,
1149 },
1150 /* Just to be safe - we don't support setting the MSEG version field. */
1151 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1152 },
1153
1154 [FEAT_VMX_VMFUNC] = {
1155 .type = MSR_FEATURE_WORD,
1156 .feat_names = {
1157 [0] = "vmx-eptp-switching",
1158 },
1159 .msr = {
1160 .index = MSR_IA32_VMX_VMFUNC,
1161 }
1162 },
1163
1164 [FEAT_14_0_ECX] = {
1165 .type = CPUID_FEATURE_WORD,
1166 .feat_names = {
1167 NULL, NULL, NULL, NULL,
1168 NULL, NULL, NULL, NULL,
1169 NULL, NULL, NULL, NULL,
1170 NULL, NULL, NULL, NULL,
1171 NULL, NULL, NULL, NULL,
1172 NULL, NULL, NULL, NULL,
1173 NULL, NULL, NULL, NULL,
1174 NULL, NULL, NULL, "intel-pt-lip",
1175 },
1176 .cpuid = {
1177 .eax = 0x14,
1178 .needs_ecx = true, .ecx = 0,
1179 .reg = R_ECX,
1180 },
1181 .tcg_features = TCG_14_0_ECX_FEATURES,
1182 },
1183
1184 };
1185
1186 typedef struct FeatureMask {
1187 FeatureWord index;
1188 uint64_t mask;
1189 } FeatureMask;
1190
1191 typedef struct FeatureDep {
1192 FeatureMask from, to;
1193 } FeatureDep;
1194
1195 static FeatureDep feature_dependencies[] = {
1196 {
1197 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
1198 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
1199 },
1200 {
1201 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
1202 .to = { FEAT_CORE_CAPABILITY, ~0ull },
1203 },
1204 {
1205 .from = { FEAT_1_ECX, CPUID_EXT_PDCM },
1206 .to = { FEAT_PERF_CAPABILITIES, ~0ull },
1207 },
1208 {
1209 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1210 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1211 },
1212 {
1213 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1214 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1215 },
1216 {
1217 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1218 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1219 },
1220 {
1221 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1222 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1223 },
1224 {
1225 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1226 .to = { FEAT_VMX_MISC, ~0ull },
1227 },
1228 {
1229 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1230 .to = { FEAT_VMX_BASIC, ~0ull },
1231 },
1232 {
1233 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1234 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1235 },
1236 {
1237 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1238 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1239 },
1240 {
1241 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1242 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1243 },
1244 {
1245 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1246 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1247 },
1248 {
1249 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1250 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1251 },
1252 {
1253 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1254 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1255 },
1256 {
1257 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT },
1258 .to = { FEAT_14_0_ECX, ~0ull },
1259 },
1260 {
1261 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1262 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1263 },
1264 {
1265 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1266 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1267 },
1268 {
1269 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1270 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1271 },
1272 {
1273 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1274 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1275 },
1276 {
1277 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1278 .to = { FEAT_VMX_VMFUNC, ~0ull },
1279 },
1280 {
1281 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM },
1282 .to = { FEAT_SVM, ~0ull },
1283 },
1284 };
1285
1286 typedef struct X86RegisterInfo32 {
1287 /* Name of register */
1288 const char *name;
1289 /* QAPI enum value register */
1290 X86CPURegister32 qapi_enum;
1291 } X86RegisterInfo32;
1292
1293 #define REGISTER(reg) \
1294 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1295 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
1296 REGISTER(EAX),
1297 REGISTER(ECX),
1298 REGISTER(EDX),
1299 REGISTER(EBX),
1300 REGISTER(ESP),
1301 REGISTER(EBP),
1302 REGISTER(ESI),
1303 REGISTER(EDI),
1304 };
1305 #undef REGISTER
1306
1307 typedef struct ExtSaveArea {
1308 uint32_t feature, bits;
1309 uint32_t offset, size;
1310 } ExtSaveArea;
1311
1312 static const ExtSaveArea x86_ext_save_areas[] = {
1313 [XSTATE_FP_BIT] = {
1314 /* x87 FP state component is always enabled if XSAVE is supported */
1315 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1316 /* x87 state is in the legacy region of the XSAVE area */
1317 .offset = 0,
1318 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1319 },
1320 [XSTATE_SSE_BIT] = {
1321 /* SSE state component is always enabled if XSAVE is supported */
1322 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1323 /* SSE state is in the legacy region of the XSAVE area */
1324 .offset = 0,
1325 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1326 },
1327 [XSTATE_YMM_BIT] =
1328 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
1329 .offset = offsetof(X86XSaveArea, avx_state),
1330 .size = sizeof(XSaveAVX) },
1331 [XSTATE_BNDREGS_BIT] =
1332 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1333 .offset = offsetof(X86XSaveArea, bndreg_state),
1334 .size = sizeof(XSaveBNDREG) },
1335 [XSTATE_BNDCSR_BIT] =
1336 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1337 .offset = offsetof(X86XSaveArea, bndcsr_state),
1338 .size = sizeof(XSaveBNDCSR) },
1339 [XSTATE_OPMASK_BIT] =
1340 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1341 .offset = offsetof(X86XSaveArea, opmask_state),
1342 .size = sizeof(XSaveOpmask) },
1343 [XSTATE_ZMM_Hi256_BIT] =
1344 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1345 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1346 .size = sizeof(XSaveZMM_Hi256) },
1347 [XSTATE_Hi16_ZMM_BIT] =
1348 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1349 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1350 .size = sizeof(XSaveHi16_ZMM) },
1351 [XSTATE_PKRU_BIT] =
1352 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
1353 .offset = offsetof(X86XSaveArea, pkru_state),
1354 .size = sizeof(XSavePKRU) },
1355 };
1356
1357 static uint32_t xsave_area_size(uint64_t mask)
1358 {
1359 int i;
1360 uint64_t ret = 0;
1361
1362 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1363 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1364 if ((mask >> i) & 1) {
1365 ret = MAX(ret, esa->offset + esa->size);
1366 }
1367 }
1368 return ret;
1369 }
1370
1371 static inline bool accel_uses_host_cpuid(void)
1372 {
1373 return kvm_enabled() || hvf_enabled();
1374 }
1375
1376 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1377 {
1378 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1379 cpu->env.features[FEAT_XSAVE_COMP_LO];
1380 }
1381
1382 /* Return name of 32-bit register, from a R_* constant */
1383 static const char *get_register_name_32(unsigned int reg)
1384 {
1385 if (reg >= CPU_NB_REGS32) {
1386 return NULL;
1387 }
1388 return x86_reg_info_32[reg].name;
1389 }
1390
1391 /*
1392 * Returns the set of feature flags that are supported and migratable by
1393 * QEMU, for a given FeatureWord.
1394 */
1395 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
1396 {
1397 FeatureWordInfo *wi = &feature_word_info[w];
1398 uint64_t r = 0;
1399 int i;
1400
1401 for (i = 0; i < 64; i++) {
1402 uint64_t f = 1ULL << i;
1403
1404 /* If the feature name is known, it is implicitly considered migratable,
1405 * unless it is explicitly set in unmigratable_flags */
1406 if ((wi->migratable_flags & f) ||
1407 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1408 r |= f;
1409 }
1410 }
1411 return r;
1412 }
1413
1414 void host_cpuid(uint32_t function, uint32_t count,
1415 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
1416 {
1417 uint32_t vec[4];
1418
1419 #ifdef __x86_64__
1420 asm volatile("cpuid"
1421 : "=a"(vec[0]), "=b"(vec[1]),
1422 "=c"(vec[2]), "=d"(vec[3])
1423 : "0"(function), "c"(count) : "cc");
1424 #elif defined(__i386__)
1425 asm volatile("pusha \n\t"
1426 "cpuid \n\t"
1427 "mov %%eax, 0(%2) \n\t"
1428 "mov %%ebx, 4(%2) \n\t"
1429 "mov %%ecx, 8(%2) \n\t"
1430 "mov %%edx, 12(%2) \n\t"
1431 "popa"
1432 : : "a"(function), "c"(count), "S"(vec)
1433 : "memory", "cc");
1434 #else
1435 abort();
1436 #endif
1437
1438 if (eax)
1439 *eax = vec[0];
1440 if (ebx)
1441 *ebx = vec[1];
1442 if (ecx)
1443 *ecx = vec[2];
1444 if (edx)
1445 *edx = vec[3];
1446 }
1447
1448 /* CPU class name definitions: */
1449
1450 /* Return type name for a given CPU model name
1451 * Caller is responsible for freeing the returned string.
1452 */
1453 static char *x86_cpu_type_name(const char *model_name)
1454 {
1455 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1456 }
1457
1458 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1459 {
1460 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1461 return object_class_by_name(typename);
1462 }
1463
1464 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1465 {
1466 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1467 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1468 return g_strndup(class_name,
1469 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1470 }
1471
1472 typedef struct X86CPUVersionDefinition {
1473 X86CPUVersion version;
1474 const char *alias;
1475 const char *note;
1476 PropValue *props;
1477 } X86CPUVersionDefinition;
1478
1479 /* Base definition for a CPU model */
1480 typedef struct X86CPUDefinition {
1481 const char *name;
1482 uint32_t level;
1483 uint32_t xlevel;
1484 /* vendor is zero-terminated, 12 character ASCII string */
1485 char vendor[CPUID_VENDOR_SZ + 1];
1486 int family;
1487 int model;
1488 int stepping;
1489 FeatureWordArray features;
1490 const char *model_id;
1491 const CPUCaches *const cache_info;
1492 /*
1493 * Definitions for alternative versions of CPU model.
1494 * List is terminated by item with version == 0.
1495 * If NULL, version 1 will be registered automatically.
1496 */
1497 const X86CPUVersionDefinition *versions;
1498 const char *deprecation_note;
1499 } X86CPUDefinition;
1500
1501 /* Reference to a specific CPU model version */
1502 struct X86CPUModel {
1503 /* Base CPU definition */
1504 const X86CPUDefinition *cpudef;
1505 /* CPU model version */
1506 X86CPUVersion version;
1507 const char *note;
1508 /*
1509 * If true, this is an alias CPU model.
1510 * This matters only for "-cpu help" and query-cpu-definitions
1511 */
1512 bool is_alias;
1513 };
1514
1515 /* Get full model name for CPU version */
1516 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef,
1517 X86CPUVersion version)
1518 {
1519 assert(version > 0);
1520 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1521 }
1522
1523 static const X86CPUVersionDefinition *
1524 x86_cpu_def_get_versions(const X86CPUDefinition *def)
1525 {
1526 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1527 static const X86CPUVersionDefinition default_version_list[] = {
1528 { 1 },
1529 { /* end of list */ }
1530 };
1531
1532 return def->versions ?: default_version_list;
1533 }
1534
1535 static const CPUCaches epyc_cache_info = {
1536 .l1d_cache = &(CPUCacheInfo) {
1537 .type = DATA_CACHE,
1538 .level = 1,
1539 .size = 32 * KiB,
1540 .line_size = 64,
1541 .associativity = 8,
1542 .partitions = 1,
1543 .sets = 64,
1544 .lines_per_tag = 1,
1545 .self_init = 1,
1546 .no_invd_sharing = true,
1547 },
1548 .l1i_cache = &(CPUCacheInfo) {
1549 .type = INSTRUCTION_CACHE,
1550 .level = 1,
1551 .size = 64 * KiB,
1552 .line_size = 64,
1553 .associativity = 4,
1554 .partitions = 1,
1555 .sets = 256,
1556 .lines_per_tag = 1,
1557 .self_init = 1,
1558 .no_invd_sharing = true,
1559 },
1560 .l2_cache = &(CPUCacheInfo) {
1561 .type = UNIFIED_CACHE,
1562 .level = 2,
1563 .size = 512 * KiB,
1564 .line_size = 64,
1565 .associativity = 8,
1566 .partitions = 1,
1567 .sets = 1024,
1568 .lines_per_tag = 1,
1569 },
1570 .l3_cache = &(CPUCacheInfo) {
1571 .type = UNIFIED_CACHE,
1572 .level = 3,
1573 .size = 8 * MiB,
1574 .line_size = 64,
1575 .associativity = 16,
1576 .partitions = 1,
1577 .sets = 8192,
1578 .lines_per_tag = 1,
1579 .self_init = true,
1580 .inclusive = true,
1581 .complex_indexing = true,
1582 },
1583 };
1584
1585 static const CPUCaches epyc_rome_cache_info = {
1586 .l1d_cache = &(CPUCacheInfo) {
1587 .type = DATA_CACHE,
1588 .level = 1,
1589 .size = 32 * KiB,
1590 .line_size = 64,
1591 .associativity = 8,
1592 .partitions = 1,
1593 .sets = 64,
1594 .lines_per_tag = 1,
1595 .self_init = 1,
1596 .no_invd_sharing = true,
1597 },
1598 .l1i_cache = &(CPUCacheInfo) {
1599 .type = INSTRUCTION_CACHE,
1600 .level = 1,
1601 .size = 32 * KiB,
1602 .line_size = 64,
1603 .associativity = 8,
1604 .partitions = 1,
1605 .sets = 64,
1606 .lines_per_tag = 1,
1607 .self_init = 1,
1608 .no_invd_sharing = true,
1609 },
1610 .l2_cache = &(CPUCacheInfo) {
1611 .type = UNIFIED_CACHE,
1612 .level = 2,
1613 .size = 512 * KiB,
1614 .line_size = 64,
1615 .associativity = 8,
1616 .partitions = 1,
1617 .sets = 1024,
1618 .lines_per_tag = 1,
1619 },
1620 .l3_cache = &(CPUCacheInfo) {
1621 .type = UNIFIED_CACHE,
1622 .level = 3,
1623 .size = 16 * MiB,
1624 .line_size = 64,
1625 .associativity = 16,
1626 .partitions = 1,
1627 .sets = 16384,
1628 .lines_per_tag = 1,
1629 .self_init = true,
1630 .inclusive = true,
1631 .complex_indexing = true,
1632 },
1633 };
1634
1635 static const CPUCaches epyc_milan_cache_info = {
1636 .l1d_cache = &(CPUCacheInfo) {
1637 .type = DATA_CACHE,
1638 .level = 1,
1639 .size = 32 * KiB,
1640 .line_size = 64,
1641 .associativity = 8,
1642 .partitions = 1,
1643 .sets = 64,
1644 .lines_per_tag = 1,
1645 .self_init = 1,
1646 .no_invd_sharing = true,
1647 },
1648 .l1i_cache = &(CPUCacheInfo) {
1649 .type = INSTRUCTION_CACHE,
1650 .level = 1,
1651 .size = 32 * KiB,
1652 .line_size = 64,
1653 .associativity = 8,
1654 .partitions = 1,
1655 .sets = 64,
1656 .lines_per_tag = 1,
1657 .self_init = 1,
1658 .no_invd_sharing = true,
1659 },
1660 .l2_cache = &(CPUCacheInfo) {
1661 .type = UNIFIED_CACHE,
1662 .level = 2,
1663 .size = 512 * KiB,
1664 .line_size = 64,
1665 .associativity = 8,
1666 .partitions = 1,
1667 .sets = 1024,
1668 .lines_per_tag = 1,
1669 },
1670 .l3_cache = &(CPUCacheInfo) {
1671 .type = UNIFIED_CACHE,
1672 .level = 3,
1673 .size = 32 * MiB,
1674 .line_size = 64,
1675 .associativity = 16,
1676 .partitions = 1,
1677 .sets = 32768,
1678 .lines_per_tag = 1,
1679 .self_init = true,
1680 .inclusive = true,
1681 .complex_indexing = true,
1682 },
1683 };
1684
1685 /* The following VMX features are not supported by KVM and are left out in the
1686 * CPU definitions:
1687 *
1688 * Dual-monitor support (all processors)
1689 * Entry to SMM
1690 * Deactivate dual-monitor treatment
1691 * Number of CR3-target values
1692 * Shutdown activity state
1693 * Wait-for-SIPI activity state
1694 * PAUSE-loop exiting (Westmere and newer)
1695 * EPT-violation #VE (Broadwell and newer)
1696 * Inject event with insn length=0 (Skylake and newer)
1697 * Conceal non-root operation from PT
1698 * Conceal VM exits from PT
1699 * Conceal VM entries from PT
1700 * Enable ENCLS exiting
1701 * Mode-based execute control (XS/XU)
1702 s TSC scaling (Skylake Server and newer)
1703 * GPA translation for PT (IceLake and newer)
1704 * User wait and pause
1705 * ENCLV exiting
1706 * Load IA32_RTIT_CTL
1707 * Clear IA32_RTIT_CTL
1708 * Advanced VM-exit information for EPT violations
1709 * Sub-page write permissions
1710 * PT in VMX operation
1711 */
1712
1713 static const X86CPUDefinition builtin_x86_defs[] = {
1714 {
1715 .name = "qemu64",
1716 .level = 0xd,
1717 .vendor = CPUID_VENDOR_AMD,
1718 .family = 15,
1719 .model = 107,
1720 .stepping = 1,
1721 .features[FEAT_1_EDX] =
1722 PPRO_FEATURES |
1723 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1724 CPUID_PSE36,
1725 .features[FEAT_1_ECX] =
1726 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1727 .features[FEAT_8000_0001_EDX] =
1728 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1729 .features[FEAT_8000_0001_ECX] =
1730 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
1731 .xlevel = 0x8000000A,
1732 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1733 },
1734 {
1735 .name = "phenom",
1736 .level = 5,
1737 .vendor = CPUID_VENDOR_AMD,
1738 .family = 16,
1739 .model = 2,
1740 .stepping = 3,
1741 /* Missing: CPUID_HT */
1742 .features[FEAT_1_EDX] =
1743 PPRO_FEATURES |
1744 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1745 CPUID_PSE36 | CPUID_VME,
1746 .features[FEAT_1_ECX] =
1747 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
1748 CPUID_EXT_POPCNT,
1749 .features[FEAT_8000_0001_EDX] =
1750 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1751 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
1752 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
1753 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1754 CPUID_EXT3_CR8LEG,
1755 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1756 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1757 .features[FEAT_8000_0001_ECX] =
1758 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
1759 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
1760 /* Missing: CPUID_SVM_LBRV */
1761 .features[FEAT_SVM] =
1762 CPUID_SVM_NPT,
1763 .xlevel = 0x8000001A,
1764 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1765 },
1766 {
1767 .name = "core2duo",
1768 .level = 10,
1769 .vendor = CPUID_VENDOR_INTEL,
1770 .family = 6,
1771 .model = 15,
1772 .stepping = 11,
1773 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1774 .features[FEAT_1_EDX] =
1775 PPRO_FEATURES |
1776 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1777 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1778 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1779 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1780 .features[FEAT_1_ECX] =
1781 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1782 CPUID_EXT_CX16,
1783 .features[FEAT_8000_0001_EDX] =
1784 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1785 .features[FEAT_8000_0001_ECX] =
1786 CPUID_EXT3_LAHF_LM,
1787 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
1788 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1789 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1790 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1791 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1792 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
1793 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1794 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1795 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1796 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1797 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1798 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1799 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1800 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
1801 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
1802 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
1803 .features[FEAT_VMX_SECONDARY_CTLS] =
1804 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
1805 .xlevel = 0x80000008,
1806 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1807 },
1808 {
1809 .name = "kvm64",
1810 .level = 0xd,
1811 .vendor = CPUID_VENDOR_INTEL,
1812 .family = 15,
1813 .model = 6,
1814 .stepping = 1,
1815 /* Missing: CPUID_HT */
1816 .features[FEAT_1_EDX] =
1817 PPRO_FEATURES | CPUID_VME |
1818 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1819 CPUID_PSE36,
1820 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
1821 .features[FEAT_1_ECX] =
1822 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1823 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
1824 .features[FEAT_8000_0001_EDX] =
1825 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1826 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1827 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1828 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1829 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
1830 .features[FEAT_8000_0001_ECX] =
1831 0,
1832 /* VMX features from Cedar Mill/Prescott */
1833 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1834 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1835 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1836 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1837 VMX_PIN_BASED_NMI_EXITING,
1838 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1839 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1840 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1841 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1842 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1843 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1844 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1845 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
1846 .xlevel = 0x80000008,
1847 .model_id = "Common KVM processor"
1848 },
1849 {
1850 .name = "qemu32",
1851 .level = 4,
1852 .vendor = CPUID_VENDOR_INTEL,
1853 .family = 6,
1854 .model = 6,
1855 .stepping = 3,
1856 .features[FEAT_1_EDX] =
1857 PPRO_FEATURES,
1858 .features[FEAT_1_ECX] =
1859 CPUID_EXT_SSE3,
1860 .xlevel = 0x80000004,
1861 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1862 },
1863 {
1864 .name = "kvm32",
1865 .level = 5,
1866 .vendor = CPUID_VENDOR_INTEL,
1867 .family = 15,
1868 .model = 6,
1869 .stepping = 1,
1870 .features[FEAT_1_EDX] =
1871 PPRO_FEATURES | CPUID_VME |
1872 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
1873 .features[FEAT_1_ECX] =
1874 CPUID_EXT_SSE3,
1875 .features[FEAT_8000_0001_ECX] =
1876 0,
1877 /* VMX features from Yonah */
1878 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1879 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1880 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1881 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1882 VMX_PIN_BASED_NMI_EXITING,
1883 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1884 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1885 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1886 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1887 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
1888 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
1889 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
1890 .xlevel = 0x80000008,
1891 .model_id = "Common 32-bit KVM processor"
1892 },
1893 {
1894 .name = "coreduo",
1895 .level = 10,
1896 .vendor = CPUID_VENDOR_INTEL,
1897 .family = 6,
1898 .model = 14,
1899 .stepping = 8,
1900 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1901 .features[FEAT_1_EDX] =
1902 PPRO_FEATURES | CPUID_VME |
1903 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1904 CPUID_SS,
1905 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
1906 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
1907 .features[FEAT_1_ECX] =
1908 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
1909 .features[FEAT_8000_0001_EDX] =
1910 CPUID_EXT2_NX,
1911 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1912 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1913 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1914 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1915 VMX_PIN_BASED_NMI_EXITING,
1916 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1917 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1918 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1919 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1920 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
1921 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
1922 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
1923 .xlevel = 0x80000008,
1924 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1925 },
1926 {
1927 .name = "486",
1928 .level = 1,
1929 .vendor = CPUID_VENDOR_INTEL,
1930 .family = 4,
1931 .model = 8,
1932 .stepping = 0,
1933 .features[FEAT_1_EDX] =
1934 I486_FEATURES,
1935 .xlevel = 0,
1936 .model_id = "",
1937 },
1938 {
1939 .name = "pentium",
1940 .level = 1,
1941 .vendor = CPUID_VENDOR_INTEL,
1942 .family = 5,
1943 .model = 4,
1944 .stepping = 3,
1945 .features[FEAT_1_EDX] =
1946 PENTIUM_FEATURES,
1947 .xlevel = 0,
1948 .model_id = "",
1949 },
1950 {
1951 .name = "pentium2",
1952 .level = 2,
1953 .vendor = CPUID_VENDOR_INTEL,
1954 .family = 6,
1955 .model = 5,
1956 .stepping = 2,
1957 .features[FEAT_1_EDX] =
1958 PENTIUM2_FEATURES,
1959 .xlevel = 0,
1960 .model_id = "",
1961 },
1962 {
1963 .name = "pentium3",
1964 .level = 3,
1965 .vendor = CPUID_VENDOR_INTEL,
1966 .family = 6,
1967 .model = 7,
1968 .stepping = 3,
1969 .features[FEAT_1_EDX] =
1970 PENTIUM3_FEATURES,
1971 .xlevel = 0,
1972 .model_id = "",
1973 },
1974 {
1975 .name = "athlon",
1976 .level = 2,
1977 .vendor = CPUID_VENDOR_AMD,
1978 .family = 6,
1979 .model = 2,
1980 .stepping = 3,
1981 .features[FEAT_1_EDX] =
1982 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
1983 CPUID_MCA,
1984 .features[FEAT_8000_0001_EDX] =
1985 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
1986 .xlevel = 0x80000008,
1987 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1988 },
1989 {
1990 .name = "n270",
1991 .level = 10,
1992 .vendor = CPUID_VENDOR_INTEL,
1993 .family = 6,
1994 .model = 28,
1995 .stepping = 2,
1996 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1997 .features[FEAT_1_EDX] =
1998 PPRO_FEATURES |
1999 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2000 CPUID_ACPI | CPUID_SS,
2001 /* Some CPUs got no CPUID_SEP */
2002 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2003 * CPUID_EXT_XTPR */
2004 .features[FEAT_1_ECX] =
2005 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
2006 CPUID_EXT_MOVBE,
2007 .features[FEAT_8000_0001_EDX] =
2008 CPUID_EXT2_NX,
2009 .features[FEAT_8000_0001_ECX] =
2010 CPUID_EXT3_LAHF_LM,
2011 .xlevel = 0x80000008,
2012 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2013 },
2014 {
2015 .name = "Conroe",
2016 .level = 10,
2017 .vendor = CPUID_VENDOR_INTEL,
2018 .family = 6,
2019 .model = 15,
2020 .stepping = 3,
2021 .features[FEAT_1_EDX] =
2022 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2023 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2024 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2025 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2026 CPUID_DE | CPUID_FP87,
2027 .features[FEAT_1_ECX] =
2028 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2029 .features[FEAT_8000_0001_EDX] =
2030 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2031 .features[FEAT_8000_0001_ECX] =
2032 CPUID_EXT3_LAHF_LM,
2033 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2034 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2035 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2036 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2037 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2038 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2039 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2040 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2041 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2042 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2043 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2044 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2045 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2046 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2047 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2048 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2049 .features[FEAT_VMX_SECONDARY_CTLS] =
2050 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
2051 .xlevel = 0x80000008,
2052 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2053 },
2054 {
2055 .name = "Penryn",
2056 .level = 10,
2057 .vendor = CPUID_VENDOR_INTEL,
2058 .family = 6,
2059 .model = 23,
2060 .stepping = 3,
2061 .features[FEAT_1_EDX] =
2062 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2063 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2064 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2065 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2066 CPUID_DE | CPUID_FP87,
2067 .features[FEAT_1_ECX] =
2068 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2069 CPUID_EXT_SSE3,
2070 .features[FEAT_8000_0001_EDX] =
2071 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2072 .features[FEAT_8000_0001_ECX] =
2073 CPUID_EXT3_LAHF_LM,
2074 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2075 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2076 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2077 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2078 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2079 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2080 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2081 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2082 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2083 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2084 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2085 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2086 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2087 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2088 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2089 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2090 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2091 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2092 .features[FEAT_VMX_SECONDARY_CTLS] =
2093 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2094 VMX_SECONDARY_EXEC_WBINVD_EXITING,
2095 .xlevel = 0x80000008,
2096 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2097 },
2098 {
2099 .name = "Nehalem",
2100 .level = 11,
2101 .vendor = CPUID_VENDOR_INTEL,
2102 .family = 6,
2103 .model = 26,
2104 .stepping = 3,
2105 .features[FEAT_1_EDX] =
2106 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2107 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2108 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2109 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2110 CPUID_DE | CPUID_FP87,
2111 .features[FEAT_1_ECX] =
2112 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2113 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2114 .features[FEAT_8000_0001_EDX] =
2115 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2116 .features[FEAT_8000_0001_ECX] =
2117 CPUID_EXT3_LAHF_LM,
2118 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2119 MSR_VMX_BASIC_TRUE_CTLS,
2120 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2121 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2122 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2123 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2124 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2125 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2126 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2127 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2128 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2129 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2130 .features[FEAT_VMX_EXIT_CTLS] =
2131 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2132 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2133 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2134 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2135 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2136 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2137 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2138 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2139 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2140 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2141 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2142 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2143 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2144 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2145 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2146 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2147 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2148 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2149 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2150 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2151 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2152 .features[FEAT_VMX_SECONDARY_CTLS] =
2153 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2154 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2155 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2156 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2157 VMX_SECONDARY_EXEC_ENABLE_VPID,
2158 .xlevel = 0x80000008,
2159 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
2160 .versions = (X86CPUVersionDefinition[]) {
2161 { .version = 1 },
2162 {
2163 .version = 2,
2164 .alias = "Nehalem-IBRS",
2165 .props = (PropValue[]) {
2166 { "spec-ctrl", "on" },
2167 { "model-id",
2168 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2169 { /* end of list */ }
2170 }
2171 },
2172 { /* end of list */ }
2173 }
2174 },
2175 {
2176 .name = "Westmere",
2177 .level = 11,
2178 .vendor = CPUID_VENDOR_INTEL,
2179 .family = 6,
2180 .model = 44,
2181 .stepping = 1,
2182 .features[FEAT_1_EDX] =
2183 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2184 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2185 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2186 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2187 CPUID_DE | CPUID_FP87,
2188 .features[FEAT_1_ECX] =
2189 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2190 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2191 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2192 .features[FEAT_8000_0001_EDX] =
2193 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2194 .features[FEAT_8000_0001_ECX] =
2195 CPUID_EXT3_LAHF_LM,
2196 .features[FEAT_6_EAX] =
2197 CPUID_6_EAX_ARAT,
2198 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2199 MSR_VMX_BASIC_TRUE_CTLS,
2200 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2201 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2202 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2203 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2204 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2205 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2206 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2207 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2208 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2209 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2210 .features[FEAT_VMX_EXIT_CTLS] =
2211 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2212 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2213 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2214 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2215 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2216 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2217 MSR_VMX_MISC_STORE_LMA,
2218 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2219 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2220 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2221 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2222 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2223 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2224 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2225 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2226 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2227 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2228 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2229 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2230 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2231 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2232 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2233 .features[FEAT_VMX_SECONDARY_CTLS] =
2234 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2235 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2236 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2237 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2238 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2239 .xlevel = 0x80000008,
2240 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
2241 .versions = (X86CPUVersionDefinition[]) {
2242 { .version = 1 },
2243 {
2244 .version = 2,
2245 .alias = "Westmere-IBRS",
2246 .props = (PropValue[]) {
2247 { "spec-ctrl", "on" },
2248 { "model-id",
2249 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2250 { /* end of list */ }
2251 }
2252 },
2253 { /* end of list */ }
2254 }
2255 },
2256 {
2257 .name = "SandyBridge",
2258 .level = 0xd,
2259 .vendor = CPUID_VENDOR_INTEL,
2260 .family = 6,
2261 .model = 42,
2262 .stepping = 1,
2263 .features[FEAT_1_EDX] =
2264 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2265 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2266 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2267 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2268 CPUID_DE | CPUID_FP87,
2269 .features[FEAT_1_ECX] =
2270 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2271 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2272 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2273 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2274 CPUID_EXT_SSE3,
2275 .features[FEAT_8000_0001_EDX] =
2276 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2277 CPUID_EXT2_SYSCALL,
2278 .features[FEAT_8000_0001_ECX] =
2279 CPUID_EXT3_LAHF_LM,
2280 .features[FEAT_XSAVE] =
2281 CPUID_XSAVE_XSAVEOPT,
2282 .features[FEAT_6_EAX] =
2283 CPUID_6_EAX_ARAT,
2284 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2285 MSR_VMX_BASIC_TRUE_CTLS,
2286 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2287 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2288 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2289 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2290 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2291 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2292 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2293 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2294 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2295 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2296 .features[FEAT_VMX_EXIT_CTLS] =
2297 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2298 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2299 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2300 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2301 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2302 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2303 MSR_VMX_MISC_STORE_LMA,
2304 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2305 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2306 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2307 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2308 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2309 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2310 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2311 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2312 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2313 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2314 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2315 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2316 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2317 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2318 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2319 .features[FEAT_VMX_SECONDARY_CTLS] =
2320 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2321 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2322 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2323 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2324 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2325 .xlevel = 0x80000008,
2326 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
2327 .versions = (X86CPUVersionDefinition[]) {
2328 { .version = 1 },
2329 {
2330 .version = 2,
2331 .alias = "SandyBridge-IBRS",
2332 .props = (PropValue[]) {
2333 { "spec-ctrl", "on" },
2334 { "model-id",
2335 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2336 { /* end of list */ }
2337 }
2338 },
2339 { /* end of list */ }
2340 }
2341 },
2342 {
2343 .name = "IvyBridge",
2344 .level = 0xd,
2345 .vendor = CPUID_VENDOR_INTEL,
2346 .family = 6,
2347 .model = 58,
2348 .stepping = 9,
2349 .features[FEAT_1_EDX] =
2350 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2351 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2352 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2353 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2354 CPUID_DE | CPUID_FP87,
2355 .features[FEAT_1_ECX] =
2356 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2357 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2358 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2359 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2360 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2361 .features[FEAT_7_0_EBX] =
2362 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2363 CPUID_7_0_EBX_ERMS,
2364 .features[FEAT_8000_0001_EDX] =
2365 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2366 CPUID_EXT2_SYSCALL,
2367 .features[FEAT_8000_0001_ECX] =
2368 CPUID_EXT3_LAHF_LM,
2369 .features[FEAT_XSAVE] =
2370 CPUID_XSAVE_XSAVEOPT,
2371 .features[FEAT_6_EAX] =
2372 CPUID_6_EAX_ARAT,
2373 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2374 MSR_VMX_BASIC_TRUE_CTLS,
2375 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2376 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2377 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2378 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2379 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2380 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2381 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2382 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2383 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2384 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2385 .features[FEAT_VMX_EXIT_CTLS] =
2386 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2387 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2388 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2389 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2390 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2391 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2392 MSR_VMX_MISC_STORE_LMA,
2393 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2394 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2395 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2396 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2397 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2398 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2399 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2400 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2401 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2402 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2403 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2404 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2405 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2406 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2407 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2408 .features[FEAT_VMX_SECONDARY_CTLS] =
2409 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2410 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2411 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2412 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2413 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2414 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2415 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2416 VMX_SECONDARY_EXEC_RDRAND_EXITING,
2417 .xlevel = 0x80000008,
2418 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
2419 .versions = (X86CPUVersionDefinition[]) {
2420 { .version = 1 },
2421 {
2422 .version = 2,
2423 .alias = "IvyBridge-IBRS",
2424 .props = (PropValue[]) {
2425 { "spec-ctrl", "on" },
2426 { "model-id",
2427 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2428 { /* end of list */ }
2429 }
2430 },
2431 { /* end of list */ }
2432 }
2433 },
2434 {
2435 .name = "Haswell",
2436 .level = 0xd,
2437 .vendor = CPUID_VENDOR_INTEL,
2438 .family = 6,
2439 .model = 60,
2440 .stepping = 4,
2441 .features[FEAT_1_EDX] =
2442 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2443 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2444 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2445 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2446 CPUID_DE | CPUID_FP87,
2447 .features[FEAT_1_ECX] =
2448 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2449 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2450 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2451 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2452 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2453 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2454 .features[FEAT_8000_0001_EDX] =
2455 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2456 CPUID_EXT2_SYSCALL,
2457 .features[FEAT_8000_0001_ECX] =
2458 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2459 .features[FEAT_7_0_EBX] =
2460 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2461 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2462 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2463 CPUID_7_0_EBX_RTM,
2464 .features[FEAT_XSAVE] =
2465 CPUID_XSAVE_XSAVEOPT,
2466 .features[FEAT_6_EAX] =
2467 CPUID_6_EAX_ARAT,
2468 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2469 MSR_VMX_BASIC_TRUE_CTLS,
2470 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2471 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2472 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2473 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2474 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2475 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2476 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2477 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2478 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2479 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2480 .features[FEAT_VMX_EXIT_CTLS] =
2481 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2482 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2483 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2484 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2485 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2486 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2487 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2488 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2489 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2490 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2491 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2492 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2493 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2494 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2495 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2496 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2497 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2498 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2499 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2500 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2501 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2502 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2503 .features[FEAT_VMX_SECONDARY_CTLS] =
2504 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2505 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2506 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2507 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2508 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2509 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2510 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2511 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2512 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2513 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2514 .xlevel = 0x80000008,
2515 .model_id = "Intel Core Processor (Haswell)",
2516 .versions = (X86CPUVersionDefinition[]) {
2517 { .version = 1 },
2518 {
2519 .version = 2,
2520 .alias = "Haswell-noTSX",
2521 .props = (PropValue[]) {
2522 { "hle", "off" },
2523 { "rtm", "off" },
2524 { "stepping", "1" },
2525 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2526 { /* end of list */ }
2527 },
2528 },
2529 {
2530 .version = 3,
2531 .alias = "Haswell-IBRS",
2532 .props = (PropValue[]) {
2533 /* Restore TSX features removed by -v2 above */
2534 { "hle", "on" },
2535 { "rtm", "on" },
2536 /*
2537 * Haswell and Haswell-IBRS had stepping=4 in
2538 * QEMU 4.0 and older
2539 */
2540 { "stepping", "4" },
2541 { "spec-ctrl", "on" },
2542 { "model-id",
2543 "Intel Core Processor (Haswell, IBRS)" },
2544 { /* end of list */ }
2545 }
2546 },
2547 {
2548 .version = 4,
2549 .alias = "Haswell-noTSX-IBRS",
2550 .props = (PropValue[]) {
2551 { "hle", "off" },
2552 { "rtm", "off" },
2553 /* spec-ctrl was already enabled by -v3 above */
2554 { "stepping", "1" },
2555 { "model-id",
2556 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2557 { /* end of list */ }
2558 }
2559 },
2560 { /* end of list */ }
2561 }
2562 },
2563 {
2564 .name = "Broadwell",
2565 .level = 0xd,
2566 .vendor = CPUID_VENDOR_INTEL,
2567 .family = 6,
2568 .model = 61,
2569 .stepping = 2,
2570 .features[FEAT_1_EDX] =
2571 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2572 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2573 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2574 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2575 CPUID_DE | CPUID_FP87,
2576 .features[FEAT_1_ECX] =
2577 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2578 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2579 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2580 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2581 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2582 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2583 .features[FEAT_8000_0001_EDX] =
2584 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2585 CPUID_EXT2_SYSCALL,
2586 .features[FEAT_8000_0001_ECX] =
2587 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2588 .features[FEAT_7_0_EBX] =
2589 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2590 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2591 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2592 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2593 CPUID_7_0_EBX_SMAP,
2594 .features[FEAT_XSAVE] =
2595 CPUID_XSAVE_XSAVEOPT,
2596 .features[FEAT_6_EAX] =
2597 CPUID_6_EAX_ARAT,
2598 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2599 MSR_VMX_BASIC_TRUE_CTLS,
2600 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2601 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2602 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2603 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2604 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2605 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2606 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2607 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2608 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2609 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2610 .features[FEAT_VMX_EXIT_CTLS] =
2611 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2612 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2613 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2614 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2615 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2616 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2617 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2618 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2619 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2620 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2621 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2622 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2623 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2624 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2625 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2626 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2627 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2628 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2629 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2630 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2631 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2632 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2633 .features[FEAT_VMX_SECONDARY_CTLS] =
2634 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2635 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2636 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2637 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2638 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2639 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2640 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2641 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2642 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2643 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2644 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2645 .xlevel = 0x80000008,
2646 .model_id = "Intel Core Processor (Broadwell)",
2647 .versions = (X86CPUVersionDefinition[]) {
2648 { .version = 1 },
2649 {
2650 .version = 2,
2651 .alias = "Broadwell-noTSX",
2652 .props = (PropValue[]) {
2653 { "hle", "off" },
2654 { "rtm", "off" },
2655 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2656 { /* end of list */ }
2657 },
2658 },
2659 {
2660 .version = 3,
2661 .alias = "Broadwell-IBRS",
2662 .props = (PropValue[]) {
2663 /* Restore TSX features removed by -v2 above */
2664 { "hle", "on" },
2665 { "rtm", "on" },
2666 { "spec-ctrl", "on" },
2667 { "model-id",
2668 "Intel Core Processor (Broadwell, IBRS)" },
2669 { /* end of list */ }
2670 }
2671 },
2672 {
2673 .version = 4,
2674 .alias = "Broadwell-noTSX-IBRS",
2675 .props = (PropValue[]) {
2676 { "hle", "off" },
2677 { "rtm", "off" },
2678 /* spec-ctrl was already enabled by -v3 above */
2679 { "model-id",
2680 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2681 { /* end of list */ }
2682 }
2683 },
2684 { /* end of list */ }
2685 }
2686 },
2687 {
2688 .name = "Skylake-Client",
2689 .level = 0xd,
2690 .vendor = CPUID_VENDOR_INTEL,
2691 .family = 6,
2692 .model = 94,
2693 .stepping = 3,
2694 .features[FEAT_1_EDX] =
2695 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2696 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2697 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2698 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2699 CPUID_DE | CPUID_FP87,
2700 .features[FEAT_1_ECX] =
2701 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2702 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2703 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2704 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2705 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2706 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2707 .features[FEAT_8000_0001_EDX] =
2708 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2709 CPUID_EXT2_SYSCALL,
2710 .features[FEAT_8000_0001_ECX] =
2711 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2712 .features[FEAT_7_0_EBX] =
2713 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2714 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2715 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2716 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2717 CPUID_7_0_EBX_SMAP,
2718 /* XSAVES is added in version 4 */
2719 .features[FEAT_XSAVE] =
2720 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2721 CPUID_XSAVE_XGETBV1,
2722 .features[FEAT_6_EAX] =
2723 CPUID_6_EAX_ARAT,
2724 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2725 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2726 MSR_VMX_BASIC_TRUE_CTLS,
2727 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2728 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2729 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2730 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2731 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2732 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2733 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2734 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2735 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2736 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2737 .features[FEAT_VMX_EXIT_CTLS] =
2738 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2739 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2740 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2741 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2742 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2743 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2744 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2745 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2746 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2747 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2748 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2749 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2750 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2751 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2752 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2753 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2754 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2755 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2756 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2757 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2758 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2759 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2760 .features[FEAT_VMX_SECONDARY_CTLS] =
2761 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2762 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2763 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2764 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2765 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2766 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2767 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2768 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2769 .xlevel = 0x80000008,
2770 .model_id = "Intel Core Processor (Skylake)",
2771 .versions = (X86CPUVersionDefinition[]) {
2772 { .version = 1 },
2773 {
2774 .version = 2,
2775 .alias = "Skylake-Client-IBRS",
2776 .props = (PropValue[]) {
2777 { "spec-ctrl", "on" },
2778 { "model-id",
2779 "Intel Core Processor (Skylake, IBRS)" },
2780 { /* end of list */ }
2781 }
2782 },
2783 {
2784 .version = 3,
2785 .alias = "Skylake-Client-noTSX-IBRS",
2786 .props = (PropValue[]) {
2787 { "hle", "off" },
2788 { "rtm", "off" },
2789 { "model-id",
2790 "Intel Core Processor (Skylake, IBRS, no TSX)" },
2791 { /* end of list */ }
2792 }
2793 },
2794 {
2795 .version = 4,
2796 .note = "IBRS, XSAVES, no TSX",
2797 .props = (PropValue[]) {
2798 { "xsaves", "on" },
2799 { "vmx-xsaves", "on" },
2800 { /* end of list */ }
2801 }
2802 },
2803 { /* end of list */ }
2804 }
2805 },
2806 {
2807 .name = "Skylake-Server",
2808 .level = 0xd,
2809 .vendor = CPUID_VENDOR_INTEL,
2810 .family = 6,
2811 .model = 85,
2812 .stepping = 4,
2813 .features[FEAT_1_EDX] =
2814 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2815 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2816 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2817 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2818 CPUID_DE | CPUID_FP87,
2819 .features[FEAT_1_ECX] =
2820 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2821 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2822 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2823 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2824 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2825 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2826 .features[FEAT_8000_0001_EDX] =
2827 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2828 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2829 .features[FEAT_8000_0001_ECX] =
2830 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2831 .features[FEAT_7_0_EBX] =
2832 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2833 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2834 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2835 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2836 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2837 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2838 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2839 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2840 .features[FEAT_7_0_ECX] =
2841 CPUID_7_0_ECX_PKU,
2842 /* XSAVES is added in version 5 */
2843 .features[FEAT_XSAVE] =
2844 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2845 CPUID_XSAVE_XGETBV1,
2846 .features[FEAT_6_EAX] =
2847 CPUID_6_EAX_ARAT,
2848 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2849 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2850 MSR_VMX_BASIC_TRUE_CTLS,
2851 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2852 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2853 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2854 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2855 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2856 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2857 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2858 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2859 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2860 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2861 .features[FEAT_VMX_EXIT_CTLS] =
2862 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2863 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2864 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2865 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2866 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2867 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2868 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2869 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2870 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2871 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2872 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2873 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2874 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2875 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2876 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2877 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2878 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2879 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2880 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2881 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2882 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2883 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2884 .features[FEAT_VMX_SECONDARY_CTLS] =
2885 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2886 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2887 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2888 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2889 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2890 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2891 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2892 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2893 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2894 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2895 .xlevel = 0x80000008,
2896 .model_id = "Intel Xeon Processor (Skylake)",
2897 .versions = (X86CPUVersionDefinition[]) {
2898 { .version = 1 },
2899 {
2900 .version = 2,
2901 .alias = "Skylake-Server-IBRS",
2902 .props = (PropValue[]) {
2903 /* clflushopt was not added to Skylake-Server-IBRS */
2904 /* TODO: add -v3 including clflushopt */
2905 { "clflushopt", "off" },
2906 { "spec-ctrl", "on" },
2907 { "model-id",
2908 "Intel Xeon Processor (Skylake, IBRS)" },
2909 { /* end of list */ }
2910 }
2911 },
2912 {
2913 .version = 3,
2914 .alias = "Skylake-Server-noTSX-IBRS",
2915 .props = (PropValue[]) {
2916 { "hle", "off" },
2917 { "rtm", "off" },
2918 { "model-id",
2919 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
2920 { /* end of list */ }
2921 }
2922 },
2923 {
2924 .version = 4,
2925 .props = (PropValue[]) {
2926 { "vmx-eptp-switching", "on" },
2927 { /* end of list */ }
2928 }
2929 },
2930 {
2931 .version = 5,
2932 .note = "IBRS, XSAVES, EPT switching, no TSX",
2933 .props = (PropValue[]) {
2934 { "xsaves", "on" },
2935 { "vmx-xsaves", "on" },
2936 { /* end of list */ }
2937 }
2938 },
2939 { /* end of list */ }
2940 }
2941 },
2942 {
2943 .name = "Cascadelake-Server",
2944 .level = 0xd,
2945 .vendor = CPUID_VENDOR_INTEL,
2946 .family = 6,
2947 .model = 85,
2948 .stepping = 6,
2949 .features[FEAT_1_EDX] =
2950 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2951 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2952 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2953 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2954 CPUID_DE | CPUID_FP87,
2955 .features[FEAT_1_ECX] =
2956 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2957 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2958 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2959 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2960 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2961 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2962 .features[FEAT_8000_0001_EDX] =
2963 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2964 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2965 .features[FEAT_8000_0001_ECX] =
2966 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2967 .features[FEAT_7_0_EBX] =
2968 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2969 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2970 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2971 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2972 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2973 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2974 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2975 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2976 .features[FEAT_7_0_ECX] =
2977 CPUID_7_0_ECX_PKU |
2978 CPUID_7_0_ECX_AVX512VNNI,
2979 .features[FEAT_7_0_EDX] =
2980 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2981 /* XSAVES is added in version 5 */
2982 .features[FEAT_XSAVE] =
2983 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2984 CPUID_XSAVE_XGETBV1,
2985 .features[FEAT_6_EAX] =
2986 CPUID_6_EAX_ARAT,
2987 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2988 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2989 MSR_VMX_BASIC_TRUE_CTLS,
2990 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2991 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2992 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2993 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2994 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2995 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2996 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2997 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2998 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2999 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3000 .features[FEAT_VMX_EXIT_CTLS] =
3001 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3002 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3003 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3004 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3005 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3006 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3007 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3008 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3009 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3010 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3011 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3012 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3013 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3014 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3015 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3016 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3017 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3018 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3019 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3020 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3021 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3022 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3023 .features[FEAT_VMX_SECONDARY_CTLS] =
3024 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3025 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3026 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3027 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3028 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3029 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3030 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3031 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3032 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3033 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3034 .xlevel = 0x80000008,
3035 .model_id = "Intel Xeon Processor (Cascadelake)",
3036 .versions = (X86CPUVersionDefinition[]) {
3037 { .version = 1 },
3038 { .version = 2,
3039 .note = "ARCH_CAPABILITIES",
3040 .props = (PropValue[]) {
3041 { "arch-capabilities", "on" },
3042 { "rdctl-no", "on" },
3043 { "ibrs-all", "on" },
3044 { "skip-l1dfl-vmentry", "on" },
3045 { "mds-no", "on" },
3046 { /* end of list */ }
3047 },
3048 },
3049 { .version = 3,
3050 .alias = "Cascadelake-Server-noTSX",
3051 .note = "ARCH_CAPABILITIES, no TSX",
3052 .props = (PropValue[]) {
3053 { "hle", "off" },
3054 { "rtm", "off" },
3055 { /* end of list */ }
3056 },
3057 },
3058 { .version = 4,
3059 .note = "ARCH_CAPABILITIES, no TSX",
3060 .props = (PropValue[]) {
3061 { "vmx-eptp-switching", "on" },
3062 { /* end of list */ }
3063 },
3064 },
3065 { .version = 5,
3066 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX",
3067 .props = (PropValue[]) {
3068 { "xsaves", "on" },
3069 { "vmx-xsaves", "on" },
3070 { /* end of list */ }
3071 },
3072 },
3073 { /* end of list */ }
3074 }
3075 },
3076 {
3077 .name = "Cooperlake",
3078 .level = 0xd,
3079 .vendor = CPUID_VENDOR_INTEL,
3080 .family = 6,
3081 .model = 85,
3082 .stepping = 10,
3083 .features[FEAT_1_EDX] =
3084 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3085 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3086 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3087 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3088 CPUID_DE | CPUID_FP87,
3089 .features[FEAT_1_ECX] =
3090 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3091 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3092 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3093 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3094 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3095 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3096 .features[FEAT_8000_0001_EDX] =
3097 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3098 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3099 .features[FEAT_8000_0001_ECX] =
3100 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3101 .features[FEAT_7_0_EBX] =
3102 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3103 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3104 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3105 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3106 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3107 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3108 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3109 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3110 .features[FEAT_7_0_ECX] =
3111 CPUID_7_0_ECX_PKU |
3112 CPUID_7_0_ECX_AVX512VNNI,
3113 .features[FEAT_7_0_EDX] =
3114 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3115 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3116 .features[FEAT_ARCH_CAPABILITIES] =
3117 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
3118 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3119 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
3120 .features[FEAT_7_1_EAX] =
3121 CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16,
3122 /* XSAVES is added in version 2 */
3123 .features[FEAT_XSAVE] =
3124 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3125 CPUID_XSAVE_XGETBV1,
3126 .features[FEAT_6_EAX] =
3127 CPUID_6_EAX_ARAT,
3128 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3129 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3130 MSR_VMX_BASIC_TRUE_CTLS,
3131 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3132 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3133 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3134 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3135 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3136 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3137 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3138 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3139 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3140 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3141 .features[FEAT_VMX_EXIT_CTLS] =
3142 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3143 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3144 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3145 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3146 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3147 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3148 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3149 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3150 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3151 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3152 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3153 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3154 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3155 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3156 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3157 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3158 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3159 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3160 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3161 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3162 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3163 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3164 .features[FEAT_VMX_SECONDARY_CTLS] =
3165 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3166 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3167 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3168 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3169 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3170 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3171 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3172 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3173 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3174 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3175 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3176 .xlevel = 0x80000008,
3177 .model_id = "Intel Xeon Processor (Cooperlake)",
3178 .versions = (X86CPUVersionDefinition[]) {
3179 { .version = 1 },
3180 { .version = 2,
3181 .note = "XSAVES",
3182 .props = (PropValue[]) {
3183 { "xsaves", "on" },
3184 { "vmx-xsaves", "on" },
3185 { /* end of list */ }
3186 },
3187 },
3188 { /* end of list */ }
3189 }
3190 },
3191 {
3192 .name = "Icelake-Client",
3193 .level = 0xd,
3194 .vendor = CPUID_VENDOR_INTEL,
3195 .family = 6,
3196 .model = 126,
3197 .stepping = 0,
3198 .features[FEAT_1_EDX] =
3199 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3200 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3201 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3202 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3203 CPUID_DE | CPUID_FP87,
3204 .features[FEAT_1_ECX] =
3205 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3206 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3207 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3208 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3209 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3210 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3211 .features[FEAT_8000_0001_EDX] =
3212 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3213 CPUID_EXT2_SYSCALL,
3214 .features[FEAT_8000_0001_ECX] =
3215 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3216 .features[FEAT_8000_0008_EBX] =
3217 CPUID_8000_0008_EBX_WBNOINVD,
3218 .features[FEAT_7_0_EBX] =
3219 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3220 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3221 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3222 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3223 CPUID_7_0_EBX_SMAP,
3224 .features[FEAT_7_0_ECX] =
3225 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3226 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3227 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3228 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3229 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3230 .features[FEAT_7_0_EDX] =
3231 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3232 /* XSAVES is added in version 3 */
3233 .features[FEAT_XSAVE] =
3234 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3235 CPUID_XSAVE_XGETBV1,
3236 .features[FEAT_6_EAX] =
3237 CPUID_6_EAX_ARAT,
3238 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3239 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3240 MSR_VMX_BASIC_TRUE_CTLS,
3241 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3242 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3243 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3244 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3245 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3246 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3247 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3248 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3249 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3250 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3251 .features[FEAT_VMX_EXIT_CTLS] =
3252 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3253 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3254 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3255 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3256 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3257 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3258 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3259 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3260 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3261 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
3262 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3263 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3264 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3265 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3266 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3267 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3268 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3269 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3270 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3271 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3272 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3273 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3274 .features[FEAT_VMX_SECONDARY_CTLS] =
3275 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3276 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3277 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3278 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3279 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3280 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3281 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3282 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3283 .xlevel = 0x80000008,
3284 .model_id = "Intel Core Processor (Icelake)",
3285 .versions = (X86CPUVersionDefinition[]) {
3286 {
3287 .version = 1,
3288 .note = "deprecated"
3289 },
3290 {
3291 .version = 2,
3292 .note = "no TSX, deprecated",
3293 .alias = "Icelake-Client-noTSX",
3294 .props = (PropValue[]) {
3295 { "hle", "off" },
3296 { "rtm", "off" },
3297 { /* end of list */ }
3298 },
3299 },
3300 {
3301 .version = 3,
3302 .note = "no TSX, XSAVES, deprecated",
3303 .props = (PropValue[]) {
3304 { "xsaves", "on" },
3305 { "vmx-xsaves", "on" },
3306 { /* end of list */ }
3307 },
3308 },
3309 { /* end of list */ }
3310 },
3311 .deprecation_note = "use Icelake-Server instead"
3312 },
3313 {
3314 .name = "Icelake-Server",
3315 .level = 0xd,
3316 .vendor = CPUID_VENDOR_INTEL,
3317 .family = 6,
3318 .model = 134,
3319 .stepping = 0,
3320 .features[FEAT_1_EDX] =
3321 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3322 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3323 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3324 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3325 CPUID_DE | CPUID_FP87,
3326 .features[FEAT_1_ECX] =
3327 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3328 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3329 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3330 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3331 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3332 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3333 .features[FEAT_8000_0001_EDX] =
3334 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3335 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3336 .features[FEAT_8000_0001_ECX] =
3337 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3338 .features[FEAT_8000_0008_EBX] =
3339 CPUID_8000_0008_EBX_WBNOINVD,
3340 .features[FEAT_7_0_EBX] =
3341 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3342 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3343 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3344 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3345 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3346 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3347 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3348 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3349 .features[FEAT_7_0_ECX] =
3350 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3351 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3352 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3353 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3354 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3355 .features[FEAT_7_0_EDX] =
3356 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3357 /* XSAVES is added in version 5 */
3358 .features[FEAT_XSAVE] =
3359 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3360 CPUID_XSAVE_XGETBV1,
3361 .features[FEAT_6_EAX] =
3362 CPUID_6_EAX_ARAT,
3363 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3364 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3365 MSR_VMX_BASIC_TRUE_CTLS,
3366 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3367 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3368 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3369 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3370 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3371 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3372 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3373 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3374 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3375 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3376 .features[FEAT_VMX_EXIT_CTLS] =
3377 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3378 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3379 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3380 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3381 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3382 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3383 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3384 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3385 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3386 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3387 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3388 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3389 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3390 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3391 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3392 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3393 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3394 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3395 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3396 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3397 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3398 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3399 .features[FEAT_VMX_SECONDARY_CTLS] =
3400 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3401 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3402 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3403 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3404 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3405 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3406 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3407 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3408 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
3409 .xlevel = 0x80000008,
3410 .model_id = "Intel Xeon Processor (Icelake)",
3411 .versions = (X86CPUVersionDefinition[]) {
3412 { .version = 1 },
3413 {
3414 .version = 2,
3415 .note = "no TSX",
3416 .alias = "Icelake-Server-noTSX",
3417 .props = (PropValue[]) {
3418 { "hle", "off" },
3419 { "rtm", "off" },
3420 { /* end of list */ }
3421 },
3422 },
3423 {
3424 .version = 3,
3425 .props = (PropValue[]) {
3426 { "arch-capabilities", "on" },
3427 { "rdctl-no", "on" },
3428 { "ibrs-all", "on" },
3429 { "skip-l1dfl-vmentry", "on" },
3430 { "mds-no", "on" },
3431 { "pschange-mc-no", "on" },
3432 { "taa-no", "on" },
3433 { /* end of list */ }
3434 },
3435 },
3436 {
3437 .version = 4,
3438 .props = (PropValue[]) {
3439 { "sha-ni", "on" },
3440 { "avx512ifma", "on" },
3441 { "rdpid", "on" },
3442 { "fsrm", "on" },
3443 { "vmx-rdseed-exit", "on" },
3444 { "vmx-pml", "on" },
3445 { "vmx-eptp-switching", "on" },
3446 { "model", "106" },
3447 { /* end of list */ }
3448 },
3449 },
3450 {
3451 .version = 5,
3452 .note = "XSAVES",
3453 .props = (PropValue[]) {
3454 { "xsaves", "on" },
3455 { "vmx-xsaves", "on" },
3456 { /* end of list */ }
3457 },
3458 },
3459 { /* end of list */ }
3460 }
3461 },
3462 {
3463 .name = "Denverton",
3464 .level = 21,
3465 .vendor = CPUID_VENDOR_INTEL,
3466 .family = 6,
3467 .model = 95,
3468 .stepping = 1,
3469 .features[FEAT_1_EDX] =
3470 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3471 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3472 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3473 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3474 CPUID_SSE | CPUID_SSE2,
3475 .features[FEAT_1_ECX] =
3476 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3477 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
3478 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3479 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
3480 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
3481 .features[FEAT_8000_0001_EDX] =
3482 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3483 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3484 .features[FEAT_8000_0001_ECX] =
3485 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3486 .features[FEAT_7_0_EBX] =
3487 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
3488 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
3489 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
3490 .features[FEAT_7_0_EDX] =
3491 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
3492 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3493 /* XSAVES is added in version 3 */
3494 .features[FEAT_XSAVE] =
3495 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
3496 .features[FEAT_6_EAX] =
3497 CPUID_6_EAX_ARAT,
3498 .features[FEAT_ARCH_CAPABILITIES] =
3499 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
3500 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3501 MSR_VMX_BASIC_TRUE_CTLS,
3502 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3503 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3504 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3505 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3506 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3507 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3508 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3509 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3510 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3511 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3512 .features[FEAT_VMX_EXIT_CTLS] =
3513 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3514 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3515 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3516 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3517 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3518 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3519 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3520 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3521 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3522 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3523 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3524 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3525 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3526 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3527 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3528 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3529 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3530 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3531 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3532 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3533 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3534 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3535 .features[FEAT_VMX_SECONDARY_CTLS] =
3536 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3537 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3538 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3539 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3540 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3541 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3542 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3543 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3544 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3545 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3546 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3547 .xlevel = 0x80000008,
3548 .model_id = "Intel Atom Processor (Denverton)",
3549 .versions = (X86CPUVersionDefinition[]) {
3550 { .version = 1 },
3551 {
3552 .version = 2,
3553 .note = "no MPX, no MONITOR",
3554 .props = (PropValue[]) {
3555 { "monitor", "off" },
3556 { "mpx", "off" },
3557 { /* end of list */ },
3558 },
3559 },
3560 {
3561 .version = 3,
3562 .note = "XSAVES, no MPX, no MONITOR",
3563