Merge tag 'edgar/xilinx-next-2022-09-21.for-upstream' of https://github.com/edgarigl...
[qemu.git] / target / i386 / cpu.c
1 /*
2 * i386 CPUID, CPU class, definitions, models
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/qemu-print.h"
24 #include "cpu.h"
25 #include "tcg/helper-tcg.h"
26 #include "sysemu/reset.h"
27 #include "sysemu/hvf.h"
28 #include "kvm/kvm_i386.h"
29 #include "sev.h"
30 #include "qapi/error.h"
31 #include "qapi/qapi-visit-machine.h"
32 #include "qapi/qmp/qerror.h"
33 #include "qapi/qapi-commands-machine-target.h"
34 #include "standard-headers/asm-x86/kvm_para.h"
35 #include "hw/qdev-properties.h"
36 #include "hw/i386/topology.h"
37 #ifndef CONFIG_USER_ONLY
38 #include "exec/address-spaces.h"
39 #include "hw/boards.h"
40 #include "hw/i386/sgx-epc.h"
41 #endif
42
43 #include "disas/capstone.h"
44 #include "cpu-internal.h"
45
46 /* Helpers for building CPUID[2] descriptors: */
47
48 struct CPUID2CacheDescriptorInfo {
49 enum CacheType type;
50 int level;
51 int size;
52 int line_size;
53 int associativity;
54 };
55
56 /*
57 * Known CPUID 2 cache descriptors.
58 * From Intel SDM Volume 2A, CPUID instruction
59 */
60 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
61 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
62 .associativity = 4, .line_size = 32, },
63 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
64 .associativity = 4, .line_size = 32, },
65 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
66 .associativity = 4, .line_size = 64, },
67 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
68 .associativity = 2, .line_size = 32, },
69 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
70 .associativity = 4, .line_size = 32, },
71 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
72 .associativity = 4, .line_size = 64, },
73 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
74 .associativity = 6, .line_size = 64, },
75 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
76 .associativity = 2, .line_size = 64, },
77 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
78 .associativity = 8, .line_size = 64, },
79 /* lines per sector is not supported cpuid2_cache_descriptor(),
80 * so descriptors 0x22, 0x23 are not included
81 */
82 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
83 .associativity = 16, .line_size = 64, },
84 /* lines per sector is not supported cpuid2_cache_descriptor(),
85 * so descriptors 0x25, 0x20 are not included
86 */
87 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
88 .associativity = 8, .line_size = 64, },
89 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
90 .associativity = 8, .line_size = 64, },
91 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
92 .associativity = 4, .line_size = 32, },
93 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
94 .associativity = 4, .line_size = 32, },
95 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
96 .associativity = 4, .line_size = 32, },
97 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
98 .associativity = 4, .line_size = 32, },
99 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
100 .associativity = 4, .line_size = 32, },
101 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
102 .associativity = 4, .line_size = 64, },
103 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
104 .associativity = 8, .line_size = 64, },
105 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
106 .associativity = 12, .line_size = 64, },
107 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
108 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
109 .associativity = 12, .line_size = 64, },
110 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
111 .associativity = 16, .line_size = 64, },
112 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
113 .associativity = 12, .line_size = 64, },
114 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
115 .associativity = 16, .line_size = 64, },
116 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
117 .associativity = 24, .line_size = 64, },
118 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
119 .associativity = 8, .line_size = 64, },
120 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
121 .associativity = 4, .line_size = 64, },
122 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
123 .associativity = 4, .line_size = 64, },
124 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
125 .associativity = 4, .line_size = 64, },
126 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
127 .associativity = 4, .line_size = 64, },
128 /* lines per sector is not supported cpuid2_cache_descriptor(),
129 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
130 */
131 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
132 .associativity = 8, .line_size = 64, },
133 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
134 .associativity = 2, .line_size = 64, },
135 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
136 .associativity = 8, .line_size = 64, },
137 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
138 .associativity = 8, .line_size = 32, },
139 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
140 .associativity = 8, .line_size = 32, },
141 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
142 .associativity = 8, .line_size = 32, },
143 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
144 .associativity = 8, .line_size = 32, },
145 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
146 .associativity = 4, .line_size = 64, },
147 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
148 .associativity = 8, .line_size = 64, },
149 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
150 .associativity = 4, .line_size = 64, },
151 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
152 .associativity = 4, .line_size = 64, },
153 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
154 .associativity = 4, .line_size = 64, },
155 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
156 .associativity = 8, .line_size = 64, },
157 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
158 .associativity = 8, .line_size = 64, },
159 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
160 .associativity = 8, .line_size = 64, },
161 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
162 .associativity = 12, .line_size = 64, },
163 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
164 .associativity = 12, .line_size = 64, },
165 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
166 .associativity = 12, .line_size = 64, },
167 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
168 .associativity = 16, .line_size = 64, },
169 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
170 .associativity = 16, .line_size = 64, },
171 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
172 .associativity = 16, .line_size = 64, },
173 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
174 .associativity = 24, .line_size = 64, },
175 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
176 .associativity = 24, .line_size = 64, },
177 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
178 .associativity = 24, .line_size = 64, },
179 };
180
181 /*
182 * "CPUID leaf 2 does not report cache descriptor information,
183 * use CPUID leaf 4 to query cache parameters"
184 */
185 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
186
187 /*
188 * Return a CPUID 2 cache descriptor for a given cache.
189 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
190 */
191 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
192 {
193 int i;
194
195 assert(cache->size > 0);
196 assert(cache->level > 0);
197 assert(cache->line_size > 0);
198 assert(cache->associativity > 0);
199 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
200 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
201 if (d->level == cache->level && d->type == cache->type &&
202 d->size == cache->size && d->line_size == cache->line_size &&
203 d->associativity == cache->associativity) {
204 return i;
205 }
206 }
207
208 return CACHE_DESCRIPTOR_UNAVAILABLE;
209 }
210
211 /* CPUID Leaf 4 constants: */
212
213 /* EAX: */
214 #define CACHE_TYPE_D 1
215 #define CACHE_TYPE_I 2
216 #define CACHE_TYPE_UNIFIED 3
217
218 #define CACHE_LEVEL(l) (l << 5)
219
220 #define CACHE_SELF_INIT_LEVEL (1 << 8)
221
222 /* EDX: */
223 #define CACHE_NO_INVD_SHARING (1 << 0)
224 #define CACHE_INCLUSIVE (1 << 1)
225 #define CACHE_COMPLEX_IDX (1 << 2)
226
227 /* Encode CacheType for CPUID[4].EAX */
228 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
229 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
230 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
231 0 /* Invalid value */)
232
233
234 /* Encode cache info for CPUID[4] */
235 static void encode_cache_cpuid4(CPUCacheInfo *cache,
236 int num_apic_ids, int num_cores,
237 uint32_t *eax, uint32_t *ebx,
238 uint32_t *ecx, uint32_t *edx)
239 {
240 assert(cache->size == cache->line_size * cache->associativity *
241 cache->partitions * cache->sets);
242
243 assert(num_apic_ids > 0);
244 *eax = CACHE_TYPE(cache->type) |
245 CACHE_LEVEL(cache->level) |
246 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
247 ((num_cores - 1) << 26) |
248 ((num_apic_ids - 1) << 14);
249
250 assert(cache->line_size > 0);
251 assert(cache->partitions > 0);
252 assert(cache->associativity > 0);
253 /* We don't implement fully-associative caches */
254 assert(cache->associativity < cache->sets);
255 *ebx = (cache->line_size - 1) |
256 ((cache->partitions - 1) << 12) |
257 ((cache->associativity - 1) << 22);
258
259 assert(cache->sets > 0);
260 *ecx = cache->sets - 1;
261
262 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
263 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
264 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
265 }
266
267 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
268 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
269 {
270 assert(cache->size % 1024 == 0);
271 assert(cache->lines_per_tag > 0);
272 assert(cache->associativity > 0);
273 assert(cache->line_size > 0);
274 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
275 (cache->lines_per_tag << 8) | (cache->line_size);
276 }
277
278 #define ASSOC_FULL 0xFF
279
280 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
281 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
282 a == 2 ? 0x2 : \
283 a == 4 ? 0x4 : \
284 a == 8 ? 0x6 : \
285 a == 16 ? 0x8 : \
286 a == 32 ? 0xA : \
287 a == 48 ? 0xB : \
288 a == 64 ? 0xC : \
289 a == 96 ? 0xD : \
290 a == 128 ? 0xE : \
291 a == ASSOC_FULL ? 0xF : \
292 0 /* invalid value */)
293
294 /*
295 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
296 * @l3 can be NULL.
297 */
298 static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
299 CPUCacheInfo *l3,
300 uint32_t *ecx, uint32_t *edx)
301 {
302 assert(l2->size % 1024 == 0);
303 assert(l2->associativity > 0);
304 assert(l2->lines_per_tag > 0);
305 assert(l2->line_size > 0);
306 *ecx = ((l2->size / 1024) << 16) |
307 (AMD_ENC_ASSOC(l2->associativity) << 12) |
308 (l2->lines_per_tag << 8) | (l2->line_size);
309
310 if (l3) {
311 assert(l3->size % (512 * 1024) == 0);
312 assert(l3->associativity > 0);
313 assert(l3->lines_per_tag > 0);
314 assert(l3->line_size > 0);
315 *edx = ((l3->size / (512 * 1024)) << 18) |
316 (AMD_ENC_ASSOC(l3->associativity) << 12) |
317 (l3->lines_per_tag << 8) | (l3->line_size);
318 } else {
319 *edx = 0;
320 }
321 }
322
323 /* Encode cache info for CPUID[8000001D] */
324 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
325 X86CPUTopoInfo *topo_info,
326 uint32_t *eax, uint32_t *ebx,
327 uint32_t *ecx, uint32_t *edx)
328 {
329 uint32_t l3_threads;
330 assert(cache->size == cache->line_size * cache->associativity *
331 cache->partitions * cache->sets);
332
333 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
334 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
335
336 /* L3 is shared among multiple cores */
337 if (cache->level == 3) {
338 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core;
339 *eax |= (l3_threads - 1) << 14;
340 } else {
341 *eax |= ((topo_info->threads_per_core - 1) << 14);
342 }
343
344 assert(cache->line_size > 0);
345 assert(cache->partitions > 0);
346 assert(cache->associativity > 0);
347 /* We don't implement fully-associative caches */
348 assert(cache->associativity < cache->sets);
349 *ebx = (cache->line_size - 1) |
350 ((cache->partitions - 1) << 12) |
351 ((cache->associativity - 1) << 22);
352
353 assert(cache->sets > 0);
354 *ecx = cache->sets - 1;
355
356 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
357 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
358 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
359 }
360
361 /* Encode cache info for CPUID[8000001E] */
362 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
363 uint32_t *eax, uint32_t *ebx,
364 uint32_t *ecx, uint32_t *edx)
365 {
366 X86CPUTopoIDs topo_ids;
367
368 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
369
370 *eax = cpu->apic_id;
371
372 /*
373 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
374 * Read-only. Reset: 0000_XXXXh.
375 * See Core::X86::Cpuid::ExtApicId.
376 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
377 * Bits Description
378 * 31:16 Reserved.
379 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
380 * The number of threads per core is ThreadsPerCore+1.
381 * 7:0 CoreId: core ID. Read-only. Reset: XXh.
382 *
383 * NOTE: CoreId is already part of apic_id. Just use it. We can
384 * use all the 8 bits to represent the core_id here.
385 */
386 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF);
387
388 /*
389 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
390 * Read-only. Reset: 0000_0XXXh.
391 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
392 * Bits Description
393 * 31:11 Reserved.
394 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
395 * ValidValues:
396 * Value Description
397 * 000b 1 node per processor.
398 * 001b 2 nodes per processor.
399 * 010b Reserved.
400 * 011b 4 nodes per processor.
401 * 111b-100b Reserved.
402 * 7:0 NodeId: Node ID. Read-only. Reset: XXh.
403 *
404 * NOTE: Hardware reserves 3 bits for number of nodes per processor.
405 * But users can create more nodes than the actual hardware can
406 * support. To genaralize we can use all the upper 8 bits for nodes.
407 * NodeId is combination of node and socket_id which is already decoded
408 * in apic_id. Just use it by shifting.
409 */
410 *ecx = ((topo_info->dies_per_pkg - 1) << 8) |
411 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
412
413 *edx = 0;
414 }
415
416 /*
417 * Definitions of the hardcoded cache entries we expose:
418 * These are legacy cache values. If there is a need to change any
419 * of these values please use builtin_x86_defs
420 */
421
422 /* L1 data cache: */
423 static CPUCacheInfo legacy_l1d_cache = {
424 .type = DATA_CACHE,
425 .level = 1,
426 .size = 32 * KiB,
427 .self_init = 1,
428 .line_size = 64,
429 .associativity = 8,
430 .sets = 64,
431 .partitions = 1,
432 .no_invd_sharing = true,
433 };
434
435 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
436 static CPUCacheInfo legacy_l1d_cache_amd = {
437 .type = DATA_CACHE,
438 .level = 1,
439 .size = 64 * KiB,
440 .self_init = 1,
441 .line_size = 64,
442 .associativity = 2,
443 .sets = 512,
444 .partitions = 1,
445 .lines_per_tag = 1,
446 .no_invd_sharing = true,
447 };
448
449 /* L1 instruction cache: */
450 static CPUCacheInfo legacy_l1i_cache = {
451 .type = INSTRUCTION_CACHE,
452 .level = 1,
453 .size = 32 * KiB,
454 .self_init = 1,
455 .line_size = 64,
456 .associativity = 8,
457 .sets = 64,
458 .partitions = 1,
459 .no_invd_sharing = true,
460 };
461
462 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
463 static CPUCacheInfo legacy_l1i_cache_amd = {
464 .type = INSTRUCTION_CACHE,
465 .level = 1,
466 .size = 64 * KiB,
467 .self_init = 1,
468 .line_size = 64,
469 .associativity = 2,
470 .sets = 512,
471 .partitions = 1,
472 .lines_per_tag = 1,
473 .no_invd_sharing = true,
474 };
475
476 /* Level 2 unified cache: */
477 static CPUCacheInfo legacy_l2_cache = {
478 .type = UNIFIED_CACHE,
479 .level = 2,
480 .size = 4 * MiB,
481 .self_init = 1,
482 .line_size = 64,
483 .associativity = 16,
484 .sets = 4096,
485 .partitions = 1,
486 .no_invd_sharing = true,
487 };
488
489 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
490 static CPUCacheInfo legacy_l2_cache_cpuid2 = {
491 .type = UNIFIED_CACHE,
492 .level = 2,
493 .size = 2 * MiB,
494 .line_size = 64,
495 .associativity = 8,
496 };
497
498
499 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
500 static CPUCacheInfo legacy_l2_cache_amd = {
501 .type = UNIFIED_CACHE,
502 .level = 2,
503 .size = 512 * KiB,
504 .line_size = 64,
505 .lines_per_tag = 1,
506 .associativity = 16,
507 .sets = 512,
508 .partitions = 1,
509 };
510
511 /* Level 3 unified cache: */
512 static CPUCacheInfo legacy_l3_cache = {
513 .type = UNIFIED_CACHE,
514 .level = 3,
515 .size = 16 * MiB,
516 .line_size = 64,
517 .associativity = 16,
518 .sets = 16384,
519 .partitions = 1,
520 .lines_per_tag = 1,
521 .self_init = true,
522 .inclusive = true,
523 .complex_indexing = true,
524 };
525
526 /* TLB definitions: */
527
528 #define L1_DTLB_2M_ASSOC 1
529 #define L1_DTLB_2M_ENTRIES 255
530 #define L1_DTLB_4K_ASSOC 1
531 #define L1_DTLB_4K_ENTRIES 255
532
533 #define L1_ITLB_2M_ASSOC 1
534 #define L1_ITLB_2M_ENTRIES 255
535 #define L1_ITLB_4K_ASSOC 1
536 #define L1_ITLB_4K_ENTRIES 255
537
538 #define L2_DTLB_2M_ASSOC 0 /* disabled */
539 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
540 #define L2_DTLB_4K_ASSOC 4
541 #define L2_DTLB_4K_ENTRIES 512
542
543 #define L2_ITLB_2M_ASSOC 0 /* disabled */
544 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
545 #define L2_ITLB_4K_ASSOC 4
546 #define L2_ITLB_4K_ENTRIES 512
547
548 /* CPUID Leaf 0x14 constants: */
549 #define INTEL_PT_MAX_SUBLEAF 0x1
550 /*
551 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
552 * MSR can be accessed;
553 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
554 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
555 * of Intel PT MSRs across warm reset;
556 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
557 */
558 #define INTEL_PT_MINIMAL_EBX 0xf
559 /*
560 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
561 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
562 * accessed;
563 * bit[01]: ToPA tables can hold any number of output entries, up to the
564 * maximum allowed by the MaskOrTableOffset field of
565 * IA32_RTIT_OUTPUT_MASK_PTRS;
566 * bit[02]: Support Single-Range Output scheme;
567 */
568 #define INTEL_PT_MINIMAL_ECX 0x7
569 /* generated packets which contain IP payloads have LIP values */
570 #define INTEL_PT_IP_LIP (1 << 31)
571 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
572 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
573 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
574 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
575 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
576
577 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
578 uint32_t vendor2, uint32_t vendor3)
579 {
580 int i;
581 for (i = 0; i < 4; i++) {
582 dst[i] = vendor1 >> (8 * i);
583 dst[i + 4] = vendor2 >> (8 * i);
584 dst[i + 8] = vendor3 >> (8 * i);
585 }
586 dst[CPUID_VENDOR_SZ] = '\0';
587 }
588
589 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
590 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
591 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
592 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
593 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
594 CPUID_PSE36 | CPUID_FXSR)
595 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
596 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
597 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
598 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
599 CPUID_PAE | CPUID_SEP | CPUID_APIC)
600
601 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
602 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
603 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
604 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
605 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
606 /* partly implemented:
607 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
608 /* missing:
609 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
610 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
611 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
612 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
613 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
614 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
615 CPUID_EXT_RDRAND)
616 /* missing:
617 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
618 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
619 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
620 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
621 CPUID_EXT_F16C */
622
623 #ifdef TARGET_X86_64
624 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
625 #else
626 #define TCG_EXT2_X86_64_FEATURES 0
627 #endif
628
629 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
630 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
631 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
632 TCG_EXT2_X86_64_FEATURES)
633 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
634 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
635 #define TCG_EXT4_FEATURES 0
636 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \
637 CPUID_SVM_SVME_ADDR_CHK)
638 #define TCG_KVM_FEATURES 0
639 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
640 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
641 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
642 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
643 CPUID_7_0_EBX_ERMS)
644 /* missing:
645 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
646 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
647 CPUID_7_0_EBX_RDSEED */
648 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
649 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
650 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS)
651 #define TCG_7_0_EDX_FEATURES 0
652 #define TCG_7_1_EAX_FEATURES 0
653 #define TCG_APM_FEATURES 0
654 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
655 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
656 /* missing:
657 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
658 #define TCG_14_0_ECX_FEATURES 0
659 #define TCG_SGX_12_0_EAX_FEATURES 0
660 #define TCG_SGX_12_0_EBX_FEATURES 0
661 #define TCG_SGX_12_1_EAX_FEATURES 0
662
663 FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
664 [FEAT_1_EDX] = {
665 .type = CPUID_FEATURE_WORD,
666 .feat_names = {
667 "fpu", "vme", "de", "pse",
668 "tsc", "msr", "pae", "mce",
669 "cx8", "apic", NULL, "sep",
670 "mtrr", "pge", "mca", "cmov",
671 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
672 NULL, "ds" /* Intel dts */, "acpi", "mmx",
673 "fxsr", "sse", "sse2", "ss",
674 "ht" /* Intel htt */, "tm", "ia64", "pbe",
675 },
676 .cpuid = {.eax = 1, .reg = R_EDX, },
677 .tcg_features = TCG_FEATURES,
678 },
679 [FEAT_1_ECX] = {
680 .type = CPUID_FEATURE_WORD,
681 .feat_names = {
682 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
683 "ds-cpl", "vmx", "smx", "est",
684 "tm2", "ssse3", "cid", NULL,
685 "fma", "cx16", "xtpr", "pdcm",
686 NULL, "pcid", "dca", "sse4.1",
687 "sse4.2", "x2apic", "movbe", "popcnt",
688 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
689 "avx", "f16c", "rdrand", "hypervisor",
690 },
691 .cpuid = { .eax = 1, .reg = R_ECX, },
692 .tcg_features = TCG_EXT_FEATURES,
693 },
694 /* Feature names that are already defined on feature_name[] but
695 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
696 * names on feat_names below. They are copied automatically
697 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
698 */
699 [FEAT_8000_0001_EDX] = {
700 .type = CPUID_FEATURE_WORD,
701 .feat_names = {
702 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
703 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
704 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
705 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
706 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
707 "nx", NULL, "mmxext", NULL /* mmx */,
708 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
709 NULL, "lm", "3dnowext", "3dnow",
710 },
711 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
712 .tcg_features = TCG_EXT2_FEATURES,
713 },
714 [FEAT_8000_0001_ECX] = {
715 .type = CPUID_FEATURE_WORD,
716 .feat_names = {
717 "lahf-lm", "cmp-legacy", "svm", "extapic",
718 "cr8legacy", "abm", "sse4a", "misalignsse",
719 "3dnowprefetch", "osvw", "ibs", "xop",
720 "skinit", "wdt", NULL, "lwp",
721 "fma4", "tce", NULL, "nodeid-msr",
722 NULL, "tbm", "topoext", "perfctr-core",
723 "perfctr-nb", NULL, NULL, NULL,
724 NULL, NULL, NULL, NULL,
725 },
726 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
727 .tcg_features = TCG_EXT3_FEATURES,
728 /*
729 * TOPOEXT is always allowed but can't be enabled blindly by
730 * "-cpu host", as it requires consistent cache topology info
731 * to be provided so it doesn't confuse guests.
732 */
733 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
734 },
735 [FEAT_C000_0001_EDX] = {
736 .type = CPUID_FEATURE_WORD,
737 .feat_names = {
738 NULL, NULL, "xstore", "xstore-en",
739 NULL, NULL, "xcrypt", "xcrypt-en",
740 "ace2", "ace2-en", "phe", "phe-en",
741 "pmm", "pmm-en", NULL, NULL,
742 NULL, NULL, NULL, NULL,
743 NULL, NULL, NULL, NULL,
744 NULL, NULL, NULL, NULL,
745 NULL, NULL, NULL, NULL,
746 },
747 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
748 .tcg_features = TCG_EXT4_FEATURES,
749 },
750 [FEAT_KVM] = {
751 .type = CPUID_FEATURE_WORD,
752 .feat_names = {
753 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
754 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
755 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
756 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
757 NULL, NULL, NULL, NULL,
758 NULL, NULL, NULL, NULL,
759 "kvmclock-stable-bit", NULL, NULL, NULL,
760 NULL, NULL, NULL, NULL,
761 },
762 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
763 .tcg_features = TCG_KVM_FEATURES,
764 },
765 [FEAT_KVM_HINTS] = {
766 .type = CPUID_FEATURE_WORD,
767 .feat_names = {
768 "kvm-hint-dedicated", NULL, NULL, NULL,
769 NULL, NULL, NULL, NULL,
770 NULL, NULL, NULL, NULL,
771 NULL, NULL, NULL, NULL,
772 NULL, NULL, NULL, NULL,
773 NULL, NULL, NULL, NULL,
774 NULL, NULL, NULL, NULL,
775 NULL, NULL, NULL, NULL,
776 },
777 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
778 .tcg_features = TCG_KVM_FEATURES,
779 /*
780 * KVM hints aren't auto-enabled by -cpu host, they need to be
781 * explicitly enabled in the command-line.
782 */
783 .no_autoenable_flags = ~0U,
784 },
785 [FEAT_SVM] = {
786 .type = CPUID_FEATURE_WORD,
787 .feat_names = {
788 "npt", "lbrv", "svm-lock", "nrip-save",
789 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
790 NULL, NULL, "pause-filter", NULL,
791 "pfthreshold", "avic", NULL, "v-vmsave-vmload",
792 "vgif", NULL, NULL, NULL,
793 NULL, NULL, NULL, NULL,
794 NULL, NULL, NULL, NULL,
795 "svme-addr-chk", NULL, NULL, NULL,
796 },
797 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
798 .tcg_features = TCG_SVM_FEATURES,
799 },
800 [FEAT_7_0_EBX] = {
801 .type = CPUID_FEATURE_WORD,
802 .feat_names = {
803 "fsgsbase", "tsc-adjust", "sgx", "bmi1",
804 "hle", "avx2", NULL, "smep",
805 "bmi2", "erms", "invpcid", "rtm",
806 NULL, NULL, "mpx", NULL,
807 "avx512f", "avx512dq", "rdseed", "adx",
808 "smap", "avx512ifma", "pcommit", "clflushopt",
809 "clwb", "intel-pt", "avx512pf", "avx512er",
810 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
811 },
812 .cpuid = {
813 .eax = 7,
814 .needs_ecx = true, .ecx = 0,
815 .reg = R_EBX,
816 },
817 .tcg_features = TCG_7_0_EBX_FEATURES,
818 },
819 [FEAT_7_0_ECX] = {
820 .type = CPUID_FEATURE_WORD,
821 .feat_names = {
822 NULL, "avx512vbmi", "umip", "pku",
823 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
824 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
825 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
826 "la57", NULL, NULL, NULL,
827 NULL, NULL, "rdpid", NULL,
828 "bus-lock-detect", "cldemote", NULL, "movdiri",
829 "movdir64b", NULL, "sgxlc", "pks",
830 },
831 .cpuid = {
832 .eax = 7,
833 .needs_ecx = true, .ecx = 0,
834 .reg = R_ECX,
835 },
836 .tcg_features = TCG_7_0_ECX_FEATURES,
837 },
838 [FEAT_7_0_EDX] = {
839 .type = CPUID_FEATURE_WORD,
840 .feat_names = {
841 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
842 "fsrm", NULL, NULL, NULL,
843 "avx512-vp2intersect", NULL, "md-clear", NULL,
844 NULL, NULL, "serialize", NULL,
845 "tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
846 NULL, NULL, NULL, "avx512-fp16",
847 NULL, NULL, "spec-ctrl", "stibp",
848 NULL, "arch-capabilities", "core-capability", "ssbd",
849 },
850 .cpuid = {
851 .eax = 7,
852 .needs_ecx = true, .ecx = 0,
853 .reg = R_EDX,
854 },
855 .tcg_features = TCG_7_0_EDX_FEATURES,
856 },
857 [FEAT_7_1_EAX] = {
858 .type = CPUID_FEATURE_WORD,
859 .feat_names = {
860 NULL, NULL, NULL, NULL,
861 "avx-vnni", "avx512-bf16", NULL, NULL,
862 NULL, NULL, NULL, NULL,
863 NULL, NULL, NULL, NULL,
864 NULL, NULL, NULL, NULL,
865 NULL, NULL, NULL, NULL,
866 NULL, NULL, NULL, NULL,
867 NULL, NULL, NULL, NULL,
868 },
869 .cpuid = {
870 .eax = 7,
871 .needs_ecx = true, .ecx = 1,
872 .reg = R_EAX,
873 },
874 .tcg_features = TCG_7_1_EAX_FEATURES,
875 },
876 [FEAT_8000_0007_EDX] = {
877 .type = CPUID_FEATURE_WORD,
878 .feat_names = {
879 NULL, NULL, NULL, NULL,
880 NULL, NULL, NULL, NULL,
881 "invtsc", NULL, NULL, NULL,
882 NULL, NULL, NULL, NULL,
883 NULL, NULL, NULL, NULL,
884 NULL, NULL, NULL, NULL,
885 NULL, NULL, NULL, NULL,
886 NULL, NULL, NULL, NULL,
887 },
888 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
889 .tcg_features = TCG_APM_FEATURES,
890 .unmigratable_flags = CPUID_APM_INVTSC,
891 },
892 [FEAT_8000_0008_EBX] = {
893 .type = CPUID_FEATURE_WORD,
894 .feat_names = {
895 "clzero", NULL, "xsaveerptr", NULL,
896 NULL, NULL, NULL, NULL,
897 NULL, "wbnoinvd", NULL, NULL,
898 "ibpb", NULL, "ibrs", "amd-stibp",
899 NULL, NULL, NULL, NULL,
900 NULL, NULL, NULL, NULL,
901 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
902 NULL, NULL, NULL, NULL,
903 },
904 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
905 .tcg_features = 0,
906 .unmigratable_flags = 0,
907 },
908 [FEAT_XSAVE] = {
909 .type = CPUID_FEATURE_WORD,
910 .feat_names = {
911 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
912 NULL, NULL, NULL, NULL,
913 NULL, NULL, NULL, NULL,
914 NULL, NULL, NULL, NULL,
915 NULL, NULL, NULL, NULL,
916 NULL, NULL, NULL, NULL,
917 NULL, NULL, NULL, NULL,
918 NULL, NULL, NULL, NULL,
919 },
920 .cpuid = {
921 .eax = 0xd,
922 .needs_ecx = true, .ecx = 1,
923 .reg = R_EAX,
924 },
925 .tcg_features = TCG_XSAVE_FEATURES,
926 },
927 [FEAT_6_EAX] = {
928 .type = CPUID_FEATURE_WORD,
929 .feat_names = {
930 NULL, NULL, "arat", NULL,
931 NULL, NULL, NULL, NULL,
932 NULL, NULL, NULL, NULL,
933 NULL, NULL, NULL, NULL,
934 NULL, NULL, NULL, NULL,
935 NULL, NULL, NULL, NULL,
936 NULL, NULL, NULL, NULL,
937 NULL, NULL, NULL, NULL,
938 },
939 .cpuid = { .eax = 6, .reg = R_EAX, },
940 .tcg_features = TCG_6_EAX_FEATURES,
941 },
942 [FEAT_XSAVE_COMP_LO] = {
943 .type = CPUID_FEATURE_WORD,
944 .cpuid = {
945 .eax = 0xD,
946 .needs_ecx = true, .ecx = 0,
947 .reg = R_EAX,
948 },
949 .tcg_features = ~0U,
950 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
951 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
952 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
953 XSTATE_PKRU_MASK,
954 },
955 [FEAT_XSAVE_COMP_HI] = {
956 .type = CPUID_FEATURE_WORD,
957 .cpuid = {
958 .eax = 0xD,
959 .needs_ecx = true, .ecx = 0,
960 .reg = R_EDX,
961 },
962 .tcg_features = ~0U,
963 },
964 /*Below are MSR exposed features*/
965 [FEAT_ARCH_CAPABILITIES] = {
966 .type = MSR_FEATURE_WORD,
967 .feat_names = {
968 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
969 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
970 "taa-no", NULL, NULL, NULL,
971 NULL, NULL, NULL, NULL,
972 NULL, NULL, NULL, NULL,
973 NULL, NULL, NULL, NULL,
974 NULL, NULL, NULL, NULL,
975 NULL, NULL, NULL, NULL,
976 },
977 .msr = {
978 .index = MSR_IA32_ARCH_CAPABILITIES,
979 },
980 },
981 [FEAT_CORE_CAPABILITY] = {
982 .type = MSR_FEATURE_WORD,
983 .feat_names = {
984 NULL, NULL, NULL, NULL,
985 NULL, "split-lock-detect", NULL, NULL,
986 NULL, NULL, NULL, NULL,
987 NULL, NULL, NULL, NULL,
988 NULL, NULL, NULL, NULL,
989 NULL, NULL, NULL, NULL,
990 NULL, NULL, NULL, NULL,
991 NULL, NULL, NULL, NULL,
992 },
993 .msr = {
994 .index = MSR_IA32_CORE_CAPABILITY,
995 },
996 },
997 [FEAT_PERF_CAPABILITIES] = {
998 .type = MSR_FEATURE_WORD,
999 .feat_names = {
1000 NULL, NULL, NULL, NULL,
1001 NULL, NULL, NULL, NULL,
1002 NULL, NULL, NULL, NULL,
1003 NULL, "full-width-write", NULL, NULL,
1004 NULL, NULL, NULL, NULL,
1005 NULL, NULL, NULL, NULL,
1006 NULL, NULL, NULL, NULL,
1007 NULL, NULL, NULL, NULL,
1008 },
1009 .msr = {
1010 .index = MSR_IA32_PERF_CAPABILITIES,
1011 },
1012 },
1013
1014 [FEAT_VMX_PROCBASED_CTLS] = {
1015 .type = MSR_FEATURE_WORD,
1016 .feat_names = {
1017 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1018 NULL, NULL, NULL, "vmx-hlt-exit",
1019 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1020 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1021 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1022 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1023 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1024 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1025 },
1026 .msr = {
1027 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1028 }
1029 },
1030
1031 [FEAT_VMX_SECONDARY_CTLS] = {
1032 .type = MSR_FEATURE_WORD,
1033 .feat_names = {
1034 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1035 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1036 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1037 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1038 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1039 "vmx-xsaves", NULL, NULL, NULL,
1040 NULL, "vmx-tsc-scaling", NULL, NULL,
1041 NULL, NULL, NULL, NULL,
1042 },
1043 .msr = {
1044 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1045 }
1046 },
1047
1048 [FEAT_VMX_PINBASED_CTLS] = {
1049 .type = MSR_FEATURE_WORD,
1050 .feat_names = {
1051 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1052 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1053 NULL, NULL, NULL, NULL,
1054 NULL, NULL, NULL, NULL,
1055 NULL, NULL, NULL, NULL,
1056 NULL, NULL, NULL, NULL,
1057 NULL, NULL, NULL, NULL,
1058 NULL, NULL, NULL, NULL,
1059 },
1060 .msr = {
1061 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1062 }
1063 },
1064
1065 [FEAT_VMX_EXIT_CTLS] = {
1066 .type = MSR_FEATURE_WORD,
1067 /*
1068 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1069 * the LM CPUID bit.
1070 */
1071 .feat_names = {
1072 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1073 NULL, NULL, NULL, NULL,
1074 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1075 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1076 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1077 "vmx-exit-save-efer", "vmx-exit-load-efer",
1078 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1079 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
1080 NULL, "vmx-exit-load-pkrs", NULL, NULL,
1081 },
1082 .msr = {
1083 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1084 }
1085 },
1086
1087 [FEAT_VMX_ENTRY_CTLS] = {
1088 .type = MSR_FEATURE_WORD,
1089 .feat_names = {
1090 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1091 NULL, NULL, NULL, NULL,
1092 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1093 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1094 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
1095 NULL, NULL, "vmx-entry-load-pkrs", NULL,
1096 NULL, NULL, NULL, NULL,
1097 NULL, NULL, NULL, NULL,
1098 },
1099 .msr = {
1100 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1101 }
1102 },
1103
1104 [FEAT_VMX_MISC] = {
1105 .type = MSR_FEATURE_WORD,
1106 .feat_names = {
1107 NULL, NULL, NULL, NULL,
1108 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1109 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1110 NULL, NULL, NULL, NULL,
1111 NULL, NULL, NULL, NULL,
1112 NULL, NULL, NULL, NULL,
1113 NULL, NULL, NULL, NULL,
1114 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1115 },
1116 .msr = {
1117 .index = MSR_IA32_VMX_MISC,
1118 }
1119 },
1120
1121 [FEAT_VMX_EPT_VPID_CAPS] = {
1122 .type = MSR_FEATURE_WORD,
1123 .feat_names = {
1124 "vmx-ept-execonly", NULL, NULL, NULL,
1125 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1126 NULL, NULL, NULL, NULL,
1127 NULL, NULL, NULL, NULL,
1128 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1129 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1130 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1131 NULL, NULL, NULL, NULL,
1132 "vmx-invvpid", NULL, NULL, NULL,
1133 NULL, NULL, NULL, NULL,
1134 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1135 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1136 NULL, NULL, NULL, NULL,
1137 NULL, NULL, NULL, NULL,
1138 NULL, NULL, NULL, NULL,
1139 NULL, NULL, NULL, NULL,
1140 NULL, NULL, NULL, NULL,
1141 },
1142 .msr = {
1143 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1144 }
1145 },
1146
1147 [FEAT_VMX_BASIC] = {
1148 .type = MSR_FEATURE_WORD,
1149 .feat_names = {
1150 [54] = "vmx-ins-outs",
1151 [55] = "vmx-true-ctls",
1152 },
1153 .msr = {
1154 .index = MSR_IA32_VMX_BASIC,
1155 },
1156 /* Just to be safe - we don't support setting the MSEG version field. */
1157 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1158 },
1159
1160 [FEAT_VMX_VMFUNC] = {
1161 .type = MSR_FEATURE_WORD,
1162 .feat_names = {
1163 [0] = "vmx-eptp-switching",
1164 },
1165 .msr = {
1166 .index = MSR_IA32_VMX_VMFUNC,
1167 }
1168 },
1169
1170 [FEAT_14_0_ECX] = {
1171 .type = CPUID_FEATURE_WORD,
1172 .feat_names = {
1173 NULL, NULL, NULL, NULL,
1174 NULL, NULL, NULL, NULL,
1175 NULL, NULL, NULL, NULL,
1176 NULL, NULL, NULL, NULL,
1177 NULL, NULL, NULL, NULL,
1178 NULL, NULL, NULL, NULL,
1179 NULL, NULL, NULL, NULL,
1180 NULL, NULL, NULL, "intel-pt-lip",
1181 },
1182 .cpuid = {
1183 .eax = 0x14,
1184 .needs_ecx = true, .ecx = 0,
1185 .reg = R_ECX,
1186 },
1187 .tcg_features = TCG_14_0_ECX_FEATURES,
1188 },
1189
1190 [FEAT_SGX_12_0_EAX] = {
1191 .type = CPUID_FEATURE_WORD,
1192 .feat_names = {
1193 "sgx1", "sgx2", NULL, NULL,
1194 NULL, NULL, NULL, NULL,
1195 NULL, NULL, NULL, NULL,
1196 NULL, NULL, NULL, NULL,
1197 NULL, NULL, NULL, NULL,
1198 NULL, NULL, NULL, NULL,
1199 NULL, NULL, NULL, NULL,
1200 NULL, NULL, NULL, NULL,
1201 },
1202 .cpuid = {
1203 .eax = 0x12,
1204 .needs_ecx = true, .ecx = 0,
1205 .reg = R_EAX,
1206 },
1207 .tcg_features = TCG_SGX_12_0_EAX_FEATURES,
1208 },
1209
1210 [FEAT_SGX_12_0_EBX] = {
1211 .type = CPUID_FEATURE_WORD,
1212 .feat_names = {
1213 "sgx-exinfo" , NULL, NULL, NULL,
1214 NULL, NULL, NULL, NULL,
1215 NULL, NULL, NULL, NULL,
1216 NULL, NULL, NULL, NULL,
1217 NULL, NULL, NULL, NULL,
1218 NULL, NULL, NULL, NULL,
1219 NULL, NULL, NULL, NULL,
1220 NULL, NULL, NULL, NULL,
1221 },
1222 .cpuid = {
1223 .eax = 0x12,
1224 .needs_ecx = true, .ecx = 0,
1225 .reg = R_EBX,
1226 },
1227 .tcg_features = TCG_SGX_12_0_EBX_FEATURES,
1228 },
1229
1230 [FEAT_SGX_12_1_EAX] = {
1231 .type = CPUID_FEATURE_WORD,
1232 .feat_names = {
1233 NULL, "sgx-debug", "sgx-mode64", NULL,
1234 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss",
1235 NULL, NULL, NULL, NULL,
1236 NULL, NULL, NULL, NULL,
1237 NULL, NULL, NULL, NULL,
1238 NULL, NULL, NULL, NULL,
1239 NULL, NULL, NULL, NULL,
1240 NULL, NULL, NULL, NULL,
1241 },
1242 .cpuid = {
1243 .eax = 0x12,
1244 .needs_ecx = true, .ecx = 1,
1245 .reg = R_EAX,
1246 },
1247 .tcg_features = TCG_SGX_12_1_EAX_FEATURES,
1248 },
1249 };
1250
1251 typedef struct FeatureMask {
1252 FeatureWord index;
1253 uint64_t mask;
1254 } FeatureMask;
1255
1256 typedef struct FeatureDep {
1257 FeatureMask from, to;
1258 } FeatureDep;
1259
1260 static FeatureDep feature_dependencies[] = {
1261 {
1262 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
1263 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
1264 },
1265 {
1266 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
1267 .to = { FEAT_CORE_CAPABILITY, ~0ull },
1268 },
1269 {
1270 .from = { FEAT_1_ECX, CPUID_EXT_PDCM },
1271 .to = { FEAT_PERF_CAPABILITIES, ~0ull },
1272 },
1273 {
1274 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1275 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1276 },
1277 {
1278 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1279 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1280 },
1281 {
1282 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1283 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1284 },
1285 {
1286 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1287 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1288 },
1289 {
1290 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1291 .to = { FEAT_VMX_MISC, ~0ull },
1292 },
1293 {
1294 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1295 .to = { FEAT_VMX_BASIC, ~0ull },
1296 },
1297 {
1298 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1299 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1300 },
1301 {
1302 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1303 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1304 },
1305 {
1306 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1307 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1308 },
1309 {
1310 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1311 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1312 },
1313 {
1314 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1315 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1316 },
1317 {
1318 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1319 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1320 },
1321 {
1322 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT },
1323 .to = { FEAT_14_0_ECX, ~0ull },
1324 },
1325 {
1326 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1327 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1328 },
1329 {
1330 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1331 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1332 },
1333 {
1334 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1335 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1336 },
1337 {
1338 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1339 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1340 },
1341 {
1342 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1343 .to = { FEAT_VMX_VMFUNC, ~0ull },
1344 },
1345 {
1346 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM },
1347 .to = { FEAT_SVM, ~0ull },
1348 },
1349 };
1350
1351 typedef struct X86RegisterInfo32 {
1352 /* Name of register */
1353 const char *name;
1354 /* QAPI enum value register */
1355 X86CPURegister32 qapi_enum;
1356 } X86RegisterInfo32;
1357
1358 #define REGISTER(reg) \
1359 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1360 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
1361 REGISTER(EAX),
1362 REGISTER(ECX),
1363 REGISTER(EDX),
1364 REGISTER(EBX),
1365 REGISTER(ESP),
1366 REGISTER(EBP),
1367 REGISTER(ESI),
1368 REGISTER(EDI),
1369 };
1370 #undef REGISTER
1371
1372 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = {
1373 [XSTATE_FP_BIT] = {
1374 /* x87 FP state component is always enabled if XSAVE is supported */
1375 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1376 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1377 },
1378 [XSTATE_SSE_BIT] = {
1379 /* SSE state component is always enabled if XSAVE is supported */
1380 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1381 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1382 },
1383 [XSTATE_YMM_BIT] =
1384 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
1385 .size = sizeof(XSaveAVX) },
1386 [XSTATE_BNDREGS_BIT] =
1387 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1388 .size = sizeof(XSaveBNDREG) },
1389 [XSTATE_BNDCSR_BIT] =
1390 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1391 .size = sizeof(XSaveBNDCSR) },
1392 [XSTATE_OPMASK_BIT] =
1393 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1394 .size = sizeof(XSaveOpmask) },
1395 [XSTATE_ZMM_Hi256_BIT] =
1396 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1397 .size = sizeof(XSaveZMM_Hi256) },
1398 [XSTATE_Hi16_ZMM_BIT] =
1399 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1400 .size = sizeof(XSaveHi16_ZMM) },
1401 [XSTATE_PKRU_BIT] =
1402 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
1403 .size = sizeof(XSavePKRU) },
1404 };
1405
1406 static uint32_t xsave_area_size(uint64_t mask)
1407 {
1408 int i;
1409 uint64_t ret = 0;
1410
1411 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1412 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1413 if ((mask >> i) & 1) {
1414 ret = MAX(ret, esa->offset + esa->size);
1415 }
1416 }
1417 return ret;
1418 }
1419
1420 static inline bool accel_uses_host_cpuid(void)
1421 {
1422 return kvm_enabled() || hvf_enabled();
1423 }
1424
1425 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1426 {
1427 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1428 cpu->env.features[FEAT_XSAVE_COMP_LO];
1429 }
1430
1431 /* Return name of 32-bit register, from a R_* constant */
1432 static const char *get_register_name_32(unsigned int reg)
1433 {
1434 if (reg >= CPU_NB_REGS32) {
1435 return NULL;
1436 }
1437 return x86_reg_info_32[reg].name;
1438 }
1439
1440 /*
1441 * Returns the set of feature flags that are supported and migratable by
1442 * QEMU, for a given FeatureWord.
1443 */
1444 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
1445 {
1446 FeatureWordInfo *wi = &feature_word_info[w];
1447 uint64_t r = 0;
1448 int i;
1449
1450 for (i = 0; i < 64; i++) {
1451 uint64_t f = 1ULL << i;
1452
1453 /* If the feature name is known, it is implicitly considered migratable,
1454 * unless it is explicitly set in unmigratable_flags */
1455 if ((wi->migratable_flags & f) ||
1456 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1457 r |= f;
1458 }
1459 }
1460 return r;
1461 }
1462
1463 void host_cpuid(uint32_t function, uint32_t count,
1464 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
1465 {
1466 uint32_t vec[4];
1467
1468 #ifdef __x86_64__
1469 asm volatile("cpuid"
1470 : "=a"(vec[0]), "=b"(vec[1]),
1471 "=c"(vec[2]), "=d"(vec[3])
1472 : "0"(function), "c"(count) : "cc");
1473 #elif defined(__i386__)
1474 asm volatile("pusha \n\t"
1475 "cpuid \n\t"
1476 "mov %%eax, 0(%2) \n\t"
1477 "mov %%ebx, 4(%2) \n\t"
1478 "mov %%ecx, 8(%2) \n\t"
1479 "mov %%edx, 12(%2) \n\t"
1480 "popa"
1481 : : "a"(function), "c"(count), "S"(vec)
1482 : "memory", "cc");
1483 #else
1484 abort();
1485 #endif
1486
1487 if (eax)
1488 *eax = vec[0];
1489 if (ebx)
1490 *ebx = vec[1];
1491 if (ecx)
1492 *ecx = vec[2];
1493 if (edx)
1494 *edx = vec[3];
1495 }
1496
1497 /* CPU class name definitions: */
1498
1499 /* Return type name for a given CPU model name
1500 * Caller is responsible for freeing the returned string.
1501 */
1502 static char *x86_cpu_type_name(const char *model_name)
1503 {
1504 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1505 }
1506
1507 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1508 {
1509 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1510 return object_class_by_name(typename);
1511 }
1512
1513 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1514 {
1515 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1516 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1517 return g_strndup(class_name,
1518 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1519 }
1520
1521 typedef struct X86CPUVersionDefinition {
1522 X86CPUVersion version;
1523 const char *alias;
1524 const char *note;
1525 PropValue *props;
1526 } X86CPUVersionDefinition;
1527
1528 /* Base definition for a CPU model */
1529 typedef struct X86CPUDefinition {
1530 const char *name;
1531 uint32_t level;
1532 uint32_t xlevel;
1533 /* vendor is zero-terminated, 12 character ASCII string */
1534 char vendor[CPUID_VENDOR_SZ + 1];
1535 int family;
1536 int model;
1537 int stepping;
1538 FeatureWordArray features;
1539 const char *model_id;
1540 const CPUCaches *const cache_info;
1541 /*
1542 * Definitions for alternative versions of CPU model.
1543 * List is terminated by item with version == 0.
1544 * If NULL, version 1 will be registered automatically.
1545 */
1546 const X86CPUVersionDefinition *versions;
1547 const char *deprecation_note;
1548 } X86CPUDefinition;
1549
1550 /* Reference to a specific CPU model version */
1551 struct X86CPUModel {
1552 /* Base CPU definition */
1553 const X86CPUDefinition *cpudef;
1554 /* CPU model version */
1555 X86CPUVersion version;
1556 const char *note;
1557 /*
1558 * If true, this is an alias CPU model.
1559 * This matters only for "-cpu help" and query-cpu-definitions
1560 */
1561 bool is_alias;
1562 };
1563
1564 /* Get full model name for CPU version */
1565 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef,
1566 X86CPUVersion version)
1567 {
1568 assert(version > 0);
1569 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1570 }
1571
1572 static const X86CPUVersionDefinition *
1573 x86_cpu_def_get_versions(const X86CPUDefinition *def)
1574 {
1575 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1576 static const X86CPUVersionDefinition default_version_list[] = {
1577 { 1 },
1578 { /* end of list */ }
1579 };
1580
1581 return def->versions ?: default_version_list;
1582 }
1583
1584 static const CPUCaches epyc_cache_info = {
1585 .l1d_cache = &(CPUCacheInfo) {
1586 .type = DATA_CACHE,
1587 .level = 1,
1588 .size = 32 * KiB,
1589 .line_size = 64,
1590 .associativity = 8,
1591 .partitions = 1,
1592 .sets = 64,
1593 .lines_per_tag = 1,
1594 .self_init = 1,
1595 .no_invd_sharing = true,
1596 },
1597 .l1i_cache = &(CPUCacheInfo) {
1598 .type = INSTRUCTION_CACHE,
1599 .level = 1,
1600 .size = 64 * KiB,
1601 .line_size = 64,
1602 .associativity = 4,
1603 .partitions = 1,
1604 .sets = 256,
1605 .lines_per_tag = 1,
1606 .self_init = 1,
1607 .no_invd_sharing = true,
1608 },
1609 .l2_cache = &(CPUCacheInfo) {
1610 .type = UNIFIED_CACHE,
1611 .level = 2,
1612 .size = 512 * KiB,
1613 .line_size = 64,
1614 .associativity = 8,
1615 .partitions = 1,
1616 .sets = 1024,
1617 .lines_per_tag = 1,
1618 },
1619 .l3_cache = &(CPUCacheInfo) {
1620 .type = UNIFIED_CACHE,
1621 .level = 3,
1622 .size = 8 * MiB,
1623 .line_size = 64,
1624 .associativity = 16,
1625 .partitions = 1,
1626 .sets = 8192,
1627 .lines_per_tag = 1,
1628 .self_init = true,
1629 .inclusive = true,
1630 .complex_indexing = true,
1631 },
1632 };
1633
1634 static const CPUCaches epyc_rome_cache_info = {
1635 .l1d_cache = &(CPUCacheInfo) {
1636 .type = DATA_CACHE,
1637 .level = 1,
1638 .size = 32 * KiB,
1639 .line_size = 64,
1640 .associativity = 8,
1641 .partitions = 1,
1642 .sets = 64,
1643 .lines_per_tag = 1,
1644 .self_init = 1,
1645 .no_invd_sharing = true,
1646 },
1647 .l1i_cache = &(CPUCacheInfo) {
1648 .type = INSTRUCTION_CACHE,
1649 .level = 1,
1650 .size = 32 * KiB,
1651 .line_size = 64,
1652 .associativity = 8,
1653 .partitions = 1,
1654 .sets = 64,
1655 .lines_per_tag = 1,
1656 .self_init = 1,
1657 .no_invd_sharing = true,
1658 },
1659 .l2_cache = &(CPUCacheInfo) {
1660 .type = UNIFIED_CACHE,
1661 .level = 2,
1662 .size = 512 * KiB,
1663 .line_size = 64,
1664 .associativity = 8,
1665 .partitions = 1,
1666 .sets = 1024,
1667 .lines_per_tag = 1,
1668 },
1669 .l3_cache = &(CPUCacheInfo) {
1670 .type = UNIFIED_CACHE,
1671 .level = 3,
1672 .size = 16 * MiB,
1673 .line_size = 64,
1674 .associativity = 16,
1675 .partitions = 1,
1676 .sets = 16384,
1677 .lines_per_tag = 1,
1678 .self_init = true,
1679 .inclusive = true,
1680 .complex_indexing = true,
1681 },
1682 };
1683
1684 static const CPUCaches epyc_milan_cache_info = {
1685 .l1d_cache = &(CPUCacheInfo) {
1686 .type = DATA_CACHE,
1687 .level = 1,
1688 .size = 32 * KiB,
1689 .line_size = 64,
1690 .associativity = 8,
1691 .partitions = 1,
1692 .sets = 64,
1693 .lines_per_tag = 1,
1694 .self_init = 1,
1695 .no_invd_sharing = true,
1696 },
1697 .l1i_cache = &(CPUCacheInfo) {
1698 .type = INSTRUCTION_CACHE,
1699 .level = 1,
1700 .size = 32 * KiB,
1701 .line_size = 64,
1702 .associativity = 8,
1703 .partitions = 1,
1704 .sets = 64,
1705 .lines_per_tag = 1,
1706 .self_init = 1,
1707 .no_invd_sharing = true,
1708 },
1709 .l2_cache = &(CPUCacheInfo) {
1710 .type = UNIFIED_CACHE,
1711 .level = 2,
1712 .size = 512 * KiB,
1713 .line_size = 64,
1714 .associativity = 8,
1715 .partitions = 1,
1716 .sets = 1024,
1717 .lines_per_tag = 1,
1718 },
1719 .l3_cache = &(CPUCacheInfo) {
1720 .type = UNIFIED_CACHE,
1721 .level = 3,
1722 .size = 32 * MiB,
1723 .line_size = 64,
1724 .associativity = 16,
1725 .partitions = 1,
1726 .sets = 32768,
1727 .lines_per_tag = 1,
1728 .self_init = true,
1729 .inclusive = true,
1730 .complex_indexing = true,
1731 },
1732 };
1733
1734 /* The following VMX features are not supported by KVM and are left out in the
1735 * CPU definitions:
1736 *
1737 * Dual-monitor support (all processors)
1738 * Entry to SMM
1739 * Deactivate dual-monitor treatment
1740 * Number of CR3-target values
1741 * Shutdown activity state
1742 * Wait-for-SIPI activity state
1743 * PAUSE-loop exiting (Westmere and newer)
1744 * EPT-violation #VE (Broadwell and newer)
1745 * Inject event with insn length=0 (Skylake and newer)
1746 * Conceal non-root operation from PT
1747 * Conceal VM exits from PT
1748 * Conceal VM entries from PT
1749 * Enable ENCLS exiting
1750 * Mode-based execute control (XS/XU)
1751 s TSC scaling (Skylake Server and newer)
1752 * GPA translation for PT (IceLake and newer)
1753 * User wait and pause
1754 * ENCLV exiting
1755 * Load IA32_RTIT_CTL
1756 * Clear IA32_RTIT_CTL
1757 * Advanced VM-exit information for EPT violations
1758 * Sub-page write permissions
1759 * PT in VMX operation
1760 */
1761
1762 static const X86CPUDefinition builtin_x86_defs[] = {
1763 {
1764 .name = "qemu64",
1765 .level = 0xd,
1766 .vendor = CPUID_VENDOR_AMD,
1767 .family = 15,
1768 .model = 107,
1769 .stepping = 1,
1770 .features[FEAT_1_EDX] =
1771 PPRO_FEATURES |
1772 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1773 CPUID_PSE36,
1774 .features[FEAT_1_ECX] =
1775 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1776 .features[FEAT_8000_0001_EDX] =
1777 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1778 .features[FEAT_8000_0001_ECX] =
1779 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
1780 .xlevel = 0x8000000A,
1781 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1782 },
1783 {
1784 .name = "phenom",
1785 .level = 5,
1786 .vendor = CPUID_VENDOR_AMD,
1787 .family = 16,
1788 .model = 2,
1789 .stepping = 3,
1790 /* Missing: CPUID_HT */
1791 .features[FEAT_1_EDX] =
1792 PPRO_FEATURES |
1793 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1794 CPUID_PSE36 | CPUID_VME,
1795 .features[FEAT_1_ECX] =
1796 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
1797 CPUID_EXT_POPCNT,
1798 .features[FEAT_8000_0001_EDX] =
1799 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1800 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
1801 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
1802 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1803 CPUID_EXT3_CR8LEG,
1804 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1805 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1806 .features[FEAT_8000_0001_ECX] =
1807 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
1808 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
1809 /* Missing: CPUID_SVM_LBRV */
1810 .features[FEAT_SVM] =
1811 CPUID_SVM_NPT,
1812 .xlevel = 0x8000001A,
1813 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1814 },
1815 {
1816 .name = "core2duo",
1817 .level = 10,
1818 .vendor = CPUID_VENDOR_INTEL,
1819 .family = 6,
1820 .model = 15,
1821 .stepping = 11,
1822 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1823 .features[FEAT_1_EDX] =
1824 PPRO_FEATURES |
1825 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1826 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1827 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1828 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1829 .features[FEAT_1_ECX] =
1830 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1831 CPUID_EXT_CX16,
1832 .features[FEAT_8000_0001_EDX] =
1833 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1834 .features[FEAT_8000_0001_ECX] =
1835 CPUID_EXT3_LAHF_LM,
1836 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
1837 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1838 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1839 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1840 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1841 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
1842 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1843 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1844 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1845 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1846 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1847 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1848 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1849 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
1850 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
1851 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
1852 .features[FEAT_VMX_SECONDARY_CTLS] =
1853 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
1854 .xlevel = 0x80000008,
1855 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1856 },
1857 {
1858 .name = "kvm64",
1859 .level = 0xd,
1860 .vendor = CPUID_VENDOR_INTEL,
1861 .family = 15,
1862 .model = 6,
1863 .stepping = 1,
1864 /* Missing: CPUID_HT */
1865 .features[FEAT_1_EDX] =
1866 PPRO_FEATURES | CPUID_VME |
1867 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1868 CPUID_PSE36,
1869 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
1870 .features[FEAT_1_ECX] =
1871 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1872 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
1873 .features[FEAT_8000_0001_EDX] =
1874 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1875 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1876 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1877 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1878 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
1879 .features[FEAT_8000_0001_ECX] =
1880 0,
1881 /* VMX features from Cedar Mill/Prescott */
1882 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1883 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1884 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1885 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1886 VMX_PIN_BASED_NMI_EXITING,
1887 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1888 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1889 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1890 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1891 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1892 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1893 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1894 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
1895 .xlevel = 0x80000008,
1896 .model_id = "Common KVM processor"
1897 },
1898 {
1899 .name = "qemu32",
1900 .level = 4,
1901 .vendor = CPUID_VENDOR_INTEL,
1902 .family = 6,
1903 .model = 6,
1904 .stepping = 3,
1905 .features[FEAT_1_EDX] =
1906 PPRO_FEATURES,
1907 .features[FEAT_1_ECX] =
1908 CPUID_EXT_SSE3,
1909 .xlevel = 0x80000004,
1910 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1911 },
1912 {
1913 .name = "kvm32",
1914 .level = 5,
1915 .vendor = CPUID_VENDOR_INTEL,
1916 .family = 15,
1917 .model = 6,
1918 .stepping = 1,
1919 .features[FEAT_1_EDX] =
1920 PPRO_FEATURES | CPUID_VME |
1921 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
1922 .features[FEAT_1_ECX] =
1923 CPUID_EXT_SSE3,
1924 .features[FEAT_8000_0001_ECX] =
1925 0,
1926 /* VMX features from Yonah */
1927 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1928 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1929 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1930 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1931 VMX_PIN_BASED_NMI_EXITING,
1932 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1933 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1934 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1935 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1936 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
1937 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
1938 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
1939 .xlevel = 0x80000008,
1940 .model_id = "Common 32-bit KVM processor"
1941 },
1942 {
1943 .name = "coreduo",
1944 .level = 10,
1945 .vendor = CPUID_VENDOR_INTEL,
1946 .family = 6,
1947 .model = 14,
1948 .stepping = 8,
1949 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1950 .features[FEAT_1_EDX] =
1951 PPRO_FEATURES | CPUID_VME |
1952 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1953 CPUID_SS,
1954 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
1955 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
1956 .features[FEAT_1_ECX] =
1957 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
1958 .features[FEAT_8000_0001_EDX] =
1959 CPUID_EXT2_NX,
1960 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1961 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1962 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1963 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1964 VMX_PIN_BASED_NMI_EXITING,
1965 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1966 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1967 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1968 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1969 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
1970 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
1971 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
1972 .xlevel = 0x80000008,
1973 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1974 },
1975 {
1976 .name = "486",
1977 .level = 1,
1978 .vendor = CPUID_VENDOR_INTEL,
1979 .family = 4,
1980 .model = 8,
1981 .stepping = 0,
1982 .features[FEAT_1_EDX] =
1983 I486_FEATURES,
1984 .xlevel = 0,
1985 .model_id = "",
1986 },
1987 {
1988 .name = "pentium",
1989 .level = 1,
1990 .vendor = CPUID_VENDOR_INTEL,
1991 .family = 5,
1992 .model = 4,
1993 .stepping = 3,
1994 .features[FEAT_1_EDX] =
1995 PENTIUM_FEATURES,
1996 .xlevel = 0,
1997 .model_id = "",
1998 },
1999 {
2000 .name = "pentium2",
2001 .level = 2,
2002 .vendor = CPUID_VENDOR_INTEL,
2003 .family = 6,
2004 .model = 5,
2005 .stepping = 2,
2006 .features[FEAT_1_EDX] =
2007 PENTIUM2_FEATURES,
2008 .xlevel = 0,
2009 .model_id = "",
2010 },
2011 {
2012 .name = "pentium3",
2013 .level = 3,
2014 .vendor = CPUID_VENDOR_INTEL,
2015 .family = 6,
2016 .model = 7,
2017 .stepping = 3,
2018 .features[FEAT_1_EDX] =
2019 PENTIUM3_FEATURES,
2020 .xlevel = 0,
2021 .model_id = "",
2022 },
2023 {
2024 .name = "athlon",
2025 .level = 2,
2026 .vendor = CPUID_VENDOR_AMD,
2027 .family = 6,
2028 .model = 2,
2029 .stepping = 3,
2030 .features[FEAT_1_EDX] =
2031 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
2032 CPUID_MCA,
2033 .features[FEAT_8000_0001_EDX] =
2034 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
2035 .xlevel = 0x80000008,
2036 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
2037 },
2038 {
2039 .name = "n270",
2040 .level = 10,
2041 .vendor = CPUID_VENDOR_INTEL,
2042 .family = 6,
2043 .model = 28,
2044 .stepping = 2,
2045 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2046 .features[FEAT_1_EDX] =
2047 PPRO_FEATURES |
2048 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2049 CPUID_ACPI | CPUID_SS,
2050 /* Some CPUs got no CPUID_SEP */
2051 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2052 * CPUID_EXT_XTPR */
2053 .features[FEAT_1_ECX] =
2054 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
2055 CPUID_EXT_MOVBE,
2056 .features[FEAT_8000_0001_EDX] =
2057 CPUID_EXT2_NX,
2058 .features[FEAT_8000_0001_ECX] =
2059 CPUID_EXT3_LAHF_LM,
2060 .xlevel = 0x80000008,
2061 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2062 },
2063 {
2064 .name = "Conroe",
2065 .level = 10,
2066 .vendor = CPUID_VENDOR_INTEL,
2067 .family = 6,
2068 .model = 15,
2069 .stepping = 3,
2070 .features[FEAT_1_EDX] =
2071 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2072 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2073 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2074 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2075 CPUID_DE | CPUID_FP87,
2076 .features[FEAT_1_ECX] =
2077 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2078 .features[FEAT_8000_0001_EDX] =
2079 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2080 .features[FEAT_8000_0001_ECX] =
2081 CPUID_EXT3_LAHF_LM,
2082 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2083 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2084 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2085 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2086 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2087 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2088 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2089 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2090 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2091 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2092 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2093 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2094 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2095 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2096 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2097 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2098 .features[FEAT_VMX_SECONDARY_CTLS] =
2099 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
2100 .xlevel = 0x80000008,
2101 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2102 },
2103 {
2104 .name = "Penryn",
2105 .level = 10,
2106 .vendor = CPUID_VENDOR_INTEL,
2107 .family = 6,
2108 .model = 23,
2109 .stepping = 3,
2110 .features[FEAT_1_EDX] =
2111 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2112 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2113 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2114 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2115 CPUID_DE | CPUID_FP87,
2116 .features[FEAT_1_ECX] =
2117 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2118 CPUID_EXT_SSE3,
2119 .features[FEAT_8000_0001_EDX] =
2120 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2121 .features[FEAT_8000_0001_ECX] =
2122 CPUID_EXT3_LAHF_LM,
2123 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2124 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2125 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2126 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2127 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2128 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2129 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2130 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2131 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2132 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2133 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2134 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2135 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2136 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2137 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2138 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2139 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2140 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2141 .features[FEAT_VMX_SECONDARY_CTLS] =
2142 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2143 VMX_SECONDARY_EXEC_WBINVD_EXITING,
2144 .xlevel = 0x80000008,
2145 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2146 },
2147 {
2148 .name = "Nehalem",
2149 .level = 11,
2150 .vendor = CPUID_VENDOR_INTEL,
2151 .family = 6,
2152 .model = 26,
2153 .stepping = 3,
2154 .features[FEAT_1_EDX] =
2155 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2156 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2157 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2158 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2159 CPUID_DE | CPUID_FP87,
2160 .features[FEAT_1_ECX] =
2161 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2162 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2163 .features[FEAT_8000_0001_EDX] =
2164 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2165 .features[FEAT_8000_0001_ECX] =
2166 CPUID_EXT3_LAHF_LM,
2167 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2168 MSR_VMX_BASIC_TRUE_CTLS,
2169 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2170 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2171 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2172 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2173 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2174 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2175 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2176 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2177 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2178 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2179 .features[FEAT_VMX_EXIT_CTLS] =
2180 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2181 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2182 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2183 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2184 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2185 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2186 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2187 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2188 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2189 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2190 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2191 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2192 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2193 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2194 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2195 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2196 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2197 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2198 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2199 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2200 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2201 .features[FEAT_VMX_SECONDARY_CTLS] =
2202 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2203 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2204 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2205 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2206 VMX_SECONDARY_EXEC_ENABLE_VPID,
2207 .xlevel = 0x80000008,
2208 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
2209 .versions = (X86CPUVersionDefinition[]) {
2210 { .version = 1 },
2211 {
2212 .version = 2,
2213 .alias = "Nehalem-IBRS",
2214 .props = (PropValue[]) {
2215 { "spec-ctrl", "on" },
2216 { "model-id",
2217 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2218 { /* end of list */ }
2219 }
2220 },
2221 { /* end of list */ }
2222 }
2223 },
2224 {
2225 .name = "Westmere",
2226 .level = 11,
2227 .vendor = CPUID_VENDOR_INTEL,
2228 .family = 6,
2229 .model = 44,
2230 .stepping = 1,
2231 .features[FEAT_1_EDX] =
2232 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2233 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2234 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2235 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2236 CPUID_DE | CPUID_FP87,
2237 .features[FEAT_1_ECX] =
2238 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2239 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2240 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2241 .features[FEAT_8000_0001_EDX] =
2242 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2243 .features[FEAT_8000_0001_ECX] =
2244 CPUID_EXT3_LAHF_LM,
2245 .features[FEAT_6_EAX] =
2246 CPUID_6_EAX_ARAT,
2247 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2248 MSR_VMX_BASIC_TRUE_CTLS,
2249 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2250 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2251 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2252 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2253 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2254 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2255 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2256 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2257 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2258 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2259 .features[FEAT_VMX_EXIT_CTLS] =
2260 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2261 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2262 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2263 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2264 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2265 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2266 MSR_VMX_MISC_STORE_LMA,
2267 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2268 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2269 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2270 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2271 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2272 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2273 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2274 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2275 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2276 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2277 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2278 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2279 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2280 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2281 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2282 .features[FEAT_VMX_SECONDARY_CTLS] =
2283 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2284 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2285 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2286 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2287 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2288 .xlevel = 0x80000008,
2289 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
2290 .versions = (X86CPUVersionDefinition[]) {
2291 { .version = 1 },
2292 {
2293 .version = 2,
2294 .alias = "Westmere-IBRS",
2295 .props = (PropValue[]) {
2296 { "spec-ctrl", "on" },
2297 { "model-id",
2298 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2299 { /* end of list */ }
2300 }
2301 },
2302 { /* end of list */ }
2303 }
2304 },
2305 {
2306 .name = "SandyBridge",
2307 .level = 0xd,
2308 .vendor = CPUID_VENDOR_INTEL,
2309 .family = 6,
2310 .model = 42,
2311 .stepping = 1,
2312 .features[FEAT_1_EDX] =
2313 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2314 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2315 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2316 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2317 CPUID_DE | CPUID_FP87,
2318 .features[FEAT_1_ECX] =
2319 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2320 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2321 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2322 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2323 CPUID_EXT_SSE3,
2324 .features[FEAT_8000_0001_EDX] =
2325 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2326 CPUID_EXT2_SYSCALL,
2327 .features[FEAT_8000_0001_ECX] =
2328 CPUID_EXT3_LAHF_LM,
2329 .features[FEAT_XSAVE] =
2330 CPUID_XSAVE_XSAVEOPT,
2331 .features[FEAT_6_EAX] =
2332 CPUID_6_EAX_ARAT,
2333 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2334 MSR_VMX_BASIC_TRUE_CTLS,
2335 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2336 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2337 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2338 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2339 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2340 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2341 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2342 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2343 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2344 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2345 .features[FEAT_VMX_EXIT_CTLS] =
2346 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2347 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2348 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2349 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2350 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2351 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2352 MSR_VMX_MISC_STORE_LMA,
2353 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2354 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2355 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2356 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2357 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2358 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2359 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2360 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2361 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2362 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2363 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2364 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2365 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2366 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2367 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2368 .features[FEAT_VMX_SECONDARY_CTLS] =
2369 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2370 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2371 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2372 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2373 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2374 .xlevel = 0x80000008,
2375 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
2376 .versions = (X86CPUVersionDefinition[]) {
2377 { .version = 1 },
2378 {
2379 .version = 2,
2380 .alias = "SandyBridge-IBRS",
2381 .props = (PropValue[]) {
2382 { "spec-ctrl", "on" },
2383 { "model-id",
2384 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2385 { /* end of list */ }
2386 }
2387 },
2388 { /* end of list */ }
2389 }
2390 },
2391 {
2392 .name = "IvyBridge",
2393 .level = 0xd,
2394 .vendor = CPUID_VENDOR_INTEL,
2395 .family = 6,
2396 .model = 58,
2397 .stepping = 9,
2398 .features[FEAT_1_EDX] =
2399 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2400 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2401 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2402 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2403 CPUID_DE | CPUID_FP87,
2404 .features[FEAT_1_ECX] =
2405 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2406 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2407 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2408 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2409 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2410 .features[FEAT_7_0_EBX] =
2411 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2412 CPUID_7_0_EBX_ERMS,
2413 .features[FEAT_8000_0001_EDX] =
2414 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2415 CPUID_EXT2_SYSCALL,
2416 .features[FEAT_8000_0001_ECX] =
2417 CPUID_EXT3_LAHF_LM,
2418 .features[FEAT_XSAVE] =
2419 CPUID_XSAVE_XSAVEOPT,
2420 .features[FEAT_6_EAX] =
2421 CPUID_6_EAX_ARAT,
2422 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2423 MSR_VMX_BASIC_TRUE_CTLS,
2424 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2425 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2426 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2427 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2428 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2429 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2430 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2431 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2432 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2433 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2434 .features[FEAT_VMX_EXIT_CTLS] =
2435 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2436 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2437 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2438 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2439 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2440 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2441 MSR_VMX_MISC_STORE_LMA,
2442 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2443 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2444 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2445 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2446 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2447 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2448 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2449 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2450 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2451 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2452 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2453 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2454 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2455 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2456 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2457 .features[FEAT_VMX_SECONDARY_CTLS] =
2458 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2459 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2460 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2461 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2462 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2463 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2464 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2465 VMX_SECONDARY_EXEC_RDRAND_EXITING,
2466 .xlevel = 0x80000008,
2467 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
2468 .versions = (X86CPUVersionDefinition[]) {
2469 { .version = 1 },
2470 {
2471 .version = 2,
2472 .alias = "IvyBridge-IBRS",
2473 .props = (PropValue[]) {
2474 { "spec-ctrl", "on" },
2475 { "model-id",
2476 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2477 { /* end of list */ }
2478 }
2479 },
2480 { /* end of list */ }
2481 }
2482 },
2483 {
2484 .name = "Haswell",
2485 .level = 0xd,
2486 .vendor = CPUID_VENDOR_INTEL,
2487 .family = 6,
2488 .model = 60,
2489 .stepping = 4,
2490 .features[FEAT_1_EDX] =
2491 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2492 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2493 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2494 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2495 CPUID_DE | CPUID_FP87,
2496 .features[FEAT_1_ECX] =
2497 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2498 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2499 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2500 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2501 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2502 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2503 .features[FEAT_8000_0001_EDX] =
2504 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2505 CPUID_EXT2_SYSCALL,
2506 .features[FEAT_8000_0001_ECX] =
2507 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2508 .features[FEAT_7_0_EBX] =
2509 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2510 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2511 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2512 CPUID_7_0_EBX_RTM,
2513 .features[FEAT_XSAVE] =
2514 CPUID_XSAVE_XSAVEOPT,
2515 .features[FEAT_6_EAX] =
2516 CPUID_6_EAX_ARAT,
2517 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2518 MSR_VMX_BASIC_TRUE_CTLS,
2519 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2520 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2521 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2522 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2523 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2524 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2525 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2526 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2527 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2528 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2529 .features[FEAT_VMX_EXIT_CTLS] =
2530 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2531 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2532 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2533 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2534 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2535 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2536 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2537 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2538 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2539 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2540 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2541 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2542 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2543 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2544 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2545 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2546 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2547 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2548 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2549 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2550 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2551 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2552 .features[FEAT_VMX_SECONDARY_CTLS] =
2553 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2554 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2555 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2556 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2557 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2558 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2559 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2560 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2561 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2562 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2563 .xlevel = 0x80000008,
2564 .model_id = "Intel Core Processor (Haswell)",
2565 .versions = (X86CPUVersionDefinition[]) {
2566 { .version = 1 },
2567 {
2568 .version = 2,
2569 .alias = "Haswell-noTSX",
2570 .props = (PropValue[]) {
2571 { "hle", "off" },
2572 { "rtm", "off" },
2573 { "stepping", "1" },
2574 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2575 { /* end of list */ }
2576 },
2577 },
2578 {
2579 .version = 3,
2580 .alias = "Haswell-IBRS",
2581 .props = (PropValue[]) {
2582 /* Restore TSX features removed by -v2 above */
2583 { "hle", "on" },
2584 { "rtm", "on" },
2585 /*
2586 * Haswell and Haswell-IBRS had stepping=4 in
2587 * QEMU 4.0 and older
2588 */
2589 { "stepping", "4" },
2590 { "spec-ctrl", "on" },
2591 { "model-id",
2592 "Intel Core Processor (Haswell, IBRS)" },
2593 { /* end of list */ }
2594 }
2595 },
2596 {
2597 .version = 4,
2598 .alias = "Haswell-noTSX-IBRS",
2599 .props = (PropValue[]) {
2600 { "hle", "off" },
2601 { "rtm", "off" },
2602 /* spec-ctrl was already enabled by -v3 above */
2603 { "stepping", "1" },
2604 { "model-id",
2605 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2606 { /* end of list */ }
2607 }
2608 },
2609 { /* end of list */ }
2610 }
2611 },
2612 {
2613 .name = "Broadwell",
2614 .level = 0xd,
2615 .vendor = CPUID_VENDOR_INTEL,
2616 .family = 6,
2617 .model = 61,
2618 .stepping = 2,
2619 .features[FEAT_1_EDX] =
2620 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2621 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2622 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2623 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2624 CPUID_DE | CPUID_FP87,
2625 .features[FEAT_1_ECX] =
2626 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2627 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2628 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2629 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2630 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2631 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2632 .features[FEAT_8000_0001_EDX] =
2633 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2634 CPUID_EXT2_SYSCALL,
2635 .features[FEAT_8000_0001_ECX] =
2636 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2637 .features[FEAT_7_0_EBX] =
2638 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2639 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2640 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2641 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2642 CPUID_7_0_EBX_SMAP,
2643 .features[FEAT_XSAVE] =
2644 CPUID_XSAVE_XSAVEOPT,
2645 .features[FEAT_6_EAX] =
2646 CPUID_6_EAX_ARAT,
2647 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2648 MSR_VMX_BASIC_TRUE_CTLS,
2649 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2650 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2651 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2652 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2653 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2654 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2655 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2656 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2657 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2658 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2659 .features[FEAT_VMX_EXIT_CTLS] =
2660 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2661 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2662 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2663 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2664 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2665 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2666 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2667 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2668 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2669 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2670 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2671 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2672 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2673 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2674 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2675 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2676 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2677 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2678 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2679 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2680 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2681 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2682 .features[FEAT_VMX_SECONDARY_CTLS] =
2683 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2684 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2685 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2686 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2687 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2688 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2689 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2690 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2691 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2692 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2693 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2694 .xlevel = 0x80000008,
2695 .model_id = "Intel Core Processor (Broadwell)",
2696 .versions = (X86CPUVersionDefinition[]) {
2697 { .version = 1 },
2698 {
2699 .version = 2,
2700 .alias = "Broadwell-noTSX",
2701 .props = (PropValue[]) {
2702 { "hle", "off" },
2703 { "rtm", "off" },
2704 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2705 { /* end of list */ }
2706 },
2707 },
2708 {
2709 .version = 3,
2710 .alias = "Broadwell-IBRS",
2711 .props = (PropValue[]) {
2712 /* Restore TSX features removed by -v2 above */
2713 { "hle", "on" },
2714 { "rtm", "on" },
2715 { "spec-ctrl", "on" },
2716 { "model-id",
2717 "Intel Core Processor (Broadwell, IBRS)" },
2718 { /* end of list */ }
2719 }
2720 },
2721 {
2722 .version = 4,
2723 .alias = "Broadwell-noTSX-IBRS",
2724 .props = (PropValue[]) {
2725 { "hle", "off" },
2726 { "rtm", "off" },
2727 /* spec-ctrl was already enabled by -v3 above */
2728 { "model-id",
2729 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2730 { /* end of list */ }
2731 }
2732 },
2733 { /* end of list */ }
2734 }
2735 },
2736 {
2737 .name = "Skylake-Client",
2738 .level = 0xd,
2739 .vendor = CPUID_VENDOR_INTEL,
2740 .family = 6,
2741 .model = 94,
2742 .stepping = 3,
2743 .features[FEAT_1_EDX] =
2744 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2745 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2746 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2747 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2748 CPUID_DE | CPUID_FP87,
2749 .features[FEAT_1_ECX] =
2750 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2751 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2752 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2753 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2754 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2755 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2756 .features[FEAT_8000_0001_EDX] =
2757 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2758 CPUID_EXT2_SYSCALL,
2759 .features[FEAT_8000_0001_ECX] =
2760 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2761 .features[FEAT_7_0_EBX] =
2762 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2763 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2764 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2765 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2766 CPUID_7_0_EBX_SMAP,
2767 /* XSAVES is added in version 4 */
2768 .features[FEAT_XSAVE] =
2769 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2770 CPUID_XSAVE_XGETBV1,
2771 .features[FEAT_6_EAX] =
2772 CPUID_6_EAX_ARAT,
2773 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2774 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2775 MSR_VMX_BASIC_TRUE_CTLS,
2776 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2777 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2778 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2779 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2780 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2781 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2782 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2783 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2784 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2785 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2786 .features[FEAT_VMX_EXIT_CTLS] =
2787 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2788 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2789 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2790 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2791 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2792 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2793 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2794 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2795 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2796 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2797 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2798 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2799 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2800 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2801 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2802 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2803 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2804 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2805 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2806 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2807 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2808 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2809 .features[FEAT_VMX_SECONDARY_CTLS] =
2810 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2811 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2812 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2813 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2814 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2815 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2816 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2817 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2818 .xlevel = 0x80000008,
2819 .model_id = "Intel Core Processor (Skylake)",
2820 .versions = (X86CPUVersionDefinition[]) {
2821 { .version = 1 },
2822 {
2823 .version = 2,
2824 .alias = "Skylake-Client-IBRS",
2825 .props = (PropValue[]) {
2826 { "spec-ctrl", "on" },
2827 { "model-id",
2828 "Intel Core Processor (Skylake, IBRS)" },
2829 { /* end of list */ }
2830 }
2831 },
2832 {
2833 .version = 3,
2834 .alias = "Skylake-Client-noTSX-IBRS",
2835 .props = (PropValue[]) {
2836 { "hle", "off" },
2837 { "rtm", "off" },
2838 { "model-id",
2839 "Intel Core Processor (Skylake, IBRS, no TSX)" },
2840 { /* end of list */ }
2841 }
2842 },
2843 {
2844 .version = 4,
2845 .note = "IBRS, XSAVES, no TSX",
2846 .props = (PropValue[]) {
2847 { "xsaves", "on" },
2848 { "vmx-xsaves", "on" },
2849 { /* end of list */ }
2850 }
2851 },
2852 { /* end of list */ }
2853 }
2854 },
2855 {
2856 .name = "Skylake-Server",
2857 .level = 0xd,
2858 .vendor = CPUID_VENDOR_INTEL,
2859 .family = 6,
2860 .model = 85,
2861 .stepping = 4,
2862 .features[FEAT_1_EDX] =
2863 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2864 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2865 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2866 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2867 CPUID_DE | CPUID_FP87,
2868 .features[FEAT_1_ECX] =
2869 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2870 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2871 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2872 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2873 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2874 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2875 .features[FEAT_8000_0001_EDX] =
2876 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2877 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2878 .features[FEAT_8000_0001_ECX] =
2879 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2880 .features[FEAT_7_0_EBX] =
2881 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2882 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2883 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2884 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2885 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2886 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2887 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2888 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2889 .features[FEAT_7_0_ECX] =
2890 CPUID_7_0_ECX_PKU,
2891 /* XSAVES is added in version 5 */
2892 .features[FEAT_XSAVE] =
2893 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2894 CPUID_XSAVE_XGETBV1,
2895 .features[FEAT_6_EAX] =
2896 CPUID_6_EAX_ARAT,
2897 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2898 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2899 MSR_VMX_BASIC_TRUE_CTLS,
2900 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2901 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2902 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2903 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2904 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2905 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2906 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2907 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2908 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2909 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2910 .features[FEAT_VMX_EXIT_CTLS] =
2911 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2912 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2913 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2914 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2915 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2916 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2917 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2918 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2919 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2920 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2921 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2922 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2923 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2924 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2925 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2926 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2927 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2928 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2929 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2930 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2931 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2932 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2933 .features[FEAT_VMX_SECONDARY_CTLS] =
2934 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2935 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2936 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2937 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2938 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2939 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2940 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2941 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2942 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2943 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2944 .xlevel = 0x80000008,
2945 .model_id = "Intel Xeon Processor (Skylake)",
2946 .versions = (X86CPUVersionDefinition[]) {
2947 { .version = 1 },
2948 {
2949 .version = 2,
2950 .alias = "Skylake-Server-IBRS",
2951 .props = (PropValue[]) {
2952 /* clflushopt was not added to Skylake-Server-IBRS */
2953 /* TODO: add -v3 including clflushopt */
2954 { "clflushopt", "off" },
2955 { "spec-ctrl", "on" },
2956 { "model-id",
2957 "Intel Xeon Processor (Skylake, IBRS)" },
2958 { /* end of list */ }
2959 }
2960 },
2961 {
2962 .version = 3,
2963 .alias = "Skylake-Server-noTSX-IBRS",
2964 .props = (PropValue[]) {
2965 { "hle", "off" },
2966 { "rtm", "off" },
2967 { "model-id",
2968 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
2969 { /* end of list */ }
2970 }
2971 },
2972 {
2973 .version = 4,
2974 .props = (PropValue[]) {
2975 { "vmx-eptp-switching", "on" },
2976 { /* end of list */ }
2977 }
2978 },
2979 {
2980 .version = 5,
2981 .note = "IBRS, XSAVES, EPT switching, no TSX",
2982 .props = (PropValue[]) {
2983 { "xsaves", "on" },
2984 { "vmx-xsaves", "on" },
2985 { /* end of list */ }
2986 }
2987 },
2988 { /* end of list */ }
2989 }
2990 },
2991 {
2992 .name = "Cascadelake-Server",
2993 .level = 0xd,
2994 .vendor = CPUID_VENDOR_INTEL,
2995 .family = 6,
2996 .model = 85,
2997 .stepping = 6,
2998 .features[FEAT_1_EDX] =
2999 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3000 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3001 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3002 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3003 CPUID_DE | CPUID_FP87,
3004 .features[FEAT_1_ECX] =
3005 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3006 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3007 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3008 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3009 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3010 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3011 .features[FEAT_8000_0001_EDX] =
3012 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3013 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3014 .features[FEAT_8000_0001_ECX] =
3015 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3016 .features[FEAT_7_0_EBX] =
3017 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3018 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3019 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3020 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3021 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3022 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3023 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3024 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3025 .features[FEAT_7_0_ECX] =
3026 CPUID_7_0_ECX_PKU |
3027 CPUID_7_0_ECX_AVX512VNNI,
3028 .features[FEAT_7_0_EDX] =
3029 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3030 /* XSAVES is added in version 5 */
3031 .features[FEAT_XSAVE] =
3032 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3033 CPUID_XSAVE_XGETBV1,
3034 .features[FEAT_6_EAX] =
3035 CPUID_6_EAX_ARAT,
3036 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3037 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3038 MSR_VMX_BASIC_TRUE_CTLS,
3039 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3040 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3041 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3042 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3043 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3044 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3045 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3046 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3047 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3048 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3049 .features[FEAT_VMX_EXIT_CTLS] =
3050 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3051 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3052 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3053 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3054 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3055 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3056 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3057 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3058 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3059 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3060 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3061 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3062 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3063 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3064 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3065 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3066 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3067 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3068 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3069 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3070 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3071 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3072 .features[FEAT_VMX_SECONDARY_CTLS] =
3073 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3074 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3075 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3076 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3077 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3078 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3079 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3080 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3081 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3082 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3083 .xlevel = 0x80000008,
3084 .model_id = "Intel Xeon Processor (Cascadelake)",
3085 .versions = (X86CPUVersionDefinition[]) {
3086 { .version = 1 },
3087 { .version = 2,
3088 .note = "ARCH_CAPABILITIES",
3089 .props = (PropValue[]) {
3090 { "arch-capabilities", "on" },
3091 { "rdctl-no", "on" },
3092 { "ibrs-all", "on" },
3093 { "skip-l1dfl-vmentry", "on" },
3094 { "mds-no", "on" },
3095 { /* end of list */ }
3096 },
3097 },
3098 { .version = 3,
3099 .alias = "Cascadelake-Server-noTSX",
3100 .note = "ARCH_CAPABILITIES, no TSX",
3101 .props = (PropValue[]) {
3102 { "hle", "off" },
3103 { "rtm", "off" },
3104 { /* end of list */ }
3105 },
3106 },
3107 { .version = 4,
3108 .note = "ARCH_CAPABILITIES, no TSX",
3109 .props = (PropValue[]) {
3110 { "vmx-eptp-switching", "on" },
3111 { /* end of list */ }
3112 },
3113 },
3114 { .version = 5,
3115 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX",
3116 .props = (PropValue[]) {
3117 { "xsaves", "on" },
3118 { "vmx-xsaves", "on" },
3119 { /* end of list */ }
3120 },
3121 },
3122 { /* end of list */ }
3123 }
3124 },
3125 {
3126 .name = "Cooperlake",
3127 .level = 0xd,
3128 .vendor = CPUID_VENDOR_INTEL,
3129 .family = 6,
3130 .model = 85,
3131 .stepping = 10,
3132 .features[FEAT_1_EDX] =
3133 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3134 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3135 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3136 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3137 CPUID_DE | CPUID_FP87,
3138 .features[FEAT_1_ECX] =
3139 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3140 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3141 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3142 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3143 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3144 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3145 .features[FEAT_8000_0001_EDX] =
3146 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3147 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3148 .features[FEAT_8000_0001_ECX] =
3149 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3150 .features[FEAT_7_0_EBX] =
3151 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3152 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3153 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3154 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3155 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3156 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3157 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3158 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3159 .features[FEAT_7_0_ECX] =
3160 CPUID_7_0_ECX_PKU |
3161 CPUID_7_0_ECX_AVX512VNNI,
3162 .features[FEAT_7_0_EDX] =
3163 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3164 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3165 .features[FEAT_ARCH_CAPABILITIES] =
3166 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
3167 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3168 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
3169 .features[FEAT_7_1_EAX] =
3170 CPUID_7_1_EAX_AVX512_BF16,
3171 /* XSAVES is added in version 2 */
3172 .features[FEAT_XSAVE] =
3173 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3174 CPUID_XSAVE_XGETBV1,
3175 .features[FEAT_6_EAX] =
3176 CPUID_6_EAX_ARAT,
3177 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3178 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3179 MSR_VMX_BASIC_TRUE_CTLS,
3180 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3181 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3182 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3183 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3184 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3185 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3186 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3187 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3188 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3189 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3190 .features[FEAT_VMX_EXIT_CTLS] =
3191 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3192 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3193 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3194 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3195 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3196 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3197 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3198 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3199 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3200 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3201 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3202 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3203 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3204 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3205 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3206 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3207 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3208 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3209 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3210 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3211 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3212 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3213 .features[FEAT_VMX_SECONDARY_CTLS] =
3214 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3215 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3216 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3217 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3218 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3219 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3220 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3221 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3222 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3223 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3224 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3225 .xlevel = 0x80000008,
3226 .model_id = "Intel Xeon Processor (Cooperlake)",
3227 .versions = (X86CPUVersionDefinition[]) {
3228 { .version = 1 },
3229 { .version = 2,
3230 .note = "XSAVES",
3231 .props = (PropValue[]) {
3232 { "xsaves", "on" },
3233 { "vmx-xsaves", "on" },
3234 { /* end of list */ }
3235 },
3236 },
3237 { /* end of list */ }
3238 }
3239 },
3240 {
3241 .name = "Icelake-Client",
3242 .level = 0xd,
3243 .vendor = CPUID_VENDOR_INTEL,
3244 .family = 6,
3245 .model = 126,
3246 .stepping = 0,
3247 .features[FEAT_1_EDX] =
3248 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3249 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3250 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3251 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3252 CPUID_DE | CPUID_FP87,
3253 .features[FEAT_1_ECX] =
3254 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3255 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3256 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3257 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3258 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3259 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3260 .features[FEAT_8000_0001_EDX] =
3261 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3262 CPUID_EXT2_SYSCALL,
3263 .features[FEAT_8000_0001_ECX] =
3264 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3265 .features[FEAT_8000_0008_EBX] =
3266 CPUID_8000_0008_EBX_WBNOINVD,
3267 .features[FEAT_7_0_EBX] =
3268 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3269 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3270 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3271 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3272 CPUID_7_0_EBX_SMAP,
3273 .features[FEAT_7_0_ECX] =
3274 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3275 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3276 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3277 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3278 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3279 .features[FEAT_7_0_EDX] =
3280 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3281 /* XSAVES is added in version 3 */
3282 .features[FEAT_XSAVE] =
3283 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3284 CPUID_XSAVE_XGETBV1,
3285 .features[FEAT_6_EAX] =
3286 CPUID_6_EAX_ARAT,
3287 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3288 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3289 MSR_VMX_BASIC_TRUE_CTLS,
3290 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3291 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3292 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3293 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3294 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3295 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3296 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3297 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3298 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3299 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3300 .features[FEAT_VMX_EXIT_CTLS] =
3301 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3302 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3303 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3304 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3305 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3306 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3307 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3308 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3309 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3310 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
3311 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3312 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3313 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3314 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3315 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3316 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3317 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3318 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3319 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3320 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3321 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3322 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3323 .features[FEAT_VMX_SECONDARY_CTLS] =
3324 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3325 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3326 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3327 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3328 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3329 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3330 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3331 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3332 .xlevel = 0x80000008,
3333 .model_id = "Intel Core Processor (Icelake)",
3334 .versions = (X86CPUVersionDefinition[]) {
3335 {
3336 .version = 1,
3337 .note = "deprecated"
3338 },
3339 {
3340 .version = 2,
3341 .note = "no TSX, deprecated",
3342 .alias = "Icelake-Client-noTSX",
3343 .props = (PropValue[]) {
3344 { "hle", "off" },
3345 { "rtm", "off" },
3346 { /* end of list */ }
3347 },
3348 },
3349 {
3350 .version = 3,
3351 .note = "no TSX, XSAVES, deprecated",
3352 .props = (PropValue[]) {
3353 { "xsaves", "on" },
3354 { "vmx-xsaves", "on" },
3355 { /* end of list */ }
3356 },
3357 },
3358 { /* end of list */ }
3359 },
3360 .deprecation_note = "use Icelake-Server instead"
3361 },
3362 {
3363 .name = "Icelake-Server",
3364 .level = 0xd,
3365 .vendor = CPUID_VENDOR_INTEL,
3366 .family = 6,
3367 .model = 134,
3368 .stepping = 0,
3369 .features[FEAT_1_EDX] =
3370 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3371 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3372 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3373 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3374 CPUID_DE | CPUID_FP87,
3375 .features[FEAT_1_ECX] =
3376 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3377 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3378 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3379 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3380 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3381 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3382 .features[FEAT_8000_0001_EDX] =
3383 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3384 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3385 .features[FEAT_8000_0001_ECX] =
3386 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3387 .features[FEAT_8000_0008_EBX] =
3388 CPUID_8000_0008_EBX_WBNOINVD,
3389 .features[FEAT_7_0_EBX] =
3390 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3391 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3392 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3393 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3394 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3395 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3396 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3397 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3398 .features[FEAT_7_0_ECX] =
3399 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3400 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3401 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3402 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3403 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3404 .features[FEAT_7_0_EDX] =
3405 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3406 /* XSAVES is added in version 5 */
3407 .features[FEAT_XSAVE] =
3408 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3409 CPUID_XSAVE_XGETBV1,
3410 .features[FEAT_6_EAX] =
3411 CPUID_6_EAX_ARAT,
3412 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3413 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3414 MSR_VMX_BASIC_TRUE_CTLS,
3415 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3416 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3417 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3418 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3419 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3420 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3421 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3422 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3423 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3424 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3425 .features[FEAT_VMX_EXIT_CTLS] =
3426 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3427 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3428 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3429 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3430 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3431 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3432 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3433 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3434 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3435 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3436 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3437 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3438 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3439 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3440 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3441 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3442 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3443 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3444 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3445 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3446 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3447 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3448 .features[FEAT_VMX_SECONDARY_CTLS] =
3449 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3450 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3451 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3452 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3453 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3454 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3455 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3456 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3457 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
3458 .xlevel = 0x80000008,
3459 .model_id = "Intel Xeon Processor (Icelake)",
3460 .versions = (X86CPUVersionDefinition[]) {
3461 { .version = 1 },
3462 {
3463 .version = 2,
3464 .note = "no TSX",
3465 .alias = "Icelake-Server-noTSX",
3466 .props = (PropValue[]) {
3467 { "hle", "off" },
3468 { "rtm", "off" },
3469 { /* end of list */ }
3470 },
3471 },
3472 {
3473 .version = 3,
3474 .props = (PropValue[]) {
3475 { "arch-capabilities", "on" },
3476 { "rdctl-no", "on" },
3477 { "ibrs-all", "on" },
3478 { "skip-l1dfl-vmentry", "on" },
3479 { "mds-no", "on" },
3480 { "pschange-mc-no", "on" },
3481 { "taa-no", "on" },
3482 { /* end of list */ }
3483 },
3484 },
3485 {
3486 .version = 4,
3487 .props = (PropValue[]) {
3488 { "sha-ni", "on" },
3489 { "avx512ifma", "on" },
3490 { "rdpid", "on" },
3491 { "fsrm", "on" },
3492 { "vmx-rdseed-exit", "on" },
3493 { "vmx-pml", "on" },
3494 { "vmx-eptp-switching", "on" },
3495 { "model", "106" },
3496 { /* end of list */ }
3497 },
3498 },
3499 {
3500 .version = 5,
3501 .note = "XSAVES",
3502 .props = (PropValue[]) {
3503 { "xsaves", "on" },
3504 { "vmx-xsaves", "on" },
3505 { /* end of list */ }
3506 },
3507 },
3508 { /* end of list */ }
3509 }
3510 },
3511 {
3512 .name = "Denverton",
3513 .level = 21,
3514 .vendor = CPUID_VENDOR_INTEL,
3515 .family = 6,
3516 .model = 95,
3517 .stepping = 1,
3518 .features[FEAT_1_EDX] =
3519 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3520 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3521 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3522 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3523 CPUID_SSE | CPUID_SSE2,
3524 .features[FEAT_1_ECX] =
3525 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3526 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
3527 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3528 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
3529 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
3530 .features[FEAT_8000_0001_EDX] =
3531 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3532 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3533 .features[FEAT_8000_0001_ECX] =
3534 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3535 .features[FEAT_7_0_EBX] =
3536 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
3537 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
3538 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
3539 .features[FEAT_7_0_EDX] =
3540 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
3541 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3542 /* XSAVES is added in version 3 */
3543 .features[FEAT_XSAVE] =
3544 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
3545 .features[FEAT_6_EAX] =
3546 CPUID_6_EAX_ARAT,
3547 .features[FEAT_ARCH_CAPABILITIES] =
3548 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
3549 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3550 MSR_VMX_BASIC_TRUE_CTLS,
3551 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3552 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3553 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3554 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3555 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3556 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3557 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3558 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3559 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3560 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3561 .features[FEAT_VMX_EXIT_CTLS] =
3562 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3563 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3564 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3565 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3566 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_T