Revert "i386: Introduce use_epyc_apic_id_encoding in X86CPUDefinition"
[qemu.git] / target / i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/bitops.h"
24 #include "qemu/qemu-print.h"
25
26 #include "cpu.h"
27 #include "exec/exec-all.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/reset.h"
30 #include "sysemu/hvf.h"
31 #include "sysemu/cpus.h"
32 #include "sysemu/xen.h"
33 #include "kvm_i386.h"
34 #include "sev_i386.h"
35
36 #include "qemu/error-report.h"
37 #include "qemu/module.h"
38 #include "qemu/option.h"
39 #include "qemu/config-file.h"
40 #include "qapi/error.h"
41 #include "qapi/qapi-visit-machine.h"
42 #include "qapi/qapi-visit-run-state.h"
43 #include "qapi/qmp/qdict.h"
44 #include "qapi/qmp/qerror.h"
45 #include "qapi/visitor.h"
46 #include "qom/qom-qobject.h"
47 #include "sysemu/arch_init.h"
48 #include "qapi/qapi-commands-machine-target.h"
49
50 #include "standard-headers/asm-x86/kvm_para.h"
51
52 #include "sysemu/sysemu.h"
53 #include "sysemu/tcg.h"
54 #include "hw/qdev-properties.h"
55 #include "hw/i386/topology.h"
56 #ifndef CONFIG_USER_ONLY
57 #include "exec/address-spaces.h"
58 #include "hw/i386/apic_internal.h"
59 #include "hw/boards.h"
60 #endif
61
62 #include "disas/capstone.h"
63
64 /* Helpers for building CPUID[2] descriptors: */
65
66 struct CPUID2CacheDescriptorInfo {
67 enum CacheType type;
68 int level;
69 int size;
70 int line_size;
71 int associativity;
72 };
73
74 /*
75 * Known CPUID 2 cache descriptors.
76 * From Intel SDM Volume 2A, CPUID instruction
77 */
78 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
79 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
80 .associativity = 4, .line_size = 32, },
81 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
82 .associativity = 4, .line_size = 32, },
83 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
84 .associativity = 4, .line_size = 64, },
85 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
86 .associativity = 2, .line_size = 32, },
87 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
88 .associativity = 4, .line_size = 32, },
89 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
90 .associativity = 4, .line_size = 64, },
91 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
92 .associativity = 6, .line_size = 64, },
93 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
94 .associativity = 2, .line_size = 64, },
95 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
96 .associativity = 8, .line_size = 64, },
97 /* lines per sector is not supported cpuid2_cache_descriptor(),
98 * so descriptors 0x22, 0x23 are not included
99 */
100 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
101 .associativity = 16, .line_size = 64, },
102 /* lines per sector is not supported cpuid2_cache_descriptor(),
103 * so descriptors 0x25, 0x20 are not included
104 */
105 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
106 .associativity = 8, .line_size = 64, },
107 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
108 .associativity = 8, .line_size = 64, },
109 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
110 .associativity = 4, .line_size = 32, },
111 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
112 .associativity = 4, .line_size = 32, },
113 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
114 .associativity = 4, .line_size = 32, },
115 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
116 .associativity = 4, .line_size = 32, },
117 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
118 .associativity = 4, .line_size = 32, },
119 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
120 .associativity = 4, .line_size = 64, },
121 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
122 .associativity = 8, .line_size = 64, },
123 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
124 .associativity = 12, .line_size = 64, },
125 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
126 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
127 .associativity = 12, .line_size = 64, },
128 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
129 .associativity = 16, .line_size = 64, },
130 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
131 .associativity = 12, .line_size = 64, },
132 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
133 .associativity = 16, .line_size = 64, },
134 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
135 .associativity = 24, .line_size = 64, },
136 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
137 .associativity = 8, .line_size = 64, },
138 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
139 .associativity = 4, .line_size = 64, },
140 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
141 .associativity = 4, .line_size = 64, },
142 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
143 .associativity = 4, .line_size = 64, },
144 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
145 .associativity = 4, .line_size = 64, },
146 /* lines per sector is not supported cpuid2_cache_descriptor(),
147 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
148 */
149 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
150 .associativity = 8, .line_size = 64, },
151 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
152 .associativity = 2, .line_size = 64, },
153 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
154 .associativity = 8, .line_size = 64, },
155 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
156 .associativity = 8, .line_size = 32, },
157 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
158 .associativity = 8, .line_size = 32, },
159 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
160 .associativity = 8, .line_size = 32, },
161 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
162 .associativity = 8, .line_size = 32, },
163 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
164 .associativity = 4, .line_size = 64, },
165 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
166 .associativity = 8, .line_size = 64, },
167 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
168 .associativity = 4, .line_size = 64, },
169 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
170 .associativity = 4, .line_size = 64, },
171 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
172 .associativity = 4, .line_size = 64, },
173 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
174 .associativity = 8, .line_size = 64, },
175 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
176 .associativity = 8, .line_size = 64, },
177 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
178 .associativity = 8, .line_size = 64, },
179 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
180 .associativity = 12, .line_size = 64, },
181 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
182 .associativity = 12, .line_size = 64, },
183 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
184 .associativity = 12, .line_size = 64, },
185 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
186 .associativity = 16, .line_size = 64, },
187 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
188 .associativity = 16, .line_size = 64, },
189 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
190 .associativity = 16, .line_size = 64, },
191 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
192 .associativity = 24, .line_size = 64, },
193 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
194 .associativity = 24, .line_size = 64, },
195 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
196 .associativity = 24, .line_size = 64, },
197 };
198
199 /*
200 * "CPUID leaf 2 does not report cache descriptor information,
201 * use CPUID leaf 4 to query cache parameters"
202 */
203 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
204
205 /*
206 * Return a CPUID 2 cache descriptor for a given cache.
207 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
208 */
209 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
210 {
211 int i;
212
213 assert(cache->size > 0);
214 assert(cache->level > 0);
215 assert(cache->line_size > 0);
216 assert(cache->associativity > 0);
217 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
218 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
219 if (d->level == cache->level && d->type == cache->type &&
220 d->size == cache->size && d->line_size == cache->line_size &&
221 d->associativity == cache->associativity) {
222 return i;
223 }
224 }
225
226 return CACHE_DESCRIPTOR_UNAVAILABLE;
227 }
228
229 /* CPUID Leaf 4 constants: */
230
231 /* EAX: */
232 #define CACHE_TYPE_D 1
233 #define CACHE_TYPE_I 2
234 #define CACHE_TYPE_UNIFIED 3
235
236 #define CACHE_LEVEL(l) (l << 5)
237
238 #define CACHE_SELF_INIT_LEVEL (1 << 8)
239
240 /* EDX: */
241 #define CACHE_NO_INVD_SHARING (1 << 0)
242 #define CACHE_INCLUSIVE (1 << 1)
243 #define CACHE_COMPLEX_IDX (1 << 2)
244
245 /* Encode CacheType for CPUID[4].EAX */
246 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
247 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
248 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
249 0 /* Invalid value */)
250
251
252 /* Encode cache info for CPUID[4] */
253 static void encode_cache_cpuid4(CPUCacheInfo *cache,
254 int num_apic_ids, int num_cores,
255 uint32_t *eax, uint32_t *ebx,
256 uint32_t *ecx, uint32_t *edx)
257 {
258 assert(cache->size == cache->line_size * cache->associativity *
259 cache->partitions * cache->sets);
260
261 assert(num_apic_ids > 0);
262 *eax = CACHE_TYPE(cache->type) |
263 CACHE_LEVEL(cache->level) |
264 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
265 ((num_cores - 1) << 26) |
266 ((num_apic_ids - 1) << 14);
267
268 assert(cache->line_size > 0);
269 assert(cache->partitions > 0);
270 assert(cache->associativity > 0);
271 /* We don't implement fully-associative caches */
272 assert(cache->associativity < cache->sets);
273 *ebx = (cache->line_size - 1) |
274 ((cache->partitions - 1) << 12) |
275 ((cache->associativity - 1) << 22);
276
277 assert(cache->sets > 0);
278 *ecx = cache->sets - 1;
279
280 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
281 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
282 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
283 }
284
285 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
286 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
287 {
288 assert(cache->size % 1024 == 0);
289 assert(cache->lines_per_tag > 0);
290 assert(cache->associativity > 0);
291 assert(cache->line_size > 0);
292 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
293 (cache->lines_per_tag << 8) | (cache->line_size);
294 }
295
296 #define ASSOC_FULL 0xFF
297
298 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
299 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
300 a == 2 ? 0x2 : \
301 a == 4 ? 0x4 : \
302 a == 8 ? 0x6 : \
303 a == 16 ? 0x8 : \
304 a == 32 ? 0xA : \
305 a == 48 ? 0xB : \
306 a == 64 ? 0xC : \
307 a == 96 ? 0xD : \
308 a == 128 ? 0xE : \
309 a == ASSOC_FULL ? 0xF : \
310 0 /* invalid value */)
311
312 /*
313 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
314 * @l3 can be NULL.
315 */
316 static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
317 CPUCacheInfo *l3,
318 uint32_t *ecx, uint32_t *edx)
319 {
320 assert(l2->size % 1024 == 0);
321 assert(l2->associativity > 0);
322 assert(l2->lines_per_tag > 0);
323 assert(l2->line_size > 0);
324 *ecx = ((l2->size / 1024) << 16) |
325 (AMD_ENC_ASSOC(l2->associativity) << 12) |
326 (l2->lines_per_tag << 8) | (l2->line_size);
327
328 if (l3) {
329 assert(l3->size % (512 * 1024) == 0);
330 assert(l3->associativity > 0);
331 assert(l3->lines_per_tag > 0);
332 assert(l3->line_size > 0);
333 *edx = ((l3->size / (512 * 1024)) << 18) |
334 (AMD_ENC_ASSOC(l3->associativity) << 12) |
335 (l3->lines_per_tag << 8) | (l3->line_size);
336 } else {
337 *edx = 0;
338 }
339 }
340
341 /* Encode cache info for CPUID[8000001D] */
342 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
343 X86CPUTopoInfo *topo_info,
344 uint32_t *eax, uint32_t *ebx,
345 uint32_t *ecx, uint32_t *edx)
346 {
347 uint32_t l3_cores;
348 unsigned nodes = MAX(topo_info->nodes_per_pkg, 1);
349
350 assert(cache->size == cache->line_size * cache->associativity *
351 cache->partitions * cache->sets);
352
353 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
354 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
355
356 /* L3 is shared among multiple cores */
357 if (cache->level == 3) {
358 l3_cores = DIV_ROUND_UP((topo_info->dies_per_pkg *
359 topo_info->cores_per_die *
360 topo_info->threads_per_core),
361 nodes);
362 *eax |= (l3_cores - 1) << 14;
363 } else {
364 *eax |= ((topo_info->threads_per_core - 1) << 14);
365 }
366
367 assert(cache->line_size > 0);
368 assert(cache->partitions > 0);
369 assert(cache->associativity > 0);
370 /* We don't implement fully-associative caches */
371 assert(cache->associativity < cache->sets);
372 *ebx = (cache->line_size - 1) |
373 ((cache->partitions - 1) << 12) |
374 ((cache->associativity - 1) << 22);
375
376 assert(cache->sets > 0);
377 *ecx = cache->sets - 1;
378
379 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
380 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
381 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
382 }
383
384 /* Encode cache info for CPUID[8000001E] */
385 static void encode_topo_cpuid8000001e(X86CPUTopoInfo *topo_info, X86CPU *cpu,
386 uint32_t *eax, uint32_t *ebx,
387 uint32_t *ecx, uint32_t *edx)
388 {
389 X86CPUTopoIDs topo_ids = {0};
390 unsigned long nodes = MAX(topo_info->nodes_per_pkg, 1);
391 int shift;
392
393 x86_topo_ids_from_apicid_epyc(cpu->apic_id, topo_info, &topo_ids);
394
395 *eax = cpu->apic_id;
396 /*
397 * CPUID_Fn8000001E_EBX
398 * 31:16 Reserved
399 * 15:8 Threads per core (The number of threads per core is
400 * Threads per core + 1)
401 * 7:0 Core id (see bit decoding below)
402 * SMT:
403 * 4:3 node id
404 * 2 Core complex id
405 * 1:0 Core id
406 * Non SMT:
407 * 5:4 node id
408 * 3 Core complex id
409 * 1:0 Core id
410 */
411 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.node_id << 3) |
412 (topo_ids.core_id);
413 /*
414 * CPUID_Fn8000001E_ECX
415 * 31:11 Reserved
416 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
417 * 7:0 Node id (see bit decoding below)
418 * 2 Socket id
419 * 1:0 Node id
420 */
421 if (nodes <= 4) {
422 *ecx = ((nodes - 1) << 8) | (topo_ids.pkg_id << 2) | topo_ids.node_id;
423 } else {
424 /*
425 * Node id fix up. Actual hardware supports up to 4 nodes. But with
426 * more than 32 cores, we may end up with more than 4 nodes.
427 * Node id is a combination of socket id and node id. Only requirement
428 * here is that this number should be unique accross the system.
429 * Shift the socket id to accommodate more nodes. We dont expect both
430 * socket id and node id to be big number at the same time. This is not
431 * an ideal config but we need to to support it. Max nodes we can have
432 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
433 * 5 bits for nodes. Find the left most set bit to represent the total
434 * number of nodes. find_last_bit returns last set bit(0 based). Left
435 * shift(+1) the socket id to represent all the nodes.
436 */
437 nodes -= 1;
438 shift = find_last_bit(&nodes, 8);
439 *ecx = (nodes << 8) | (topo_ids.pkg_id << (shift + 1)) |
440 topo_ids.node_id;
441 }
442 *edx = 0;
443 }
444
445 /*
446 * Definitions of the hardcoded cache entries we expose:
447 * These are legacy cache values. If there is a need to change any
448 * of these values please use builtin_x86_defs
449 */
450
451 /* L1 data cache: */
452 static CPUCacheInfo legacy_l1d_cache = {
453 .type = DATA_CACHE,
454 .level = 1,
455 .size = 32 * KiB,
456 .self_init = 1,
457 .line_size = 64,
458 .associativity = 8,
459 .sets = 64,
460 .partitions = 1,
461 .no_invd_sharing = true,
462 };
463
464 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
465 static CPUCacheInfo legacy_l1d_cache_amd = {
466 .type = DATA_CACHE,
467 .level = 1,
468 .size = 64 * KiB,
469 .self_init = 1,
470 .line_size = 64,
471 .associativity = 2,
472 .sets = 512,
473 .partitions = 1,
474 .lines_per_tag = 1,
475 .no_invd_sharing = true,
476 };
477
478 /* L1 instruction cache: */
479 static CPUCacheInfo legacy_l1i_cache = {
480 .type = INSTRUCTION_CACHE,
481 .level = 1,
482 .size = 32 * KiB,
483 .self_init = 1,
484 .line_size = 64,
485 .associativity = 8,
486 .sets = 64,
487 .partitions = 1,
488 .no_invd_sharing = true,
489 };
490
491 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
492 static CPUCacheInfo legacy_l1i_cache_amd = {
493 .type = INSTRUCTION_CACHE,
494 .level = 1,
495 .size = 64 * KiB,
496 .self_init = 1,
497 .line_size = 64,
498 .associativity = 2,
499 .sets = 512,
500 .partitions = 1,
501 .lines_per_tag = 1,
502 .no_invd_sharing = true,
503 };
504
505 /* Level 2 unified cache: */
506 static CPUCacheInfo legacy_l2_cache = {
507 .type = UNIFIED_CACHE,
508 .level = 2,
509 .size = 4 * MiB,
510 .self_init = 1,
511 .line_size = 64,
512 .associativity = 16,
513 .sets = 4096,
514 .partitions = 1,
515 .no_invd_sharing = true,
516 };
517
518 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
519 static CPUCacheInfo legacy_l2_cache_cpuid2 = {
520 .type = UNIFIED_CACHE,
521 .level = 2,
522 .size = 2 * MiB,
523 .line_size = 64,
524 .associativity = 8,
525 };
526
527
528 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
529 static CPUCacheInfo legacy_l2_cache_amd = {
530 .type = UNIFIED_CACHE,
531 .level = 2,
532 .size = 512 * KiB,
533 .line_size = 64,
534 .lines_per_tag = 1,
535 .associativity = 16,
536 .sets = 512,
537 .partitions = 1,
538 };
539
540 /* Level 3 unified cache: */
541 static CPUCacheInfo legacy_l3_cache = {
542 .type = UNIFIED_CACHE,
543 .level = 3,
544 .size = 16 * MiB,
545 .line_size = 64,
546 .associativity = 16,
547 .sets = 16384,
548 .partitions = 1,
549 .lines_per_tag = 1,
550 .self_init = true,
551 .inclusive = true,
552 .complex_indexing = true,
553 };
554
555 /* TLB definitions: */
556
557 #define L1_DTLB_2M_ASSOC 1
558 #define L1_DTLB_2M_ENTRIES 255
559 #define L1_DTLB_4K_ASSOC 1
560 #define L1_DTLB_4K_ENTRIES 255
561
562 #define L1_ITLB_2M_ASSOC 1
563 #define L1_ITLB_2M_ENTRIES 255
564 #define L1_ITLB_4K_ASSOC 1
565 #define L1_ITLB_4K_ENTRIES 255
566
567 #define L2_DTLB_2M_ASSOC 0 /* disabled */
568 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
569 #define L2_DTLB_4K_ASSOC 4
570 #define L2_DTLB_4K_ENTRIES 512
571
572 #define L2_ITLB_2M_ASSOC 0 /* disabled */
573 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
574 #define L2_ITLB_4K_ASSOC 4
575 #define L2_ITLB_4K_ENTRIES 512
576
577 /* CPUID Leaf 0x14 constants: */
578 #define INTEL_PT_MAX_SUBLEAF 0x1
579 /*
580 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
581 * MSR can be accessed;
582 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
583 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
584 * of Intel PT MSRs across warm reset;
585 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
586 */
587 #define INTEL_PT_MINIMAL_EBX 0xf
588 /*
589 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
590 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
591 * accessed;
592 * bit[01]: ToPA tables can hold any number of output entries, up to the
593 * maximum allowed by the MaskOrTableOffset field of
594 * IA32_RTIT_OUTPUT_MASK_PTRS;
595 * bit[02]: Support Single-Range Output scheme;
596 */
597 #define INTEL_PT_MINIMAL_ECX 0x7
598 /* generated packets which contain IP payloads have LIP values */
599 #define INTEL_PT_IP_LIP (1 << 31)
600 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
601 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
602 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
603 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
604 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
605
606 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
607 uint32_t vendor2, uint32_t vendor3)
608 {
609 int i;
610 for (i = 0; i < 4; i++) {
611 dst[i] = vendor1 >> (8 * i);
612 dst[i + 4] = vendor2 >> (8 * i);
613 dst[i + 8] = vendor3 >> (8 * i);
614 }
615 dst[CPUID_VENDOR_SZ] = '\0';
616 }
617
618 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
619 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
620 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
621 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
622 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
623 CPUID_PSE36 | CPUID_FXSR)
624 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
625 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
626 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
627 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
628 CPUID_PAE | CPUID_SEP | CPUID_APIC)
629
630 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
631 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
632 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
633 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
634 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
635 /* partly implemented:
636 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
637 /* missing:
638 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
639 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
640 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
641 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
642 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
643 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
644 CPUID_EXT_RDRAND)
645 /* missing:
646 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
647 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
648 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
649 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
650 CPUID_EXT_F16C */
651
652 #ifdef TARGET_X86_64
653 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
654 #else
655 #define TCG_EXT2_X86_64_FEATURES 0
656 #endif
657
658 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
659 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
660 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
661 TCG_EXT2_X86_64_FEATURES)
662 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
663 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
664 #define TCG_EXT4_FEATURES 0
665 #define TCG_SVM_FEATURES CPUID_SVM_NPT
666 #define TCG_KVM_FEATURES 0
667 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
668 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
669 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
670 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
671 CPUID_7_0_EBX_ERMS)
672 /* missing:
673 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
674 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
675 CPUID_7_0_EBX_RDSEED */
676 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
677 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
678 CPUID_7_0_ECX_LA57)
679 #define TCG_7_0_EDX_FEATURES 0
680 #define TCG_7_1_EAX_FEATURES 0
681 #define TCG_APM_FEATURES 0
682 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
683 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
684 /* missing:
685 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
686
687 typedef enum FeatureWordType {
688 CPUID_FEATURE_WORD,
689 MSR_FEATURE_WORD,
690 } FeatureWordType;
691
692 typedef struct FeatureWordInfo {
693 FeatureWordType type;
694 /* feature flags names are taken from "Intel Processor Identification and
695 * the CPUID Instruction" and AMD's "CPUID Specification".
696 * In cases of disagreement between feature naming conventions,
697 * aliases may be added.
698 */
699 const char *feat_names[64];
700 union {
701 /* If type==CPUID_FEATURE_WORD */
702 struct {
703 uint32_t eax; /* Input EAX for CPUID */
704 bool needs_ecx; /* CPUID instruction uses ECX as input */
705 uint32_t ecx; /* Input ECX value for CPUID */
706 int reg; /* output register (R_* constant) */
707 } cpuid;
708 /* If type==MSR_FEATURE_WORD */
709 struct {
710 uint32_t index;
711 } msr;
712 };
713 uint64_t tcg_features; /* Feature flags supported by TCG */
714 uint64_t unmigratable_flags; /* Feature flags known to be unmigratable */
715 uint64_t migratable_flags; /* Feature flags known to be migratable */
716 /* Features that shouldn't be auto-enabled by "-cpu host" */
717 uint64_t no_autoenable_flags;
718 } FeatureWordInfo;
719
720 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
721 [FEAT_1_EDX] = {
722 .type = CPUID_FEATURE_WORD,
723 .feat_names = {
724 "fpu", "vme", "de", "pse",
725 "tsc", "msr", "pae", "mce",
726 "cx8", "apic", NULL, "sep",
727 "mtrr", "pge", "mca", "cmov",
728 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
729 NULL, "ds" /* Intel dts */, "acpi", "mmx",
730 "fxsr", "sse", "sse2", "ss",
731 "ht" /* Intel htt */, "tm", "ia64", "pbe",
732 },
733 .cpuid = {.eax = 1, .reg = R_EDX, },
734 .tcg_features = TCG_FEATURES,
735 },
736 [FEAT_1_ECX] = {
737 .type = CPUID_FEATURE_WORD,
738 .feat_names = {
739 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
740 "ds-cpl", "vmx", "smx", "est",
741 "tm2", "ssse3", "cid", NULL,
742 "fma", "cx16", "xtpr", "pdcm",
743 NULL, "pcid", "dca", "sse4.1",
744 "sse4.2", "x2apic", "movbe", "popcnt",
745 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
746 "avx", "f16c", "rdrand", "hypervisor",
747 },
748 .cpuid = { .eax = 1, .reg = R_ECX, },
749 .tcg_features = TCG_EXT_FEATURES,
750 },
751 /* Feature names that are already defined on feature_name[] but
752 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
753 * names on feat_names below. They are copied automatically
754 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
755 */
756 [FEAT_8000_0001_EDX] = {
757 .type = CPUID_FEATURE_WORD,
758 .feat_names = {
759 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
760 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
761 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
762 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
763 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
764 "nx", NULL, "mmxext", NULL /* mmx */,
765 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
766 NULL, "lm", "3dnowext", "3dnow",
767 },
768 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
769 .tcg_features = TCG_EXT2_FEATURES,
770 },
771 [FEAT_8000_0001_ECX] = {
772 .type = CPUID_FEATURE_WORD,
773 .feat_names = {
774 "lahf-lm", "cmp-legacy", "svm", "extapic",
775 "cr8legacy", "abm", "sse4a", "misalignsse",
776 "3dnowprefetch", "osvw", "ibs", "xop",
777 "skinit", "wdt", NULL, "lwp",
778 "fma4", "tce", NULL, "nodeid-msr",
779 NULL, "tbm", "topoext", "perfctr-core",
780 "perfctr-nb", NULL, NULL, NULL,
781 NULL, NULL, NULL, NULL,
782 },
783 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
784 .tcg_features = TCG_EXT3_FEATURES,
785 /*
786 * TOPOEXT is always allowed but can't be enabled blindly by
787 * "-cpu host", as it requires consistent cache topology info
788 * to be provided so it doesn't confuse guests.
789 */
790 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
791 },
792 [FEAT_C000_0001_EDX] = {
793 .type = CPUID_FEATURE_WORD,
794 .feat_names = {
795 NULL, NULL, "xstore", "xstore-en",
796 NULL, NULL, "xcrypt", "xcrypt-en",
797 "ace2", "ace2-en", "phe", "phe-en",
798 "pmm", "pmm-en", NULL, NULL,
799 NULL, NULL, NULL, NULL,
800 NULL, NULL, NULL, NULL,
801 NULL, NULL, NULL, NULL,
802 NULL, NULL, NULL, NULL,
803 },
804 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
805 .tcg_features = TCG_EXT4_FEATURES,
806 },
807 [FEAT_KVM] = {
808 .type = CPUID_FEATURE_WORD,
809 .feat_names = {
810 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
811 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
812 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
813 "kvm-poll-control", "kvm-pv-sched-yield", NULL, NULL,
814 NULL, NULL, NULL, NULL,
815 NULL, NULL, NULL, NULL,
816 "kvmclock-stable-bit", NULL, NULL, NULL,
817 NULL, NULL, NULL, NULL,
818 },
819 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
820 .tcg_features = TCG_KVM_FEATURES,
821 },
822 [FEAT_KVM_HINTS] = {
823 .type = CPUID_FEATURE_WORD,
824 .feat_names = {
825 "kvm-hint-dedicated", NULL, NULL, NULL,
826 NULL, NULL, NULL, NULL,
827 NULL, NULL, NULL, NULL,
828 NULL, NULL, NULL, NULL,
829 NULL, NULL, NULL, NULL,
830 NULL, NULL, NULL, NULL,
831 NULL, NULL, NULL, NULL,
832 NULL, NULL, NULL, NULL,
833 },
834 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
835 .tcg_features = TCG_KVM_FEATURES,
836 /*
837 * KVM hints aren't auto-enabled by -cpu host, they need to be
838 * explicitly enabled in the command-line.
839 */
840 .no_autoenable_flags = ~0U,
841 },
842 /*
843 * .feat_names are commented out for Hyper-V enlightenments because we
844 * don't want to have two different ways for enabling them on QEMU command
845 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
846 * enabling several feature bits simultaneously, exposing these bits
847 * individually may just confuse guests.
848 */
849 [FEAT_HYPERV_EAX] = {
850 .type = CPUID_FEATURE_WORD,
851 .feat_names = {
852 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
853 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
854 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
855 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
856 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
857 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
858 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
859 NULL, NULL,
860 NULL, NULL, NULL, NULL,
861 NULL, NULL, NULL, NULL,
862 NULL, NULL, NULL, NULL,
863 NULL, NULL, NULL, NULL,
864 },
865 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
866 },
867 [FEAT_HYPERV_EBX] = {
868 .type = CPUID_FEATURE_WORD,
869 .feat_names = {
870 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
871 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
872 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
873 NULL /* hv_create_port */, NULL /* hv_connect_port */,
874 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
875 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
876 NULL, NULL,
877 NULL, NULL, NULL, NULL,
878 NULL, NULL, NULL, NULL,
879 NULL, NULL, NULL, NULL,
880 NULL, NULL, NULL, NULL,
881 },
882 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
883 },
884 [FEAT_HYPERV_EDX] = {
885 .type = CPUID_FEATURE_WORD,
886 .feat_names = {
887 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
888 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
889 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
890 NULL, NULL,
891 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
892 NULL, NULL, NULL, NULL,
893 NULL, NULL, NULL, NULL,
894 NULL, NULL, NULL, NULL,
895 NULL, NULL, NULL, NULL,
896 NULL, NULL, NULL, NULL,
897 },
898 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
899 },
900 [FEAT_HV_RECOMM_EAX] = {
901 .type = CPUID_FEATURE_WORD,
902 .feat_names = {
903 NULL /* hv_recommend_pv_as_switch */,
904 NULL /* hv_recommend_pv_tlbflush_local */,
905 NULL /* hv_recommend_pv_tlbflush_remote */,
906 NULL /* hv_recommend_msr_apic_access */,
907 NULL /* hv_recommend_msr_reset */,
908 NULL /* hv_recommend_relaxed_timing */,
909 NULL /* hv_recommend_dma_remapping */,
910 NULL /* hv_recommend_int_remapping */,
911 NULL /* hv_recommend_x2apic_msrs */,
912 NULL /* hv_recommend_autoeoi_deprecation */,
913 NULL /* hv_recommend_pv_ipi */,
914 NULL /* hv_recommend_ex_hypercalls */,
915 NULL /* hv_hypervisor_is_nested */,
916 NULL /* hv_recommend_int_mbec */,
917 NULL /* hv_recommend_evmcs */,
918 NULL,
919 NULL, NULL, NULL, NULL,
920 NULL, NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 },
924 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
925 },
926 [FEAT_HV_NESTED_EAX] = {
927 .type = CPUID_FEATURE_WORD,
928 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
929 },
930 [FEAT_SVM] = {
931 .type = CPUID_FEATURE_WORD,
932 .feat_names = {
933 "npt", "lbrv", "svm-lock", "nrip-save",
934 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
935 NULL, NULL, "pause-filter", NULL,
936 "pfthreshold", NULL, NULL, NULL,
937 NULL, NULL, NULL, NULL,
938 NULL, NULL, NULL, NULL,
939 NULL, NULL, NULL, NULL,
940 NULL, NULL, NULL, NULL,
941 },
942 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
943 .tcg_features = TCG_SVM_FEATURES,
944 },
945 [FEAT_7_0_EBX] = {
946 .type = CPUID_FEATURE_WORD,
947 .feat_names = {
948 "fsgsbase", "tsc-adjust", NULL, "bmi1",
949 "hle", "avx2", NULL, "smep",
950 "bmi2", "erms", "invpcid", "rtm",
951 NULL, NULL, "mpx", NULL,
952 "avx512f", "avx512dq", "rdseed", "adx",
953 "smap", "avx512ifma", "pcommit", "clflushopt",
954 "clwb", "intel-pt", "avx512pf", "avx512er",
955 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
956 },
957 .cpuid = {
958 .eax = 7,
959 .needs_ecx = true, .ecx = 0,
960 .reg = R_EBX,
961 },
962 .tcg_features = TCG_7_0_EBX_FEATURES,
963 },
964 [FEAT_7_0_ECX] = {
965 .type = CPUID_FEATURE_WORD,
966 .feat_names = {
967 NULL, "avx512vbmi", "umip", "pku",
968 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
969 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
970 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
971 "la57", NULL, NULL, NULL,
972 NULL, NULL, "rdpid", NULL,
973 NULL, "cldemote", NULL, "movdiri",
974 "movdir64b", NULL, NULL, NULL,
975 },
976 .cpuid = {
977 .eax = 7,
978 .needs_ecx = true, .ecx = 0,
979 .reg = R_ECX,
980 },
981 .tcg_features = TCG_7_0_ECX_FEATURES,
982 },
983 [FEAT_7_0_EDX] = {
984 .type = CPUID_FEATURE_WORD,
985 .feat_names = {
986 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
987 "fsrm", NULL, NULL, NULL,
988 "avx512-vp2intersect", NULL, "md-clear", NULL,
989 NULL, NULL, "serialize", NULL,
990 "tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
991 NULL, NULL, NULL, NULL,
992 NULL, NULL, "spec-ctrl", "stibp",
993 NULL, "arch-capabilities", "core-capability", "ssbd",
994 },
995 .cpuid = {
996 .eax = 7,
997 .needs_ecx = true, .ecx = 0,
998 .reg = R_EDX,
999 },
1000 .tcg_features = TCG_7_0_EDX_FEATURES,
1001 },
1002 [FEAT_7_1_EAX] = {
1003 .type = CPUID_FEATURE_WORD,
1004 .feat_names = {
1005 NULL, NULL, NULL, NULL,
1006 NULL, "avx512-bf16", NULL, NULL,
1007 NULL, NULL, NULL, NULL,
1008 NULL, NULL, NULL, NULL,
1009 NULL, NULL, NULL, NULL,
1010 NULL, NULL, NULL, NULL,
1011 NULL, NULL, NULL, NULL,
1012 NULL, NULL, NULL, NULL,
1013 },
1014 .cpuid = {
1015 .eax = 7,
1016 .needs_ecx = true, .ecx = 1,
1017 .reg = R_EAX,
1018 },
1019 .tcg_features = TCG_7_1_EAX_FEATURES,
1020 },
1021 [FEAT_8000_0007_EDX] = {
1022 .type = CPUID_FEATURE_WORD,
1023 .feat_names = {
1024 NULL, NULL, NULL, NULL,
1025 NULL, NULL, NULL, NULL,
1026 "invtsc", NULL, NULL, NULL,
1027 NULL, NULL, NULL, NULL,
1028 NULL, NULL, NULL, NULL,
1029 NULL, NULL, NULL, NULL,
1030 NULL, NULL, NULL, NULL,
1031 NULL, NULL, NULL, NULL,
1032 },
1033 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
1034 .tcg_features = TCG_APM_FEATURES,
1035 .unmigratable_flags = CPUID_APM_INVTSC,
1036 },
1037 [FEAT_8000_0008_EBX] = {
1038 .type = CPUID_FEATURE_WORD,
1039 .feat_names = {
1040 "clzero", NULL, "xsaveerptr", NULL,
1041 NULL, NULL, NULL, NULL,
1042 NULL, "wbnoinvd", NULL, NULL,
1043 "ibpb", NULL, NULL, "amd-stibp",
1044 NULL, NULL, NULL, NULL,
1045 NULL, NULL, NULL, NULL,
1046 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1047 NULL, NULL, NULL, NULL,
1048 },
1049 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1050 .tcg_features = 0,
1051 .unmigratable_flags = 0,
1052 },
1053 [FEAT_XSAVE] = {
1054 .type = CPUID_FEATURE_WORD,
1055 .feat_names = {
1056 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1057 NULL, NULL, NULL, NULL,
1058 NULL, NULL, NULL, NULL,
1059 NULL, NULL, NULL, NULL,
1060 NULL, NULL, NULL, NULL,
1061 NULL, NULL, NULL, NULL,
1062 NULL, NULL, NULL, NULL,
1063 NULL, NULL, NULL, NULL,
1064 },
1065 .cpuid = {
1066 .eax = 0xd,
1067 .needs_ecx = true, .ecx = 1,
1068 .reg = R_EAX,
1069 },
1070 .tcg_features = TCG_XSAVE_FEATURES,
1071 },
1072 [FEAT_6_EAX] = {
1073 .type = CPUID_FEATURE_WORD,
1074 .feat_names = {
1075 NULL, NULL, "arat", NULL,
1076 NULL, NULL, NULL, NULL,
1077 NULL, NULL, NULL, NULL,
1078 NULL, NULL, NULL, NULL,
1079 NULL, NULL, NULL, NULL,
1080 NULL, NULL, NULL, NULL,
1081 NULL, NULL, NULL, NULL,
1082 NULL, NULL, NULL, NULL,
1083 },
1084 .cpuid = { .eax = 6, .reg = R_EAX, },
1085 .tcg_features = TCG_6_EAX_FEATURES,
1086 },
1087 [FEAT_XSAVE_COMP_LO] = {
1088 .type = CPUID_FEATURE_WORD,
1089 .cpuid = {
1090 .eax = 0xD,
1091 .needs_ecx = true, .ecx = 0,
1092 .reg = R_EAX,
1093 },
1094 .tcg_features = ~0U,
1095 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1096 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1097 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1098 XSTATE_PKRU_MASK,
1099 },
1100 [FEAT_XSAVE_COMP_HI] = {
1101 .type = CPUID_FEATURE_WORD,
1102 .cpuid = {
1103 .eax = 0xD,
1104 .needs_ecx = true, .ecx = 0,
1105 .reg = R_EDX,
1106 },
1107 .tcg_features = ~0U,
1108 },
1109 /*Below are MSR exposed features*/
1110 [FEAT_ARCH_CAPABILITIES] = {
1111 .type = MSR_FEATURE_WORD,
1112 .feat_names = {
1113 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1114 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
1115 "taa-no", NULL, NULL, NULL,
1116 NULL, NULL, NULL, NULL,
1117 NULL, NULL, NULL, NULL,
1118 NULL, NULL, NULL, NULL,
1119 NULL, NULL, NULL, NULL,
1120 NULL, NULL, NULL, NULL,
1121 },
1122 .msr = {
1123 .index = MSR_IA32_ARCH_CAPABILITIES,
1124 },
1125 },
1126 [FEAT_CORE_CAPABILITY] = {
1127 .type = MSR_FEATURE_WORD,
1128 .feat_names = {
1129 NULL, NULL, NULL, NULL,
1130 NULL, "split-lock-detect", NULL, NULL,
1131 NULL, NULL, NULL, NULL,
1132 NULL, NULL, NULL, NULL,
1133 NULL, NULL, NULL, NULL,
1134 NULL, NULL, NULL, NULL,
1135 NULL, NULL, NULL, NULL,
1136 NULL, NULL, NULL, NULL,
1137 },
1138 .msr = {
1139 .index = MSR_IA32_CORE_CAPABILITY,
1140 },
1141 },
1142 [FEAT_PERF_CAPABILITIES] = {
1143 .type = MSR_FEATURE_WORD,
1144 .feat_names = {
1145 NULL, NULL, NULL, NULL,
1146 NULL, NULL, NULL, NULL,
1147 NULL, NULL, NULL, NULL,
1148 NULL, "full-width-write", NULL, NULL,
1149 NULL, NULL, NULL, NULL,
1150 NULL, NULL, NULL, NULL,
1151 NULL, NULL, NULL, NULL,
1152 NULL, NULL, NULL, NULL,
1153 },
1154 .msr = {
1155 .index = MSR_IA32_PERF_CAPABILITIES,
1156 },
1157 },
1158
1159 [FEAT_VMX_PROCBASED_CTLS] = {
1160 .type = MSR_FEATURE_WORD,
1161 .feat_names = {
1162 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1163 NULL, NULL, NULL, "vmx-hlt-exit",
1164 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1165 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1166 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1167 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1168 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1169 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1170 },
1171 .msr = {
1172 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1173 }
1174 },
1175
1176 [FEAT_VMX_SECONDARY_CTLS] = {
1177 .type = MSR_FEATURE_WORD,
1178 .feat_names = {
1179 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1180 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1181 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1182 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1183 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1184 "vmx-xsaves", NULL, NULL, NULL,
1185 NULL, NULL, NULL, NULL,
1186 NULL, NULL, NULL, NULL,
1187 },
1188 .msr = {
1189 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1190 }
1191 },
1192
1193 [FEAT_VMX_PINBASED_CTLS] = {
1194 .type = MSR_FEATURE_WORD,
1195 .feat_names = {
1196 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1197 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1198 NULL, NULL, NULL, NULL,
1199 NULL, NULL, NULL, NULL,
1200 NULL, NULL, NULL, NULL,
1201 NULL, NULL, NULL, NULL,
1202 NULL, NULL, NULL, NULL,
1203 NULL, NULL, NULL, NULL,
1204 },
1205 .msr = {
1206 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1207 }
1208 },
1209
1210 [FEAT_VMX_EXIT_CTLS] = {
1211 .type = MSR_FEATURE_WORD,
1212 /*
1213 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1214 * the LM CPUID bit.
1215 */
1216 .feat_names = {
1217 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1218 NULL, NULL, NULL, NULL,
1219 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1220 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1221 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1222 "vmx-exit-save-efer", "vmx-exit-load-efer",
1223 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1224 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
1225 NULL, NULL, NULL, NULL,
1226 },
1227 .msr = {
1228 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1229 }
1230 },
1231
1232 [FEAT_VMX_ENTRY_CTLS] = {
1233 .type = MSR_FEATURE_WORD,
1234 .feat_names = {
1235 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1236 NULL, NULL, NULL, NULL,
1237 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1238 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1239 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
1240 NULL, NULL, NULL, NULL,
1241 NULL, NULL, NULL, NULL,
1242 NULL, NULL, NULL, NULL,
1243 },
1244 .msr = {
1245 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1246 }
1247 },
1248
1249 [FEAT_VMX_MISC] = {
1250 .type = MSR_FEATURE_WORD,
1251 .feat_names = {
1252 NULL, NULL, NULL, NULL,
1253 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1254 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1255 NULL, NULL, NULL, NULL,
1256 NULL, NULL, NULL, NULL,
1257 NULL, NULL, NULL, NULL,
1258 NULL, NULL, NULL, NULL,
1259 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1260 },
1261 .msr = {
1262 .index = MSR_IA32_VMX_MISC,
1263 }
1264 },
1265
1266 [FEAT_VMX_EPT_VPID_CAPS] = {
1267 .type = MSR_FEATURE_WORD,
1268 .feat_names = {
1269 "vmx-ept-execonly", NULL, NULL, NULL,
1270 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1271 NULL, NULL, NULL, NULL,
1272 NULL, NULL, NULL, NULL,
1273 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1274 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1275 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1276 NULL, NULL, NULL, NULL,
1277 "vmx-invvpid", NULL, NULL, NULL,
1278 NULL, NULL, NULL, NULL,
1279 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1280 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1281 NULL, NULL, NULL, NULL,
1282 NULL, NULL, NULL, NULL,
1283 NULL, NULL, NULL, NULL,
1284 NULL, NULL, NULL, NULL,
1285 NULL, NULL, NULL, NULL,
1286 },
1287 .msr = {
1288 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1289 }
1290 },
1291
1292 [FEAT_VMX_BASIC] = {
1293 .type = MSR_FEATURE_WORD,
1294 .feat_names = {
1295 [54] = "vmx-ins-outs",
1296 [55] = "vmx-true-ctls",
1297 },
1298 .msr = {
1299 .index = MSR_IA32_VMX_BASIC,
1300 },
1301 /* Just to be safe - we don't support setting the MSEG version field. */
1302 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1303 },
1304
1305 [FEAT_VMX_VMFUNC] = {
1306 .type = MSR_FEATURE_WORD,
1307 .feat_names = {
1308 [0] = "vmx-eptp-switching",
1309 },
1310 .msr = {
1311 .index = MSR_IA32_VMX_VMFUNC,
1312 }
1313 },
1314
1315 };
1316
1317 typedef struct FeatureMask {
1318 FeatureWord index;
1319 uint64_t mask;
1320 } FeatureMask;
1321
1322 typedef struct FeatureDep {
1323 FeatureMask from, to;
1324 } FeatureDep;
1325
1326 static FeatureDep feature_dependencies[] = {
1327 {
1328 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
1329 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
1330 },
1331 {
1332 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
1333 .to = { FEAT_CORE_CAPABILITY, ~0ull },
1334 },
1335 {
1336 .from = { FEAT_1_ECX, CPUID_EXT_PDCM },
1337 .to = { FEAT_PERF_CAPABILITIES, ~0ull },
1338 },
1339 {
1340 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1341 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1342 },
1343 {
1344 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1345 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1346 },
1347 {
1348 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1349 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1350 },
1351 {
1352 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1353 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1354 },
1355 {
1356 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1357 .to = { FEAT_VMX_MISC, ~0ull },
1358 },
1359 {
1360 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1361 .to = { FEAT_VMX_BASIC, ~0ull },
1362 },
1363 {
1364 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1365 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1366 },
1367 {
1368 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1369 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1370 },
1371 {
1372 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1373 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1374 },
1375 {
1376 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1377 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1378 },
1379 {
1380 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1381 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1382 },
1383 {
1384 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1385 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1386 },
1387 {
1388 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1389 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1390 },
1391 {
1392 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1393 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1394 },
1395 {
1396 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1397 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1398 },
1399 {
1400 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1401 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1402 },
1403 {
1404 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1405 .to = { FEAT_VMX_VMFUNC, ~0ull },
1406 },
1407 {
1408 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM },
1409 .to = { FEAT_SVM, ~0ull },
1410 },
1411 };
1412
1413 typedef struct X86RegisterInfo32 {
1414 /* Name of register */
1415 const char *name;
1416 /* QAPI enum value register */
1417 X86CPURegister32 qapi_enum;
1418 } X86RegisterInfo32;
1419
1420 #define REGISTER(reg) \
1421 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1422 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
1423 REGISTER(EAX),
1424 REGISTER(ECX),
1425 REGISTER(EDX),
1426 REGISTER(EBX),
1427 REGISTER(ESP),
1428 REGISTER(EBP),
1429 REGISTER(ESI),
1430 REGISTER(EDI),
1431 };
1432 #undef REGISTER
1433
1434 typedef struct ExtSaveArea {
1435 uint32_t feature, bits;
1436 uint32_t offset, size;
1437 } ExtSaveArea;
1438
1439 static const ExtSaveArea x86_ext_save_areas[] = {
1440 [XSTATE_FP_BIT] = {
1441 /* x87 FP state component is always enabled if XSAVE is supported */
1442 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1443 /* x87 state is in the legacy region of the XSAVE area */
1444 .offset = 0,
1445 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1446 },
1447 [XSTATE_SSE_BIT] = {
1448 /* SSE state component is always enabled if XSAVE is supported */
1449 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1450 /* SSE state is in the legacy region of the XSAVE area */
1451 .offset = 0,
1452 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1453 },
1454 [XSTATE_YMM_BIT] =
1455 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
1456 .offset = offsetof(X86XSaveArea, avx_state),
1457 .size = sizeof(XSaveAVX) },
1458 [XSTATE_BNDREGS_BIT] =
1459 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1460 .offset = offsetof(X86XSaveArea, bndreg_state),
1461 .size = sizeof(XSaveBNDREG) },
1462 [XSTATE_BNDCSR_BIT] =
1463 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1464 .offset = offsetof(X86XSaveArea, bndcsr_state),
1465 .size = sizeof(XSaveBNDCSR) },
1466 [XSTATE_OPMASK_BIT] =
1467 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1468 .offset = offsetof(X86XSaveArea, opmask_state),
1469 .size = sizeof(XSaveOpmask) },
1470 [XSTATE_ZMM_Hi256_BIT] =
1471 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1472 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1473 .size = sizeof(XSaveZMM_Hi256) },
1474 [XSTATE_Hi16_ZMM_BIT] =
1475 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1476 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1477 .size = sizeof(XSaveHi16_ZMM) },
1478 [XSTATE_PKRU_BIT] =
1479 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
1480 .offset = offsetof(X86XSaveArea, pkru_state),
1481 .size = sizeof(XSavePKRU) },
1482 };
1483
1484 static uint32_t xsave_area_size(uint64_t mask)
1485 {
1486 int i;
1487 uint64_t ret = 0;
1488
1489 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1490 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1491 if ((mask >> i) & 1) {
1492 ret = MAX(ret, esa->offset + esa->size);
1493 }
1494 }
1495 return ret;
1496 }
1497
1498 static inline bool accel_uses_host_cpuid(void)
1499 {
1500 return kvm_enabled() || hvf_enabled();
1501 }
1502
1503 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1504 {
1505 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1506 cpu->env.features[FEAT_XSAVE_COMP_LO];
1507 }
1508
1509 const char *get_register_name_32(unsigned int reg)
1510 {
1511 if (reg >= CPU_NB_REGS32) {
1512 return NULL;
1513 }
1514 return x86_reg_info_32[reg].name;
1515 }
1516
1517 /*
1518 * Returns the set of feature flags that are supported and migratable by
1519 * QEMU, for a given FeatureWord.
1520 */
1521 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
1522 {
1523 FeatureWordInfo *wi = &feature_word_info[w];
1524 uint64_t r = 0;
1525 int i;
1526
1527 for (i = 0; i < 64; i++) {
1528 uint64_t f = 1ULL << i;
1529
1530 /* If the feature name is known, it is implicitly considered migratable,
1531 * unless it is explicitly set in unmigratable_flags */
1532 if ((wi->migratable_flags & f) ||
1533 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1534 r |= f;
1535 }
1536 }
1537 return r;
1538 }
1539
1540 void host_cpuid(uint32_t function, uint32_t count,
1541 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
1542 {
1543 uint32_t vec[4];
1544
1545 #ifdef __x86_64__
1546 asm volatile("cpuid"
1547 : "=a"(vec[0]), "=b"(vec[1]),
1548 "=c"(vec[2]), "=d"(vec[3])
1549 : "0"(function), "c"(count) : "cc");
1550 #elif defined(__i386__)
1551 asm volatile("pusha \n\t"
1552 "cpuid \n\t"
1553 "mov %%eax, 0(%2) \n\t"
1554 "mov %%ebx, 4(%2) \n\t"
1555 "mov %%ecx, 8(%2) \n\t"
1556 "mov %%edx, 12(%2) \n\t"
1557 "popa"
1558 : : "a"(function), "c"(count), "S"(vec)
1559 : "memory", "cc");
1560 #else
1561 abort();
1562 #endif
1563
1564 if (eax)
1565 *eax = vec[0];
1566 if (ebx)
1567 *ebx = vec[1];
1568 if (ecx)
1569 *ecx = vec[2];
1570 if (edx)
1571 *edx = vec[3];
1572 }
1573
1574 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1575 {
1576 uint32_t eax, ebx, ecx, edx;
1577
1578 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1579 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1580
1581 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1582 if (family) {
1583 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1584 }
1585 if (model) {
1586 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1587 }
1588 if (stepping) {
1589 *stepping = eax & 0x0F;
1590 }
1591 }
1592
1593 /* CPU class name definitions: */
1594
1595 /* Return type name for a given CPU model name
1596 * Caller is responsible for freeing the returned string.
1597 */
1598 static char *x86_cpu_type_name(const char *model_name)
1599 {
1600 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1601 }
1602
1603 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1604 {
1605 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1606 return object_class_by_name(typename);
1607 }
1608
1609 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1610 {
1611 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1612 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1613 return g_strndup(class_name,
1614 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1615 }
1616
1617 typedef struct PropValue {
1618 const char *prop, *value;
1619 } PropValue;
1620
1621 typedef struct X86CPUVersionDefinition {
1622 X86CPUVersion version;
1623 const char *alias;
1624 const char *note;
1625 PropValue *props;
1626 } X86CPUVersionDefinition;
1627
1628 /* Base definition for a CPU model */
1629 typedef struct X86CPUDefinition {
1630 const char *name;
1631 uint32_t level;
1632 uint32_t xlevel;
1633 /* vendor is zero-terminated, 12 character ASCII string */
1634 char vendor[CPUID_VENDOR_SZ + 1];
1635 int family;
1636 int model;
1637 int stepping;
1638 FeatureWordArray features;
1639 const char *model_id;
1640 CPUCaches *cache_info;
1641 /*
1642 * Definitions for alternative versions of CPU model.
1643 * List is terminated by item with version == 0.
1644 * If NULL, version 1 will be registered automatically.
1645 */
1646 const X86CPUVersionDefinition *versions;
1647 } X86CPUDefinition;
1648
1649 /* Reference to a specific CPU model version */
1650 struct X86CPUModel {
1651 /* Base CPU definition */
1652 X86CPUDefinition *cpudef;
1653 /* CPU model version */
1654 X86CPUVersion version;
1655 const char *note;
1656 /*
1657 * If true, this is an alias CPU model.
1658 * This matters only for "-cpu help" and query-cpu-definitions
1659 */
1660 bool is_alias;
1661 };
1662
1663 /* Get full model name for CPU version */
1664 static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef,
1665 X86CPUVersion version)
1666 {
1667 assert(version > 0);
1668 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1669 }
1670
1671 static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def)
1672 {
1673 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1674 static const X86CPUVersionDefinition default_version_list[] = {
1675 { 1 },
1676 { /* end of list */ }
1677 };
1678
1679 return def->versions ?: default_version_list;
1680 }
1681
1682 static CPUCaches epyc_cache_info = {
1683 .l1d_cache = &(CPUCacheInfo) {
1684 .type = DATA_CACHE,
1685 .level = 1,
1686 .size = 32 * KiB,
1687 .line_size = 64,
1688 .associativity = 8,
1689 .partitions = 1,
1690 .sets = 64,
1691 .lines_per_tag = 1,
1692 .self_init = 1,
1693 .no_invd_sharing = true,
1694 },
1695 .l1i_cache = &(CPUCacheInfo) {
1696 .type = INSTRUCTION_CACHE,
1697 .level = 1,
1698 .size = 64 * KiB,
1699 .line_size = 64,
1700 .associativity = 4,
1701 .partitions = 1,
1702 .sets = 256,
1703 .lines_per_tag = 1,
1704 .self_init = 1,
1705 .no_invd_sharing = true,
1706 },
1707 .l2_cache = &(CPUCacheInfo) {
1708 .type = UNIFIED_CACHE,
1709 .level = 2,
1710 .size = 512 * KiB,
1711 .line_size = 64,
1712 .associativity = 8,
1713 .partitions = 1,
1714 .sets = 1024,
1715 .lines_per_tag = 1,
1716 },
1717 .l3_cache = &(CPUCacheInfo) {
1718 .type = UNIFIED_CACHE,
1719 .level = 3,
1720 .size = 8 * MiB,
1721 .line_size = 64,
1722 .associativity = 16,
1723 .partitions = 1,
1724 .sets = 8192,
1725 .lines_per_tag = 1,
1726 .self_init = true,
1727 .inclusive = true,
1728 .complex_indexing = true,
1729 },
1730 };
1731
1732 static CPUCaches epyc_rome_cache_info = {
1733 .l1d_cache = &(CPUCacheInfo) {
1734 .type = DATA_CACHE,
1735 .level = 1,
1736 .size = 32 * KiB,
1737 .line_size = 64,
1738 .associativity = 8,
1739 .partitions = 1,
1740 .sets = 64,
1741 .lines_per_tag = 1,
1742 .self_init = 1,
1743 .no_invd_sharing = true,
1744 },
1745 .l1i_cache = &(CPUCacheInfo) {
1746 .type = INSTRUCTION_CACHE,
1747 .level = 1,
1748 .size = 32 * KiB,
1749 .line_size = 64,
1750 .associativity = 8,
1751 .partitions = 1,
1752 .sets = 64,
1753 .lines_per_tag = 1,
1754 .self_init = 1,
1755 .no_invd_sharing = true,
1756 },
1757 .l2_cache = &(CPUCacheInfo) {
1758 .type = UNIFIED_CACHE,
1759 .level = 2,
1760 .size = 512 * KiB,
1761 .line_size = 64,
1762 .associativity = 8,
1763 .partitions = 1,
1764 .sets = 1024,
1765 .lines_per_tag = 1,
1766 },
1767 .l3_cache = &(CPUCacheInfo) {
1768 .type = UNIFIED_CACHE,
1769 .level = 3,
1770 .size = 16 * MiB,
1771 .line_size = 64,
1772 .associativity = 16,
1773 .partitions = 1,
1774 .sets = 16384,
1775 .lines_per_tag = 1,
1776 .self_init = true,
1777 .inclusive = true,
1778 .complex_indexing = true,
1779 },
1780 };
1781
1782 /* The following VMX features are not supported by KVM and are left out in the
1783 * CPU definitions:
1784 *
1785 * Dual-monitor support (all processors)
1786 * Entry to SMM
1787 * Deactivate dual-monitor treatment
1788 * Number of CR3-target values
1789 * Shutdown activity state
1790 * Wait-for-SIPI activity state
1791 * PAUSE-loop exiting (Westmere and newer)
1792 * EPT-violation #VE (Broadwell and newer)
1793 * Inject event with insn length=0 (Skylake and newer)
1794 * Conceal non-root operation from PT
1795 * Conceal VM exits from PT
1796 * Conceal VM entries from PT
1797 * Enable ENCLS exiting
1798 * Mode-based execute control (XS/XU)
1799 s TSC scaling (Skylake Server and newer)
1800 * GPA translation for PT (IceLake and newer)
1801 * User wait and pause
1802 * ENCLV exiting
1803 * Load IA32_RTIT_CTL
1804 * Clear IA32_RTIT_CTL
1805 * Advanced VM-exit information for EPT violations
1806 * Sub-page write permissions
1807 * PT in VMX operation
1808 */
1809
1810 static X86CPUDefinition builtin_x86_defs[] = {
1811 {
1812 .name = "qemu64",
1813 .level = 0xd,
1814 .vendor = CPUID_VENDOR_AMD,
1815 .family = 6,
1816 .model = 6,
1817 .stepping = 3,
1818 .features[FEAT_1_EDX] =
1819 PPRO_FEATURES |
1820 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1821 CPUID_PSE36,
1822 .features[FEAT_1_ECX] =
1823 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1824 .features[FEAT_8000_0001_EDX] =
1825 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1826 .features[FEAT_8000_0001_ECX] =
1827 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
1828 .xlevel = 0x8000000A,
1829 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1830 },
1831 {
1832 .name = "phenom",
1833 .level = 5,
1834 .vendor = CPUID_VENDOR_AMD,
1835 .family = 16,
1836 .model = 2,
1837 .stepping = 3,
1838 /* Missing: CPUID_HT */
1839 .features[FEAT_1_EDX] =
1840 PPRO_FEATURES |
1841 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1842 CPUID_PSE36 | CPUID_VME,
1843 .features[FEAT_1_ECX] =
1844 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
1845 CPUID_EXT_POPCNT,
1846 .features[FEAT_8000_0001_EDX] =
1847 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1848 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
1849 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
1850 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1851 CPUID_EXT3_CR8LEG,
1852 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1853 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1854 .features[FEAT_8000_0001_ECX] =
1855 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
1856 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
1857 /* Missing: CPUID_SVM_LBRV */
1858 .features[FEAT_SVM] =
1859 CPUID_SVM_NPT,
1860 .xlevel = 0x8000001A,
1861 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1862 },
1863 {
1864 .name = "core2duo",
1865 .level = 10,
1866 .vendor = CPUID_VENDOR_INTEL,
1867 .family = 6,
1868 .model = 15,
1869 .stepping = 11,
1870 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1871 .features[FEAT_1_EDX] =
1872 PPRO_FEATURES |
1873 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1874 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1875 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1876 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1877 .features[FEAT_1_ECX] =
1878 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1879 CPUID_EXT_CX16,
1880 .features[FEAT_8000_0001_EDX] =
1881 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1882 .features[FEAT_8000_0001_ECX] =
1883 CPUID_EXT3_LAHF_LM,
1884 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
1885 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1886 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1887 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1888 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1889 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
1890 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1891 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1892 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1893 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1894 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1895 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1896 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1897 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
1898 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
1899 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
1900 .features[FEAT_VMX_SECONDARY_CTLS] =
1901 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
1902 .xlevel = 0x80000008,
1903 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1904 },
1905 {
1906 .name = "kvm64",
1907 .level = 0xd,
1908 .vendor = CPUID_VENDOR_INTEL,
1909 .family = 15,
1910 .model = 6,
1911 .stepping = 1,
1912 /* Missing: CPUID_HT */
1913 .features[FEAT_1_EDX] =
1914 PPRO_FEATURES | CPUID_VME |
1915 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1916 CPUID_PSE36,
1917 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
1918 .features[FEAT_1_ECX] =
1919 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1920 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
1921 .features[FEAT_8000_0001_EDX] =
1922 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1923 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1924 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1925 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1926 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
1927 .features[FEAT_8000_0001_ECX] =
1928 0,
1929 /* VMX features from Cedar Mill/Prescott */
1930 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1931 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1932 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1933 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1934 VMX_PIN_BASED_NMI_EXITING,
1935 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1936 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1937 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1938 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1939 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1940 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1941 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1942 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
1943 .xlevel = 0x80000008,
1944 .model_id = "Common KVM processor"
1945 },
1946 {
1947 .name = "qemu32",
1948 .level = 4,
1949 .vendor = CPUID_VENDOR_INTEL,
1950 .family = 6,
1951 .model = 6,
1952 .stepping = 3,
1953 .features[FEAT_1_EDX] =
1954 PPRO_FEATURES,
1955 .features[FEAT_1_ECX] =
1956 CPUID_EXT_SSE3,
1957 .xlevel = 0x80000004,
1958 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1959 },
1960 {
1961 .name = "kvm32",
1962 .level = 5,
1963 .vendor = CPUID_VENDOR_INTEL,
1964 .family = 15,
1965 .model = 6,
1966 .stepping = 1,
1967 .features[FEAT_1_EDX] =
1968 PPRO_FEATURES | CPUID_VME |
1969 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
1970 .features[FEAT_1_ECX] =
1971 CPUID_EXT_SSE3,
1972 .features[FEAT_8000_0001_ECX] =
1973 0,
1974 /* VMX features from Yonah */
1975 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1976 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1977 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1978 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1979 VMX_PIN_BASED_NMI_EXITING,
1980 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1981 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1982 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1983 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1984 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
1985 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
1986 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
1987 .xlevel = 0x80000008,
1988 .model_id = "Common 32-bit KVM processor"
1989 },
1990 {
1991 .name = "coreduo",
1992 .level = 10,
1993 .vendor = CPUID_VENDOR_INTEL,
1994 .family = 6,
1995 .model = 14,
1996 .stepping = 8,
1997 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1998 .features[FEAT_1_EDX] =
1999 PPRO_FEATURES | CPUID_VME |
2000 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
2001 CPUID_SS,
2002 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
2003 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
2004 .features[FEAT_1_ECX] =
2005 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
2006 .features[FEAT_8000_0001_EDX] =
2007 CPUID_EXT2_NX,
2008 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2009 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2010 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2011 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2012 VMX_PIN_BASED_NMI_EXITING,
2013 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2014 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2015 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2016 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2017 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2018 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2019 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
2020 .xlevel = 0x80000008,
2021 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
2022 },
2023 {
2024 .name = "486",
2025 .level = 1,
2026 .vendor = CPUID_VENDOR_INTEL,
2027 .family = 4,
2028 .model = 8,
2029 .stepping = 0,
2030 .features[FEAT_1_EDX] =
2031 I486_FEATURES,
2032 .xlevel = 0,
2033 .model_id = "",
2034 },
2035 {
2036 .name = "pentium",
2037 .level = 1,
2038 .vendor = CPUID_VENDOR_INTEL,
2039 .family = 5,
2040 .model = 4,
2041 .stepping = 3,
2042 .features[FEAT_1_EDX] =
2043 PENTIUM_FEATURES,
2044 .xlevel = 0,
2045 .model_id = "",
2046 },
2047 {
2048 .name = "pentium2",
2049 .level = 2,
2050 .vendor = CPUID_VENDOR_INTEL,
2051 .family = 6,
2052 .model = 5,
2053 .stepping = 2,
2054 .features[FEAT_1_EDX] =
2055 PENTIUM2_FEATURES,
2056 .xlevel = 0,
2057 .model_id = "",
2058 },
2059 {
2060 .name = "pentium3",
2061 .level = 3,
2062 .vendor = CPUID_VENDOR_INTEL,
2063 .family = 6,
2064 .model = 7,
2065 .stepping = 3,
2066 .features[FEAT_1_EDX] =
2067 PENTIUM3_FEATURES,
2068 .xlevel = 0,
2069 .model_id = "",
2070 },
2071 {
2072 .name = "athlon",
2073 .level = 2,
2074 .vendor = CPUID_VENDOR_AMD,
2075 .family = 6,
2076 .model = 2,
2077 .stepping = 3,
2078 .features[FEAT_1_EDX] =
2079 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
2080 CPUID_MCA,
2081 .features[FEAT_8000_0001_EDX] =
2082 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
2083 .xlevel = 0x80000008,
2084 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
2085 },
2086 {
2087 .name = "n270",
2088 .level = 10,
2089 .vendor = CPUID_VENDOR_INTEL,
2090 .family = 6,
2091 .model = 28,
2092 .stepping = 2,
2093 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2094 .features[FEAT_1_EDX] =
2095 PPRO_FEATURES |
2096 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2097 CPUID_ACPI | CPUID_SS,
2098 /* Some CPUs got no CPUID_SEP */
2099 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2100 * CPUID_EXT_XTPR */
2101 .features[FEAT_1_ECX] =
2102 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
2103 CPUID_EXT_MOVBE,
2104 .features[FEAT_8000_0001_EDX] =
2105 CPUID_EXT2_NX,
2106 .features[FEAT_8000_0001_ECX] =
2107 CPUID_EXT3_LAHF_LM,
2108 .xlevel = 0x80000008,
2109 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2110 },
2111 {
2112 .name = "Conroe",
2113 .level = 10,
2114 .vendor = CPUID_VENDOR_INTEL,
2115 .family = 6,
2116 .model = 15,
2117 .stepping = 3,
2118 .features[FEAT_1_EDX] =
2119 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2120 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2121 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2122 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2123 CPUID_DE | CPUID_FP87,
2124 .features[FEAT_1_ECX] =
2125 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2126 .features[FEAT_8000_0001_EDX] =
2127 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2128 .features[FEAT_8000_0001_ECX] =
2129 CPUID_EXT3_LAHF_LM,
2130 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2131 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2132 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2133 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2134 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2135 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2136 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2137 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2138 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2139 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2140 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2141 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2142 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2143 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2144 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2145 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2146 .features[FEAT_VMX_SECONDARY_CTLS] =
2147 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
2148 .xlevel = 0x80000008,
2149 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2150 },
2151 {
2152 .name = "Penryn",
2153 .level = 10,
2154 .vendor = CPUID_VENDOR_INTEL,
2155 .family = 6,
2156 .model = 23,
2157 .stepping = 3,
2158 .features[FEAT_1_EDX] =
2159 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2160 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2161 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2162 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2163 CPUID_DE | CPUID_FP87,
2164 .features[FEAT_1_ECX] =
2165 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2166 CPUID_EXT_SSE3,
2167 .features[FEAT_8000_0001_EDX] =
2168 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2169 .features[FEAT_8000_0001_ECX] =
2170 CPUID_EXT3_LAHF_LM,
2171 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2172 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2173 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2174 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2175 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2176 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2177 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2178 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2179 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2180 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2181 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2182 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2183 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2184 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2185 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2186 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2187 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2188 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2189 .features[FEAT_VMX_SECONDARY_CTLS] =
2190 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2191 VMX_SECONDARY_EXEC_WBINVD_EXITING,
2192 .xlevel = 0x80000008,
2193 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2194 },
2195 {
2196 .name = "Nehalem",
2197 .level = 11,
2198 .vendor = CPUID_VENDOR_INTEL,
2199 .family = 6,
2200 .model = 26,
2201 .stepping = 3,
2202 .features[FEAT_1_EDX] =
2203 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2204 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2205 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2206 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2207 CPUID_DE | CPUID_FP87,
2208 .features[FEAT_1_ECX] =
2209 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2210 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2211 .features[FEAT_8000_0001_EDX] =
2212 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2213 .features[FEAT_8000_0001_ECX] =
2214 CPUID_EXT3_LAHF_LM,
2215 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2216 MSR_VMX_BASIC_TRUE_CTLS,
2217 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2218 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2219 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2220 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2221 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2222 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2223 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2224 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2225 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2226 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2227 .features[FEAT_VMX_EXIT_CTLS] =
2228 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2229 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2230 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2231 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2232 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2233 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2234 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2235 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2236 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2237 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2238 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2239 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2240 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2241 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2242 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2243 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2244 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2245 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2246 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2247 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2248 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2249 .features[FEAT_VMX_SECONDARY_CTLS] =
2250 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2251 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2252 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2253 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2254 VMX_SECONDARY_EXEC_ENABLE_VPID,
2255 .xlevel = 0x80000008,
2256 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
2257 .versions = (X86CPUVersionDefinition[]) {
2258 { .version = 1 },
2259 {
2260 .version = 2,
2261 .alias = "Nehalem-IBRS",
2262 .props = (PropValue[]) {
2263 { "spec-ctrl", "on" },
2264 { "model-id",
2265 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2266 { /* end of list */ }
2267 }
2268 },
2269 { /* end of list */ }
2270 }
2271 },
2272 {
2273 .name = "Westmere",
2274 .level = 11,
2275 .vendor = CPUID_VENDOR_INTEL,
2276 .family = 6,
2277 .model = 44,
2278 .stepping = 1,
2279 .features[FEAT_1_EDX] =
2280 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2281 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2282 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2283 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2284 CPUID_DE | CPUID_FP87,
2285 .features[FEAT_1_ECX] =
2286 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2287 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2288 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2289 .features[FEAT_8000_0001_EDX] =
2290 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2291 .features[FEAT_8000_0001_ECX] =
2292 CPUID_EXT3_LAHF_LM,
2293 .features[FEAT_6_EAX] =
2294 CPUID_6_EAX_ARAT,
2295 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2296 MSR_VMX_BASIC_TRUE_CTLS,
2297 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2298 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2299 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2300 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2301 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2302 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2303 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2304 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2305 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2306 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2307 .features[FEAT_VMX_EXIT_CTLS] =
2308 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2309 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2310 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2311 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2312 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2313 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2314 MSR_VMX_MISC_STORE_LMA,
2315 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2316 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2317 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2318 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2319 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2320 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2321 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2322 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2323 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2324 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2325 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2326 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2327 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2328 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2329 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2330 .features[FEAT_VMX_SECONDARY_CTLS] =
2331 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2332 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2333 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2334 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2335 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2336 .xlevel = 0x80000008,
2337 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
2338 .versions = (X86CPUVersionDefinition[]) {
2339 { .version = 1 },
2340 {
2341 .version = 2,
2342 .alias = "Westmere-IBRS",
2343 .props = (PropValue[]) {
2344 { "spec-ctrl", "on" },
2345 { "model-id",
2346 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2347 { /* end of list */ }
2348 }
2349 },
2350 { /* end of list */ }
2351 }
2352 },
2353 {
2354 .name = "SandyBridge",
2355 .level = 0xd,
2356 .vendor = CPUID_VENDOR_INTEL,
2357 .family = 6,
2358 .model = 42,
2359 .stepping = 1,
2360 .features[FEAT_1_EDX] =
2361 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2362 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2363 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2364 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2365 CPUID_DE | CPUID_FP87,
2366 .features[FEAT_1_ECX] =
2367 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2368 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2369 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2370 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2371 CPUID_EXT_SSE3,
2372 .features[FEAT_8000_0001_EDX] =
2373 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2374 CPUID_EXT2_SYSCALL,
2375 .features[FEAT_8000_0001_ECX] =
2376 CPUID_EXT3_LAHF_LM,
2377 .features[FEAT_XSAVE] =
2378 CPUID_XSAVE_XSAVEOPT,
2379 .features[FEAT_6_EAX] =
2380 CPUID_6_EAX_ARAT,
2381 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2382 MSR_VMX_BASIC_TRUE_CTLS,
2383 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2384 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2385 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2386 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2387 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2388 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2389 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2390 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2391 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2392 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2393 .features[FEAT_VMX_EXIT_CTLS] =
2394 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2395 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2396 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2397 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2398 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2399 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2400 MSR_VMX_MISC_STORE_LMA,
2401 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2402 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2403 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2404 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2405 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2406 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2407 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2408 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2409 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2410 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2411 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2412 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2413 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2414 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2415 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2416 .features[FEAT_VMX_SECONDARY_CTLS] =
2417 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2418 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2419 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2420 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2421 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2422 .xlevel = 0x80000008,
2423 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
2424 .versions = (X86CPUVersionDefinition[]) {
2425 { .version = 1 },
2426 {
2427 .version = 2,
2428 .alias = "SandyBridge-IBRS",
2429 .props = (PropValue[]) {
2430 { "spec-ctrl", "on" },
2431 { "model-id",
2432 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2433 { /* end of list */ }
2434 }
2435 },
2436 { /* end of list */ }
2437 }
2438 },
2439 {
2440 .name = "IvyBridge",
2441 .level = 0xd,
2442 .vendor = CPUID_VENDOR_INTEL,
2443 .family = 6,
2444 .model = 58,
2445 .stepping = 9,
2446 .features[FEAT_1_EDX] =
2447 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2448 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2449 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2450 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2451 CPUID_DE | CPUID_FP87,
2452 .features[FEAT_1_ECX] =
2453 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2454 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2455 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2456 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2457 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2458 .features[FEAT_7_0_EBX] =
2459 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2460 CPUID_7_0_EBX_ERMS,
2461 .features[FEAT_8000_0001_EDX] =
2462 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2463 CPUID_EXT2_SYSCALL,
2464 .features[FEAT_8000_0001_ECX] =
2465 CPUID_EXT3_LAHF_LM,
2466 .features[FEAT_XSAVE] =
2467 CPUID_XSAVE_XSAVEOPT,
2468 .features[FEAT_6_EAX] =
2469 CPUID_6_EAX_ARAT,
2470 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2471 MSR_VMX_BASIC_TRUE_CTLS,
2472 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2473 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2474 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2475 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2476 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2477 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2478 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2479 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2480 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2481 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2482 .features[FEAT_VMX_EXIT_CTLS] =
2483 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2484 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2485 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2486 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2487 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2488 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2489 MSR_VMX_MISC_STORE_LMA,
2490 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2491 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2492 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2493 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2494 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2495 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2496 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2497 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2498 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2499 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2500 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2501 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2502 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2503 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2504 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2505 .features[FEAT_VMX_SECONDARY_CTLS] =
2506 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2507 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2508 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2509 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2510 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2511 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2512 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2513 VMX_SECONDARY_EXEC_RDRAND_EXITING,
2514 .xlevel = 0x80000008,
2515 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
2516 .versions = (X86CPUVersionDefinition[]) {
2517 { .version = 1 },
2518 {
2519 .version = 2,
2520 .alias = "IvyBridge-IBRS",
2521 .props = (PropValue[]) {
2522 { "spec-ctrl", "on" },
2523 { "model-id",
2524 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2525 { /* end of list */ }
2526 }
2527 },
2528 { /* end of list */ }
2529 }
2530 },
2531 {
2532 .name = "Haswell",
2533 .level = 0xd,
2534 .vendor = CPUID_VENDOR_INTEL,
2535 .family = 6,
2536 .model = 60,
2537 .stepping = 4,
2538 .features[FEAT_1_EDX] =
2539 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2540 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2541 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2542 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2543 CPUID_DE | CPUID_FP87,
2544 .features[FEAT_1_ECX] =
2545 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2546 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2547 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2548 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2549 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2550 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2551 .features[FEAT_8000_0001_EDX] =
2552 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2553 CPUID_EXT2_SYSCALL,
2554 .features[FEAT_8000_0001_ECX] =
2555 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2556 .features[FEAT_7_0_EBX] =
2557 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2558 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2559 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2560 CPUID_7_0_EBX_RTM,
2561 .features[FEAT_XSAVE] =
2562 CPUID_XSAVE_XSAVEOPT,
2563 .features[FEAT_6_EAX] =
2564 CPUID_6_EAX_ARAT,
2565 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2566 MSR_VMX_BASIC_TRUE_CTLS,
2567 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2568 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2569 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2570 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2571 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2572 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2573 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2574 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2575 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2576 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2577 .features[FEAT_VMX_EXIT_CTLS] =
2578 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2579 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2580 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2581 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2582 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2583 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2584 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2585 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2586 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2587 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2588 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2589 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2590 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2591 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2592 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2593 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2594 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2595 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2596 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2597 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2598 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2599 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2600 .features[FEAT_VMX_SECONDARY_CTLS] =
2601 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2602 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2603 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2604 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2605 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2606 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2607 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2608 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2609 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2610 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2611 .xlevel = 0x80000008,
2612 .model_id = "Intel Core Processor (Haswell)",
2613 .versions = (X86CPUVersionDefinition[]) {
2614 { .version = 1 },
2615 {
2616 .version = 2,
2617 .alias = "Haswell-noTSX",
2618 .props = (PropValue[]) {
2619 { "hle", "off" },
2620 { "rtm", "off" },
2621 { "stepping", "1" },
2622 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2623 { /* end of list */ }
2624 },
2625 },
2626 {
2627 .version = 3,
2628 .alias = "Haswell-IBRS",
2629 .props = (PropValue[]) {
2630 /* Restore TSX features removed by -v2 above */
2631 { "hle", "on" },
2632 { "rtm", "on" },
2633 /*
2634 * Haswell and Haswell-IBRS had stepping=4 in
2635 * QEMU 4.0 and older
2636 */
2637 { "stepping", "4" },
2638 { "spec-ctrl", "on" },
2639 { "model-id",
2640 "Intel Core Processor (Haswell, IBRS)" },
2641 { /* end of list */ }
2642 }
2643 },
2644 {
2645 .version = 4,
2646 .alias = "Haswell-noTSX-IBRS",
2647 .props = (PropValue[]) {
2648 { "hle", "off" },
2649 { "rtm", "off" },
2650 /* spec-ctrl was already enabled by -v3 above */
2651 { "stepping", "1" },
2652 { "model-id",
2653 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2654 { /* end of list */ }
2655 }
2656 },
2657 { /* end of list */ }
2658 }
2659 },
2660 {
2661 .name = "Broadwell",
2662 .level = 0xd,
2663 .vendor = CPUID_VENDOR_INTEL,
2664 .family = 6,
2665 .model = 61,
2666 .stepping = 2,
2667 .features[FEAT_1_EDX] =
2668 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2669 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2670 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2671 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2672 CPUID_DE | CPUID_FP87,
2673 .features[FEAT_1_ECX] =
2674 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2675 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2676 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2677 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2678 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2679 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2680 .features[FEAT_8000_0001_EDX] =
2681 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2682 CPUID_EXT2_SYSCALL,
2683 .features[FEAT_8000_0001_ECX] =
2684 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2685 .features[FEAT_7_0_EBX] =
2686 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2687 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2688 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2689 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2690 CPUID_7_0_EBX_SMAP,
2691 .features[FEAT_XSAVE] =
2692 CPUID_XSAVE_XSAVEOPT,
2693 .features[FEAT_6_EAX] =
2694 CPUID_6_EAX_ARAT,
2695 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2696 MSR_VMX_BASIC_TRUE_CTLS,
2697 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2698 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2699 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2700 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2701 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2702 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2703 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2704 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2705 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2706 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2707 .features[FEAT_VMX_EXIT_CTLS] =
2708 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2709 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2710 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2711 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2712 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2713 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2714 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2715 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2716 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2717 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2718 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2719 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2720 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2721 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2722 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2723 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2724 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2725 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2726 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2727 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2728 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2729 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2730 .features[FEAT_VMX_SECONDARY_CTLS] =
2731 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2732 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2733 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2734 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2735 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2736 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2737 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2738 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2739 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2740 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2741 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2742 .xlevel = 0x80000008,
2743 .model_id = "Intel Core Processor (Broadwell)",
2744 .versions = (X86CPUVersionDefinition[]) {
2745 { .version = 1 },
2746 {
2747 .version = 2,
2748 .alias = "Broadwell-noTSX",
2749 .props = (PropValue[]) {
2750 { "hle", "off" },
2751 { "rtm", "off" },
2752 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2753 { /* end of list */ }
2754 },
2755 },
2756 {
2757 .version = 3,
2758 .alias = "Broadwell-IBRS",
2759 .props = (PropValue[]) {
2760 /* Restore TSX features removed by -v2 above */
2761 { "hle", "on" },
2762 { "rtm", "on" },
2763 { "spec-ctrl", "on" },
2764 { "model-id",
2765 "Intel Core Processor (Broadwell, IBRS)" },
2766 { /* end of list */ }
2767 }
2768 },
2769 {
2770 .version = 4,
2771 .alias = "Broadwell-noTSX-IBRS",
2772 .props = (PropValue[]) {
2773 { "hle", "off" },
2774 { "rtm", "off" },
2775 /* spec-ctrl was already enabled by -v3 above */
2776 { "model-id",
2777 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2778 { /* end of list */ }
2779 }
2780 },
2781 { /* end of list */ }
2782 }
2783 },
2784 {
2785 .name = "Skylake-Client",
2786 .level = 0xd,
2787 .vendor = CPUID_VENDOR_INTEL,
2788 .family = 6,
2789 .model = 94,
2790 .stepping = 3,
2791 .features[FEAT_1_EDX] =
2792 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2793 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2794 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2795 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2796 CPUID_DE | CPUID_FP87,
2797 .features[FEAT_1_ECX] =
2798 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2799 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2800 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2801 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2802 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2803 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2804 .features[FEAT_8000_0001_EDX] =
2805 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2806 CPUID_EXT2_SYSCALL,
2807 .features[FEAT_8000_0001_ECX] =
2808 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2809 .features[FEAT_7_0_EBX] =
2810 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2811 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2812 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2813 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2814 CPUID_7_0_EBX_SMAP,
2815 /* Missing: XSAVES (not supported by some Linux versions,
2816 * including v4.1 to v4.12).
2817 * KVM doesn't yet expose any XSAVES state save component,
2818 * and the only one defined in Skylake (processor tracing)
2819 * probably will block migration anyway.
2820 */
2821 .features[FEAT_XSAVE] =
2822 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2823 CPUID_XSAVE_XGETBV1,
2824 .features[FEAT_6_EAX] =
2825 CPUID_6_EAX_ARAT,
2826 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2827 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2828 MSR_VMX_BASIC_TRUE_CTLS,
2829 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2830 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2831 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2832 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2833 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2834 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2835 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2836 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2837 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2838 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2839 .features[FEAT_VMX_EXIT_CTLS] =
2840 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2841 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2842 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2843 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2844 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2845 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2846 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2847 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2848 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2849 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2850 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2851 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2852 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2853 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2854 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2855 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2856 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2857 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2858 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2859 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2860 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2861 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2862 .features[FEAT_VMX_SECONDARY_CTLS] =
2863 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2864 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2865 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2866 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2867 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2868 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2869 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2870 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2871 .xlevel = 0x80000008,
2872 .model_id = "Intel Core Processor (Skylake)",
2873 .versions = (X86CPUVersionDefinition[]) {
2874 { .version = 1 },
2875 {
2876 .version = 2,
2877 .alias = "Skylake-Client-IBRS",
2878 .props = (PropValue[]) {
2879 { "spec-ctrl", "on" },
2880 { "model-id",
2881 "Intel Core Processor (Skylake, IBRS)" },
2882 { /* end of list */ }
2883 }
2884 },
2885 {
2886 .version = 3,
2887 .alias = "Skylake-Client-noTSX-IBRS",
2888 .props = (PropValue[]) {
2889 { "hle", "off" },
2890 { "rtm", "off" },
2891 { "model-id",
2892 "Intel Core Processor (Skylake, IBRS, no TSX)" },
2893 { /* end of list */ }
2894 }
2895 },
2896 { /* end of list */ }
2897 }
2898 },
2899 {
2900 .name = "Skylake-Server",
2901 .level = 0xd,
2902 .vendor = CPUID_VENDOR_INTEL,
2903 .family = 6,
2904 .model = 85,
2905 .stepping = 4,
2906 .features[FEAT_1_EDX] =
2907 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2908 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2909 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2910 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2911 CPUID_DE | CPUID_FP87,
2912 .features[FEAT_1_ECX] =
2913 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2914 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2915 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2916 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2917 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2918 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2919 .features[FEAT_8000_0001_EDX] =
2920 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2921 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2922 .features[FEAT_8000_0001_ECX] =
2923 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2924 .features[FEAT_7_0_EBX] =
2925 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2926 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2927 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2928 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2929 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2930 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2931 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2932 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2933 .features[FEAT_7_0_ECX] =
2934 CPUID_7_0_ECX_PKU,
2935 /* Missing: XSAVES (not supported by some Linux versions,
2936 * including v4.1 to v4.12).
2937 * KVM doesn't yet expose any XSAVES state save component,
2938 * and the only one defined in Skylake (processor tracing)
2939 * probably will block migration anyway.
2940 */
2941 .features[FEAT_XSAVE] =
2942 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2943 CPUID_XSAVE_XGETBV1,
2944 .features[FEAT_6_EAX] =
2945 CPUID_6_EAX_ARAT,
2946 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2947 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2948 MSR_VMX_BASIC_TRUE_CTLS,
2949 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2950 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2951 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2952 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2953 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2954 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2955 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2956 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2957 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2958 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2959 .features[FEAT_VMX_EXIT_CTLS] =
2960 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2961 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2962 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2963 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2964 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2965 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2966 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2967 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2968 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2969 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2970 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2971 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2972 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2973 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2974 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2975 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2976 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2977 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2978 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2979 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2980 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2981 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2982 .features[FEAT_VMX_SECONDARY_CTLS] =
2983 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2984 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2985 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2986 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2987 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2988 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2989 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2990 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2991 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2992 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2993 .xlevel = 0x80000008,
2994 .model_id = "Intel Xeon Processor (Skylake)",
2995 .versions = (X86CPUVersionDefinition[]) {
2996 { .version = 1 },
2997 {
2998 .version = 2,
2999 .alias = "Skylake-Server-IBRS",
3000 .props = (PropValue[]) {
3001 /* clflushopt was not added to Skylake-Server-IBRS */
3002 /* TODO: add -v3 including clflushopt */
3003 { "clflushopt", "off" },
3004 { "spec-ctrl", "on" },
3005 { "model-id",
3006 "Intel Xeon Processor (Skylake, IBRS)" },
3007 { /* end of list */ }
3008 }
3009 },
3010 {
3011 .version = 3,
3012 .alias = "Skylake-Server-noTSX-IBRS",
3013 .props = (PropValue[]) {
3014 { "hle", "off" },
3015 { "rtm", "off" },
3016 { "model-id",
3017 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
3018 { /* end of list */ }
3019 }
3020 },
3021 {
3022 .version = 4,
3023 .props = (PropValue[]) {
3024 { "vmx-eptp-switching", "on" },
3025 { /* end of list */ }
3026 }
3027 },
3028 { /* end of list */ }
3029 }
3030 },
3031 {
3032 .name = "Cascadelake-Server",
3033 .level = 0xd,
3034 .vendor = CPUID_VENDOR_INTEL,
3035 .family = 6,
3036 .model = 85,
3037 .stepping = 6,
3038 .features[FEAT_1_EDX] =
3039 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3040 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3041 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3042 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3043 CPUID_DE | CPUID_FP87,
3044 .features[FEAT_1_ECX] =
3045 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3046 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3047 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3048 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3049 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3050 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3051 .features[FEAT_8000_0001_EDX] =
3052 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3053 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3054 .features[FEAT_8000_0001_ECX] =
3055 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3056 .features[FEAT_7_0_EBX] =
3057 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3058 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3059 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3060 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3061 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3062 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3063 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3064 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3065 .features[FEAT_7_0_ECX] =
3066 CPUID_7_0_ECX_PKU |
3067 CPUID_7_0_ECX_AVX512VNNI,
3068 .features[FEAT_7_0_EDX] =
3069 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3070 /* Missing: XSAVES (not supported by some Linux versions,
3071 * including v4.1 to v4.12).
3072 * KVM doesn't yet expose any XSAVES state save component,
3073 * and the only one defined in Skylake (processor tracing)
3074 * probably will block migration anyway.
3075 */
3076 .features[FEAT_XSAVE] =
3077 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3078 CPUID_XSAVE_XGETBV1,
3079 .features[FEAT_6_EAX] =
3080 CPUID_6_EAX_ARAT,
3081 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3082 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3083 MSR_VMX_BASIC_TRUE_CTLS,
3084 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3085 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3086 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3087 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3088 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3089 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3090 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3091 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3092 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3093 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3094 .features[FEAT_VMX_EXIT_CTLS] =
3095 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3096 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3097 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3098 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3099 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3100 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3101 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3102 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3103 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3104 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3105 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3106 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3107 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3108 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3109 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3110 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3111 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3112 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3113 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3114 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3115 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3116 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3117 .features[FEAT_VMX_SECONDARY_CTLS] =
3118 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3119 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3120 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3121 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3122 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3123 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3124 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3125 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3126 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3127 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3128 .xlevel = 0x80000008,
3129 .model_id = "Intel Xeon Processor (Cascadelake)",
3130 .versions = (X86CPUVersionDefinition[]) {
3131 { .version = 1 },
3132 { .version = 2,
3133 .note = "ARCH_CAPABILITIES",
3134 .props = (PropValue[]) {
3135 { "arch-capabilities", "on" },
3136 { "rdctl-no", "on" },
3137 { "ibrs-all", "on" },
3138 { "skip-l1dfl-vmentry", "on" },
3139 { "mds-no", "on" },
3140 { /* end of list */ }
3141 },
3142 },
3143 { .version = 3,
3144 .alias = "Cascadelake-Server-noTSX",
3145 .note = "ARCH_CAPABILITIES, no TSX",
3146 .props = (PropValue[]) {
3147 { "hle", "off" },
3148 { "rtm", "off" },
3149 { /* end of list */ }
3150 },
3151 },
3152 { .version = 4,
3153 .note = "ARCH_CAPABILITIES, no TSX",
3154 .props = (PropValue[]) {
3155 { "vmx-eptp-switching", "on" },
3156 { /* end of list */ }
3157 },
3158 },
3159 { /* end of list */ }
3160 }
3161 },
3162 {
3163 .name = "Cooperlake",
3164 .level = 0xd,
3165 .vendor = CPUID_VENDOR_INTEL,
3166 .family = 6,
3167 .model = 85,
3168 .stepping = 10,
3169 .features[FEAT_1_EDX] =
3170 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3171 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3172 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3173 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3174 CPUID_DE | CPUID_FP87,
3175 .features[FEAT_1_ECX] =
3176 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
317