target/i386: kvm: Add support for KVM_CAP_EXCEPTION_PAYLOAD
[qemu.git] / target / i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/bitops.h"
24 #include "qemu/qemu-print.h"
25
26 #include "cpu.h"
27 #include "exec/exec-all.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/hvf.h"
30 #include "sysemu/cpus.h"
31 #include "kvm_i386.h"
32 #include "sev_i386.h"
33
34 #include "qemu/error-report.h"
35 #include "qemu/module.h"
36 #include "qemu/option.h"
37 #include "qemu/config-file.h"
38 #include "qapi/error.h"
39 #include "qapi/qapi-visit-misc.h"
40 #include "qapi/qapi-visit-run-state.h"
41 #include "qapi/qmp/qdict.h"
42 #include "qapi/qmp/qerror.h"
43 #include "qapi/visitor.h"
44 #include "qom/qom-qobject.h"
45 #include "sysemu/arch_init.h"
46 #include "qapi/qapi-commands-target.h"
47
48 #include "standard-headers/asm-x86/kvm_para.h"
49
50 #include "sysemu/sysemu.h"
51 #include "sysemu/tcg.h"
52 #include "hw/qdev-properties.h"
53 #include "hw/i386/topology.h"
54 #ifndef CONFIG_USER_ONLY
55 #include "exec/address-spaces.h"
56 #include "hw/hw.h"
57 #include "hw/xen/xen.h"
58 #include "hw/i386/apic_internal.h"
59 #endif
60
61 #include "disas/capstone.h"
62
63 /* Helpers for building CPUID[2] descriptors: */
64
65 struct CPUID2CacheDescriptorInfo {
66 enum CacheType type;
67 int level;
68 int size;
69 int line_size;
70 int associativity;
71 };
72
73 /*
74 * Known CPUID 2 cache descriptors.
75 * From Intel SDM Volume 2A, CPUID instruction
76 */
77 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
78 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
79 .associativity = 4, .line_size = 32, },
80 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
81 .associativity = 4, .line_size = 32, },
82 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
83 .associativity = 4, .line_size = 64, },
84 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
85 .associativity = 2, .line_size = 32, },
86 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
87 .associativity = 4, .line_size = 32, },
88 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
89 .associativity = 4, .line_size = 64, },
90 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
91 .associativity = 6, .line_size = 64, },
92 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
93 .associativity = 2, .line_size = 64, },
94 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
95 .associativity = 8, .line_size = 64, },
96 /* lines per sector is not supported cpuid2_cache_descriptor(),
97 * so descriptors 0x22, 0x23 are not included
98 */
99 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
100 .associativity = 16, .line_size = 64, },
101 /* lines per sector is not supported cpuid2_cache_descriptor(),
102 * so descriptors 0x25, 0x20 are not included
103 */
104 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
105 .associativity = 8, .line_size = 64, },
106 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
107 .associativity = 8, .line_size = 64, },
108 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
109 .associativity = 4, .line_size = 32, },
110 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
111 .associativity = 4, .line_size = 32, },
112 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
113 .associativity = 4, .line_size = 32, },
114 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
115 .associativity = 4, .line_size = 32, },
116 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
117 .associativity = 4, .line_size = 32, },
118 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
119 .associativity = 4, .line_size = 64, },
120 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
121 .associativity = 8, .line_size = 64, },
122 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
123 .associativity = 12, .line_size = 64, },
124 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
125 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
126 .associativity = 12, .line_size = 64, },
127 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
128 .associativity = 16, .line_size = 64, },
129 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
130 .associativity = 12, .line_size = 64, },
131 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
132 .associativity = 16, .line_size = 64, },
133 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
134 .associativity = 24, .line_size = 64, },
135 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
136 .associativity = 8, .line_size = 64, },
137 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
138 .associativity = 4, .line_size = 64, },
139 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
140 .associativity = 4, .line_size = 64, },
141 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
142 .associativity = 4, .line_size = 64, },
143 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
144 .associativity = 4, .line_size = 64, },
145 /* lines per sector is not supported cpuid2_cache_descriptor(),
146 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
147 */
148 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
149 .associativity = 8, .line_size = 64, },
150 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
151 .associativity = 2, .line_size = 64, },
152 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
153 .associativity = 8, .line_size = 64, },
154 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
155 .associativity = 8, .line_size = 32, },
156 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
157 .associativity = 8, .line_size = 32, },
158 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
159 .associativity = 8, .line_size = 32, },
160 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
161 .associativity = 8, .line_size = 32, },
162 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
163 .associativity = 4, .line_size = 64, },
164 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
165 .associativity = 8, .line_size = 64, },
166 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
167 .associativity = 4, .line_size = 64, },
168 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
169 .associativity = 4, .line_size = 64, },
170 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
171 .associativity = 4, .line_size = 64, },
172 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
173 .associativity = 8, .line_size = 64, },
174 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
175 .associativity = 8, .line_size = 64, },
176 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
177 .associativity = 8, .line_size = 64, },
178 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
179 .associativity = 12, .line_size = 64, },
180 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
181 .associativity = 12, .line_size = 64, },
182 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
183 .associativity = 12, .line_size = 64, },
184 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
185 .associativity = 16, .line_size = 64, },
186 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
187 .associativity = 16, .line_size = 64, },
188 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
189 .associativity = 16, .line_size = 64, },
190 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
191 .associativity = 24, .line_size = 64, },
192 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
193 .associativity = 24, .line_size = 64, },
194 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
195 .associativity = 24, .line_size = 64, },
196 };
197
198 /*
199 * "CPUID leaf 2 does not report cache descriptor information,
200 * use CPUID leaf 4 to query cache parameters"
201 */
202 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
203
204 /*
205 * Return a CPUID 2 cache descriptor for a given cache.
206 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
207 */
208 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
209 {
210 int i;
211
212 assert(cache->size > 0);
213 assert(cache->level > 0);
214 assert(cache->line_size > 0);
215 assert(cache->associativity > 0);
216 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
217 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
218 if (d->level == cache->level && d->type == cache->type &&
219 d->size == cache->size && d->line_size == cache->line_size &&
220 d->associativity == cache->associativity) {
221 return i;
222 }
223 }
224
225 return CACHE_DESCRIPTOR_UNAVAILABLE;
226 }
227
228 /* CPUID Leaf 4 constants: */
229
230 /* EAX: */
231 #define CACHE_TYPE_D 1
232 #define CACHE_TYPE_I 2
233 #define CACHE_TYPE_UNIFIED 3
234
235 #define CACHE_LEVEL(l) (l << 5)
236
237 #define CACHE_SELF_INIT_LEVEL (1 << 8)
238
239 /* EDX: */
240 #define CACHE_NO_INVD_SHARING (1 << 0)
241 #define CACHE_INCLUSIVE (1 << 1)
242 #define CACHE_COMPLEX_IDX (1 << 2)
243
244 /* Encode CacheType for CPUID[4].EAX */
245 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
246 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
247 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
248 0 /* Invalid value */)
249
250
251 /* Encode cache info for CPUID[4] */
252 static void encode_cache_cpuid4(CPUCacheInfo *cache,
253 int num_apic_ids, int num_cores,
254 uint32_t *eax, uint32_t *ebx,
255 uint32_t *ecx, uint32_t *edx)
256 {
257 assert(cache->size == cache->line_size * cache->associativity *
258 cache->partitions * cache->sets);
259
260 assert(num_apic_ids > 0);
261 *eax = CACHE_TYPE(cache->type) |
262 CACHE_LEVEL(cache->level) |
263 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
264 ((num_cores - 1) << 26) |
265 ((num_apic_ids - 1) << 14);
266
267 assert(cache->line_size > 0);
268 assert(cache->partitions > 0);
269 assert(cache->associativity > 0);
270 /* We don't implement fully-associative caches */
271 assert(cache->associativity < cache->sets);
272 *ebx = (cache->line_size - 1) |
273 ((cache->partitions - 1) << 12) |
274 ((cache->associativity - 1) << 22);
275
276 assert(cache->sets > 0);
277 *ecx = cache->sets - 1;
278
279 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
280 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
281 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
282 }
283
284 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
285 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
286 {
287 assert(cache->size % 1024 == 0);
288 assert(cache->lines_per_tag > 0);
289 assert(cache->associativity > 0);
290 assert(cache->line_size > 0);
291 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
292 (cache->lines_per_tag << 8) | (cache->line_size);
293 }
294
295 #define ASSOC_FULL 0xFF
296
297 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
298 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
299 a == 2 ? 0x2 : \
300 a == 4 ? 0x4 : \
301 a == 8 ? 0x6 : \
302 a == 16 ? 0x8 : \
303 a == 32 ? 0xA : \
304 a == 48 ? 0xB : \
305 a == 64 ? 0xC : \
306 a == 96 ? 0xD : \
307 a == 128 ? 0xE : \
308 a == ASSOC_FULL ? 0xF : \
309 0 /* invalid value */)
310
311 /*
312 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
313 * @l3 can be NULL.
314 */
315 static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
316 CPUCacheInfo *l3,
317 uint32_t *ecx, uint32_t *edx)
318 {
319 assert(l2->size % 1024 == 0);
320 assert(l2->associativity > 0);
321 assert(l2->lines_per_tag > 0);
322 assert(l2->line_size > 0);
323 *ecx = ((l2->size / 1024) << 16) |
324 (AMD_ENC_ASSOC(l2->associativity) << 12) |
325 (l2->lines_per_tag << 8) | (l2->line_size);
326
327 if (l3) {
328 assert(l3->size % (512 * 1024) == 0);
329 assert(l3->associativity > 0);
330 assert(l3->lines_per_tag > 0);
331 assert(l3->line_size > 0);
332 *edx = ((l3->size / (512 * 1024)) << 18) |
333 (AMD_ENC_ASSOC(l3->associativity) << 12) |
334 (l3->lines_per_tag << 8) | (l3->line_size);
335 } else {
336 *edx = 0;
337 }
338 }
339
340 /*
341 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
342 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
343 * Define the constants to build the cpu topology. Right now, TOPOEXT
344 * feature is enabled only on EPYC. So, these constants are based on
345 * EPYC supported configurations. We may need to handle the cases if
346 * these values change in future.
347 */
348 /* Maximum core complexes in a node */
349 #define MAX_CCX 2
350 /* Maximum cores in a core complex */
351 #define MAX_CORES_IN_CCX 4
352 /* Maximum cores in a node */
353 #define MAX_CORES_IN_NODE 8
354 /* Maximum nodes in a socket */
355 #define MAX_NODES_PER_SOCKET 4
356
357 /*
358 * Figure out the number of nodes required to build this config.
359 * Max cores in a node is 8
360 */
361 static int nodes_in_socket(int nr_cores)
362 {
363 int nodes;
364
365 nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
366
367 /* Hardware does not support config with 3 nodes, return 4 in that case */
368 return (nodes == 3) ? 4 : nodes;
369 }
370
371 /*
372 * Decide the number of cores in a core complex with the given nr_cores using
373 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
374 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
375 * L3 cache is shared across all cores in a core complex. So, this will also
376 * tell us how many cores are sharing the L3 cache.
377 */
378 static int cores_in_core_complex(int nr_cores)
379 {
380 int nodes;
381
382 /* Check if we can fit all the cores in one core complex */
383 if (nr_cores <= MAX_CORES_IN_CCX) {
384 return nr_cores;
385 }
386 /* Get the number of nodes required to build this config */
387 nodes = nodes_in_socket(nr_cores);
388
389 /*
390 * Divide the cores accros all the core complexes
391 * Return rounded up value
392 */
393 return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
394 }
395
396 /* Encode cache info for CPUID[8000001D] */
397 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
398 uint32_t *eax, uint32_t *ebx,
399 uint32_t *ecx, uint32_t *edx)
400 {
401 uint32_t l3_cores;
402 assert(cache->size == cache->line_size * cache->associativity *
403 cache->partitions * cache->sets);
404
405 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
406 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
407
408 /* L3 is shared among multiple cores */
409 if (cache->level == 3) {
410 l3_cores = cores_in_core_complex(cs->nr_cores);
411 *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
412 } else {
413 *eax |= ((cs->nr_threads - 1) << 14);
414 }
415
416 assert(cache->line_size > 0);
417 assert(cache->partitions > 0);
418 assert(cache->associativity > 0);
419 /* We don't implement fully-associative caches */
420 assert(cache->associativity < cache->sets);
421 *ebx = (cache->line_size - 1) |
422 ((cache->partitions - 1) << 12) |
423 ((cache->associativity - 1) << 22);
424
425 assert(cache->sets > 0);
426 *ecx = cache->sets - 1;
427
428 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
429 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
430 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
431 }
432
433 /* Data structure to hold the configuration info for a given core index */
434 struct core_topology {
435 /* core complex id of the current core index */
436 int ccx_id;
437 /*
438 * Adjusted core index for this core in the topology
439 * This can be 0,1,2,3 with max 4 cores in a core complex
440 */
441 int core_id;
442 /* Node id for this core index */
443 int node_id;
444 /* Number of nodes in this config */
445 int num_nodes;
446 };
447
448 /*
449 * Build the configuration closely match the EPYC hardware. Using the EPYC
450 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
451 * right now. This could change in future.
452 * nr_cores : Total number of cores in the config
453 * core_id : Core index of the current CPU
454 * topo : Data structure to hold all the config info for this core index
455 */
456 static void build_core_topology(int nr_cores, int core_id,
457 struct core_topology *topo)
458 {
459 int nodes, cores_in_ccx;
460
461 /* First get the number of nodes required */
462 nodes = nodes_in_socket(nr_cores);
463
464 cores_in_ccx = cores_in_core_complex(nr_cores);
465
466 topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
467 topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
468 topo->core_id = core_id % cores_in_ccx;
469 topo->num_nodes = nodes;
470 }
471
472 /* Encode cache info for CPUID[8000001E] */
473 static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
474 uint32_t *eax, uint32_t *ebx,
475 uint32_t *ecx, uint32_t *edx)
476 {
477 struct core_topology topo = {0};
478 unsigned long nodes;
479 int shift;
480
481 build_core_topology(cs->nr_cores, cpu->core_id, &topo);
482 *eax = cpu->apic_id;
483 /*
484 * CPUID_Fn8000001E_EBX
485 * 31:16 Reserved
486 * 15:8 Threads per core (The number of threads per core is
487 * Threads per core + 1)
488 * 7:0 Core id (see bit decoding below)
489 * SMT:
490 * 4:3 node id
491 * 2 Core complex id
492 * 1:0 Core id
493 * Non SMT:
494 * 5:4 node id
495 * 3 Core complex id
496 * 1:0 Core id
497 */
498 if (cs->nr_threads - 1) {
499 *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
500 (topo.ccx_id << 2) | topo.core_id;
501 } else {
502 *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
503 }
504 /*
505 * CPUID_Fn8000001E_ECX
506 * 31:11 Reserved
507 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
508 * 7:0 Node id (see bit decoding below)
509 * 2 Socket id
510 * 1:0 Node id
511 */
512 if (topo.num_nodes <= 4) {
513 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
514 topo.node_id;
515 } else {
516 /*
517 * Node id fix up. Actual hardware supports up to 4 nodes. But with
518 * more than 32 cores, we may end up with more than 4 nodes.
519 * Node id is a combination of socket id and node id. Only requirement
520 * here is that this number should be unique accross the system.
521 * Shift the socket id to accommodate more nodes. We dont expect both
522 * socket id and node id to be big number at the same time. This is not
523 * an ideal config but we need to to support it. Max nodes we can have
524 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
525 * 5 bits for nodes. Find the left most set bit to represent the total
526 * number of nodes. find_last_bit returns last set bit(0 based). Left
527 * shift(+1) the socket id to represent all the nodes.
528 */
529 nodes = topo.num_nodes - 1;
530 shift = find_last_bit(&nodes, 8);
531 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
532 topo.node_id;
533 }
534 *edx = 0;
535 }
536
537 /*
538 * Definitions of the hardcoded cache entries we expose:
539 * These are legacy cache values. If there is a need to change any
540 * of these values please use builtin_x86_defs
541 */
542
543 /* L1 data cache: */
544 static CPUCacheInfo legacy_l1d_cache = {
545 .type = DATA_CACHE,
546 .level = 1,
547 .size = 32 * KiB,
548 .self_init = 1,
549 .line_size = 64,
550 .associativity = 8,
551 .sets = 64,
552 .partitions = 1,
553 .no_invd_sharing = true,
554 };
555
556 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
557 static CPUCacheInfo legacy_l1d_cache_amd = {
558 .type = DATA_CACHE,
559 .level = 1,
560 .size = 64 * KiB,
561 .self_init = 1,
562 .line_size = 64,
563 .associativity = 2,
564 .sets = 512,
565 .partitions = 1,
566 .lines_per_tag = 1,
567 .no_invd_sharing = true,
568 };
569
570 /* L1 instruction cache: */
571 static CPUCacheInfo legacy_l1i_cache = {
572 .type = INSTRUCTION_CACHE,
573 .level = 1,
574 .size = 32 * KiB,
575 .self_init = 1,
576 .line_size = 64,
577 .associativity = 8,
578 .sets = 64,
579 .partitions = 1,
580 .no_invd_sharing = true,
581 };
582
583 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
584 static CPUCacheInfo legacy_l1i_cache_amd = {
585 .type = INSTRUCTION_CACHE,
586 .level = 1,
587 .size = 64 * KiB,
588 .self_init = 1,
589 .line_size = 64,
590 .associativity = 2,
591 .sets = 512,
592 .partitions = 1,
593 .lines_per_tag = 1,
594 .no_invd_sharing = true,
595 };
596
597 /* Level 2 unified cache: */
598 static CPUCacheInfo legacy_l2_cache = {
599 .type = UNIFIED_CACHE,
600 .level = 2,
601 .size = 4 * MiB,
602 .self_init = 1,
603 .line_size = 64,
604 .associativity = 16,
605 .sets = 4096,
606 .partitions = 1,
607 .no_invd_sharing = true,
608 };
609
610 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
611 static CPUCacheInfo legacy_l2_cache_cpuid2 = {
612 .type = UNIFIED_CACHE,
613 .level = 2,
614 .size = 2 * MiB,
615 .line_size = 64,
616 .associativity = 8,
617 };
618
619
620 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
621 static CPUCacheInfo legacy_l2_cache_amd = {
622 .type = UNIFIED_CACHE,
623 .level = 2,
624 .size = 512 * KiB,
625 .line_size = 64,
626 .lines_per_tag = 1,
627 .associativity = 16,
628 .sets = 512,
629 .partitions = 1,
630 };
631
632 /* Level 3 unified cache: */
633 static CPUCacheInfo legacy_l3_cache = {
634 .type = UNIFIED_CACHE,
635 .level = 3,
636 .size = 16 * MiB,
637 .line_size = 64,
638 .associativity = 16,
639 .sets = 16384,
640 .partitions = 1,
641 .lines_per_tag = 1,
642 .self_init = true,
643 .inclusive = true,
644 .complex_indexing = true,
645 };
646
647 /* TLB definitions: */
648
649 #define L1_DTLB_2M_ASSOC 1
650 #define L1_DTLB_2M_ENTRIES 255
651 #define L1_DTLB_4K_ASSOC 1
652 #define L1_DTLB_4K_ENTRIES 255
653
654 #define L1_ITLB_2M_ASSOC 1
655 #define L1_ITLB_2M_ENTRIES 255
656 #define L1_ITLB_4K_ASSOC 1
657 #define L1_ITLB_4K_ENTRIES 255
658
659 #define L2_DTLB_2M_ASSOC 0 /* disabled */
660 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
661 #define L2_DTLB_4K_ASSOC 4
662 #define L2_DTLB_4K_ENTRIES 512
663
664 #define L2_ITLB_2M_ASSOC 0 /* disabled */
665 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
666 #define L2_ITLB_4K_ASSOC 4
667 #define L2_ITLB_4K_ENTRIES 512
668
669 /* CPUID Leaf 0x14 constants: */
670 #define INTEL_PT_MAX_SUBLEAF 0x1
671 /*
672 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
673 * MSR can be accessed;
674 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
675 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
676 * of Intel PT MSRs across warm reset;
677 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
678 */
679 #define INTEL_PT_MINIMAL_EBX 0xf
680 /*
681 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
682 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
683 * accessed;
684 * bit[01]: ToPA tables can hold any number of output entries, up to the
685 * maximum allowed by the MaskOrTableOffset field of
686 * IA32_RTIT_OUTPUT_MASK_PTRS;
687 * bit[02]: Support Single-Range Output scheme;
688 */
689 #define INTEL_PT_MINIMAL_ECX 0x7
690 /* generated packets which contain IP payloads have LIP values */
691 #define INTEL_PT_IP_LIP (1 << 31)
692 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
693 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
694 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
695 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
696 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
697
698 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
699 uint32_t vendor2, uint32_t vendor3)
700 {
701 int i;
702 for (i = 0; i < 4; i++) {
703 dst[i] = vendor1 >> (8 * i);
704 dst[i + 4] = vendor2 >> (8 * i);
705 dst[i + 8] = vendor3 >> (8 * i);
706 }
707 dst[CPUID_VENDOR_SZ] = '\0';
708 }
709
710 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
711 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
712 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
713 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
714 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
715 CPUID_PSE36 | CPUID_FXSR)
716 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
717 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
718 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
719 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
720 CPUID_PAE | CPUID_SEP | CPUID_APIC)
721
722 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
723 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
724 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
725 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
726 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
727 /* partly implemented:
728 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
729 /* missing:
730 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
731 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
732 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
733 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
734 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
735 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
736 CPUID_EXT_RDRAND)
737 /* missing:
738 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
739 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
740 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
741 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
742 CPUID_EXT_F16C */
743
744 #ifdef TARGET_X86_64
745 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
746 #else
747 #define TCG_EXT2_X86_64_FEATURES 0
748 #endif
749
750 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
751 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
752 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
753 TCG_EXT2_X86_64_FEATURES)
754 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
755 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
756 #define TCG_EXT4_FEATURES 0
757 #define TCG_SVM_FEATURES CPUID_SVM_NPT
758 #define TCG_KVM_FEATURES 0
759 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
760 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
761 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
762 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
763 CPUID_7_0_EBX_ERMS)
764 /* missing:
765 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
766 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
767 CPUID_7_0_EBX_RDSEED */
768 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
769 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
770 CPUID_7_0_ECX_LA57)
771 #define TCG_7_0_EDX_FEATURES 0
772 #define TCG_APM_FEATURES 0
773 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
774 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
775 /* missing:
776 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
777
778 typedef enum FeatureWordType {
779 CPUID_FEATURE_WORD,
780 MSR_FEATURE_WORD,
781 } FeatureWordType;
782
783 typedef struct FeatureWordInfo {
784 FeatureWordType type;
785 /* feature flags names are taken from "Intel Processor Identification and
786 * the CPUID Instruction" and AMD's "CPUID Specification".
787 * In cases of disagreement between feature naming conventions,
788 * aliases may be added.
789 */
790 const char *feat_names[32];
791 union {
792 /* If type==CPUID_FEATURE_WORD */
793 struct {
794 uint32_t eax; /* Input EAX for CPUID */
795 bool needs_ecx; /* CPUID instruction uses ECX as input */
796 uint32_t ecx; /* Input ECX value for CPUID */
797 int reg; /* output register (R_* constant) */
798 } cpuid;
799 /* If type==MSR_FEATURE_WORD */
800 struct {
801 uint32_t index;
802 struct { /*CPUID that enumerate this MSR*/
803 FeatureWord cpuid_class;
804 uint32_t cpuid_flag;
805 } cpuid_dep;
806 } msr;
807 };
808 uint32_t tcg_features; /* Feature flags supported by TCG */
809 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
810 uint32_t migratable_flags; /* Feature flags known to be migratable */
811 /* Features that shouldn't be auto-enabled by "-cpu host" */
812 uint32_t no_autoenable_flags;
813 } FeatureWordInfo;
814
815 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
816 [FEAT_1_EDX] = {
817 .type = CPUID_FEATURE_WORD,
818 .feat_names = {
819 "fpu", "vme", "de", "pse",
820 "tsc", "msr", "pae", "mce",
821 "cx8", "apic", NULL, "sep",
822 "mtrr", "pge", "mca", "cmov",
823 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
824 NULL, "ds" /* Intel dts */, "acpi", "mmx",
825 "fxsr", "sse", "sse2", "ss",
826 "ht" /* Intel htt */, "tm", "ia64", "pbe",
827 },
828 .cpuid = {.eax = 1, .reg = R_EDX, },
829 .tcg_features = TCG_FEATURES,
830 },
831 [FEAT_1_ECX] = {
832 .type = CPUID_FEATURE_WORD,
833 .feat_names = {
834 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
835 "ds-cpl", "vmx", "smx", "est",
836 "tm2", "ssse3", "cid", NULL,
837 "fma", "cx16", "xtpr", "pdcm",
838 NULL, "pcid", "dca", "sse4.1",
839 "sse4.2", "x2apic", "movbe", "popcnt",
840 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
841 "avx", "f16c", "rdrand", "hypervisor",
842 },
843 .cpuid = { .eax = 1, .reg = R_ECX, },
844 .tcg_features = TCG_EXT_FEATURES,
845 },
846 /* Feature names that are already defined on feature_name[] but
847 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
848 * names on feat_names below. They are copied automatically
849 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
850 */
851 [FEAT_8000_0001_EDX] = {
852 .type = CPUID_FEATURE_WORD,
853 .feat_names = {
854 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
855 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
856 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
857 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
858 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
859 "nx", NULL, "mmxext", NULL /* mmx */,
860 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
861 NULL, "lm", "3dnowext", "3dnow",
862 },
863 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
864 .tcg_features = TCG_EXT2_FEATURES,
865 },
866 [FEAT_8000_0001_ECX] = {
867 .type = CPUID_FEATURE_WORD,
868 .feat_names = {
869 "lahf-lm", "cmp-legacy", "svm", "extapic",
870 "cr8legacy", "abm", "sse4a", "misalignsse",
871 "3dnowprefetch", "osvw", "ibs", "xop",
872 "skinit", "wdt", NULL, "lwp",
873 "fma4", "tce", NULL, "nodeid-msr",
874 NULL, "tbm", "topoext", "perfctr-core",
875 "perfctr-nb", NULL, NULL, NULL,
876 NULL, NULL, NULL, NULL,
877 },
878 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
879 .tcg_features = TCG_EXT3_FEATURES,
880 /*
881 * TOPOEXT is always allowed but can't be enabled blindly by
882 * "-cpu host", as it requires consistent cache topology info
883 * to be provided so it doesn't confuse guests.
884 */
885 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
886 },
887 [FEAT_C000_0001_EDX] = {
888 .type = CPUID_FEATURE_WORD,
889 .feat_names = {
890 NULL, NULL, "xstore", "xstore-en",
891 NULL, NULL, "xcrypt", "xcrypt-en",
892 "ace2", "ace2-en", "phe", "phe-en",
893 "pmm", "pmm-en", NULL, NULL,
894 NULL, NULL, NULL, NULL,
895 NULL, NULL, NULL, NULL,
896 NULL, NULL, NULL, NULL,
897 NULL, NULL, NULL, NULL,
898 },
899 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
900 .tcg_features = TCG_EXT4_FEATURES,
901 },
902 [FEAT_KVM] = {
903 .type = CPUID_FEATURE_WORD,
904 .feat_names = {
905 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
906 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
907 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
908 NULL, NULL, NULL, NULL,
909 NULL, NULL, NULL, NULL,
910 NULL, NULL, NULL, NULL,
911 "kvmclock-stable-bit", NULL, NULL, NULL,
912 NULL, NULL, NULL, NULL,
913 },
914 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
915 .tcg_features = TCG_KVM_FEATURES,
916 },
917 [FEAT_KVM_HINTS] = {
918 .type = CPUID_FEATURE_WORD,
919 .feat_names = {
920 "kvm-hint-dedicated", NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 NULL, NULL, NULL, NULL,
924 NULL, NULL, NULL, NULL,
925 NULL, NULL, NULL, NULL,
926 NULL, NULL, NULL, NULL,
927 NULL, NULL, NULL, NULL,
928 },
929 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
930 .tcg_features = TCG_KVM_FEATURES,
931 /*
932 * KVM hints aren't auto-enabled by -cpu host, they need to be
933 * explicitly enabled in the command-line.
934 */
935 .no_autoenable_flags = ~0U,
936 },
937 /*
938 * .feat_names are commented out for Hyper-V enlightenments because we
939 * don't want to have two different ways for enabling them on QEMU command
940 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
941 * enabling several feature bits simultaneously, exposing these bits
942 * individually may just confuse guests.
943 */
944 [FEAT_HYPERV_EAX] = {
945 .type = CPUID_FEATURE_WORD,
946 .feat_names = {
947 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
948 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
949 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
950 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
951 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
952 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
953 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
954 NULL, NULL,
955 NULL, NULL, NULL, NULL,
956 NULL, NULL, NULL, NULL,
957 NULL, NULL, NULL, NULL,
958 NULL, NULL, NULL, NULL,
959 },
960 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
961 },
962 [FEAT_HYPERV_EBX] = {
963 .type = CPUID_FEATURE_WORD,
964 .feat_names = {
965 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
966 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
967 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
968 NULL /* hv_create_port */, NULL /* hv_connect_port */,
969 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
970 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
971 NULL, NULL,
972 NULL, NULL, NULL, NULL,
973 NULL, NULL, NULL, NULL,
974 NULL, NULL, NULL, NULL,
975 NULL, NULL, NULL, NULL,
976 },
977 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
978 },
979 [FEAT_HYPERV_EDX] = {
980 .type = CPUID_FEATURE_WORD,
981 .feat_names = {
982 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
983 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
984 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
985 NULL, NULL,
986 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
987 NULL, NULL, NULL, NULL,
988 NULL, NULL, NULL, NULL,
989 NULL, NULL, NULL, NULL,
990 NULL, NULL, NULL, NULL,
991 NULL, NULL, NULL, NULL,
992 },
993 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
994 },
995 [FEAT_HV_RECOMM_EAX] = {
996 .type = CPUID_FEATURE_WORD,
997 .feat_names = {
998 NULL /* hv_recommend_pv_as_switch */,
999 NULL /* hv_recommend_pv_tlbflush_local */,
1000 NULL /* hv_recommend_pv_tlbflush_remote */,
1001 NULL /* hv_recommend_msr_apic_access */,
1002 NULL /* hv_recommend_msr_reset */,
1003 NULL /* hv_recommend_relaxed_timing */,
1004 NULL /* hv_recommend_dma_remapping */,
1005 NULL /* hv_recommend_int_remapping */,
1006 NULL /* hv_recommend_x2apic_msrs */,
1007 NULL /* hv_recommend_autoeoi_deprecation */,
1008 NULL /* hv_recommend_pv_ipi */,
1009 NULL /* hv_recommend_ex_hypercalls */,
1010 NULL /* hv_hypervisor_is_nested */,
1011 NULL /* hv_recommend_int_mbec */,
1012 NULL /* hv_recommend_evmcs */,
1013 NULL,
1014 NULL, NULL, NULL, NULL,
1015 NULL, NULL, NULL, NULL,
1016 NULL, NULL, NULL, NULL,
1017 NULL, NULL, NULL, NULL,
1018 },
1019 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
1020 },
1021 [FEAT_HV_NESTED_EAX] = {
1022 .type = CPUID_FEATURE_WORD,
1023 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
1024 },
1025 [FEAT_SVM] = {
1026 .type = CPUID_FEATURE_WORD,
1027 .feat_names = {
1028 "npt", "lbrv", "svm-lock", "nrip-save",
1029 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1030 NULL, NULL, "pause-filter", NULL,
1031 "pfthreshold", NULL, NULL, NULL,
1032 NULL, NULL, NULL, NULL,
1033 NULL, NULL, NULL, NULL,
1034 NULL, NULL, NULL, NULL,
1035 NULL, NULL, NULL, NULL,
1036 },
1037 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
1038 .tcg_features = TCG_SVM_FEATURES,
1039 },
1040 [FEAT_7_0_EBX] = {
1041 .type = CPUID_FEATURE_WORD,
1042 .feat_names = {
1043 "fsgsbase", "tsc-adjust", NULL, "bmi1",
1044 "hle", "avx2", NULL, "smep",
1045 "bmi2", "erms", "invpcid", "rtm",
1046 NULL, NULL, "mpx", NULL,
1047 "avx512f", "avx512dq", "rdseed", "adx",
1048 "smap", "avx512ifma", "pcommit", "clflushopt",
1049 "clwb", "intel-pt", "avx512pf", "avx512er",
1050 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
1051 },
1052 .cpuid = {
1053 .eax = 7,
1054 .needs_ecx = true, .ecx = 0,
1055 .reg = R_EBX,
1056 },
1057 .tcg_features = TCG_7_0_EBX_FEATURES,
1058 },
1059 [FEAT_7_0_ECX] = {
1060 .type = CPUID_FEATURE_WORD,
1061 .feat_names = {
1062 NULL, "avx512vbmi", "umip", "pku",
1063 NULL /* ospke */, NULL, "avx512vbmi2", NULL,
1064 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1065 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
1066 "la57", NULL, NULL, NULL,
1067 NULL, NULL, "rdpid", NULL,
1068 NULL, "cldemote", NULL, "movdiri",
1069 "movdir64b", NULL, NULL, NULL,
1070 },
1071 .cpuid = {
1072 .eax = 7,
1073 .needs_ecx = true, .ecx = 0,
1074 .reg = R_ECX,
1075 },
1076 .tcg_features = TCG_7_0_ECX_FEATURES,
1077 },
1078 [FEAT_7_0_EDX] = {
1079 .type = CPUID_FEATURE_WORD,
1080 .feat_names = {
1081 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1082 NULL, NULL, NULL, NULL,
1083 NULL, NULL, "md-clear", NULL,
1084 NULL, NULL, NULL, NULL,
1085 NULL, NULL, NULL, NULL,
1086 NULL, NULL, NULL, NULL,
1087 NULL, NULL, "spec-ctrl", "stibp",
1088 NULL, "arch-capabilities", "core-capability", "ssbd",
1089 },
1090 .cpuid = {
1091 .eax = 7,
1092 .needs_ecx = true, .ecx = 0,
1093 .reg = R_EDX,
1094 },
1095 .tcg_features = TCG_7_0_EDX_FEATURES,
1096 },
1097 [FEAT_8000_0007_EDX] = {
1098 .type = CPUID_FEATURE_WORD,
1099 .feat_names = {
1100 NULL, NULL, NULL, NULL,
1101 NULL, NULL, NULL, NULL,
1102 "invtsc", NULL, NULL, NULL,
1103 NULL, NULL, NULL, NULL,
1104 NULL, NULL, NULL, NULL,
1105 NULL, NULL, NULL, NULL,
1106 NULL, NULL, NULL, NULL,
1107 NULL, NULL, NULL, NULL,
1108 },
1109 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
1110 .tcg_features = TCG_APM_FEATURES,
1111 .unmigratable_flags = CPUID_APM_INVTSC,
1112 },
1113 [FEAT_8000_0008_EBX] = {
1114 .type = CPUID_FEATURE_WORD,
1115 .feat_names = {
1116 NULL, NULL, NULL, NULL,
1117 NULL, NULL, NULL, NULL,
1118 NULL, "wbnoinvd", NULL, NULL,
1119 "ibpb", NULL, NULL, NULL,
1120 NULL, NULL, NULL, NULL,
1121 NULL, NULL, NULL, NULL,
1122 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1123 NULL, NULL, NULL, NULL,
1124 },
1125 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1126 .tcg_features = 0,
1127 .unmigratable_flags = 0,
1128 },
1129 [FEAT_XSAVE] = {
1130 .type = CPUID_FEATURE_WORD,
1131 .feat_names = {
1132 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1133 NULL, NULL, NULL, NULL,
1134 NULL, NULL, NULL, NULL,
1135 NULL, NULL, NULL, NULL,
1136 NULL, NULL, NULL, NULL,
1137 NULL, NULL, NULL, NULL,
1138 NULL, NULL, NULL, NULL,
1139 NULL, NULL, NULL, NULL,
1140 },
1141 .cpuid = {
1142 .eax = 0xd,
1143 .needs_ecx = true, .ecx = 1,
1144 .reg = R_EAX,
1145 },
1146 .tcg_features = TCG_XSAVE_FEATURES,
1147 },
1148 [FEAT_6_EAX] = {
1149 .type = CPUID_FEATURE_WORD,
1150 .feat_names = {
1151 NULL, NULL, "arat", NULL,
1152 NULL, NULL, NULL, NULL,
1153 NULL, NULL, NULL, NULL,
1154 NULL, NULL, NULL, NULL,
1155 NULL, NULL, NULL, NULL,
1156 NULL, NULL, NULL, NULL,
1157 NULL, NULL, NULL, NULL,
1158 NULL, NULL, NULL, NULL,
1159 },
1160 .cpuid = { .eax = 6, .reg = R_EAX, },
1161 .tcg_features = TCG_6_EAX_FEATURES,
1162 },
1163 [FEAT_XSAVE_COMP_LO] = {
1164 .type = CPUID_FEATURE_WORD,
1165 .cpuid = {
1166 .eax = 0xD,
1167 .needs_ecx = true, .ecx = 0,
1168 .reg = R_EAX,
1169 },
1170 .tcg_features = ~0U,
1171 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1172 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1173 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1174 XSTATE_PKRU_MASK,
1175 },
1176 [FEAT_XSAVE_COMP_HI] = {
1177 .type = CPUID_FEATURE_WORD,
1178 .cpuid = {
1179 .eax = 0xD,
1180 .needs_ecx = true, .ecx = 0,
1181 .reg = R_EDX,
1182 },
1183 .tcg_features = ~0U,
1184 },
1185 /*Below are MSR exposed features*/
1186 [FEAT_ARCH_CAPABILITIES] = {
1187 .type = MSR_FEATURE_WORD,
1188 .feat_names = {
1189 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1190 "ssb-no", "mds-no", NULL, NULL,
1191 NULL, NULL, NULL, NULL,
1192 NULL, NULL, NULL, NULL,
1193 NULL, NULL, NULL, NULL,
1194 NULL, NULL, NULL, NULL,
1195 NULL, NULL, NULL, NULL,
1196 NULL, NULL, NULL, NULL,
1197 },
1198 .msr = {
1199 .index = MSR_IA32_ARCH_CAPABILITIES,
1200 .cpuid_dep = {
1201 FEAT_7_0_EDX,
1202 CPUID_7_0_EDX_ARCH_CAPABILITIES
1203 }
1204 },
1205 },
1206 [FEAT_CORE_CAPABILITY] = {
1207 .type = MSR_FEATURE_WORD,
1208 .feat_names = {
1209 NULL, NULL, NULL, NULL,
1210 NULL, "split-lock-detect", NULL, NULL,
1211 NULL, NULL, NULL, NULL,
1212 NULL, NULL, NULL, NULL,
1213 NULL, NULL, NULL, NULL,
1214 NULL, NULL, NULL, NULL,
1215 NULL, NULL, NULL, NULL,
1216 NULL, NULL, NULL, NULL,
1217 },
1218 .msr = {
1219 .index = MSR_IA32_CORE_CAPABILITY,
1220 .cpuid_dep = {
1221 FEAT_7_0_EDX,
1222 CPUID_7_0_EDX_CORE_CAPABILITY,
1223 },
1224 },
1225 },
1226 };
1227
1228 typedef struct X86RegisterInfo32 {
1229 /* Name of register */
1230 const char *name;
1231 /* QAPI enum value register */
1232 X86CPURegister32 qapi_enum;
1233 } X86RegisterInfo32;
1234
1235 #define REGISTER(reg) \
1236 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1237 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
1238 REGISTER(EAX),
1239 REGISTER(ECX),
1240 REGISTER(EDX),
1241 REGISTER(EBX),
1242 REGISTER(ESP),
1243 REGISTER(EBP),
1244 REGISTER(ESI),
1245 REGISTER(EDI),
1246 };
1247 #undef REGISTER
1248
1249 typedef struct ExtSaveArea {
1250 uint32_t feature, bits;
1251 uint32_t offset, size;
1252 } ExtSaveArea;
1253
1254 static const ExtSaveArea x86_ext_save_areas[] = {
1255 [XSTATE_FP_BIT] = {
1256 /* x87 FP state component is always enabled if XSAVE is supported */
1257 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1258 /* x87 state is in the legacy region of the XSAVE area */
1259 .offset = 0,
1260 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1261 },
1262 [XSTATE_SSE_BIT] = {
1263 /* SSE state component is always enabled if XSAVE is supported */
1264 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1265 /* SSE state is in the legacy region of the XSAVE area */
1266 .offset = 0,
1267 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1268 },
1269 [XSTATE_YMM_BIT] =
1270 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
1271 .offset = offsetof(X86XSaveArea, avx_state),
1272 .size = sizeof(XSaveAVX) },
1273 [XSTATE_BNDREGS_BIT] =
1274 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1275 .offset = offsetof(X86XSaveArea, bndreg_state),
1276 .size = sizeof(XSaveBNDREG) },
1277 [XSTATE_BNDCSR_BIT] =
1278 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1279 .offset = offsetof(X86XSaveArea, bndcsr_state),
1280 .size = sizeof(XSaveBNDCSR) },
1281 [XSTATE_OPMASK_BIT] =
1282 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1283 .offset = offsetof(X86XSaveArea, opmask_state),
1284 .size = sizeof(XSaveOpmask) },
1285 [XSTATE_ZMM_Hi256_BIT] =
1286 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1287 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1288 .size = sizeof(XSaveZMM_Hi256) },
1289 [XSTATE_Hi16_ZMM_BIT] =
1290 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1291 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1292 .size = sizeof(XSaveHi16_ZMM) },
1293 [XSTATE_PKRU_BIT] =
1294 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
1295 .offset = offsetof(X86XSaveArea, pkru_state),
1296 .size = sizeof(XSavePKRU) },
1297 };
1298
1299 static uint32_t xsave_area_size(uint64_t mask)
1300 {
1301 int i;
1302 uint64_t ret = 0;
1303
1304 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1305 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1306 if ((mask >> i) & 1) {
1307 ret = MAX(ret, esa->offset + esa->size);
1308 }
1309 }
1310 return ret;
1311 }
1312
1313 static inline bool accel_uses_host_cpuid(void)
1314 {
1315 return kvm_enabled() || hvf_enabled();
1316 }
1317
1318 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1319 {
1320 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1321 cpu->env.features[FEAT_XSAVE_COMP_LO];
1322 }
1323
1324 const char *get_register_name_32(unsigned int reg)
1325 {
1326 if (reg >= CPU_NB_REGS32) {
1327 return NULL;
1328 }
1329 return x86_reg_info_32[reg].name;
1330 }
1331
1332 /*
1333 * Returns the set of feature flags that are supported and migratable by
1334 * QEMU, for a given FeatureWord.
1335 */
1336 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
1337 {
1338 FeatureWordInfo *wi = &feature_word_info[w];
1339 uint32_t r = 0;
1340 int i;
1341
1342 for (i = 0; i < 32; i++) {
1343 uint32_t f = 1U << i;
1344
1345 /* If the feature name is known, it is implicitly considered migratable,
1346 * unless it is explicitly set in unmigratable_flags */
1347 if ((wi->migratable_flags & f) ||
1348 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1349 r |= f;
1350 }
1351 }
1352 return r;
1353 }
1354
1355 void host_cpuid(uint32_t function, uint32_t count,
1356 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
1357 {
1358 uint32_t vec[4];
1359
1360 #ifdef __x86_64__
1361 asm volatile("cpuid"
1362 : "=a"(vec[0]), "=b"(vec[1]),
1363 "=c"(vec[2]), "=d"(vec[3])
1364 : "0"(function), "c"(count) : "cc");
1365 #elif defined(__i386__)
1366 asm volatile("pusha \n\t"
1367 "cpuid \n\t"
1368 "mov %%eax, 0(%2) \n\t"
1369 "mov %%ebx, 4(%2) \n\t"
1370 "mov %%ecx, 8(%2) \n\t"
1371 "mov %%edx, 12(%2) \n\t"
1372 "popa"
1373 : : "a"(function), "c"(count), "S"(vec)
1374 : "memory", "cc");
1375 #else
1376 abort();
1377 #endif
1378
1379 if (eax)
1380 *eax = vec[0];
1381 if (ebx)
1382 *ebx = vec[1];
1383 if (ecx)
1384 *ecx = vec[2];
1385 if (edx)
1386 *edx = vec[3];
1387 }
1388
1389 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1390 {
1391 uint32_t eax, ebx, ecx, edx;
1392
1393 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1394 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1395
1396 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1397 if (family) {
1398 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1399 }
1400 if (model) {
1401 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1402 }
1403 if (stepping) {
1404 *stepping = eax & 0x0F;
1405 }
1406 }
1407
1408 /* CPU class name definitions: */
1409
1410 /* Return type name for a given CPU model name
1411 * Caller is responsible for freeing the returned string.
1412 */
1413 static char *x86_cpu_type_name(const char *model_name)
1414 {
1415 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1416 }
1417
1418 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1419 {
1420 ObjectClass *oc;
1421 char *typename = x86_cpu_type_name(cpu_model);
1422 oc = object_class_by_name(typename);
1423 g_free(typename);
1424 return oc;
1425 }
1426
1427 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1428 {
1429 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1430 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1431 return g_strndup(class_name,
1432 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1433 }
1434
1435 struct X86CPUDefinition {
1436 const char *name;
1437 uint32_t level;
1438 uint32_t xlevel;
1439 /* vendor is zero-terminated, 12 character ASCII string */
1440 char vendor[CPUID_VENDOR_SZ + 1];
1441 int family;
1442 int model;
1443 int stepping;
1444 FeatureWordArray features;
1445 const char *model_id;
1446 CPUCaches *cache_info;
1447 };
1448
1449 static CPUCaches epyc_cache_info = {
1450 .l1d_cache = &(CPUCacheInfo) {
1451 .type = DATA_CACHE,
1452 .level = 1,
1453 .size = 32 * KiB,
1454 .line_size = 64,
1455 .associativity = 8,
1456 .partitions = 1,
1457 .sets = 64,
1458 .lines_per_tag = 1,
1459 .self_init = 1,
1460 .no_invd_sharing = true,
1461 },
1462 .l1i_cache = &(CPUCacheInfo) {
1463 .type = INSTRUCTION_CACHE,
1464 .level = 1,
1465 .size = 64 * KiB,
1466 .line_size = 64,
1467 .associativity = 4,
1468 .partitions = 1,
1469 .sets = 256,
1470 .lines_per_tag = 1,
1471 .self_init = 1,
1472 .no_invd_sharing = true,
1473 },
1474 .l2_cache = &(CPUCacheInfo) {
1475 .type = UNIFIED_CACHE,
1476 .level = 2,
1477 .size = 512 * KiB,
1478 .line_size = 64,
1479 .associativity = 8,
1480 .partitions = 1,
1481 .sets = 1024,
1482 .lines_per_tag = 1,
1483 },
1484 .l3_cache = &(CPUCacheInfo) {
1485 .type = UNIFIED_CACHE,
1486 .level = 3,
1487 .size = 8 * MiB,
1488 .line_size = 64,
1489 .associativity = 16,
1490 .partitions = 1,
1491 .sets = 8192,
1492 .lines_per_tag = 1,
1493 .self_init = true,
1494 .inclusive = true,
1495 .complex_indexing = true,
1496 },
1497 };
1498
1499 static X86CPUDefinition builtin_x86_defs[] = {
1500 {
1501 .name = "qemu64",
1502 .level = 0xd,
1503 .vendor = CPUID_VENDOR_AMD,
1504 .family = 6,
1505 .model = 6,
1506 .stepping = 3,
1507 .features[FEAT_1_EDX] =
1508 PPRO_FEATURES |
1509 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1510 CPUID_PSE36,
1511 .features[FEAT_1_ECX] =
1512 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1513 .features[FEAT_8000_0001_EDX] =
1514 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1515 .features[FEAT_8000_0001_ECX] =
1516 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
1517 .xlevel = 0x8000000A,
1518 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1519 },
1520 {
1521 .name = "phenom",
1522 .level = 5,
1523 .vendor = CPUID_VENDOR_AMD,
1524 .family = 16,
1525 .model = 2,
1526 .stepping = 3,
1527 /* Missing: CPUID_HT */
1528 .features[FEAT_1_EDX] =
1529 PPRO_FEATURES |
1530 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1531 CPUID_PSE36 | CPUID_VME,
1532 .features[FEAT_1_ECX] =
1533 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
1534 CPUID_EXT_POPCNT,
1535 .features[FEAT_8000_0001_EDX] =
1536 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1537 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
1538 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
1539 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1540 CPUID_EXT3_CR8LEG,
1541 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1542 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1543 .features[FEAT_8000_0001_ECX] =
1544 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
1545 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
1546 /* Missing: CPUID_SVM_LBRV */
1547 .features[FEAT_SVM] =
1548 CPUID_SVM_NPT,
1549 .xlevel = 0x8000001A,
1550 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1551 },
1552 {
1553 .name = "core2duo",
1554 .level = 10,
1555 .vendor = CPUID_VENDOR_INTEL,
1556 .family = 6,
1557 .model = 15,
1558 .stepping = 11,
1559 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1560 .features[FEAT_1_EDX] =
1561 PPRO_FEATURES |
1562 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1563 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1564 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1565 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1566 .features[FEAT_1_ECX] =
1567 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1568 CPUID_EXT_CX16,
1569 .features[FEAT_8000_0001_EDX] =
1570 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1571 .features[FEAT_8000_0001_ECX] =
1572 CPUID_EXT3_LAHF_LM,
1573 .xlevel = 0x80000008,
1574 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1575 },
1576 {
1577 .name = "kvm64",
1578 .level = 0xd,
1579 .vendor = CPUID_VENDOR_INTEL,
1580 .family = 15,
1581 .model = 6,
1582 .stepping = 1,
1583 /* Missing: CPUID_HT */
1584 .features[FEAT_1_EDX] =
1585 PPRO_FEATURES | CPUID_VME |
1586 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1587 CPUID_PSE36,
1588 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
1589 .features[FEAT_1_ECX] =
1590 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1591 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
1592 .features[FEAT_8000_0001_EDX] =
1593 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1594 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1595 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1596 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1597 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
1598 .features[FEAT_8000_0001_ECX] =
1599 0,
1600 .xlevel = 0x80000008,
1601 .model_id = "Common KVM processor"
1602 },
1603 {
1604 .name = "qemu32",
1605 .level = 4,
1606 .vendor = CPUID_VENDOR_INTEL,
1607 .family = 6,
1608 .model = 6,
1609 .stepping = 3,
1610 .features[FEAT_1_EDX] =
1611 PPRO_FEATURES,
1612 .features[FEAT_1_ECX] =
1613 CPUID_EXT_SSE3,
1614 .xlevel = 0x80000004,
1615 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1616 },
1617 {
1618 .name = "kvm32",
1619 .level = 5,
1620 .vendor = CPUID_VENDOR_INTEL,
1621 .family = 15,
1622 .model = 6,
1623 .stepping = 1,
1624 .features[FEAT_1_EDX] =
1625 PPRO_FEATURES | CPUID_VME |
1626 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
1627 .features[FEAT_1_ECX] =
1628 CPUID_EXT_SSE3,
1629 .features[FEAT_8000_0001_ECX] =
1630 0,
1631 .xlevel = 0x80000008,
1632 .model_id = "Common 32-bit KVM processor"
1633 },
1634 {
1635 .name = "coreduo",
1636 .level = 10,
1637 .vendor = CPUID_VENDOR_INTEL,
1638 .family = 6,
1639 .model = 14,
1640 .stepping = 8,
1641 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1642 .features[FEAT_1_EDX] =
1643 PPRO_FEATURES | CPUID_VME |
1644 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1645 CPUID_SS,
1646 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
1647 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
1648 .features[FEAT_1_ECX] =
1649 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
1650 .features[FEAT_8000_0001_EDX] =
1651 CPUID_EXT2_NX,
1652 .xlevel = 0x80000008,
1653 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1654 },
1655 {
1656 .name = "486",
1657 .level = 1,
1658 .vendor = CPUID_VENDOR_INTEL,
1659 .family = 4,
1660 .model = 8,
1661 .stepping = 0,
1662 .features[FEAT_1_EDX] =
1663 I486_FEATURES,
1664 .xlevel = 0,
1665 .model_id = "",
1666 },
1667 {
1668 .name = "pentium",
1669 .level = 1,
1670 .vendor = CPUID_VENDOR_INTEL,
1671 .family = 5,
1672 .model = 4,
1673 .stepping = 3,
1674 .features[FEAT_1_EDX] =
1675 PENTIUM_FEATURES,
1676 .xlevel = 0,
1677 .model_id = "",
1678 },
1679 {
1680 .name = "pentium2",
1681 .level = 2,
1682 .vendor = CPUID_VENDOR_INTEL,
1683 .family = 6,
1684 .model = 5,
1685 .stepping = 2,
1686 .features[FEAT_1_EDX] =
1687 PENTIUM2_FEATURES,
1688 .xlevel = 0,
1689 .model_id = "",
1690 },
1691 {
1692 .name = "pentium3",
1693 .level = 3,
1694 .vendor = CPUID_VENDOR_INTEL,
1695 .family = 6,
1696 .model = 7,
1697 .stepping = 3,
1698 .features[FEAT_1_EDX] =
1699 PENTIUM3_FEATURES,
1700 .xlevel = 0,
1701 .model_id = "",
1702 },
1703 {
1704 .name = "athlon",
1705 .level = 2,
1706 .vendor = CPUID_VENDOR_AMD,
1707 .family = 6,
1708 .model = 2,
1709 .stepping = 3,
1710 .features[FEAT_1_EDX] =
1711 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
1712 CPUID_MCA,
1713 .features[FEAT_8000_0001_EDX] =
1714 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
1715 .xlevel = 0x80000008,
1716 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1717 },
1718 {
1719 .name = "n270",
1720 .level = 10,
1721 .vendor = CPUID_VENDOR_INTEL,
1722 .family = 6,
1723 .model = 28,
1724 .stepping = 2,
1725 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1726 .features[FEAT_1_EDX] =
1727 PPRO_FEATURES |
1728 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1729 CPUID_ACPI | CPUID_SS,
1730 /* Some CPUs got no CPUID_SEP */
1731 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1732 * CPUID_EXT_XTPR */
1733 .features[FEAT_1_ECX] =
1734 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1735 CPUID_EXT_MOVBE,
1736 .features[FEAT_8000_0001_EDX] =
1737 CPUID_EXT2_NX,
1738 .features[FEAT_8000_0001_ECX] =
1739 CPUID_EXT3_LAHF_LM,
1740 .xlevel = 0x80000008,
1741 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1742 },
1743 {
1744 .name = "Conroe",
1745 .level = 10,
1746 .vendor = CPUID_VENDOR_INTEL,
1747 .family = 6,
1748 .model = 15,
1749 .stepping = 3,
1750 .features[FEAT_1_EDX] =
1751 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1752 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1753 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1754 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1755 CPUID_DE | CPUID_FP87,
1756 .features[FEAT_1_ECX] =
1757 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1758 .features[FEAT_8000_0001_EDX] =
1759 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1760 .features[FEAT_8000_0001_ECX] =
1761 CPUID_EXT3_LAHF_LM,
1762 .xlevel = 0x80000008,
1763 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1764 },
1765 {
1766 .name = "Penryn",
1767 .level = 10,
1768 .vendor = CPUID_VENDOR_INTEL,
1769 .family = 6,
1770 .model = 23,
1771 .stepping = 3,
1772 .features[FEAT_1_EDX] =
1773 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1774 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1775 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1776 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1777 CPUID_DE | CPUID_FP87,
1778 .features[FEAT_1_ECX] =
1779 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1780 CPUID_EXT_SSE3,
1781 .features[FEAT_8000_0001_EDX] =
1782 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1783 .features[FEAT_8000_0001_ECX] =
1784 CPUID_EXT3_LAHF_LM,
1785 .xlevel = 0x80000008,
1786 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1787 },
1788 {
1789 .name = "Nehalem",
1790 .level = 11,
1791 .vendor = CPUID_VENDOR_INTEL,
1792 .family = 6,
1793 .model = 26,
1794 .stepping = 3,
1795 .features[FEAT_1_EDX] =
1796 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1797 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1798 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1799 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1800 CPUID_DE | CPUID_FP87,
1801 .features[FEAT_1_ECX] =
1802 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1803 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1804 .features[FEAT_8000_0001_EDX] =
1805 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1806 .features[FEAT_8000_0001_ECX] =
1807 CPUID_EXT3_LAHF_LM,
1808 .xlevel = 0x80000008,
1809 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1810 },
1811 {
1812 .name = "Nehalem-IBRS",
1813 .level = 11,
1814 .vendor = CPUID_VENDOR_INTEL,
1815 .family = 6,
1816 .model = 26,
1817 .stepping = 3,
1818 .features[FEAT_1_EDX] =
1819 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1820 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1821 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1822 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1823 CPUID_DE | CPUID_FP87,
1824 .features[FEAT_1_ECX] =
1825 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1826 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1827 .features[FEAT_7_0_EDX] =
1828 CPUID_7_0_EDX_SPEC_CTRL,
1829 .features[FEAT_8000_0001_EDX] =
1830 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1831 .features[FEAT_8000_0001_ECX] =
1832 CPUID_EXT3_LAHF_LM,
1833 .xlevel = 0x80000008,
1834 .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1835 },
1836 {
1837 .name = "Westmere",
1838 .level = 11,
1839 .vendor = CPUID_VENDOR_INTEL,
1840 .family = 6,
1841 .model = 44,
1842 .stepping = 1,
1843 .features[FEAT_1_EDX] =
1844 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1845 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1846 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1847 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1848 CPUID_DE | CPUID_FP87,
1849 .features[FEAT_1_ECX] =
1850 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1851 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1852 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1853 .features[FEAT_8000_0001_EDX] =
1854 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1855 .features[FEAT_8000_0001_ECX] =
1856 CPUID_EXT3_LAHF_LM,
1857 .features[FEAT_6_EAX] =
1858 CPUID_6_EAX_ARAT,
1859 .xlevel = 0x80000008,
1860 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1861 },
1862 {
1863 .name = "Westmere-IBRS",
1864 .level = 11,
1865 .vendor = CPUID_VENDOR_INTEL,
1866 .family = 6,
1867 .model = 44,
1868 .stepping = 1,
1869 .features[FEAT_1_EDX] =
1870 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1871 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1872 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1873 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1874 CPUID_DE | CPUID_FP87,
1875 .features[FEAT_1_ECX] =
1876 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1877 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1878 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1879 .features[FEAT_8000_0001_EDX] =
1880 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1881 .features[FEAT_8000_0001_ECX] =
1882 CPUID_EXT3_LAHF_LM,
1883 .features[FEAT_7_0_EDX] =
1884 CPUID_7_0_EDX_SPEC_CTRL,
1885 .features[FEAT_6_EAX] =
1886 CPUID_6_EAX_ARAT,
1887 .xlevel = 0x80000008,
1888 .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
1889 },
1890 {
1891 .name = "SandyBridge",
1892 .level = 0xd,
1893 .vendor = CPUID_VENDOR_INTEL,
1894 .family = 6,
1895 .model = 42,
1896 .stepping = 1,
1897 .features[FEAT_1_EDX] =
1898 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1899 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1900 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1901 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1902 CPUID_DE | CPUID_FP87,
1903 .features[FEAT_1_ECX] =
1904 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1905 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1906 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1907 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1908 CPUID_EXT_SSE3,
1909 .features[FEAT_8000_0001_EDX] =
1910 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1911 CPUID_EXT2_SYSCALL,
1912 .features[FEAT_8000_0001_ECX] =
1913 CPUID_EXT3_LAHF_LM,
1914 .features[FEAT_XSAVE] =
1915 CPUID_XSAVE_XSAVEOPT,
1916 .features[FEAT_6_EAX] =
1917 CPUID_6_EAX_ARAT,
1918 .xlevel = 0x80000008,
1919 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1920 },
1921 {
1922 .name = "SandyBridge-IBRS",
1923 .level = 0xd,
1924 .vendor = CPUID_VENDOR_INTEL,
1925 .family = 6,
1926 .model = 42,
1927 .stepping = 1,
1928 .features[FEAT_1_EDX] =
1929 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1930 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1931 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1932 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1933 CPUID_DE | CPUID_FP87,
1934 .features[FEAT_1_ECX] =
1935 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1936 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1937 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1938 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1939 CPUID_EXT_SSE3,
1940 .features[FEAT_8000_0001_EDX] =
1941 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1942 CPUID_EXT2_SYSCALL,
1943 .features[FEAT_8000_0001_ECX] =
1944 CPUID_EXT3_LAHF_LM,
1945 .features[FEAT_7_0_EDX] =
1946 CPUID_7_0_EDX_SPEC_CTRL,
1947 .features[FEAT_XSAVE] =
1948 CPUID_XSAVE_XSAVEOPT,
1949 .features[FEAT_6_EAX] =
1950 CPUID_6_EAX_ARAT,
1951 .xlevel = 0x80000008,
1952 .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1953 },
1954 {
1955 .name = "IvyBridge",
1956 .level = 0xd,
1957 .vendor = CPUID_VENDOR_INTEL,
1958 .family = 6,
1959 .model = 58,
1960 .stepping = 9,
1961 .features[FEAT_1_EDX] =
1962 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1963 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1964 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1965 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1966 CPUID_DE | CPUID_FP87,
1967 .features[FEAT_1_ECX] =
1968 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1969 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1970 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1971 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1972 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1973 .features[FEAT_7_0_EBX] =
1974 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1975 CPUID_7_0_EBX_ERMS,
1976 .features[FEAT_8000_0001_EDX] =
1977 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1978 CPUID_EXT2_SYSCALL,
1979 .features[FEAT_8000_0001_ECX] =
1980 CPUID_EXT3_LAHF_LM,
1981 .features[FEAT_XSAVE] =
1982 CPUID_XSAVE_XSAVEOPT,
1983 .features[FEAT_6_EAX] =
1984 CPUID_6_EAX_ARAT,
1985 .xlevel = 0x80000008,
1986 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1987 },
1988 {
1989 .name = "IvyBridge-IBRS",
1990 .level = 0xd,
1991 .vendor = CPUID_VENDOR_INTEL,
1992 .family = 6,
1993 .model = 58,
1994 .stepping = 9,
1995 .features[FEAT_1_EDX] =
1996 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1997 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1998 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1999 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2000 CPUID_DE | CPUID_FP87,
2001 .features[FEAT_1_ECX] =
2002 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2003 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2004 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2005 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2006 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2007 .features[FEAT_7_0_EBX] =
2008 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2009 CPUID_7_0_EBX_ERMS,
2010 .features[FEAT_8000_0001_EDX] =
2011 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2012 CPUID_EXT2_SYSCALL,
2013 .features[FEAT_8000_0001_ECX] =
2014 CPUID_EXT3_LAHF_LM,
2015 .features[FEAT_7_0_EDX] =
2016 CPUID_7_0_EDX_SPEC_CTRL,
2017 .features[FEAT_XSAVE] =
2018 CPUID_XSAVE_XSAVEOPT,
2019 .features[FEAT_6_EAX] =
2020 CPUID_6_EAX_ARAT,
2021 .xlevel = 0x80000008,
2022 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
2023 },
2024 {
2025 .name = "Haswell-noTSX",
2026 .level = 0xd,
2027 .vendor = CPUID_VENDOR_INTEL,
2028 .family = 6,
2029 .model = 60,
2030 .stepping = 1,
2031 .features[FEAT_1_EDX] =
2032 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2033 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2034 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2035 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2036 CPUID_DE | CPUID_FP87,
2037 .features[FEAT_1_ECX] =
2038 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2039 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2040 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2041 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2042 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2043 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2044 .features[FEAT_8000_0001_EDX] =
2045 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2046 CPUID_EXT2_SYSCALL,
2047 .features[FEAT_8000_0001_ECX] =
2048 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2049 .features[FEAT_7_0_EBX] =
2050 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2051 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2052 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2053 .features[FEAT_XSAVE] =
2054 CPUID_XSAVE_XSAVEOPT,
2055 .features[FEAT_6_EAX] =
2056 CPUID_6_EAX_ARAT,
2057 .xlevel = 0x80000008,
2058 .model_id = "Intel Core Processor (Haswell, no TSX)",
2059 },
2060 {
2061 .name = "Haswell-noTSX-IBRS",
2062 .level = 0xd,
2063 .vendor = CPUID_VENDOR_INTEL,
2064 .family = 6,
2065 .model = 60,
2066 .stepping = 1,
2067 .features[FEAT_1_EDX] =
2068 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2069 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2070 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2071 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2072 CPUID_DE | CPUID_FP87,
2073 .features[FEAT_1_ECX] =
2074 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2075 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2076 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2077 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2078 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2079 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2080 .features[FEAT_8000_0001_EDX] =
2081 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2082 CPUID_EXT2_SYSCALL,
2083 .features[FEAT_8000_0001_ECX] =
2084 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2085 .features[FEAT_7_0_EDX] =
2086 CPUID_7_0_EDX_SPEC_CTRL,
2087 .features[FEAT_7_0_EBX] =
2088 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2089 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2090 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2091 .features[FEAT_XSAVE] =
2092 CPUID_XSAVE_XSAVEOPT,
2093 .features[FEAT_6_EAX] =
2094 CPUID_6_EAX_ARAT,
2095 .xlevel = 0x80000008,
2096 .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
2097 },
2098 {
2099 .name = "Haswell",
2100 .level = 0xd,
2101 .vendor = CPUID_VENDOR_INTEL,
2102 .family = 6,
2103 .model = 60,
2104 .stepping = 4,
2105 .features[FEAT_1_EDX] =
2106 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2107 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2108 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2109 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2110 CPUID_DE | CPUID_FP87,
2111 .features[FEAT_1_ECX] =
2112 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2113 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2114 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2115 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2116 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2117 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2118 .features[FEAT_8000_0001_EDX] =
2119 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2120 CPUID_EXT2_SYSCALL,
2121 .features[FEAT_8000_0001_ECX] =
2122 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2123 .features[FEAT_7_0_EBX] =
2124 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2125 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2126 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2127 CPUID_7_0_EBX_RTM,
2128 .features[FEAT_XSAVE] =
2129 CPUID_XSAVE_XSAVEOPT,
2130 .features[FEAT_6_EAX] =
2131 CPUID_6_EAX_ARAT,
2132 .xlevel = 0x80000008,
2133 .model_id = "Intel Core Processor (Haswell)",
2134 },
2135 {
2136 .name = "Haswell-IBRS",
2137 .level = 0xd,
2138 .vendor = CPUID_VENDOR_INTEL,
2139 .family = 6,
2140 .model = 60,
2141 .stepping = 4,
2142 .features[FEAT_1_EDX] =
2143 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2144 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2145 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2146 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2147 CPUID_DE | CPUID_FP87,
2148 .features[FEAT_1_ECX] =
2149 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2150 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2151 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2152 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2153 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2154 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2155 .features[FEAT_8000_0001_EDX] =
2156 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2157 CPUID_EXT2_SYSCALL,
2158 .features[FEAT_8000_0001_ECX] =
2159 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2160 .features[FEAT_7_0_EDX] =
2161 CPUID_7_0_EDX_SPEC_CTRL,
2162 .features[FEAT_7_0_EBX] =
2163 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2164 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2165 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2166 CPUID_7_0_EBX_RTM,
2167 .features[FEAT_XSAVE] =
2168 CPUID_XSAVE_XSAVEOPT,
2169 .features[FEAT_6_EAX] =
2170 CPUID_6_EAX_ARAT,
2171 .xlevel = 0x80000008,
2172 .model_id = "Intel Core Processor (Haswell, IBRS)",
2173 },
2174 {
2175 .name = "Broadwell-noTSX",
2176 .level = 0xd,
2177 .vendor = CPUID_VENDOR_INTEL,
2178 .family = 6,
2179 .model = 61,
2180 .stepping = 2,
2181 .features[FEAT_1_EDX] =
2182 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2183 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2184 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2185 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2186 CPUID_DE | CPUID_FP87,
2187 .features[FEAT_1_ECX] =
2188 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2189 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2190 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2191 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2192 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2193 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2194 .features[FEAT_8000_0001_EDX] =
2195 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2196 CPUID_EXT2_SYSCALL,
2197 .features[FEAT_8000_0001_ECX] =
2198 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2199 .features[FEAT_7_0_EBX] =
2200 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2201 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2202 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2203 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2204 CPUID_7_0_EBX_SMAP,
2205 .features[FEAT_XSAVE] =
2206 CPUID_XSAVE_XSAVEOPT,
2207 .features[FEAT_6_EAX] =
2208 CPUID_6_EAX_ARAT,
2209 .xlevel = 0x80000008,
2210 .model_id = "Intel Core Processor (Broadwell, no TSX)",
2211 },
2212 {
2213 .name = "Broadwell-noTSX-IBRS",
2214 .level = 0xd,
2215 .vendor = CPUID_VENDOR_INTEL,
2216 .family = 6,
2217 .model = 61,
2218 .stepping = 2,
2219 .features[FEAT_1_EDX] =
2220 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2221 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2222 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2223 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2224 CPUID_DE | CPUID_FP87,
2225 .features[FEAT_1_ECX] =
2226 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2227 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2228 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2229 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2230 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2231 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2232 .features[FEAT_8000_0001_EDX] =
2233 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2234 CPUID_EXT2_SYSCALL,
2235 .features[FEAT_8000_0001_ECX] =
2236 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2237 .features[FEAT_7_0_EDX] =
2238 CPUID_7_0_EDX_SPEC_CTRL,
2239 .features[FEAT_7_0_EBX] =
2240 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2241 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2242 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2243 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2244 CPUID_7_0_EBX_SMAP,
2245 .features[FEAT_XSAVE] =
2246 CPUID_XSAVE_XSAVEOPT,
2247 .features[FEAT_6_EAX] =
2248 CPUID_6_EAX_ARAT,
2249 .xlevel = 0x80000008,
2250 .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
2251 },
2252 {
2253 .name = "Broadwell",
2254 .level = 0xd,
2255 .vendor = CPUID_VENDOR_INTEL,
2256 .family = 6,
2257 .model = 61,
2258 .stepping = 2,
2259 .features[FEAT_1_EDX] =
2260 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2261 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2262 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2263 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2264 CPUID_DE | CPUID_FP87,
2265 .features[FEAT_1_ECX] =
2266 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2267 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2268 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2269 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2270 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2271 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2272 .features[FEAT_8000_0001_EDX] =
2273 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2274 CPUID_EXT2_SYSCALL,
2275 .features[FEAT_8000_0001_ECX] =
2276 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2277 .features[FEAT_7_0_EBX] =
2278 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2279 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2280 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2281 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2282 CPUID_7_0_EBX_SMAP,
2283 .features[FEAT_XSAVE] =
2284 CPUID_XSAVE_XSAVEOPT,
2285 .features[FEAT_6_EAX] =
2286 CPUID_6_EAX_ARAT,
2287 .xlevel = 0x80000008,
2288 .model_id = "Intel Core Processor (Broadwell)",
2289 },
2290 {
2291 .name = "Broadwell-IBRS",
2292 .level = 0xd,
2293 .vendor = CPUID_VENDOR_INTEL,
2294 .family = 6,
2295 .model = 61,
2296 .stepping = 2,
2297 .features[FEAT_1_EDX] =
2298 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2299 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2300 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2301 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2302 CPUID_DE | CPUID_FP87,
2303 .features[FEAT_1_ECX] =
2304 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2305 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2306 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2307 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2308 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2309 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2310 .features[FEAT_8000_0001_EDX] =
2311 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2312 CPUID_EXT2_SYSCALL,
2313 .features[FEAT_8000_0001_ECX] =
2314 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2315 .features[FEAT_7_0_EDX] =
2316 CPUID_7_0_EDX_SPEC_CTRL,
2317 .features[FEAT_7_0_EBX] =
2318 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2319 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2320 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2321 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2322 CPUID_7_0_EBX_SMAP,
2323 .features[FEAT_XSAVE] =
2324 CPUID_XSAVE_XSAVEOPT,
2325 .features[FEAT_6_EAX] =
2326 CPUID_6_EAX_ARAT,
2327 .xlevel = 0x80000008,
2328 .model_id = "Intel Core Processor (Broadwell, IBRS)",
2329 },
2330 {
2331 .name = "Skylake-Client",
2332 .level = 0xd,
2333 .vendor = CPUID_VENDOR_INTEL,
2334 .family = 6,
2335 .model = 94,
2336 .stepping = 3,
2337 .features[FEAT_1_EDX] =
2338 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2339 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2340 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2341 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2342 CPUID_DE | CPUID_FP87,
2343 .features[FEAT_1_ECX] =
2344 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2345 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2346 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2347 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2348 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2349 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2350 .features[FEAT_8000_0001_EDX] =
2351 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2352 CPUID_EXT2_SYSCALL,
2353 .features[FEAT_8000_0001_ECX] =
2354 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2355 .features[FEAT_7_0_EBX] =
2356 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2357 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2358 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2359 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2360 CPUID_7_0_EBX_SMAP,
2361 /* Missing: XSAVES (not supported by some Linux versions,
2362 * including v4.1 to v4.12).
2363 * KVM doesn't yet expose any XSAVES state save component,
2364 * and the only one defined in Skylake (processor tracing)
2365 * probably will block migration anyway.
2366 */
2367 .features[FEAT_XSAVE] =
2368 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2369 CPUID_XSAVE_XGETBV1,
2370 .features[FEAT_6_EAX] =
2371 CPUID_6_EAX_ARAT,
2372 .xlevel = 0x80000008,
2373 .model_id = "Intel Core Processor (Skylake)",
2374 },
2375 {
2376 .name = "Skylake-Client-IBRS",
2377 .level = 0xd,
2378 .vendor = CPUID_VENDOR_INTEL,
2379 .family = 6,
2380 .model = 94,
2381 .stepping = 3,
2382 .features[FEAT_1_EDX] =
2383 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2384 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2385 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2386 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2387 CPUID_DE | CPUID_FP87,
2388 .features[FEAT_1_ECX] =
2389 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2390 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2391 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2392 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2393 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2394 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2395 .features[FEAT_8000_0001_EDX] =
2396 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2397 CPUID_EXT2_SYSCALL,
2398 .features[FEAT_8000_0001_ECX] =
2399 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2400 .features[FEAT_7_0_EDX] =
2401 CPUID_7_0_EDX_SPEC_CTRL,
2402 .features[FEAT_7_0_EBX] =
2403 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2404 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2405 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2406 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2407 CPUID_7_0_EBX_SMAP,
2408 /* Missing: XSAVES (not supported by some Linux versions,
2409 * including v4.1 to v4.12).
2410 * KVM doesn't yet expose any XSAVES state save component,
2411 * and the only one defined in Skylake (processor tracing)
2412 * probably will block migration anyway.
2413 */
2414 .features[FEAT_XSAVE] =
2415 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2416 CPUID_XSAVE_XGETBV1,
2417 .features[FEAT_6_EAX] =
2418 CPUID_6_EAX_ARAT,
2419 .xlevel = 0x80000008,
2420 .model_id = "Intel Core Processor (Skylake, IBRS)",
2421 },
2422 {
2423 .name = "Skylake-Server",
2424 .level = 0xd,
2425 .vendor = CPUID_VENDOR_INTEL,
2426 .family = 6,
2427 .model = 85,
2428 .stepping = 4,
2429 .features[FEAT_1_EDX] =
2430 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2431 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2432 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2433 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2434 CPUID_DE | CPUID_FP87,
2435 .features[FEAT_1_ECX] =
2436 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2437 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2438 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2439 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2440 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2441 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2442 .features[FEAT_8000_0001_EDX] =
2443 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2444 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2445 .features[FEAT_8000_0001_ECX] =
2446 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2447 .features[FEAT_7_0_EBX] =
2448 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2449 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2450 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2451 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2452 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2453 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2454 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2455 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2456 .features[FEAT_7_0_ECX] =
2457 CPUID_7_0_ECX_PKU,
2458 /* Missing: XSAVES (not supported by some Linux versions,
2459 * including v4.1 to v4.12).
2460 * KVM doesn't yet expose any XSAVES state save component,
2461 * and the only one defined in Skylake (processor tracing)
2462 * probably will block migration anyway.
2463 */
2464 .features[FEAT_XSAVE] =
2465 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2466 CPUID_XSAVE_XGETBV1,
2467 .features[FEAT_6_EAX] =
2468 CPUID_6_EAX_ARAT,
2469 .xlevel = 0x80000008,
2470 .model_id = "Intel Xeon Processor (Skylake)",
2471 },
2472 {
2473 .name = "Skylake-Server-IBRS",
2474 .level = 0xd,
2475 .vendor = CPUID_VENDOR_INTEL,
2476 .family = 6,
2477 .model = 85,
2478 .stepping = 4,
2479 .features[FEAT_1_EDX] =
2480 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2481 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2482 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2483 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2484 CPUID_DE | CPUID_FP87,
2485 .features[FEAT_1_ECX] =
2486 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2487 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2488 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2489 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2490 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2491 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2492 .features[FEAT_8000_0001_EDX] =
2493 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2494 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2495 .features[FEAT_8000_0001_ECX] =
2496 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2497 .features[FEAT_7_0_EDX] =
2498 CPUID_7_0_EDX_SPEC_CTRL,
2499 .features[FEAT_7_0_EBX] =
2500 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2501 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2502 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2503 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2504 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2505 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2506 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2507 CPUID_7_0_EBX_AVX512VL,
2508 .features[FEAT_7_0_ECX] =
2509 CPUID_7_0_ECX_PKU,
2510 /* Missing: XSAVES (not supported by some Linux versions,
2511 * including v4.1 to v4.12).
2512 * KVM doesn't yet expose any XSAVES state save component,
2513 * and the only one defined in Skylake (processor tracing)
2514 * probably will block migration anyway.
2515 */
2516 .features[FEAT_XSAVE] =
2517 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2518 CPUID_XSAVE_XGETBV1,
2519 .features[FEAT_6_EAX] =
2520 CPUID_6_EAX_ARAT,
2521 .xlevel = 0x80000008,
2522 .model_id = "Intel Xeon Processor (Skylake, IBRS)",
2523 },
2524 {
2525 .name = "Cascadelake-Server",
2526 .level = 0xd,
2527 .vendor = CPUID_VENDOR_INTEL,
2528 .family = 6,
2529 .model = 85,
2530 .stepping = 6,
2531 .features[FEAT_1_EDX] =
2532 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2533 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2534 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2535 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2536 CPUID_DE | CPUID_FP87,
2537 .features[FEAT_1_ECX] =
2538 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2539 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2540 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2541 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2542 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2543 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2544 .features[FEAT_8000_0001_EDX] =
2545 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2546 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2547 .features[FEAT_8000_0001_ECX] =
2548 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2549 .features[FEAT_7_0_EBX] =
2550 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2551 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2552 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2553 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2554 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2555 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2556 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2557 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2558 .features[FEAT_7_0_ECX] =
2559 CPUID_7_0_ECX_PKU |
2560 CPUID_7_0_ECX_AVX512VNNI,
2561 .features[FEAT_7_0_EDX] =
2562 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2563 /* Missing: XSAVES (not supported by some Linux versions,
2564 * including v4.1 to v4.12).
2565 * KVM doesn't yet expose any XSAVES state save component,
2566 * and the only one defined in Skylake (processor tracing)
2567 * probably will block migration anyway.
2568 */
2569 .features[FEAT_XSAVE] =
2570 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2571 CPUID_XSAVE_XGETBV1,
2572 .features[FEAT_6_EAX] =
2573 CPUID_6_EAX_ARAT,
2574 .xlevel = 0x80000008,
2575 .model_id = "Intel Xeon Processor (Cascadelake)",
2576 },
2577 {
2578 .name = "Icelake-Client",
2579 .level = 0xd,
2580 .vendor = CPUID_VENDOR_INTEL,
2581 .family = 6,
2582 .model = 126,
2583 .stepping = 0,
2584 .features[FEAT_1_EDX] =
2585 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2586 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2587 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2588 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2589 CPUID_DE | CPUID_FP87,
2590 .features[FEAT_1_ECX] =
2591 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2592 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2593 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2594 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2595 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2596 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2597 .features[FEAT_8000_0001_EDX] =
2598 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2599 CPUID_EXT2_SYSCALL,
2600 .features[FEAT_8000_0001_ECX] =
2601 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2602 .features[FEAT_8000_0008_EBX] =
2603 CPUID_8000_0008_EBX_WBNOINVD,
2604 .features[FEAT_7_0_EBX] =
2605 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2606 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2607 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2608 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2609 CPUID_7_0_EBX_SMAP,
2610 .features[FEAT_7_0_ECX] =
2611 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2612 CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2613 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2614 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2615 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2616 .features[FEAT_7_0_EDX] =
2617 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2618 /* Missing: XSAVES (not supported by some Linux versions,
2619 * including v4.1 to v4.12).
2620 * KVM doesn't yet expose any XSAVES state save component,
2621 * and the only one defined in Skylake (processor tracing)
2622 * probably will block migration anyway.
2623 */
2624 .features[FEAT_XSAVE] =
2625 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2626 CPUID_XSAVE_XGETBV1,
2627 .features[FEAT_6_EAX] =
2628 CPUID_6_EAX_ARAT,
2629 .xlevel = 0x80000008,
2630 .model_id = "Intel Core Processor (Icelake)",
2631 },
2632 {
2633 .name = "Icelake-Server",
2634 .level = 0xd,
2635 .vendor = CPUID_VENDOR_INTEL,
2636 .family = 6,
2637 .model = 134,
2638 .stepping = 0,
2639 .features[FEAT_1_EDX] =
2640 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2641 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2642 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2643 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2644 CPUID_DE | CPUID_FP87,
2645 .features[FEAT_1_ECX] =
2646 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2647 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2648 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2649 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2650 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2651 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2652 .features[FEAT_8000_0001_EDX] =
2653 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2654 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2655 .features[FEAT_8000_0001_ECX] =
2656 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2657 .features[FEAT_8000_0008_EBX] =
2658 CPUID_8000_0008_EBX_WBNOINVD,
2659 .features[FEAT_7_0_EBX] =
2660 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2661 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2662 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2663 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2664 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2665 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2666 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2667 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2668 .features[FEAT_7_0_ECX] =
2669 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2670 CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2671 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2672 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2673 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
2674 .features[FEAT_7_0_EDX] =
2675 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2676 /* Missing: XSAVES (not supported by some Linux versions,
2677 * including v4.1 to v4.12).
2678 * KVM doesn't yet expose any XSAVES state save component,
2679 * and the only one defined in Skylake (processor tracing)
2680 * probably will block migration anyway.
2681 */
2682 .features[FEAT_XSAVE] =
2683 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2684 CPUID_XSAVE_XGETBV1,
2685 .features[FEAT_6_EAX] =
2686 CPUID_6_EAX_ARAT,
2687 .xlevel = 0x80000008,
2688 .model_id = "Intel Xeon Processor (Icelake)",
2689 },
2690 {
2691 .name = "KnightsMill",
2692 .level = 0xd,
2693 .vendor = CPUID_VENDOR_INTEL,
2694 .family = 6,
2695 .model = 133,
2696 .stepping = 0,
2697 .features[FEAT_1_EDX] =
2698 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
2699 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
2700 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
2701 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
2702 CPUID_PSE | CPUID_DE | CPUID_FP87,
2703 .features[FEAT_1_ECX] =
2704 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2705 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2706 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2707 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2708 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2709 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2710 .features[FEAT_8000_0001_EDX] =
2711 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2712 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2713 .features[FEAT_8000_0001_ECX] =
2714 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2715 .features[FEAT_7_0_EBX] =
2716 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2717 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
2718 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
2719 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
2720 CPUID_7_0_EBX_AVX512ER,
2721 .features[FEAT_7_0_ECX] =
2722 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2723 .features[FEAT_7_0_EDX] =
2724 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
2725 .features[FEAT_XSAVE] =
2726 CPUID_XSAVE_XSAVEOPT,
2727 .features[FEAT_6_EAX] =
2728 CPUID_6_EAX_ARAT,
2729 .xlevel = 0x80000008,
2730 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
2731 },
2732 {
2733 .name = "Opteron_G1",
2734 .level = 5,
2735 .vendor = CPUID_VENDOR_AMD,
2736 .family = 15,
2737 .model = 6,
2738 .stepping = 1,
2739 .features[FEAT_1_EDX] =
2740 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2741 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2742 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2743 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2744 CPUID_DE | CPUID_FP87,
2745 .features[FEAT_1_ECX] =
2746 CPUID_EXT_SSE3,
2747 .features[FEAT_8000_0001_EDX] =
2748 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2749 .xlevel = 0x80000008,
2750 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
2751 },
2752 {
2753 .name = "Opteron_G2",
2754 .level = 5,
2755 .vendor = CPUID_VENDOR_AMD,
2756 .family = 15,
2757 .model = 6,
2758 .stepping = 1,
2759 .features[FEAT_1_EDX] =
2760 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2761 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2762 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2763 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2764 CPUID_DE | CPUID_FP87,
2765 .features[FEAT_1_ECX] =
2766 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
2767 .features[FEAT_8000_0001_EDX] =
2768 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2769 .features[FEAT_8000_0001_ECX] =
2770 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
2771 .xlevel = 0x80000008,
2772 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
2773 },
2774 {
2775 .name = "Opteron_G3",
2776 .level = 5,
2777 .vendor = CPUID_VENDOR_AMD,
2778 .family = 16,
2779 .model = 2,
2780 .stepping = 3,
2781 .features[FEAT_1_EDX] =
2782 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2783 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2784 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2785 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2786 CPUID_DE | CPUID_FP87,
2787 .features[FEAT_1_ECX] =
2788 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
2789 CPUID_EXT_SSE3,
2790 .features[FEAT_8000_0001_EDX] =
2791 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
2792 CPUID_EXT2_RDTSCP,
2793 .features[FEAT_8000_0001_ECX] =
2794 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
2795 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
2796 .xlevel = 0x80000008,
2797 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
2798 },
2799 {
2800 .name = "Opteron_G4",
2801 .level = 0xd,
2802 .vendor = CPUID_VENDOR_AMD,
2803 .family = 21,
2804 .model = 1,
2805 .stepping = 2,
2806 .features[FEAT_1_EDX] =
2807 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2808 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2809 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2810 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2811 CPUID_DE | CPUID_FP87,
2812 .features[FEAT_1_ECX] =
2813 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2814 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2815 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2816 CPUID_EXT_SSE3,
2817 .features[FEAT_8000_0001_EDX] =
2818 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2819 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
2820 .features[FEAT_8000_0001_ECX] =
2821 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
2822 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2823 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2824 CPUID_EXT3_LAHF_LM,
2825 .features[FEAT_SVM] =
2826 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2827 /* no xsaveopt! */
2828 .xlevel = 0x8000001A,
2829 .model_id = "AMD Opteron 62xx class CPU",
2830 },
2831 {
2832 .name = "Opteron_G5",
2833 .level = 0xd,
2834 .vendor = CPUID_VENDOR_AMD,
2835 .family = 21,
2836 .model = 2,
2837 .stepping = 0,
2838 .features[FEAT_1_EDX] =
2839 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2840 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2841 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2842 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2843 CPUID_DE | CPUID_FP87,
2844 .features[FEAT_1_ECX] =
2845 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
2846 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2847 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
2848 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2849 .features[FEAT_8000_0001_EDX] =
2850 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2851 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
2852 .features[FEAT_8000_0001_ECX] =
2853 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
2854 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2855 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2856 CPUID_EXT3_LAHF_LM,
2857 .features[FEAT_SVM] =
2858 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2859 /* no xsaveopt! */
2860 .xlevel = 0x8000001A,
2861 .model_id = "AMD Opteron 63xx class CPU",
2862 },
2863 {
2864 .name = "EPYC",
2865 .level = 0xd,
2866 .vendor = CPUID_VENDOR_AMD,
2867 .family = 23,
2868 .model = 1,
2869 .stepping = 2,
2870 .features[FEAT_1_EDX] =
2871 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2872 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2873 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2874 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2875 CPUID_VME | CPUID_FP87,
2876 .features[FEAT_1_ECX] =
2877 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2878 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2879 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2880 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2881 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2882 .features[FEAT_8000_0001_EDX] =
2883 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2884 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2885 CPUID_EXT2_SYSCALL,
2886 .features[FEAT_8000_0001_ECX] =
2887 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2888 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2889 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2890 CPUID_EXT3_TOPOEXT,
2891 .features[FEAT_7_0_EBX] =
2892 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2893 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2894 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2895 CPUID_7_0_EBX_SHA_NI,
2896 /* Missing: XSAVES (not supported by some Linux versions,
2897 * including v4.1 to v4.12).
2898 * KVM doesn't yet expose any XSAVES state save component.
2899 */
2900 .features[FEAT_XSAVE] =
2901 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2902 CPUID_XSAVE_XGETBV1,
2903 .features[FEAT_6_EAX] =
2904 CPUID_6_EAX_ARAT,
2905 .features[FEAT_SVM] =
2906 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2907 .xlevel = 0x8000001E,
2908 .model_id = "AMD EPYC Processor",
2909 .cache_info = &epyc_cache_info,
2910 },
2911 {
2912 .name = "EPYC-IBPB",
2913 .level = 0xd,
2914 .vendor = CPUID_VENDOR_AMD,
2915 .family = 23,
2916 .model = 1,
2917 .stepping = 2,
2918 .features[FEAT_1_EDX] =
2919 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2920 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2921 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2922 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2923 CPUID_VME | CPUID_FP87,
2924 .features[FEAT_1_ECX] =
2925 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2926 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2927 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2928 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2929 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2930 .features[FEAT_8000_0001_EDX] =
2931 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2932 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2933 CPUID_EXT2_SYSCALL,
2934 .features[FEAT_8000_0001_ECX] =
2935 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2936 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2937 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2938 CPUID_EXT3_TOPOEXT,
2939 .features[FEAT_8000_0008_EBX] =
2940 CPUID_8000_0008_EBX_IBPB,
2941 .features[FEAT_7_0_EBX] =
2942 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2943 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2944 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2945 CPUID_7_0_EBX_SHA_NI,
2946 /* Missing: XSAVES (not supported by some Linux versions,
2947 * including v4.1 to v4.12).
2948 * KVM doesn't yet expose any XSAVES state save component.
2949 */
2950 .features[FEAT_XSAVE] =
2951 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2952 CPUID_XSAVE_XGETBV1,
2953 .features[FEAT_6_EAX] =
2954 CPUID_6_EAX_ARAT,
2955 .features[FEAT_SVM] =
2956 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2957 .xlevel = 0x8000001E,
2958 .model_id = "AMD EPYC Processor (with IBPB)",
2959 .cache_info = &epyc_cache_info,
2960 },
2961 {
2962 .name = "Dhyana",
2963 .level = 0xd,
2964 .vendor = CPUID_VENDOR_HYGON,
2965 .family = 24,
2966 .model = 0,
2967 .stepping = 1,
2968 .features[FEAT_1_EDX] =
2969 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2970 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2971 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2972 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2973 CPUID_VME | CPUID_FP87,
2974 .features[FEAT_1_ECX] =
2975 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2976 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
2977 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2978 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2979 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
2980 .features[FEAT_8000_0001_EDX] =
2981 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2982 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2983 CPUID_EXT2_SYSCALL,
2984 .features[FEAT_8000_0001_ECX] =
2985 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2986 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2987 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2988 CPUID_EXT3_TOPOEXT,
2989 .features[FEAT_8000_0008_EBX] =
2990 CPUID_8000_0008_EBX_IBPB,
2991 .features[FEAT_7_0_EBX] =
2992 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2993 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2994 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
2995 /*
2996 * Missing: XSAVES (not supported by some Linux versions,
2997 * including v4.1 to v4.12).
2998 * KVM doesn't yet expose any XSAVES state save component.
2999 */
3000 .features[FEAT_XSAVE] =
3001 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3002 CPUID_XSAVE_XGETBV1,
3003 .features[FEAT_6_EAX] =
3004 CPUID_6_EAX_ARAT,
3005 .features[FEAT_SVM] =
3006 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3007 .xlevel = 0x8000001E,
3008 .model_id = "Hygon Dhyana Processor",
3009 .cache_info = &epyc_cache_info,
3010 },
3011 };
3012
3013 typedef struct PropValue {
3014 const char *prop, *value;
3015 } PropValue;
3016
3017 /* KVM-specific features that are automatically added/removed
3018 * from all CPU models when KVM is enabled.
3019 */
3020 static PropValue kvm_default_props[] = {
3021 { "kvmclock", "on" },
3022 { "kvm-nopiodelay", "on" },
3023 { "kvm-asyncpf", "on" },
3024 { "kvm-steal-time", "on" },
3025 { "kvm-pv-eoi", "on" },
3026 { "kvmclock-stable-bit", "on" },
3027 { "x2apic", "on" },
3028 { "acpi", "off" },
3029 { "monitor", "off" },
3030 { "svm", "off" },
3031 { NULL, NULL },
3032 };
3033
3034 /* TCG-specific defaults that override all CPU models when using TCG
3035 */
3036 static PropValue tcg_default_props[] = {
3037 { "vme", "off" },
3038 { NULL, NULL },
3039 };
3040
3041
3042 void x86_cpu_change_kvm_default(const char *prop, const char *value)
3043 {
3044 PropValue *pv;
3045 for (pv = kvm_default_props; pv->prop; pv++) {
3046 if (!strcmp(pv->prop, prop)) {
3047 pv->value = value;
3048 break;
3049 }
3050 }
3051
3052 /* It is valid to call this function only for properties that
3053 * are already present in the kvm_default_props table.
3054 */
3055 assert(pv->prop);
3056 }
3057
3058 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3059 bool migratable_only);
3060
3061 static bool lmce_supported(void)
3062 {
3063 uint64_t mce_cap = 0;
3064
3065 #ifdef CONFIG_KVM
3066 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
3067 return false;
3068 }
3069 #endif
3070
3071 return !!(mce_cap & MCG_LMCE_P);
3072 }
3073
3074 #define CPUID_MODEL_ID_SZ 48
3075
3076 /**
3077 * cpu_x86_fill_model_id:
3078 * Get CPUID model ID string from host CPU.
3079 *
3080 * @str should have at least CPUID_MODEL_ID_SZ bytes
3081 *
3082 * The function does NOT add a null terminator to the string
3083 * automatically.
3084 */
3085 static int cpu_x86_fill_model_id(char *str)
3086 {
3087 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3088 int i;
3089
3090 for (i = 0; i < 3; i++) {
3091 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
3092 memcpy(str + i * 16 + 0, &eax, 4);
3093 memcpy(str + i * 16 + 4, &ebx, 4);
3094 memcpy(str + i * 16 + 8, &ecx, 4);
3095 memcpy(str + i * 16 + 12, &edx, 4);
3096 }
3097 return 0;
3098 }
3099
3100 static Property max_x86_cpu_properties[] = {
3101 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
3102 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
3103 DEFINE_PROP_END_OF_LIST()
3104 };
3105
3106 static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
3107 {
3108 DeviceClass *dc = DEVICE_CLASS(oc);
3109 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3110
3111 xcc->ordering = 9;
3112
3113 xcc->model_description =
3114 "Enables all features supported by the accelerator in the current host";
3115
3116 dc->props = max_x86_cpu_properties;
3117 }
3118
3119 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
3120
3121 static void max_x86_cpu_initfn(Object *obj)
3122 {
3123 X86CPU *cpu = X86_CPU(obj);
3124 CPUX86State *env = &cpu->env;
3125 KVMState *s = kvm_state;
3126
3127 /* We can't fill the features array here because we don't know yet if
3128 * "migratable" is true or false.
3129 */
3130 cpu->max_features = true;
3131
3132 if (accel_uses_host_cpuid()) {
3133 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
3134 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
3135 int family, model, stepping;
3136 X86CPUDefinition host_cpudef = { };
3137 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3138
3139 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
3140 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
3141
3142 host_vendor_fms(vendor, &family, &model, &stepping);
3143
3144 cpu_x86_fill_model_id(model_id);
3145
3146 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
3147 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
3148 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
3149 object_property_set_int(OBJECT(cpu), stepping, "stepping",
3150 &error_abort);
3151 object_property_set_str(OBJECT(cpu), model_id, "model-id",
3152 &error_abort);
3153
3154 if (kvm_enabled()) {
3155 env->cpuid_min_level =
3156 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
3157 env->cpuid_min_xlevel =
3158 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
3159 env->cpuid_min_xlevel2 =
3160 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
3161 } else {
3162 env->cpuid_min_level =
3163 hvf_get_supported_cpuid(0x0, 0, R_EAX);
3164 env->cpuid_min_xlevel =
3165 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
3166 env->cpuid_min_xlevel2 =
3167 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
3168 }
3169
3170 if (lmce_supported()) {
3171 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
3172 }
3173 } else {
3174 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
3175 "vendor", &error_abort);
3176 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
3177 object_property_set_int(OBJECT(cpu), 6, "model"<