i386/cpu: Consolidate die-id validity in smp context
[qemu.git] / target / i386 / cpu.h
1 /*
2 * i386 virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef I386_CPU_H
21 #define I386_CPU_H
22
23 #include "sysemu/tcg.h"
24 #include "cpu-qom.h"
25 #include "hyperv-proto.h"
26 #include "exec/cpu-defs.h"
27
28 /* The x86 has a strong memory model with some store-after-load re-ordering */
29 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
30
31 /* Maximum instruction code size */
32 #define TARGET_MAX_INSN_SIZE 16
33
34 /* support for self modifying code even if the modified instruction is
35 close to the modifying instruction */
36 #define TARGET_HAS_PRECISE_SMC
37
38 #ifdef TARGET_X86_64
39 #define I386_ELF_MACHINE EM_X86_64
40 #define ELF_MACHINE_UNAME "x86_64"
41 #else
42 #define I386_ELF_MACHINE EM_386
43 #define ELF_MACHINE_UNAME "i686"
44 #endif
45
46 enum {
47 R_EAX = 0,
48 R_ECX = 1,
49 R_EDX = 2,
50 R_EBX = 3,
51 R_ESP = 4,
52 R_EBP = 5,
53 R_ESI = 6,
54 R_EDI = 7,
55 R_R8 = 8,
56 R_R9 = 9,
57 R_R10 = 10,
58 R_R11 = 11,
59 R_R12 = 12,
60 R_R13 = 13,
61 R_R14 = 14,
62 R_R15 = 15,
63
64 R_AL = 0,
65 R_CL = 1,
66 R_DL = 2,
67 R_BL = 3,
68 R_AH = 4,
69 R_CH = 5,
70 R_DH = 6,
71 R_BH = 7,
72 };
73
74 typedef enum X86Seg {
75 R_ES = 0,
76 R_CS = 1,
77 R_SS = 2,
78 R_DS = 3,
79 R_FS = 4,
80 R_GS = 5,
81 R_LDTR = 6,
82 R_TR = 7,
83 } X86Seg;
84
85 /* segment descriptor fields */
86 #define DESC_G_SHIFT 23
87 #define DESC_G_MASK (1 << DESC_G_SHIFT)
88 #define DESC_B_SHIFT 22
89 #define DESC_B_MASK (1 << DESC_B_SHIFT)
90 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
91 #define DESC_L_MASK (1 << DESC_L_SHIFT)
92 #define DESC_AVL_SHIFT 20
93 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT)
94 #define DESC_P_SHIFT 15
95 #define DESC_P_MASK (1 << DESC_P_SHIFT)
96 #define DESC_DPL_SHIFT 13
97 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
98 #define DESC_S_SHIFT 12
99 #define DESC_S_MASK (1 << DESC_S_SHIFT)
100 #define DESC_TYPE_SHIFT 8
101 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
102 #define DESC_A_MASK (1 << 8)
103
104 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
105 #define DESC_C_MASK (1 << 10) /* code: conforming */
106 #define DESC_R_MASK (1 << 9) /* code: readable */
107
108 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
109 #define DESC_W_MASK (1 << 9) /* data: writable */
110
111 #define DESC_TSS_BUSY_MASK (1 << 9)
112
113 /* eflags masks */
114 #define CC_C 0x0001
115 #define CC_P 0x0004
116 #define CC_A 0x0010
117 #define CC_Z 0x0040
118 #define CC_S 0x0080
119 #define CC_O 0x0800
120
121 #define TF_SHIFT 8
122 #define IOPL_SHIFT 12
123 #define VM_SHIFT 17
124
125 #define TF_MASK 0x00000100
126 #define IF_MASK 0x00000200
127 #define DF_MASK 0x00000400
128 #define IOPL_MASK 0x00003000
129 #define NT_MASK 0x00004000
130 #define RF_MASK 0x00010000
131 #define VM_MASK 0x00020000
132 #define AC_MASK 0x00040000
133 #define VIF_MASK 0x00080000
134 #define VIP_MASK 0x00100000
135 #define ID_MASK 0x00200000
136
137 /* hidden flags - used internally by qemu to represent additional cpu
138 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
139 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
140 positions to ease oring with eflags. */
141 /* current cpl */
142 #define HF_CPL_SHIFT 0
143 /* true if hardware interrupts must be disabled for next instruction */
144 #define HF_INHIBIT_IRQ_SHIFT 3
145 /* 16 or 32 segments */
146 #define HF_CS32_SHIFT 4
147 #define HF_SS32_SHIFT 5
148 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
149 #define HF_ADDSEG_SHIFT 6
150 /* copy of CR0.PE (protected mode) */
151 #define HF_PE_SHIFT 7
152 #define HF_TF_SHIFT 8 /* must be same as eflags */
153 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
154 #define HF_EM_SHIFT 10
155 #define HF_TS_SHIFT 11
156 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
157 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
158 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
159 #define HF_RF_SHIFT 16 /* must be same as eflags */
160 #define HF_VM_SHIFT 17 /* must be same as eflags */
161 #define HF_AC_SHIFT 18 /* must be same as eflags */
162 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */
163 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
164 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */
165 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
166 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */
167 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */
168 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */
169 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */
170
171 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
172 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
173 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
174 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
175 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
176 #define HF_PE_MASK (1 << HF_PE_SHIFT)
177 #define HF_TF_MASK (1 << HF_TF_SHIFT)
178 #define HF_MP_MASK (1 << HF_MP_SHIFT)
179 #define HF_EM_MASK (1 << HF_EM_SHIFT)
180 #define HF_TS_MASK (1 << HF_TS_SHIFT)
181 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
182 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
183 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
184 #define HF_RF_MASK (1 << HF_RF_SHIFT)
185 #define HF_VM_MASK (1 << HF_VM_SHIFT)
186 #define HF_AC_MASK (1 << HF_AC_SHIFT)
187 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
188 #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
189 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT)
190 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
191 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
192 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
193 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
194 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
195
196 /* hflags2 */
197
198 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
199 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
200 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */
201 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
202 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
203 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */
204 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */
205
206 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
207 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
208 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
209 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
210 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
211 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
212 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
213
214 #define CR0_PE_SHIFT 0
215 #define CR0_MP_SHIFT 1
216
217 #define CR0_PE_MASK (1U << 0)
218 #define CR0_MP_MASK (1U << 1)
219 #define CR0_EM_MASK (1U << 2)
220 #define CR0_TS_MASK (1U << 3)
221 #define CR0_ET_MASK (1U << 4)
222 #define CR0_NE_MASK (1U << 5)
223 #define CR0_WP_MASK (1U << 16)
224 #define CR0_AM_MASK (1U << 18)
225 #define CR0_PG_MASK (1U << 31)
226
227 #define CR4_VME_MASK (1U << 0)
228 #define CR4_PVI_MASK (1U << 1)
229 #define CR4_TSD_MASK (1U << 2)
230 #define CR4_DE_MASK (1U << 3)
231 #define CR4_PSE_MASK (1U << 4)
232 #define CR4_PAE_MASK (1U << 5)
233 #define CR4_MCE_MASK (1U << 6)
234 #define CR4_PGE_MASK (1U << 7)
235 #define CR4_PCE_MASK (1U << 8)
236 #define CR4_OSFXSR_SHIFT 9
237 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
238 #define CR4_OSXMMEXCPT_MASK (1U << 10)
239 #define CR4_LA57_MASK (1U << 12)
240 #define CR4_VMXE_MASK (1U << 13)
241 #define CR4_SMXE_MASK (1U << 14)
242 #define CR4_FSGSBASE_MASK (1U << 16)
243 #define CR4_PCIDE_MASK (1U << 17)
244 #define CR4_OSXSAVE_MASK (1U << 18)
245 #define CR4_SMEP_MASK (1U << 20)
246 #define CR4_SMAP_MASK (1U << 21)
247 #define CR4_PKE_MASK (1U << 22)
248
249 #define DR6_BD (1 << 13)
250 #define DR6_BS (1 << 14)
251 #define DR6_BT (1 << 15)
252 #define DR6_FIXED_1 0xffff0ff0
253
254 #define DR7_GD (1 << 13)
255 #define DR7_TYPE_SHIFT 16
256 #define DR7_LEN_SHIFT 18
257 #define DR7_FIXED_1 0x00000400
258 #define DR7_GLOBAL_BP_MASK 0xaa
259 #define DR7_LOCAL_BP_MASK 0x55
260 #define DR7_MAX_BP 4
261 #define DR7_TYPE_BP_INST 0x0
262 #define DR7_TYPE_DATA_WR 0x1
263 #define DR7_TYPE_IO_RW 0x2
264 #define DR7_TYPE_DATA_RW 0x3
265
266 #define PG_PRESENT_BIT 0
267 #define PG_RW_BIT 1
268 #define PG_USER_BIT 2
269 #define PG_PWT_BIT 3
270 #define PG_PCD_BIT 4
271 #define PG_ACCESSED_BIT 5
272 #define PG_DIRTY_BIT 6
273 #define PG_PSE_BIT 7
274 #define PG_GLOBAL_BIT 8
275 #define PG_PSE_PAT_BIT 12
276 #define PG_PKRU_BIT 59
277 #define PG_NX_BIT 63
278
279 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
280 #define PG_RW_MASK (1 << PG_RW_BIT)
281 #define PG_USER_MASK (1 << PG_USER_BIT)
282 #define PG_PWT_MASK (1 << PG_PWT_BIT)
283 #define PG_PCD_MASK (1 << PG_PCD_BIT)
284 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
285 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
286 #define PG_PSE_MASK (1 << PG_PSE_BIT)
287 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
288 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
289 #define PG_ADDRESS_MASK 0x000ffffffffff000LL
290 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
291 #define PG_HI_USER_MASK 0x7ff0000000000000LL
292 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
293 #define PG_NX_MASK (1ULL << PG_NX_BIT)
294
295 #define PG_ERROR_W_BIT 1
296
297 #define PG_ERROR_P_MASK 0x01
298 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
299 #define PG_ERROR_U_MASK 0x04
300 #define PG_ERROR_RSVD_MASK 0x08
301 #define PG_ERROR_I_D_MASK 0x10
302 #define PG_ERROR_PK_MASK 0x20
303
304 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
305 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
306 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */
307
308 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
309 #define MCE_BANKS_DEF 10
310
311 #define MCG_CAP_BANKS_MASK 0xff
312
313 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
314 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
315 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
316 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */
317
318 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
319
320 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
321 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
322 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
323 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
324 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
325 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
326 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
327 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
328 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
329
330 /* MISC register defines */
331 #define MCM_ADDR_SEGOFF 0 /* segment offset */
332 #define MCM_ADDR_LINEAR 1 /* linear address */
333 #define MCM_ADDR_PHYS 2 /* physical address */
334 #define MCM_ADDR_MEM 3 /* memory address */
335 #define MCM_ADDR_GENERIC 7 /* generic */
336
337 #define MSR_IA32_TSC 0x10
338 #define MSR_IA32_APICBASE 0x1b
339 #define MSR_IA32_APICBASE_BSP (1<<8)
340 #define MSR_IA32_APICBASE_ENABLE (1<<11)
341 #define MSR_IA32_APICBASE_EXTD (1 << 10)
342 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
343 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
344 #define MSR_TSC_ADJUST 0x0000003b
345 #define MSR_IA32_SPEC_CTRL 0x48
346 #define MSR_VIRT_SSBD 0xc001011f
347 #define MSR_IA32_PRED_CMD 0x49
348 #define MSR_IA32_CORE_CAPABILITY 0xcf
349 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
350 #define MSR_IA32_TSCDEADLINE 0x6e0
351
352 #define FEATURE_CONTROL_LOCKED (1<<0)
353 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
354 #define FEATURE_CONTROL_LMCE (1<<20)
355
356 #define MSR_P6_PERFCTR0 0xc1
357
358 #define MSR_IA32_SMBASE 0x9e
359 #define MSR_SMI_COUNT 0x34
360 #define MSR_MTRRcap 0xfe
361 #define MSR_MTRRcap_VCNT 8
362 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
363 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
364
365 #define MSR_IA32_SYSENTER_CS 0x174
366 #define MSR_IA32_SYSENTER_ESP 0x175
367 #define MSR_IA32_SYSENTER_EIP 0x176
368
369 #define MSR_MCG_CAP 0x179
370 #define MSR_MCG_STATUS 0x17a
371 #define MSR_MCG_CTL 0x17b
372 #define MSR_MCG_EXT_CTL 0x4d0
373
374 #define MSR_P6_EVNTSEL0 0x186
375
376 #define MSR_IA32_PERF_STATUS 0x198
377
378 #define MSR_IA32_MISC_ENABLE 0x1a0
379 /* Indicates good rep/movs microcode on some processors: */
380 #define MSR_IA32_MISC_ENABLE_DEFAULT 1
381 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
382
383 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
384 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
385
386 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
387
388 #define MSR_MTRRfix64K_00000 0x250
389 #define MSR_MTRRfix16K_80000 0x258
390 #define MSR_MTRRfix16K_A0000 0x259
391 #define MSR_MTRRfix4K_C0000 0x268
392 #define MSR_MTRRfix4K_C8000 0x269
393 #define MSR_MTRRfix4K_D0000 0x26a
394 #define MSR_MTRRfix4K_D8000 0x26b
395 #define MSR_MTRRfix4K_E0000 0x26c
396 #define MSR_MTRRfix4K_E8000 0x26d
397 #define MSR_MTRRfix4K_F0000 0x26e
398 #define MSR_MTRRfix4K_F8000 0x26f
399
400 #define MSR_PAT 0x277
401
402 #define MSR_MTRRdefType 0x2ff
403
404 #define MSR_CORE_PERF_FIXED_CTR0 0x309
405 #define MSR_CORE_PERF_FIXED_CTR1 0x30a
406 #define MSR_CORE_PERF_FIXED_CTR2 0x30b
407 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
408 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
409 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
410 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
411
412 #define MSR_MC0_CTL 0x400
413 #define MSR_MC0_STATUS 0x401
414 #define MSR_MC0_ADDR 0x402
415 #define MSR_MC0_MISC 0x403
416
417 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560
418 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561
419 #define MSR_IA32_RTIT_CTL 0x570
420 #define MSR_IA32_RTIT_STATUS 0x571
421 #define MSR_IA32_RTIT_CR3_MATCH 0x572
422 #define MSR_IA32_RTIT_ADDR0_A 0x580
423 #define MSR_IA32_RTIT_ADDR0_B 0x581
424 #define MSR_IA32_RTIT_ADDR1_A 0x582
425 #define MSR_IA32_RTIT_ADDR1_B 0x583
426 #define MSR_IA32_RTIT_ADDR2_A 0x584
427 #define MSR_IA32_RTIT_ADDR2_B 0x585
428 #define MSR_IA32_RTIT_ADDR3_A 0x586
429 #define MSR_IA32_RTIT_ADDR3_B 0x587
430 #define MAX_RTIT_ADDRS 8
431
432 #define MSR_EFER 0xc0000080
433
434 #define MSR_EFER_SCE (1 << 0)
435 #define MSR_EFER_LME (1 << 8)
436 #define MSR_EFER_LMA (1 << 10)
437 #define MSR_EFER_NXE (1 << 11)
438 #define MSR_EFER_SVME (1 << 12)
439 #define MSR_EFER_FFXSR (1 << 14)
440
441 #define MSR_STAR 0xc0000081
442 #define MSR_LSTAR 0xc0000082
443 #define MSR_CSTAR 0xc0000083
444 #define MSR_FMASK 0xc0000084
445 #define MSR_FSBASE 0xc0000100
446 #define MSR_GSBASE 0xc0000101
447 #define MSR_KERNELGSBASE 0xc0000102
448 #define MSR_TSC_AUX 0xc0000103
449
450 #define MSR_VM_HSAVE_PA 0xc0010117
451
452 #define MSR_IA32_BNDCFGS 0x00000d90
453 #define MSR_IA32_XSS 0x00000da0
454
455 #define XSTATE_FP_BIT 0
456 #define XSTATE_SSE_BIT 1
457 #define XSTATE_YMM_BIT 2
458 #define XSTATE_BNDREGS_BIT 3
459 #define XSTATE_BNDCSR_BIT 4
460 #define XSTATE_OPMASK_BIT 5
461 #define XSTATE_ZMM_Hi256_BIT 6
462 #define XSTATE_Hi16_ZMM_BIT 7
463 #define XSTATE_PKRU_BIT 9
464
465 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
466 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
467 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
468 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
469 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
470 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
471 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
472 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
473 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
474
475 /* CPUID feature words */
476 typedef enum FeatureWord {
477 FEAT_1_EDX, /* CPUID[1].EDX */
478 FEAT_1_ECX, /* CPUID[1].ECX */
479 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
480 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */
481 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */
482 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
483 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
484 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
485 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */
486 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
487 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
488 FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */
489 FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */
490 FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */
491 FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */
492 FEAT_HV_RECOMM_EAX, /* CPUID[4000_0004].EAX */
493 FEAT_HV_NESTED_EAX, /* CPUID[4000_000A].EAX */
494 FEAT_SVM, /* CPUID[8000_000A].EDX */
495 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */
496 FEAT_6_EAX, /* CPUID[6].EAX */
497 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
498 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
499 FEAT_ARCH_CAPABILITIES,
500 FEAT_CORE_CAPABILITY,
501 FEATURE_WORDS,
502 } FeatureWord;
503
504 typedef uint32_t FeatureWordArray[FEATURE_WORDS];
505
506 /* cpuid_features bits */
507 #define CPUID_FP87 (1U << 0)
508 #define CPUID_VME (1U << 1)
509 #define CPUID_DE (1U << 2)
510 #define CPUID_PSE (1U << 3)
511 #define CPUID_TSC (1U << 4)
512 #define CPUID_MSR (1U << 5)
513 #define CPUID_PAE (1U << 6)
514 #define CPUID_MCE (1U << 7)
515 #define CPUID_CX8 (1U << 8)
516 #define CPUID_APIC (1U << 9)
517 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */
518 #define CPUID_MTRR (1U << 12)
519 #define CPUID_PGE (1U << 13)
520 #define CPUID_MCA (1U << 14)
521 #define CPUID_CMOV (1U << 15)
522 #define CPUID_PAT (1U << 16)
523 #define CPUID_PSE36 (1U << 17)
524 #define CPUID_PN (1U << 18)
525 #define CPUID_CLFLUSH (1U << 19)
526 #define CPUID_DTS (1U << 21)
527 #define CPUID_ACPI (1U << 22)
528 #define CPUID_MMX (1U << 23)
529 #define CPUID_FXSR (1U << 24)
530 #define CPUID_SSE (1U << 25)
531 #define CPUID_SSE2 (1U << 26)
532 #define CPUID_SS (1U << 27)
533 #define CPUID_HT (1U << 28)
534 #define CPUID_TM (1U << 29)
535 #define CPUID_IA64 (1U << 30)
536 #define CPUID_PBE (1U << 31)
537
538 #define CPUID_EXT_SSE3 (1U << 0)
539 #define CPUID_EXT_PCLMULQDQ (1U << 1)
540 #define CPUID_EXT_DTES64 (1U << 2)
541 #define CPUID_EXT_MONITOR (1U << 3)
542 #define CPUID_EXT_DSCPL (1U << 4)
543 #define CPUID_EXT_VMX (1U << 5)
544 #define CPUID_EXT_SMX (1U << 6)
545 #define CPUID_EXT_EST (1U << 7)
546 #define CPUID_EXT_TM2 (1U << 8)
547 #define CPUID_EXT_SSSE3 (1U << 9)
548 #define CPUID_EXT_CID (1U << 10)
549 #define CPUID_EXT_FMA (1U << 12)
550 #define CPUID_EXT_CX16 (1U << 13)
551 #define CPUID_EXT_XTPR (1U << 14)
552 #define CPUID_EXT_PDCM (1U << 15)
553 #define CPUID_EXT_PCID (1U << 17)
554 #define CPUID_EXT_DCA (1U << 18)
555 #define CPUID_EXT_SSE41 (1U << 19)
556 #define CPUID_EXT_SSE42 (1U << 20)
557 #define CPUID_EXT_X2APIC (1U << 21)
558 #define CPUID_EXT_MOVBE (1U << 22)
559 #define CPUID_EXT_POPCNT (1U << 23)
560 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
561 #define CPUID_EXT_AES (1U << 25)
562 #define CPUID_EXT_XSAVE (1U << 26)
563 #define CPUID_EXT_OSXSAVE (1U << 27)
564 #define CPUID_EXT_AVX (1U << 28)
565 #define CPUID_EXT_F16C (1U << 29)
566 #define CPUID_EXT_RDRAND (1U << 30)
567 #define CPUID_EXT_HYPERVISOR (1U << 31)
568
569 #define CPUID_EXT2_FPU (1U << 0)
570 #define CPUID_EXT2_VME (1U << 1)
571 #define CPUID_EXT2_DE (1U << 2)
572 #define CPUID_EXT2_PSE (1U << 3)
573 #define CPUID_EXT2_TSC (1U << 4)
574 #define CPUID_EXT2_MSR (1U << 5)
575 #define CPUID_EXT2_PAE (1U << 6)
576 #define CPUID_EXT2_MCE (1U << 7)
577 #define CPUID_EXT2_CX8 (1U << 8)
578 #define CPUID_EXT2_APIC (1U << 9)
579 #define CPUID_EXT2_SYSCALL (1U << 11)
580 #define CPUID_EXT2_MTRR (1U << 12)
581 #define CPUID_EXT2_PGE (1U << 13)
582 #define CPUID_EXT2_MCA (1U << 14)
583 #define CPUID_EXT2_CMOV (1U << 15)
584 #define CPUID_EXT2_PAT (1U << 16)
585 #define CPUID_EXT2_PSE36 (1U << 17)
586 #define CPUID_EXT2_MP (1U << 19)
587 #define CPUID_EXT2_NX (1U << 20)
588 #define CPUID_EXT2_MMXEXT (1U << 22)
589 #define CPUID_EXT2_MMX (1U << 23)
590 #define CPUID_EXT2_FXSR (1U << 24)
591 #define CPUID_EXT2_FFXSR (1U << 25)
592 #define CPUID_EXT2_PDPE1GB (1U << 26)
593 #define CPUID_EXT2_RDTSCP (1U << 27)
594 #define CPUID_EXT2_LM (1U << 29)
595 #define CPUID_EXT2_3DNOWEXT (1U << 30)
596 #define CPUID_EXT2_3DNOW (1U << 31)
597
598 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
599 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
600 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
601 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
602 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
603 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
604 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
605 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
606 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
607 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
608
609 #define CPUID_EXT3_LAHF_LM (1U << 0)
610 #define CPUID_EXT3_CMP_LEG (1U << 1)
611 #define CPUID_EXT3_SVM (1U << 2)
612 #define CPUID_EXT3_EXTAPIC (1U << 3)
613 #define CPUID_EXT3_CR8LEG (1U << 4)
614 #define CPUID_EXT3_ABM (1U << 5)
615 #define CPUID_EXT3_SSE4A (1U << 6)
616 #define CPUID_EXT3_MISALIGNSSE (1U << 7)
617 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
618 #define CPUID_EXT3_OSVW (1U << 9)
619 #define CPUID_EXT3_IBS (1U << 10)
620 #define CPUID_EXT3_XOP (1U << 11)
621 #define CPUID_EXT3_SKINIT (1U << 12)
622 #define CPUID_EXT3_WDT (1U << 13)
623 #define CPUID_EXT3_LWP (1U << 15)
624 #define CPUID_EXT3_FMA4 (1U << 16)
625 #define CPUID_EXT3_TCE (1U << 17)
626 #define CPUID_EXT3_NODEID (1U << 19)
627 #define CPUID_EXT3_TBM (1U << 21)
628 #define CPUID_EXT3_TOPOEXT (1U << 22)
629 #define CPUID_EXT3_PERFCORE (1U << 23)
630 #define CPUID_EXT3_PERFNB (1U << 24)
631
632 #define CPUID_SVM_NPT (1U << 0)
633 #define CPUID_SVM_LBRV (1U << 1)
634 #define CPUID_SVM_SVMLOCK (1U << 2)
635 #define CPUID_SVM_NRIPSAVE (1U << 3)
636 #define CPUID_SVM_TSCSCALE (1U << 4)
637 #define CPUID_SVM_VMCBCLEAN (1U << 5)
638 #define CPUID_SVM_FLUSHASID (1U << 6)
639 #define CPUID_SVM_DECODEASSIST (1U << 7)
640 #define CPUID_SVM_PAUSEFILTER (1U << 10)
641 #define CPUID_SVM_PFTHRESHOLD (1U << 12)
642
643 #define CPUID_7_0_EBX_FSGSBASE (1U << 0)
644 #define CPUID_7_0_EBX_BMI1 (1U << 3)
645 #define CPUID_7_0_EBX_HLE (1U << 4)
646 #define CPUID_7_0_EBX_AVX2 (1U << 5)
647 #define CPUID_7_0_EBX_SMEP (1U << 7)
648 #define CPUID_7_0_EBX_BMI2 (1U << 8)
649 #define CPUID_7_0_EBX_ERMS (1U << 9)
650 #define CPUID_7_0_EBX_INVPCID (1U << 10)
651 #define CPUID_7_0_EBX_RTM (1U << 11)
652 #define CPUID_7_0_EBX_MPX (1U << 14)
653 #define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */
654 #define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */
655 #define CPUID_7_0_EBX_RDSEED (1U << 18)
656 #define CPUID_7_0_EBX_ADX (1U << 19)
657 #define CPUID_7_0_EBX_SMAP (1U << 20)
658 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */
659 #define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */
660 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */
661 #define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */
662 #define CPUID_7_0_EBX_INTEL_PT (1U << 25) /* Intel Processor Trace */
663 #define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
664 #define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
665 #define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
666 #define CPUID_7_0_EBX_SHA_NI (1U << 29) /* SHA1/SHA256 Instruction Extensions */
667 #define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */
668 #define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */
669
670 #define CPUID_7_0_ECX_AVX512BMI (1U << 1)
671 #define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */
672 #define CPUID_7_0_ECX_UMIP (1U << 2)
673 #define CPUID_7_0_ECX_PKU (1U << 3)
674 #define CPUID_7_0_ECX_OSPKE (1U << 4)
675 #define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */
676 #define CPUID_7_0_ECX_GFNI (1U << 8)
677 #define CPUID_7_0_ECX_VAES (1U << 9)
678 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
679 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
680 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
681 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */
682 #define CPUID_7_0_ECX_LA57 (1U << 16)
683 #define CPUID_7_0_ECX_RDPID (1U << 22)
684 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */
685 #define CPUID_7_0_ECX_MOVDIRI (1U << 27) /* MOVDIRI Instruction */
686 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28) /* MOVDIR64B Instruction */
687
688 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
689 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
690 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */
691 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/
692 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) /*Core Capability*/
693 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */
694
695 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9) /* Write back and
696 do not invalidate cache */
697 #define CPUID_8000_0008_EBX_IBPB (1U << 12) /* Indirect Branch Prediction Barrier */
698
699 #define CPUID_XSAVE_XSAVEOPT (1U << 0)
700 #define CPUID_XSAVE_XSAVEC (1U << 1)
701 #define CPUID_XSAVE_XGETBV1 (1U << 2)
702 #define CPUID_XSAVE_XSAVES (1U << 3)
703
704 #define CPUID_6_EAX_ARAT (1U << 2)
705
706 /* CPUID[0x80000007].EDX flags: */
707 #define CPUID_APM_INVTSC (1U << 8)
708
709 #define CPUID_VENDOR_SZ 12
710
711 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
712 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
713 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
714 #define CPUID_VENDOR_INTEL "GenuineIntel"
715
716 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
717 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
718 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
719 #define CPUID_VENDOR_AMD "AuthenticAMD"
720
721 #define CPUID_VENDOR_VIA "CentaurHauls"
722
723 #define CPUID_VENDOR_HYGON "HygonGenuine"
724
725 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
726 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
727 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
728 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
729 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
730 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
731
732 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */
733 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
734
735 /* CPUID[0xB].ECX level types */
736 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
737 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
738 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
739
740 /* MSR Feature Bits */
741 #define MSR_ARCH_CAP_RDCL_NO (1U << 0)
742 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
743 #define MSR_ARCH_CAP_RSBA (1U << 2)
744 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
745 #define MSR_ARCH_CAP_SSB_NO (1U << 4)
746
747 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
748
749 /* Supported Hyper-V Enlightenments */
750 #define HYPERV_FEAT_RELAXED 0
751 #define HYPERV_FEAT_VAPIC 1
752 #define HYPERV_FEAT_TIME 2
753 #define HYPERV_FEAT_CRASH 3
754 #define HYPERV_FEAT_RESET 4
755 #define HYPERV_FEAT_VPINDEX 5
756 #define HYPERV_FEAT_RUNTIME 6
757 #define HYPERV_FEAT_SYNIC 7
758 #define HYPERV_FEAT_STIMER 8
759 #define HYPERV_FEAT_FREQUENCIES 9
760 #define HYPERV_FEAT_REENLIGHTENMENT 10
761 #define HYPERV_FEAT_TLBFLUSH 11
762 #define HYPERV_FEAT_EVMCS 12
763 #define HYPERV_FEAT_IPI 13
764 #define HYPERV_FEAT_STIMER_DIRECT 14
765
766 #ifndef HYPERV_SPINLOCK_NEVER_RETRY
767 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
768 #endif
769
770 #define EXCP00_DIVZ 0
771 #define EXCP01_DB 1
772 #define EXCP02_NMI 2
773 #define EXCP03_INT3 3
774 #define EXCP04_INTO 4
775 #define EXCP05_BOUND 5
776 #define EXCP06_ILLOP 6
777 #define EXCP07_PREX 7
778 #define EXCP08_DBLE 8
779 #define EXCP09_XERR 9
780 #define EXCP0A_TSS 10
781 #define EXCP0B_NOSEG 11
782 #define EXCP0C_STACK 12
783 #define EXCP0D_GPF 13
784 #define EXCP0E_PAGE 14
785 #define EXCP10_COPR 16
786 #define EXCP11_ALGN 17
787 #define EXCP12_MCHK 18
788
789 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation
790 for syscall instruction */
791 #define EXCP_VMEXIT 0x100
792
793 /* i386-specific interrupt pending bits. */
794 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
795 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
796 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
797 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
798 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
799 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
800 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
801
802 /* Use a clearer name for this. */
803 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
804
805 /* Instead of computing the condition codes after each x86 instruction,
806 * QEMU just stores one operand (called CC_SRC), the result
807 * (called CC_DST) and the type of operation (called CC_OP). When the
808 * condition codes are needed, the condition codes can be calculated
809 * using this information. Condition codes are not generated if they
810 * are only needed for conditional branches.
811 */
812 typedef enum {
813 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
814 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
815
816 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
817 CC_OP_MULW,
818 CC_OP_MULL,
819 CC_OP_MULQ,
820
821 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
822 CC_OP_ADDW,
823 CC_OP_ADDL,
824 CC_OP_ADDQ,
825
826 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
827 CC_OP_ADCW,
828 CC_OP_ADCL,
829 CC_OP_ADCQ,
830
831 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
832 CC_OP_SUBW,
833 CC_OP_SUBL,
834 CC_OP_SUBQ,
835
836 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
837 CC_OP_SBBW,
838 CC_OP_SBBL,
839 CC_OP_SBBQ,
840
841 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
842 CC_OP_LOGICW,
843 CC_OP_LOGICL,
844 CC_OP_LOGICQ,
845
846 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
847 CC_OP_INCW,
848 CC_OP_INCL,
849 CC_OP_INCQ,
850
851 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
852 CC_OP_DECW,
853 CC_OP_DECL,
854 CC_OP_DECQ,
855
856 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
857 CC_OP_SHLW,
858 CC_OP_SHLL,
859 CC_OP_SHLQ,
860
861 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
862 CC_OP_SARW,
863 CC_OP_SARL,
864 CC_OP_SARQ,
865
866 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
867 CC_OP_BMILGW,
868 CC_OP_BMILGL,
869 CC_OP_BMILGQ,
870
871 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */
872 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */
873 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */
874
875 CC_OP_CLR, /* Z set, all other flags clear. */
876 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */
877
878 CC_OP_NB,
879 } CCOp;
880
881 typedef struct SegmentCache {
882 uint32_t selector;
883 target_ulong base;
884 uint32_t limit;
885 uint32_t flags;
886 } SegmentCache;
887
888 #define MMREG_UNION(n, bits) \
889 union n { \
890 uint8_t _b_##n[(bits)/8]; \
891 uint16_t _w_##n[(bits)/16]; \
892 uint32_t _l_##n[(bits)/32]; \
893 uint64_t _q_##n[(bits)/64]; \
894 float32 _s_##n[(bits)/32]; \
895 float64 _d_##n[(bits)/64]; \
896 }
897
898 typedef union {
899 uint8_t _b[16];
900 uint16_t _w[8];
901 uint32_t _l[4];
902 uint64_t _q[2];
903 } XMMReg;
904
905 typedef union {
906 uint8_t _b[32];
907 uint16_t _w[16];
908 uint32_t _l[8];
909 uint64_t _q[4];
910 } YMMReg;
911
912 typedef MMREG_UNION(ZMMReg, 512) ZMMReg;
913 typedef MMREG_UNION(MMXReg, 64) MMXReg;
914
915 typedef struct BNDReg {
916 uint64_t lb;
917 uint64_t ub;
918 } BNDReg;
919
920 typedef struct BNDCSReg {
921 uint64_t cfgu;
922 uint64_t sts;
923 } BNDCSReg;
924
925 #define BNDCFG_ENABLE 1ULL
926 #define BNDCFG_BNDPRESERVE 2ULL
927 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
928
929 #ifdef HOST_WORDS_BIGENDIAN
930 #define ZMM_B(n) _b_ZMMReg[63 - (n)]
931 #define ZMM_W(n) _w_ZMMReg[31 - (n)]
932 #define ZMM_L(n) _l_ZMMReg[15 - (n)]
933 #define ZMM_S(n) _s_ZMMReg[15 - (n)]
934 #define ZMM_Q(n) _q_ZMMReg[7 - (n)]
935 #define ZMM_D(n) _d_ZMMReg[7 - (n)]
936
937 #define MMX_B(n) _b_MMXReg[7 - (n)]
938 #define MMX_W(n) _w_MMXReg[3 - (n)]
939 #define MMX_L(n) _l_MMXReg[1 - (n)]
940 #define MMX_S(n) _s_MMXReg[1 - (n)]
941 #else
942 #define ZMM_B(n) _b_ZMMReg[n]
943 #define ZMM_W(n) _w_ZMMReg[n]
944 #define ZMM_L(n) _l_ZMMReg[n]
945 #define ZMM_S(n) _s_ZMMReg[n]
946 #define ZMM_Q(n) _q_ZMMReg[n]
947 #define ZMM_D(n) _d_ZMMReg[n]
948
949 #define MMX_B(n) _b_MMXReg[n]
950 #define MMX_W(n) _w_MMXReg[n]
951 #define MMX_L(n) _l_MMXReg[n]
952 #define MMX_S(n) _s_MMXReg[n]
953 #endif
954 #define MMX_Q(n) _q_MMXReg[n]
955
956 typedef union {
957 floatx80 d __attribute__((aligned(16)));
958 MMXReg mmx;
959 } FPReg;
960
961 typedef struct {
962 uint64_t base;
963 uint64_t mask;
964 } MTRRVar;
965
966 #define CPU_NB_REGS64 16
967 #define CPU_NB_REGS32 8
968
969 #ifdef TARGET_X86_64
970 #define CPU_NB_REGS CPU_NB_REGS64
971 #else
972 #define CPU_NB_REGS CPU_NB_REGS32
973 #endif
974
975 #define MAX_FIXED_COUNTERS 3
976 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
977
978 #define TARGET_INSN_START_EXTRA_WORDS 1
979
980 #define NB_OPMASK_REGS 8
981
982 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
983 * that APIC ID hasn't been set yet
984 */
985 #define UNASSIGNED_APIC_ID 0xFFFFFFFF
986
987 typedef union X86LegacyXSaveArea {
988 struct {
989 uint16_t fcw;
990 uint16_t fsw;
991 uint8_t ftw;
992 uint8_t reserved;
993 uint16_t fpop;
994 uint64_t fpip;
995 uint64_t fpdp;
996 uint32_t mxcsr;
997 uint32_t mxcsr_mask;
998 FPReg fpregs[8];
999 uint8_t xmm_regs[16][16];
1000 };
1001 uint8_t data[512];
1002 } X86LegacyXSaveArea;
1003
1004 typedef struct X86XSaveHeader {
1005 uint64_t xstate_bv;
1006 uint64_t xcomp_bv;
1007 uint64_t reserve0;
1008 uint8_t reserved[40];
1009 } X86XSaveHeader;
1010
1011 /* Ext. save area 2: AVX State */
1012 typedef struct XSaveAVX {
1013 uint8_t ymmh[16][16];
1014 } XSaveAVX;
1015
1016 /* Ext. save area 3: BNDREG */
1017 typedef struct XSaveBNDREG {
1018 BNDReg bnd_regs[4];
1019 } XSaveBNDREG;
1020
1021 /* Ext. save area 4: BNDCSR */
1022 typedef union XSaveBNDCSR {
1023 BNDCSReg bndcsr;
1024 uint8_t data[64];
1025 } XSaveBNDCSR;
1026
1027 /* Ext. save area 5: Opmask */
1028 typedef struct XSaveOpmask {
1029 uint64_t opmask_regs[NB_OPMASK_REGS];
1030 } XSaveOpmask;
1031
1032 /* Ext. save area 6: ZMM_Hi256 */
1033 typedef struct XSaveZMM_Hi256 {
1034 uint8_t zmm_hi256[16][32];
1035 } XSaveZMM_Hi256;
1036
1037 /* Ext. save area 7: Hi16_ZMM */
1038 typedef struct XSaveHi16_ZMM {
1039 uint8_t hi16_zmm[16][64];
1040 } XSaveHi16_ZMM;
1041
1042 /* Ext. save area 9: PKRU state */
1043 typedef struct XSavePKRU {
1044 uint32_t pkru;
1045 uint32_t padding;
1046 } XSavePKRU;
1047
1048 typedef struct X86XSaveArea {
1049 X86LegacyXSaveArea legacy;
1050 X86XSaveHeader header;
1051
1052 /* Extended save areas: */
1053
1054 /* AVX State: */
1055 XSaveAVX avx_state;
1056 uint8_t padding[960 - 576 - sizeof(XSaveAVX)];
1057 /* MPX State: */
1058 XSaveBNDREG bndreg_state;
1059 XSaveBNDCSR bndcsr_state;
1060 /* AVX-512 State: */
1061 XSaveOpmask opmask_state;
1062 XSaveZMM_Hi256 zmm_hi256_state;
1063 XSaveHi16_ZMM hi16_zmm_state;
1064 /* PKRU State: */
1065 XSavePKRU pkru_state;
1066 } X86XSaveArea;
1067
1068 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240);
1069 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1070 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0);
1071 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1072 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400);
1073 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1074 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440);
1075 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1076 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480);
1077 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1078 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680);
1079 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1080 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80);
1081 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1082
1083 typedef enum TPRAccess {
1084 TPR_ACCESS_READ,
1085 TPR_ACCESS_WRITE,
1086 } TPRAccess;
1087
1088 /* Cache information data structures: */
1089
1090 enum CacheType {
1091 DATA_CACHE,
1092 INSTRUCTION_CACHE,
1093 UNIFIED_CACHE
1094 };
1095
1096 typedef struct CPUCacheInfo {
1097 enum CacheType type;
1098 uint8_t level;
1099 /* Size in bytes */
1100 uint32_t size;
1101 /* Line size, in bytes */
1102 uint16_t line_size;
1103 /*
1104 * Associativity.
1105 * Note: representation of fully-associative caches is not implemented
1106 */
1107 uint8_t associativity;
1108 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
1109 uint8_t partitions;
1110 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
1111 uint32_t sets;
1112 /*
1113 * Lines per tag.
1114 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
1115 * (Is this synonym to @partitions?)
1116 */
1117 uint8_t lines_per_tag;
1118
1119 /* Self-initializing cache */
1120 bool self_init;
1121 /*
1122 * WBINVD/INVD is not guaranteed to act upon lower level caches of
1123 * non-originating threads sharing this cache.
1124 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
1125 */
1126 bool no_invd_sharing;
1127 /*
1128 * Cache is inclusive of lower cache levels.
1129 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
1130 */
1131 bool inclusive;
1132 /*
1133 * A complex function is used to index the cache, potentially using all
1134 * address bits. CPUID[4].EDX[bit 2].
1135 */
1136 bool complex_indexing;
1137 } CPUCacheInfo;
1138
1139
1140 typedef struct CPUCaches {
1141 CPUCacheInfo *l1d_cache;
1142 CPUCacheInfo *l1i_cache;
1143 CPUCacheInfo *l2_cache;
1144 CPUCacheInfo *l3_cache;
1145 } CPUCaches;
1146
1147 typedef struct CPUX86State {
1148 /* standard registers */
1149 target_ulong regs[CPU_NB_REGS];
1150 target_ulong eip;
1151 target_ulong eflags; /* eflags register. During CPU emulation, CC
1152 flags and DF are set to zero because they are
1153 stored elsewhere */
1154
1155 /* emulator internal eflags handling */
1156 target_ulong cc_dst;
1157 target_ulong cc_src;
1158 target_ulong cc_src2;
1159 uint32_t cc_op;
1160 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
1161 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
1162 are known at translation time. */
1163 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
1164
1165 /* segments */
1166 SegmentCache segs[6]; /* selector values */
1167 SegmentCache ldt;
1168 SegmentCache tr;
1169 SegmentCache gdt; /* only base and limit are used */
1170 SegmentCache idt; /* only base and limit are used */
1171
1172 target_ulong cr[5]; /* NOTE: cr1 is unused */
1173 int32_t a20_mask;
1174
1175 BNDReg bnd_regs[4];
1176 BNDCSReg bndcs_regs;
1177 uint64_t msr_bndcfgs;
1178 uint64_t efer;
1179
1180 /* Beginning of state preserved by INIT (dummy marker). */
1181 struct {} start_init_save;
1182
1183 /* FPU state */
1184 unsigned int fpstt; /* top of stack index */
1185 uint16_t fpus;
1186 uint16_t fpuc;
1187 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
1188 FPReg fpregs[8];
1189 /* KVM-only so far */
1190 uint16_t fpop;
1191 uint64_t fpip;
1192 uint64_t fpdp;
1193
1194 /* emulator internal variables */
1195 float_status fp_status;
1196 floatx80 ft0;
1197
1198 float_status mmx_status; /* for 3DNow! float ops */
1199 float_status sse_status;
1200 uint32_t mxcsr;
1201 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
1202 ZMMReg xmm_t0;
1203 MMXReg mmx_t0;
1204
1205 XMMReg ymmh_regs[CPU_NB_REGS];
1206
1207 uint64_t opmask_regs[NB_OPMASK_REGS];
1208 YMMReg zmmh_regs[CPU_NB_REGS];
1209 ZMMReg hi16_zmm_regs[CPU_NB_REGS];
1210
1211 /* sysenter registers */
1212 uint32_t sysenter_cs;
1213 target_ulong sysenter_esp;
1214 target_ulong sysenter_eip;
1215 uint64_t star;
1216
1217 uint64_t vm_hsave;
1218
1219 #ifdef TARGET_X86_64
1220 target_ulong lstar;
1221 target_ulong cstar;
1222 target_ulong fmask;
1223 target_ulong kernelgsbase;
1224 #endif
1225
1226 uint64_t tsc;
1227 uint64_t tsc_adjust;
1228 uint64_t tsc_deadline;
1229 uint64_t tsc_aux;
1230
1231 uint64_t xcr0;
1232
1233 uint64_t mcg_status;
1234 uint64_t msr_ia32_misc_enable;
1235 uint64_t msr_ia32_feature_control;
1236
1237 uint64_t msr_fixed_ctr_ctrl;
1238 uint64_t msr_global_ctrl;
1239 uint64_t msr_global_status;
1240 uint64_t msr_global_ovf_ctrl;
1241 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1242 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1243 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1244
1245 uint64_t pat;
1246 uint32_t smbase;
1247 uint64_t msr_smi_count;
1248
1249 uint32_t pkru;
1250
1251 uint64_t spec_ctrl;
1252 uint64_t virt_ssbd;
1253
1254 /* End of state preserved by INIT (dummy marker). */
1255 struct {} end_init_save;
1256
1257 uint64_t system_time_msr;
1258 uint64_t wall_clock_msr;
1259 uint64_t steal_time_msr;
1260 uint64_t async_pf_en_msr;
1261 uint64_t pv_eoi_en_msr;
1262
1263 /* Partition-wide HV MSRs, will be updated only on the first vcpu */
1264 uint64_t msr_hv_hypercall;
1265 uint64_t msr_hv_guest_os_id;
1266 uint64_t msr_hv_tsc;
1267
1268 /* Per-VCPU HV MSRs */
1269 uint64_t msr_hv_vapic;
1270 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1271 uint64_t msr_hv_runtime;
1272 uint64_t msr_hv_synic_control;
1273 uint64_t msr_hv_synic_evt_page;
1274 uint64_t msr_hv_synic_msg_page;
1275 uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
1276 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
1277 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1278 uint64_t msr_hv_reenlightenment_control;
1279 uint64_t msr_hv_tsc_emulation_control;
1280 uint64_t msr_hv_tsc_emulation_status;
1281
1282 uint64_t msr_rtit_ctrl;
1283 uint64_t msr_rtit_status;
1284 uint64_t msr_rtit_output_base;
1285 uint64_t msr_rtit_output_mask;
1286 uint64_t msr_rtit_cr3_match;
1287 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
1288
1289 /* exception/interrupt handling */
1290 int error_code;
1291 int exception_is_int;
1292 target_ulong exception_next_eip;
1293 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */
1294 union {
1295 struct CPUBreakpoint *cpu_breakpoint[4];
1296 struct CPUWatchpoint *cpu_watchpoint[4];
1297 }; /* break/watchpoints for dr[0..3] */
1298 int old_exception; /* exception in flight */
1299
1300 uint64_t vm_vmcb;
1301 uint64_t tsc_offset;
1302 uint64_t intercept;
1303 uint16_t intercept_cr_read;
1304 uint16_t intercept_cr_write;
1305 uint16_t intercept_dr_read;
1306 uint16_t intercept_dr_write;
1307 uint32_t intercept_exceptions;
1308 uint64_t nested_cr3;
1309 uint32_t nested_pg_mode;
1310 uint8_t v_tpr;
1311
1312 /* KVM states, automatically cleared on reset */
1313 uint8_t nmi_injected;
1314 uint8_t nmi_pending;
1315
1316 uintptr_t retaddr;
1317
1318 /* Fields up to this point are cleared by a CPU reset */
1319 struct {} end_reset_fields;
1320
1321 /* Fields after this point are preserved across CPU reset. */
1322
1323 /* processor features (e.g. for CPUID insn) */
1324 /* Minimum level/xlevel/xlevel2, based on CPU model + features */
1325 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1326 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */
1327 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1328 /* Actual level/xlevel/xlevel2 value: */
1329 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1330 uint32_t cpuid_vendor1;
1331 uint32_t cpuid_vendor2;
1332 uint32_t cpuid_vendor3;
1333 uint32_t cpuid_version;
1334 FeatureWordArray features;
1335 /* Features that were explicitly enabled/disabled */
1336 FeatureWordArray user_features;
1337 uint32_t cpuid_model[12];
1338 /* Cache information for CPUID. When legacy-cache=on, the cache data
1339 * on each CPUID leaf will be different, because we keep compatibility
1340 * with old QEMU versions.
1341 */
1342 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
1343
1344 /* MTRRs */
1345 uint64_t mtrr_fixed[11];
1346 uint64_t mtrr_deftype;
1347 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1348
1349 /* For KVM */
1350 uint32_t mp_state;
1351 int32_t exception_nr;
1352 int32_t interrupt_injected;
1353 uint8_t soft_interrupt;
1354 uint8_t exception_pending;
1355 uint8_t exception_injected;
1356 uint8_t has_error_code;
1357 uint8_t exception_has_payload;
1358 uint64_t exception_payload;
1359 uint32_t ins_len;
1360 uint32_t sipi_vector;
1361 bool tsc_valid;
1362 int64_t tsc_khz;
1363 int64_t user_tsc_khz; /* for sanity check only */
1364 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1365 void *xsave_buf;
1366 #endif
1367 #if defined(CONFIG_KVM)
1368 struct kvm_nested_state *nested_state;
1369 #endif
1370 #if defined(CONFIG_HVF)
1371 HVFX86EmulatorState *hvf_emul;
1372 #endif
1373
1374 uint64_t mcg_cap;
1375 uint64_t mcg_ctl;
1376 uint64_t mcg_ext_ctl;
1377 uint64_t mce_banks[MCE_BANKS_DEF*4];
1378 uint64_t xstate_bv;
1379
1380 /* vmstate */
1381 uint16_t fpus_vmstate;
1382 uint16_t fptag_vmstate;
1383 uint16_t fpregs_format_vmstate;
1384
1385 uint64_t xss;
1386
1387 TPRAccess tpr_access_type;
1388
1389 unsigned nr_dies;
1390 } CPUX86State;
1391
1392 struct kvm_msrs;
1393
1394 /**
1395 * X86CPU:
1396 * @env: #CPUX86State
1397 * @migratable: If set, only migratable flags will be accepted when "enforce"
1398 * mode is used, and only migratable flags will be included in the "host"
1399 * CPU model.
1400 *
1401 * An x86 CPU.
1402 */
1403 struct X86CPU {
1404 /*< private >*/
1405 CPUState parent_obj;
1406 /*< public >*/
1407
1408 CPUNegativeOffsetState neg;
1409 CPUX86State env;
1410
1411 int hyperv_spinlock_attempts;
1412 char *hyperv_vendor_id;
1413 bool hyperv_synic_kvm_only;
1414 uint64_t hyperv_features;
1415 bool hyperv_passthrough;
1416
1417 bool check_cpuid;
1418 bool enforce_cpuid;
1419 bool expose_kvm;
1420 bool expose_tcg;
1421 bool migratable;
1422 bool migrate_smi_count;
1423 bool max_features; /* Enable all supported features automatically */
1424 uint32_t apic_id;
1425
1426 /* Enables publishing of TSC increment and Local APIC bus frequencies to
1427 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */
1428 bool vmware_cpuid_freq;
1429
1430 /* if true the CPUID code directly forward host cache leaves to the guest */
1431 bool cache_info_passthrough;
1432
1433 /* if true the CPUID code directly forwards
1434 * host monitor/mwait leaves to the guest */
1435 struct {
1436 uint32_t eax;
1437 uint32_t ebx;
1438 uint32_t ecx;
1439 uint32_t edx;
1440 } mwait;
1441
1442 /* Features that were filtered out because of missing host capabilities */
1443 uint32_t filtered_features[FEATURE_WORDS];
1444
1445 /* Enable PMU CPUID bits. This can't be enabled by default yet because
1446 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
1447 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
1448 * capabilities) directly to the guest.
1449 */
1450 bool enable_pmu;
1451
1452 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
1453 * disabled by default to avoid breaking migration between QEMU with
1454 * different LMCE configurations.
1455 */
1456 bool enable_lmce;
1457
1458 /* Compatibility bits for old machine types.
1459 * If true present virtual l3 cache for VM, the vcpus in the same virtual
1460 * socket share an virtual l3 cache.
1461 */
1462 bool enable_l3_cache;
1463
1464 /* Compatibility bits for old machine types.
1465 * If true present the old cache topology information
1466 */
1467 bool legacy_cache;
1468
1469 /* Compatibility bits for old machine types: */
1470 bool enable_cpuid_0xb;
1471
1472 /* Enable auto level-increase for all CPUID leaves */
1473 bool full_cpuid_auto_level;
1474
1475 /* Enable auto level-increase for Intel Processor Trace leave */
1476 bool intel_pt_auto_level;
1477
1478 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */
1479 bool fill_mtrr_mask;
1480
1481 /* if true override the phys_bits value with a value read from the host */
1482 bool host_phys_bits;
1483
1484 /* if set, limit maximum value for phys_bits when host_phys_bits is true */
1485 uint8_t host_phys_bits_limit;
1486
1487 /* Stop SMI delivery for migration compatibility with old machines */
1488 bool kvm_no_smi_migration;
1489
1490 /* Number of physical address bits supported */
1491 uint32_t phys_bits;
1492
1493 /* in order to simplify APIC support, we leave this pointer to the
1494 user */
1495 struct DeviceState *apic_state;
1496 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
1497 Notifier machine_done;
1498
1499 struct kvm_msrs *kvm_msr_buf;
1500
1501 int32_t node_id; /* NUMA node this CPU belongs to */
1502 int32_t socket_id;
1503 int32_t die_id;
1504 int32_t core_id;
1505 int32_t thread_id;
1506
1507 int32_t hv_max_vps;
1508 };
1509
1510
1511 #ifndef CONFIG_USER_ONLY
1512 extern struct VMStateDescription vmstate_x86_cpu;
1513 #endif
1514
1515 /**
1516 * x86_cpu_do_interrupt:
1517 * @cpu: vCPU the interrupt is to be handled by.
1518 */
1519 void x86_cpu_do_interrupt(CPUState *cpu);
1520 bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
1521 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
1522
1523 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
1524 int cpuid, void *opaque);
1525 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
1526 int cpuid, void *opaque);
1527 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1528 void *opaque);
1529 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1530 void *opaque);
1531
1532 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
1533 Error **errp);
1534
1535 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags);
1536
1537 hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1538
1539 int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1540 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1541
1542 void x86_cpu_exec_enter(CPUState *cpu);
1543 void x86_cpu_exec_exit(CPUState *cpu);
1544
1545 void x86_cpu_list(void);
1546 int cpu_x86_support_mca_broadcast(CPUX86State *env);
1547
1548 int cpu_get_pic_interrupt(CPUX86State *s);
1549 /* MSDOS compatibility mode FPU exception support */
1550 void cpu_set_ferr(CPUX86State *s);
1551 /* mpx_helper.c */
1552 void cpu_sync_bndcs_hflags(CPUX86State *env);
1553
1554 /* this function must always be used to load data in the segment
1555 cache: it synchronizes the hflags with the segment cache values */
1556 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
1557 int seg_reg, unsigned int selector,
1558 target_ulong base,
1559 unsigned int limit,
1560 unsigned int flags)
1561 {
1562 SegmentCache *sc;
1563 unsigned int new_hflags;
1564
1565 sc = &env->segs[seg_reg];
1566 sc->selector = selector;
1567 sc->base = base;
1568 sc->limit = limit;
1569 sc->flags = flags;
1570
1571 /* update the hidden flags */
1572 {
1573 if (seg_reg == R_CS) {
1574 #ifdef TARGET_X86_64
1575 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
1576 /* long mode */
1577 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1578 env->hflags &= ~(HF_ADDSEG_MASK);
1579 } else
1580 #endif
1581 {
1582 /* legacy / compatibility case */
1583 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
1584 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
1585 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
1586 new_hflags;
1587 }
1588 }
1589 if (seg_reg == R_SS) {
1590 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
1591 #if HF_CPL_MASK != 3
1592 #error HF_CPL_MASK is hardcoded
1593 #endif
1594 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
1595 /* Possibly switch between BNDCFGS and BNDCFGU */
1596 cpu_sync_bndcs_hflags(env);
1597 }
1598 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
1599 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
1600 if (env->hflags & HF_CS64_MASK) {
1601 /* zero base assumed for DS, ES and SS in long mode */
1602 } else if (!(env->cr[0] & CR0_PE_MASK) ||
1603 (env->eflags & VM_MASK) ||
1604 !(env->hflags & HF_CS32_MASK)) {
1605 /* XXX: try to avoid this test. The problem comes from the
1606 fact that is real mode or vm86 mode we only modify the
1607 'base' and 'selector' fields of the segment cache to go
1608 faster. A solution may be to force addseg to one in
1609 translate-i386.c. */
1610 new_hflags |= HF_ADDSEG_MASK;
1611 } else {
1612 new_hflags |= ((env->segs[R_DS].base |
1613 env->segs[R_ES].base |
1614 env->segs[R_SS].base) != 0) <<
1615 HF_ADDSEG_SHIFT;
1616 }
1617 env->hflags = (env->hflags &
1618 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
1619 }
1620 }
1621
1622 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
1623 uint8_t sipi_vector)
1624 {
1625 CPUState *cs = CPU(cpu);
1626 CPUX86State *env = &cpu->env;
1627
1628 env->eip = 0;
1629 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
1630 sipi_vector << 12,
1631 env->segs[R_CS].limit,
1632 env->segs[R_CS].flags);
1633 cs->halted = 0;
1634 }
1635
1636 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1637 target_ulong *base, unsigned int *limit,
1638 unsigned int *flags);
1639
1640 /* op_helper.c */
1641 /* used for debug or cpu save/restore */
1642
1643 /* cpu-exec.c */
1644 /* the following helpers are only usable in user mode simulation as
1645 they can trigger unexpected exceptions */
1646 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1647 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1648 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1649 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr);
1650 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr);
1651
1652 /* you can call this signal handler from your SIGBUS and SIGSEGV
1653 signal handlers to inform the virtual CPU of exceptions. non zero
1654 is returned if the signal was handled by the virtual CPU. */
1655 int cpu_x86_signal_handler(int host_signum, void *pinfo,
1656 void *puc);
1657
1658 /* cpu.c */
1659 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1660 uint32_t *eax, uint32_t *ebx,
1661 uint32_t *ecx, uint32_t *edx);
1662 void cpu_clear_apic_feature(CPUX86State *env);
1663 void host_cpuid(uint32_t function, uint32_t count,
1664 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1665 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
1666
1667 /* helper.c */
1668 bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
1669 MMUAccessType access_type, int mmu_idx,
1670 bool probe, uintptr_t retaddr);
1671 void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1672
1673 #ifndef CONFIG_USER_ONLY
1674 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
1675 {
1676 return !!attrs.secure;
1677 }
1678
1679 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
1680 {
1681 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
1682 }
1683
1684 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
1685 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
1686 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
1687 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
1688 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
1689 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
1690 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
1691 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
1692 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
1693 #endif
1694
1695 void breakpoint_handler(CPUState *cs);
1696
1697 /* will be suppressed */
1698 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1699 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1700 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1701 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
1702
1703 /* hw/pc.c */
1704 uint64_t cpu_get_tsc(CPUX86State *env);
1705
1706 /* XXX: This value should match the one returned by CPUID
1707 * and in exec.c */
1708 # if defined(TARGET_X86_64)
1709 # define TCG_PHYS_ADDR_BITS 40
1710 # else
1711 # define TCG_PHYS_ADDR_BITS 36
1712 # endif
1713
1714 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
1715
1716 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
1717 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
1718 #define CPU_RESOLVING_TYPE TYPE_X86_CPU
1719
1720 #ifdef TARGET_X86_64
1721 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
1722 #else
1723 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
1724 #endif
1725
1726 #define cpu_signal_handler cpu_x86_signal_handler
1727 #define cpu_list x86_cpu_list
1728
1729 /* MMU modes definitions */
1730 #define MMU_MODE0_SUFFIX _ksmap
1731 #define MMU_MODE1_SUFFIX _user
1732 #define MMU_MODE2_SUFFIX _knosmap /* SMAP disabled or CPL<3 && AC=1 */
1733 #define MMU_KSMAP_IDX 0
1734 #define MMU_USER_IDX 1
1735 #define MMU_KNOSMAP_IDX 2
1736 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
1737 {
1738 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1739 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
1740 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1741 }
1742
1743 static inline int cpu_mmu_index_kernel(CPUX86State *env)
1744 {
1745 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
1746 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
1747 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1748 }
1749
1750 #define CC_DST (env->cc_dst)
1751 #define CC_SRC (env->cc_src)
1752 #define CC_SRC2 (env->cc_src2)
1753 #define CC_OP (env->cc_op)
1754
1755 /* n must be a constant to be efficient */
1756 static inline target_long lshift(target_long x, int n)
1757 {
1758 if (n >= 0) {
1759 return x << n;
1760 } else {
1761 return x >> (-n);
1762 }
1763 }
1764
1765 /* float macros */
1766 #define FT0 (env->ft0)
1767 #define ST0 (env->fpregs[env->fpstt].d)
1768 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
1769 #define ST1 ST(1)
1770
1771 /* translate.c */
1772 void tcg_x86_init(void);
1773
1774 typedef CPUX86State CPUArchState;
1775 typedef X86CPU ArchCPU;
1776
1777 #include "exec/cpu-all.h"
1778 #include "svm.h"
1779
1780 #if !defined(CONFIG_USER_ONLY)
1781 #include "hw/i386/apic.h"
1782 #endif
1783
1784 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
1785 target_ulong *cs_base, uint32_t *flags)
1786 {
1787 *cs_base = env->segs[R_CS].base;
1788 *pc = *cs_base + env->eip;
1789 *flags = env->hflags |
1790 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
1791 }
1792
1793 void do_cpu_init(X86CPU *cpu);
1794 void do_cpu_sipi(X86CPU *cpu);
1795
1796 #define MCE_INJECT_BROADCAST 1
1797 #define MCE_INJECT_UNCOND_AO 2
1798
1799 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
1800 uint64_t status, uint64_t mcg_status, uint64_t addr,
1801 uint64_t misc, int flags);
1802
1803 /* excp_helper.c */
1804 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
1805 void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
1806 uintptr_t retaddr);
1807 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
1808 int error_code);
1809 void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
1810 int error_code, uintptr_t retaddr);
1811 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
1812 int error_code, int next_eip_addend);
1813
1814 /* cc_helper.c */
1815 extern const uint8_t parity_table[256];
1816 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
1817
1818 static inline uint32_t cpu_compute_eflags(CPUX86State *env)
1819 {
1820 uint32_t eflags = env->eflags;
1821 if (tcg_enabled()) {
1822 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
1823 }
1824 return eflags;
1825 }
1826
1827 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
1828 * after generating a call to a helper that uses this.
1829 */
1830 static inline void cpu_load_eflags(CPUX86State *env, int eflags,
1831 int update_mask)
1832 {
1833 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1834 CC_OP = CC_OP_EFLAGS;
1835 env->df = 1 - (2 * ((eflags >> 10) & 1));
1836 env->eflags = (env->eflags & ~update_mask) |
1837 (eflags & update_mask) | 0x2;
1838 }
1839
1840 /* load efer and update the corresponding hflags. XXX: do consistency
1841 checks with cpuid bits? */
1842 static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
1843 {
1844 env->efer = val;
1845 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
1846 if (env->efer & MSR_EFER_LMA) {
1847 env->hflags |= HF_LMA_MASK;
1848 }
1849 if (env->efer & MSR_EFER_SVME) {
1850 env->hflags |= HF_SVME_MASK;
1851 }
1852 }
1853
1854 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
1855 {
1856 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
1857 }
1858
1859 static inline int32_t x86_get_a20_mask(CPUX86State *env)
1860 {
1861 if (env->hflags & HF_SMM_MASK) {
1862 return -1;
1863 } else {
1864 return env->a20_mask;
1865 }
1866 }
1867
1868 static inline bool cpu_has_vmx(CPUX86State *env)
1869 {
1870 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX;
1871 }
1872
1873 /* fpu_helper.c */
1874 void update_fp_status(CPUX86State *env);
1875 void update_mxcsr_status(CPUX86State *env);
1876
1877 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
1878 {
1879 env->mxcsr = mxcsr;
1880 if (tcg_enabled()) {
1881 update_mxcsr_status(env);
1882 }
1883 }
1884
1885 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
1886 {
1887 env->fpuc = fpuc;
1888 if (tcg_enabled()) {
1889 update_fp_status(env);
1890 }
1891 }
1892
1893 /* mem_helper.c */
1894 void helper_lock_init(void);
1895
1896 /* svm_helper.c */
1897 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
1898 uint64_t param, uintptr_t retaddr);
1899 void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
1900 uint64_t exit_info_1, uintptr_t retaddr);
1901 void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
1902
1903 /* seg_helper.c */
1904 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
1905
1906 /* smm_helper.c */
1907 void do_smm_enter(X86CPU *cpu);
1908
1909 /* apic.c */
1910 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
1911 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
1912 TPRAccess access);
1913
1914
1915 /* Change the value of a KVM-specific default
1916 *
1917 * If value is NULL, no default will be set and the original
1918 * value from the CPU model table will be kept.
1919 *
1920 * It is valid to call this function only for properties that
1921 * are already present in the kvm_default_props table.
1922 */
1923 void x86_cpu_change_kvm_default(const char *prop, const char *value);
1924
1925 /* Return name of 32-bit register, from a R_* constant */
1926 const char *get_register_name_32(unsigned int reg);
1927
1928 void enable_compat_apic_id_mode(void);
1929
1930 #define APIC_DEFAULT_ADDRESS 0xfee00000
1931 #define APIC_SPACE_SIZE 0x100000
1932
1933 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
1934
1935 /* cpu.c */
1936 bool cpu_is_bsp(X86CPU *cpu);
1937
1938 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf);
1939 void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf);
1940 void x86_update_hflags(CPUX86State* env);
1941
1942 static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat)
1943 {
1944 return !!(cpu->hyperv_features & BIT(feat));
1945 }
1946
1947 #endif /* I386_CPU_H */