i386: Introduce use_epyc_apic_id_encoding in X86CPUDefinition
[qemu.git] / target / i386 / cpu.h
1 /*
2 * i386 virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef I386_CPU_H
21 #define I386_CPU_H
22
23 #include "sysemu/tcg.h"
24 #include "cpu-qom.h"
25 #include "hyperv-proto.h"
26 #include "exec/cpu-defs.h"
27 #include "qapi/qapi-types-common.h"
28
29 /* The x86 has a strong memory model with some store-after-load re-ordering */
30 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
31
32 /* Maximum instruction code size */
33 #define TARGET_MAX_INSN_SIZE 16
34
35 /* support for self modifying code even if the modified instruction is
36 close to the modifying instruction */
37 #define TARGET_HAS_PRECISE_SMC
38
39 #ifdef TARGET_X86_64
40 #define I386_ELF_MACHINE EM_X86_64
41 #define ELF_MACHINE_UNAME "x86_64"
42 #else
43 #define I386_ELF_MACHINE EM_386
44 #define ELF_MACHINE_UNAME "i686"
45 #endif
46
47 enum {
48 R_EAX = 0,
49 R_ECX = 1,
50 R_EDX = 2,
51 R_EBX = 3,
52 R_ESP = 4,
53 R_EBP = 5,
54 R_ESI = 6,
55 R_EDI = 7,
56 R_R8 = 8,
57 R_R9 = 9,
58 R_R10 = 10,
59 R_R11 = 11,
60 R_R12 = 12,
61 R_R13 = 13,
62 R_R14 = 14,
63 R_R15 = 15,
64
65 R_AL = 0,
66 R_CL = 1,
67 R_DL = 2,
68 R_BL = 3,
69 R_AH = 4,
70 R_CH = 5,
71 R_DH = 6,
72 R_BH = 7,
73 };
74
75 typedef enum X86Seg {
76 R_ES = 0,
77 R_CS = 1,
78 R_SS = 2,
79 R_DS = 3,
80 R_FS = 4,
81 R_GS = 5,
82 R_LDTR = 6,
83 R_TR = 7,
84 } X86Seg;
85
86 /* segment descriptor fields */
87 #define DESC_G_SHIFT 23
88 #define DESC_G_MASK (1 << DESC_G_SHIFT)
89 #define DESC_B_SHIFT 22
90 #define DESC_B_MASK (1 << DESC_B_SHIFT)
91 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
92 #define DESC_L_MASK (1 << DESC_L_SHIFT)
93 #define DESC_AVL_SHIFT 20
94 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT)
95 #define DESC_P_SHIFT 15
96 #define DESC_P_MASK (1 << DESC_P_SHIFT)
97 #define DESC_DPL_SHIFT 13
98 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
99 #define DESC_S_SHIFT 12
100 #define DESC_S_MASK (1 << DESC_S_SHIFT)
101 #define DESC_TYPE_SHIFT 8
102 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
103 #define DESC_A_MASK (1 << 8)
104
105 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
106 #define DESC_C_MASK (1 << 10) /* code: conforming */
107 #define DESC_R_MASK (1 << 9) /* code: readable */
108
109 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
110 #define DESC_W_MASK (1 << 9) /* data: writable */
111
112 #define DESC_TSS_BUSY_MASK (1 << 9)
113
114 /* eflags masks */
115 #define CC_C 0x0001
116 #define CC_P 0x0004
117 #define CC_A 0x0010
118 #define CC_Z 0x0040
119 #define CC_S 0x0080
120 #define CC_O 0x0800
121
122 #define TF_SHIFT 8
123 #define IOPL_SHIFT 12
124 #define VM_SHIFT 17
125
126 #define TF_MASK 0x00000100
127 #define IF_MASK 0x00000200
128 #define DF_MASK 0x00000400
129 #define IOPL_MASK 0x00003000
130 #define NT_MASK 0x00004000
131 #define RF_MASK 0x00010000
132 #define VM_MASK 0x00020000
133 #define AC_MASK 0x00040000
134 #define VIF_MASK 0x00080000
135 #define VIP_MASK 0x00100000
136 #define ID_MASK 0x00200000
137
138 /* hidden flags - used internally by qemu to represent additional cpu
139 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
140 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
141 positions to ease oring with eflags. */
142 /* current cpl */
143 #define HF_CPL_SHIFT 0
144 /* true if hardware interrupts must be disabled for next instruction */
145 #define HF_INHIBIT_IRQ_SHIFT 3
146 /* 16 or 32 segments */
147 #define HF_CS32_SHIFT 4
148 #define HF_SS32_SHIFT 5
149 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
150 #define HF_ADDSEG_SHIFT 6
151 /* copy of CR0.PE (protected mode) */
152 #define HF_PE_SHIFT 7
153 #define HF_TF_SHIFT 8 /* must be same as eflags */
154 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
155 #define HF_EM_SHIFT 10
156 #define HF_TS_SHIFT 11
157 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
158 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
159 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
160 #define HF_RF_SHIFT 16 /* must be same as eflags */
161 #define HF_VM_SHIFT 17 /* must be same as eflags */
162 #define HF_AC_SHIFT 18 /* must be same as eflags */
163 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */
164 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
165 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */
166 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
167 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */
168 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */
169 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */
170 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */
171
172 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
173 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
174 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
175 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
176 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
177 #define HF_PE_MASK (1 << HF_PE_SHIFT)
178 #define HF_TF_MASK (1 << HF_TF_SHIFT)
179 #define HF_MP_MASK (1 << HF_MP_SHIFT)
180 #define HF_EM_MASK (1 << HF_EM_SHIFT)
181 #define HF_TS_MASK (1 << HF_TS_SHIFT)
182 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
183 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
184 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
185 #define HF_RF_MASK (1 << HF_RF_SHIFT)
186 #define HF_VM_MASK (1 << HF_VM_SHIFT)
187 #define HF_AC_MASK (1 << HF_AC_SHIFT)
188 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
189 #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
190 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT)
191 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
192 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
193 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
194 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
195 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
196
197 /* hflags2 */
198
199 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
200 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
201 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */
202 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
203 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
204 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */
205 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */
206 #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */
207
208 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
209 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
210 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
211 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
212 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
213 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
214 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
215 #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT)
216
217 #define CR0_PE_SHIFT 0
218 #define CR0_MP_SHIFT 1
219
220 #define CR0_PE_MASK (1U << 0)
221 #define CR0_MP_MASK (1U << 1)
222 #define CR0_EM_MASK (1U << 2)
223 #define CR0_TS_MASK (1U << 3)
224 #define CR0_ET_MASK (1U << 4)
225 #define CR0_NE_MASK (1U << 5)
226 #define CR0_WP_MASK (1U << 16)
227 #define CR0_AM_MASK (1U << 18)
228 #define CR0_PG_MASK (1U << 31)
229
230 #define CR4_VME_MASK (1U << 0)
231 #define CR4_PVI_MASK (1U << 1)
232 #define CR4_TSD_MASK (1U << 2)
233 #define CR4_DE_MASK (1U << 3)
234 #define CR4_PSE_MASK (1U << 4)
235 #define CR4_PAE_MASK (1U << 5)
236 #define CR4_MCE_MASK (1U << 6)
237 #define CR4_PGE_MASK (1U << 7)
238 #define CR4_PCE_MASK (1U << 8)
239 #define CR4_OSFXSR_SHIFT 9
240 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
241 #define CR4_OSXMMEXCPT_MASK (1U << 10)
242 #define CR4_LA57_MASK (1U << 12)
243 #define CR4_VMXE_MASK (1U << 13)
244 #define CR4_SMXE_MASK (1U << 14)
245 #define CR4_FSGSBASE_MASK (1U << 16)
246 #define CR4_PCIDE_MASK (1U << 17)
247 #define CR4_OSXSAVE_MASK (1U << 18)
248 #define CR4_SMEP_MASK (1U << 20)
249 #define CR4_SMAP_MASK (1U << 21)
250 #define CR4_PKE_MASK (1U << 22)
251
252 #define DR6_BD (1 << 13)
253 #define DR6_BS (1 << 14)
254 #define DR6_BT (1 << 15)
255 #define DR6_FIXED_1 0xffff0ff0
256
257 #define DR7_GD (1 << 13)
258 #define DR7_TYPE_SHIFT 16
259 #define DR7_LEN_SHIFT 18
260 #define DR7_FIXED_1 0x00000400
261 #define DR7_GLOBAL_BP_MASK 0xaa
262 #define DR7_LOCAL_BP_MASK 0x55
263 #define DR7_MAX_BP 4
264 #define DR7_TYPE_BP_INST 0x0
265 #define DR7_TYPE_DATA_WR 0x1
266 #define DR7_TYPE_IO_RW 0x2
267 #define DR7_TYPE_DATA_RW 0x3
268
269 #define PG_PRESENT_BIT 0
270 #define PG_RW_BIT 1
271 #define PG_USER_BIT 2
272 #define PG_PWT_BIT 3
273 #define PG_PCD_BIT 4
274 #define PG_ACCESSED_BIT 5
275 #define PG_DIRTY_BIT 6
276 #define PG_PSE_BIT 7
277 #define PG_GLOBAL_BIT 8
278 #define PG_PSE_PAT_BIT 12
279 #define PG_PKRU_BIT 59
280 #define PG_NX_BIT 63
281
282 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
283 #define PG_RW_MASK (1 << PG_RW_BIT)
284 #define PG_USER_MASK (1 << PG_USER_BIT)
285 #define PG_PWT_MASK (1 << PG_PWT_BIT)
286 #define PG_PCD_MASK (1 << PG_PCD_BIT)
287 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
288 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
289 #define PG_PSE_MASK (1 << PG_PSE_BIT)
290 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
291 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
292 #define PG_ADDRESS_MASK 0x000ffffffffff000LL
293 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
294 #define PG_HI_USER_MASK 0x7ff0000000000000LL
295 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
296 #define PG_NX_MASK (1ULL << PG_NX_BIT)
297
298 #define PG_ERROR_W_BIT 1
299
300 #define PG_ERROR_P_MASK 0x01
301 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
302 #define PG_ERROR_U_MASK 0x04
303 #define PG_ERROR_RSVD_MASK 0x08
304 #define PG_ERROR_I_D_MASK 0x10
305 #define PG_ERROR_PK_MASK 0x20
306
307 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
308 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
309 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */
310
311 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
312 #define MCE_BANKS_DEF 10
313
314 #define MCG_CAP_BANKS_MASK 0xff
315
316 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
317 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
318 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
319 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */
320
321 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
322
323 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
324 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
325 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
326 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
327 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
328 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
329 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
330 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
331 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
332
333 /* MISC register defines */
334 #define MCM_ADDR_SEGOFF 0 /* segment offset */
335 #define MCM_ADDR_LINEAR 1 /* linear address */
336 #define MCM_ADDR_PHYS 2 /* physical address */
337 #define MCM_ADDR_MEM 3 /* memory address */
338 #define MCM_ADDR_GENERIC 7 /* generic */
339
340 #define MSR_IA32_TSC 0x10
341 #define MSR_IA32_APICBASE 0x1b
342 #define MSR_IA32_APICBASE_BSP (1<<8)
343 #define MSR_IA32_APICBASE_ENABLE (1<<11)
344 #define MSR_IA32_APICBASE_EXTD (1 << 10)
345 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
346 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
347 #define MSR_TSC_ADJUST 0x0000003b
348 #define MSR_IA32_SPEC_CTRL 0x48
349 #define MSR_VIRT_SSBD 0xc001011f
350 #define MSR_IA32_PRED_CMD 0x49
351 #define MSR_IA32_UCODE_REV 0x8b
352 #define MSR_IA32_CORE_CAPABILITY 0xcf
353
354 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
355 #define ARCH_CAP_TSX_CTRL_MSR (1<<7)
356
357 #define MSR_IA32_TSX_CTRL 0x122
358 #define MSR_IA32_TSCDEADLINE 0x6e0
359
360 #define FEATURE_CONTROL_LOCKED (1<<0)
361 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
362 #define FEATURE_CONTROL_LMCE (1<<20)
363
364 #define MSR_P6_PERFCTR0 0xc1
365
366 #define MSR_IA32_SMBASE 0x9e
367 #define MSR_SMI_COUNT 0x34
368 #define MSR_MTRRcap 0xfe
369 #define MSR_MTRRcap_VCNT 8
370 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
371 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
372
373 #define MSR_IA32_SYSENTER_CS 0x174
374 #define MSR_IA32_SYSENTER_ESP 0x175
375 #define MSR_IA32_SYSENTER_EIP 0x176
376
377 #define MSR_MCG_CAP 0x179
378 #define MSR_MCG_STATUS 0x17a
379 #define MSR_MCG_CTL 0x17b
380 #define MSR_MCG_EXT_CTL 0x4d0
381
382 #define MSR_P6_EVNTSEL0 0x186
383
384 #define MSR_IA32_PERF_STATUS 0x198
385
386 #define MSR_IA32_MISC_ENABLE 0x1a0
387 /* Indicates good rep/movs microcode on some processors: */
388 #define MSR_IA32_MISC_ENABLE_DEFAULT 1
389 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
390
391 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
392 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
393
394 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
395
396 #define MSR_MTRRfix64K_00000 0x250
397 #define MSR_MTRRfix16K_80000 0x258
398 #define MSR_MTRRfix16K_A0000 0x259
399 #define MSR_MTRRfix4K_C0000 0x268
400 #define MSR_MTRRfix4K_C8000 0x269
401 #define MSR_MTRRfix4K_D0000 0x26a
402 #define MSR_MTRRfix4K_D8000 0x26b
403 #define MSR_MTRRfix4K_E0000 0x26c
404 #define MSR_MTRRfix4K_E8000 0x26d
405 #define MSR_MTRRfix4K_F0000 0x26e
406 #define MSR_MTRRfix4K_F8000 0x26f
407
408 #define MSR_PAT 0x277
409
410 #define MSR_MTRRdefType 0x2ff
411
412 #define MSR_CORE_PERF_FIXED_CTR0 0x309
413 #define MSR_CORE_PERF_FIXED_CTR1 0x30a
414 #define MSR_CORE_PERF_FIXED_CTR2 0x30b
415 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
416 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
417 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
418 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
419
420 #define MSR_MC0_CTL 0x400
421 #define MSR_MC0_STATUS 0x401
422 #define MSR_MC0_ADDR 0x402
423 #define MSR_MC0_MISC 0x403
424
425 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560
426 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561
427 #define MSR_IA32_RTIT_CTL 0x570
428 #define MSR_IA32_RTIT_STATUS 0x571
429 #define MSR_IA32_RTIT_CR3_MATCH 0x572
430 #define MSR_IA32_RTIT_ADDR0_A 0x580
431 #define MSR_IA32_RTIT_ADDR0_B 0x581
432 #define MSR_IA32_RTIT_ADDR1_A 0x582
433 #define MSR_IA32_RTIT_ADDR1_B 0x583
434 #define MSR_IA32_RTIT_ADDR2_A 0x584
435 #define MSR_IA32_RTIT_ADDR2_B 0x585
436 #define MSR_IA32_RTIT_ADDR3_A 0x586
437 #define MSR_IA32_RTIT_ADDR3_B 0x587
438 #define MAX_RTIT_ADDRS 8
439
440 #define MSR_EFER 0xc0000080
441
442 #define MSR_EFER_SCE (1 << 0)
443 #define MSR_EFER_LME (1 << 8)
444 #define MSR_EFER_LMA (1 << 10)
445 #define MSR_EFER_NXE (1 << 11)
446 #define MSR_EFER_SVME (1 << 12)
447 #define MSR_EFER_FFXSR (1 << 14)
448
449 #define MSR_STAR 0xc0000081
450 #define MSR_LSTAR 0xc0000082
451 #define MSR_CSTAR 0xc0000083
452 #define MSR_FMASK 0xc0000084
453 #define MSR_FSBASE 0xc0000100
454 #define MSR_GSBASE 0xc0000101
455 #define MSR_KERNELGSBASE 0xc0000102
456 #define MSR_TSC_AUX 0xc0000103
457
458 #define MSR_VM_HSAVE_PA 0xc0010117
459
460 #define MSR_IA32_BNDCFGS 0x00000d90
461 #define MSR_IA32_XSS 0x00000da0
462 #define MSR_IA32_UMWAIT_CONTROL 0xe1
463
464 #define MSR_IA32_VMX_BASIC 0x00000480
465 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
466 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
467 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
468 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
469 #define MSR_IA32_VMX_MISC 0x00000485
470 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
471 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
472 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
473 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
474 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
475 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
476 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
477 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
478 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
479 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
480 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
481 #define MSR_IA32_VMX_VMFUNC 0x00000491
482
483 #define XSTATE_FP_BIT 0
484 #define XSTATE_SSE_BIT 1
485 #define XSTATE_YMM_BIT 2
486 #define XSTATE_BNDREGS_BIT 3
487 #define XSTATE_BNDCSR_BIT 4
488 #define XSTATE_OPMASK_BIT 5
489 #define XSTATE_ZMM_Hi256_BIT 6
490 #define XSTATE_Hi16_ZMM_BIT 7
491 #define XSTATE_PKRU_BIT 9
492
493 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
494 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
495 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
496 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
497 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
498 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
499 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
500 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
501 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
502
503 /* CPUID feature words */
504 typedef enum FeatureWord {
505 FEAT_1_EDX, /* CPUID[1].EDX */
506 FEAT_1_ECX, /* CPUID[1].ECX */
507 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
508 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */
509 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */
510 FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */
511 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
512 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
513 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
514 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */
515 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
516 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
517 FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */
518 FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */
519 FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */
520 FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */
521 FEAT_HV_RECOMM_EAX, /* CPUID[4000_0004].EAX */
522 FEAT_HV_NESTED_EAX, /* CPUID[4000_000A].EAX */
523 FEAT_SVM, /* CPUID[8000_000A].EDX */
524 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */
525 FEAT_6_EAX, /* CPUID[6].EAX */
526 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
527 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
528 FEAT_ARCH_CAPABILITIES,
529 FEAT_CORE_CAPABILITY,
530 FEAT_VMX_PROCBASED_CTLS,
531 FEAT_VMX_SECONDARY_CTLS,
532 FEAT_VMX_PINBASED_CTLS,
533 FEAT_VMX_EXIT_CTLS,
534 FEAT_VMX_ENTRY_CTLS,
535 FEAT_VMX_MISC,
536 FEAT_VMX_EPT_VPID_CAPS,
537 FEAT_VMX_BASIC,
538 FEAT_VMX_VMFUNC,
539 FEATURE_WORDS,
540 } FeatureWord;
541
542 typedef uint64_t FeatureWordArray[FEATURE_WORDS];
543
544 /* cpuid_features bits */
545 #define CPUID_FP87 (1U << 0)
546 #define CPUID_VME (1U << 1)
547 #define CPUID_DE (1U << 2)
548 #define CPUID_PSE (1U << 3)
549 #define CPUID_TSC (1U << 4)
550 #define CPUID_MSR (1U << 5)
551 #define CPUID_PAE (1U << 6)
552 #define CPUID_MCE (1U << 7)
553 #define CPUID_CX8 (1U << 8)
554 #define CPUID_APIC (1U << 9)
555 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */
556 #define CPUID_MTRR (1U << 12)
557 #define CPUID_PGE (1U << 13)
558 #define CPUID_MCA (1U << 14)
559 #define CPUID_CMOV (1U << 15)
560 #define CPUID_PAT (1U << 16)
561 #define CPUID_PSE36 (1U << 17)
562 #define CPUID_PN (1U << 18)
563 #define CPUID_CLFLUSH (1U << 19)
564 #define CPUID_DTS (1U << 21)
565 #define CPUID_ACPI (1U << 22)
566 #define CPUID_MMX (1U << 23)
567 #define CPUID_FXSR (1U << 24)
568 #define CPUID_SSE (1U << 25)
569 #define CPUID_SSE2 (1U << 26)
570 #define CPUID_SS (1U << 27)
571 #define CPUID_HT (1U << 28)
572 #define CPUID_TM (1U << 29)
573 #define CPUID_IA64 (1U << 30)
574 #define CPUID_PBE (1U << 31)
575
576 #define CPUID_EXT_SSE3 (1U << 0)
577 #define CPUID_EXT_PCLMULQDQ (1U << 1)
578 #define CPUID_EXT_DTES64 (1U << 2)
579 #define CPUID_EXT_MONITOR (1U << 3)
580 #define CPUID_EXT_DSCPL (1U << 4)
581 #define CPUID_EXT_VMX (1U << 5)
582 #define CPUID_EXT_SMX (1U << 6)
583 #define CPUID_EXT_EST (1U << 7)
584 #define CPUID_EXT_TM2 (1U << 8)
585 #define CPUID_EXT_SSSE3 (1U << 9)
586 #define CPUID_EXT_CID (1U << 10)
587 #define CPUID_EXT_FMA (1U << 12)
588 #define CPUID_EXT_CX16 (1U << 13)
589 #define CPUID_EXT_XTPR (1U << 14)
590 #define CPUID_EXT_PDCM (1U << 15)
591 #define CPUID_EXT_PCID (1U << 17)
592 #define CPUID_EXT_DCA (1U << 18)
593 #define CPUID_EXT_SSE41 (1U << 19)
594 #define CPUID_EXT_SSE42 (1U << 20)
595 #define CPUID_EXT_X2APIC (1U << 21)
596 #define CPUID_EXT_MOVBE (1U << 22)
597 #define CPUID_EXT_POPCNT (1U << 23)
598 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
599 #define CPUID_EXT_AES (1U << 25)
600 #define CPUID_EXT_XSAVE (1U << 26)
601 #define CPUID_EXT_OSXSAVE (1U << 27)
602 #define CPUID_EXT_AVX (1U << 28)
603 #define CPUID_EXT_F16C (1U << 29)
604 #define CPUID_EXT_RDRAND (1U << 30)
605 #define CPUID_EXT_HYPERVISOR (1U << 31)
606
607 #define CPUID_EXT2_FPU (1U << 0)
608 #define CPUID_EXT2_VME (1U << 1)
609 #define CPUID_EXT2_DE (1U << 2)
610 #define CPUID_EXT2_PSE (1U << 3)
611 #define CPUID_EXT2_TSC (1U << 4)
612 #define CPUID_EXT2_MSR (1U << 5)
613 #define CPUID_EXT2_PAE (1U << 6)
614 #define CPUID_EXT2_MCE (1U << 7)
615 #define CPUID_EXT2_CX8 (1U << 8)
616 #define CPUID_EXT2_APIC (1U << 9)
617 #define CPUID_EXT2_SYSCALL (1U << 11)
618 #define CPUID_EXT2_MTRR (1U << 12)
619 #define CPUID_EXT2_PGE (1U << 13)
620 #define CPUID_EXT2_MCA (1U << 14)
621 #define CPUID_EXT2_CMOV (1U << 15)
622 #define CPUID_EXT2_PAT (1U << 16)
623 #define CPUID_EXT2_PSE36 (1U << 17)
624 #define CPUID_EXT2_MP (1U << 19)
625 #define CPUID_EXT2_NX (1U << 20)
626 #define CPUID_EXT2_MMXEXT (1U << 22)
627 #define CPUID_EXT2_MMX (1U << 23)
628 #define CPUID_EXT2_FXSR (1U << 24)
629 #define CPUID_EXT2_FFXSR (1U << 25)
630 #define CPUID_EXT2_PDPE1GB (1U << 26)
631 #define CPUID_EXT2_RDTSCP (1U << 27)
632 #define CPUID_EXT2_LM (1U << 29)
633 #define CPUID_EXT2_3DNOWEXT (1U << 30)
634 #define CPUID_EXT2_3DNOW (1U << 31)
635
636 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
637 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
638 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
639 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
640 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
641 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
642 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
643 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
644 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
645 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
646
647 #define CPUID_EXT3_LAHF_LM (1U << 0)
648 #define CPUID_EXT3_CMP_LEG (1U << 1)
649 #define CPUID_EXT3_SVM (1U << 2)
650 #define CPUID_EXT3_EXTAPIC (1U << 3)
651 #define CPUID_EXT3_CR8LEG (1U << 4)
652 #define CPUID_EXT3_ABM (1U << 5)
653 #define CPUID_EXT3_SSE4A (1U << 6)
654 #define CPUID_EXT3_MISALIGNSSE (1U << 7)
655 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
656 #define CPUID_EXT3_OSVW (1U << 9)
657 #define CPUID_EXT3_IBS (1U << 10)
658 #define CPUID_EXT3_XOP (1U << 11)
659 #define CPUID_EXT3_SKINIT (1U << 12)
660 #define CPUID_EXT3_WDT (1U << 13)
661 #define CPUID_EXT3_LWP (1U << 15)
662 #define CPUID_EXT3_FMA4 (1U << 16)
663 #define CPUID_EXT3_TCE (1U << 17)
664 #define CPUID_EXT3_NODEID (1U << 19)
665 #define CPUID_EXT3_TBM (1U << 21)
666 #define CPUID_EXT3_TOPOEXT (1U << 22)
667 #define CPUID_EXT3_PERFCORE (1U << 23)
668 #define CPUID_EXT3_PERFNB (1U << 24)
669
670 #define CPUID_SVM_NPT (1U << 0)
671 #define CPUID_SVM_LBRV (1U << 1)
672 #define CPUID_SVM_SVMLOCK (1U << 2)
673 #define CPUID_SVM_NRIPSAVE (1U << 3)
674 #define CPUID_SVM_TSCSCALE (1U << 4)
675 #define CPUID_SVM_VMCBCLEAN (1U << 5)
676 #define CPUID_SVM_FLUSHASID (1U << 6)
677 #define CPUID_SVM_DECODEASSIST (1U << 7)
678 #define CPUID_SVM_PAUSEFILTER (1U << 10)
679 #define CPUID_SVM_PFTHRESHOLD (1U << 12)
680
681 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
682 #define CPUID_7_0_EBX_FSGSBASE (1U << 0)
683 /* 1st Group of Advanced Bit Manipulation Extensions */
684 #define CPUID_7_0_EBX_BMI1 (1U << 3)
685 /* Hardware Lock Elision */
686 #define CPUID_7_0_EBX_HLE (1U << 4)
687 /* Intel Advanced Vector Extensions 2 */
688 #define CPUID_7_0_EBX_AVX2 (1U << 5)
689 /* Supervisor-mode Execution Prevention */
690 #define CPUID_7_0_EBX_SMEP (1U << 7)
691 /* 2nd Group of Advanced Bit Manipulation Extensions */
692 #define CPUID_7_0_EBX_BMI2 (1U << 8)
693 /* Enhanced REP MOVSB/STOSB */
694 #define CPUID_7_0_EBX_ERMS (1U << 9)
695 /* Invalidate Process-Context Identifier */
696 #define CPUID_7_0_EBX_INVPCID (1U << 10)
697 /* Restricted Transactional Memory */
698 #define CPUID_7_0_EBX_RTM (1U << 11)
699 /* Memory Protection Extension */
700 #define CPUID_7_0_EBX_MPX (1U << 14)
701 /* AVX-512 Foundation */
702 #define CPUID_7_0_EBX_AVX512F (1U << 16)
703 /* AVX-512 Doubleword & Quadword Instruction */
704 #define CPUID_7_0_EBX_AVX512DQ (1U << 17)
705 /* Read Random SEED */
706 #define CPUID_7_0_EBX_RDSEED (1U << 18)
707 /* ADCX and ADOX instructions */
708 #define CPUID_7_0_EBX_ADX (1U << 19)
709 /* Supervisor Mode Access Prevention */
710 #define CPUID_7_0_EBX_SMAP (1U << 20)
711 /* AVX-512 Integer Fused Multiply Add */
712 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
713 /* Persistent Commit */
714 #define CPUID_7_0_EBX_PCOMMIT (1U << 22)
715 /* Flush a Cache Line Optimized */
716 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
717 /* Cache Line Write Back */
718 #define CPUID_7_0_EBX_CLWB (1U << 24)
719 /* Intel Processor Trace */
720 #define CPUID_7_0_EBX_INTEL_PT (1U << 25)
721 /* AVX-512 Prefetch */
722 #define CPUID_7_0_EBX_AVX512PF (1U << 26)
723 /* AVX-512 Exponential and Reciprocal */
724 #define CPUID_7_0_EBX_AVX512ER (1U << 27)
725 /* AVX-512 Conflict Detection */
726 #define CPUID_7_0_EBX_AVX512CD (1U << 28)
727 /* SHA1/SHA256 Instruction Extensions */
728 #define CPUID_7_0_EBX_SHA_NI (1U << 29)
729 /* AVX-512 Byte and Word Instructions */
730 #define CPUID_7_0_EBX_AVX512BW (1U << 30)
731 /* AVX-512 Vector Length Extensions */
732 #define CPUID_7_0_EBX_AVX512VL (1U << 31)
733
734 /* AVX-512 Vector Byte Manipulation Instruction */
735 #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1)
736 /* User-Mode Instruction Prevention */
737 #define CPUID_7_0_ECX_UMIP (1U << 2)
738 /* Protection Keys for User-mode Pages */
739 #define CPUID_7_0_ECX_PKU (1U << 3)
740 /* OS Enable Protection Keys */
741 #define CPUID_7_0_ECX_OSPKE (1U << 4)
742 /* UMONITOR/UMWAIT/TPAUSE Instructions */
743 #define CPUID_7_0_ECX_WAITPKG (1U << 5)
744 /* Additional AVX-512 Vector Byte Manipulation Instruction */
745 #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6)
746 /* Galois Field New Instructions */
747 #define CPUID_7_0_ECX_GFNI (1U << 8)
748 /* Vector AES Instructions */
749 #define CPUID_7_0_ECX_VAES (1U << 9)
750 /* Carry-Less Multiplication Quadword */
751 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
752 /* Vector Neural Network Instructions */
753 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
754 /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */
755 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
756 /* POPCNT for vectors of DW/QW */
757 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
758 /* 5-level Page Tables */
759 #define CPUID_7_0_ECX_LA57 (1U << 16)
760 /* Read Processor ID */
761 #define CPUID_7_0_ECX_RDPID (1U << 22)
762 /* Cache Line Demote Instruction */
763 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
764 /* Move Doubleword as Direct Store Instruction */
765 #define CPUID_7_0_ECX_MOVDIRI (1U << 27)
766 /* Move 64 Bytes as Direct Store Instruction */
767 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28)
768
769 /* AVX512 Neural Network Instructions */
770 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
771 /* AVX512 Multiply Accumulation Single Precision */
772 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
773 /* Speculation Control */
774 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
775 /* Single Thread Indirect Branch Predictors */
776 #define CPUID_7_0_EDX_STIBP (1U << 27)
777 /* Arch Capabilities */
778 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
779 /* Core Capability */
780 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30)
781 /* Speculative Store Bypass Disable */
782 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
783
784 /* AVX512 BFloat16 Instruction */
785 #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
786
787 /* CLZERO instruction */
788 #define CPUID_8000_0008_EBX_CLZERO (1U << 0)
789 /* Always save/restore FP error pointers */
790 #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2)
791 /* Write back and do not invalidate cache */
792 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
793 /* Indirect Branch Prediction Barrier */
794 #define CPUID_8000_0008_EBX_IBPB (1U << 12)
795 /* Single Thread Indirect Branch Predictors */
796 #define CPUID_8000_0008_EBX_STIBP (1U << 15)
797
798 #define CPUID_XSAVE_XSAVEOPT (1U << 0)
799 #define CPUID_XSAVE_XSAVEC (1U << 1)
800 #define CPUID_XSAVE_XGETBV1 (1U << 2)
801 #define CPUID_XSAVE_XSAVES (1U << 3)
802
803 #define CPUID_6_EAX_ARAT (1U << 2)
804
805 /* CPUID[0x80000007].EDX flags: */
806 #define CPUID_APM_INVTSC (1U << 8)
807
808 #define CPUID_VENDOR_SZ 12
809
810 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
811 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
812 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
813 #define CPUID_VENDOR_INTEL "GenuineIntel"
814
815 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
816 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
817 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
818 #define CPUID_VENDOR_AMD "AuthenticAMD"
819
820 #define CPUID_VENDOR_VIA "CentaurHauls"
821
822 #define CPUID_VENDOR_HYGON "HygonGenuine"
823
824 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
825 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
826 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
827 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
828 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
829 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
830
831 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */
832 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
833
834 /* CPUID[0xB].ECX level types */
835 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
836 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
837 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
838 #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
839
840 /* MSR Feature Bits */
841 #define MSR_ARCH_CAP_RDCL_NO (1U << 0)
842 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
843 #define MSR_ARCH_CAP_RSBA (1U << 2)
844 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
845 #define MSR_ARCH_CAP_SSB_NO (1U << 4)
846 #define MSR_ARCH_CAP_MDS_NO (1U << 5)
847 #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
848 #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
849 #define MSR_ARCH_CAP_TAA_NO (1U << 8)
850
851 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
852
853 /* VMX MSR features */
854 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull
855 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32)
856 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32)
857 #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49)
858 #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54)
859 #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55)
860
861 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full
862 #define MSR_VMX_MISC_STORE_LMA (1ULL << 5)
863 #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6)
864 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7)
865 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8)
866 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull
867 #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29)
868 #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30)
869
870 #define MSR_VMX_EPT_EXECONLY (1ULL << 0)
871 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6)
872 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7)
873 #define MSR_VMX_EPT_UC (1ULL << 8)
874 #define MSR_VMX_EPT_WB (1ULL << 14)
875 #define MSR_VMX_EPT_2MB (1ULL << 16)
876 #define MSR_VMX_EPT_1GB (1ULL << 17)
877 #define MSR_VMX_EPT_INVEPT (1ULL << 20)
878 #define MSR_VMX_EPT_AD_BITS (1ULL << 21)
879 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22)
880 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25)
881 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26)
882 #define MSR_VMX_EPT_INVVPID (1ULL << 32)
883 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40)
884 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41)
885 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42)
886 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43)
887
888 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0)
889
890
891 /* VMX controls */
892 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
893 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008
894 #define VMX_CPU_BASED_HLT_EXITING 0x00000080
895 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200
896 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400
897 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800
898 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000
899 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000
900 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000
901 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000
902 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000
903 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000
904 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
905 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000
906 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000
907 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000
908 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
909 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000
910 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000
911 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000
912 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
913
914 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
915 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002
916 #define VMX_SECONDARY_EXEC_DESC 0x00000004
917 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008
918 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
919 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020
920 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040
921 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
922 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
923 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
924 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
925 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800
926 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
927 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000
928 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000
929 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000
930 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000
931 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000
932 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000
933
934 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001
935 #define VMX_PIN_BASED_NMI_EXITING 0x00000008
936 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020
937 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
938 #define VMX_PIN_BASED_POSTED_INTR 0x00000080
939
940 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
941 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
942 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
943 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
944 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000
945 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000
946 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000
947 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000
948 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
949 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000
950 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000
951 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
952
953 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
954 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200
955 #define VMX_VM_ENTRY_SMM 0x00000400
956 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
957 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
958 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000
959 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000
960 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000
961 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000
962 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
963
964 /* Supported Hyper-V Enlightenments */
965 #define HYPERV_FEAT_RELAXED 0
966 #define HYPERV_FEAT_VAPIC 1
967 #define HYPERV_FEAT_TIME 2
968 #define HYPERV_FEAT_CRASH 3
969 #define HYPERV_FEAT_RESET 4
970 #define HYPERV_FEAT_VPINDEX 5
971 #define HYPERV_FEAT_RUNTIME 6
972 #define HYPERV_FEAT_SYNIC 7
973 #define HYPERV_FEAT_STIMER 8
974 #define HYPERV_FEAT_FREQUENCIES 9
975 #define HYPERV_FEAT_REENLIGHTENMENT 10
976 #define HYPERV_FEAT_TLBFLUSH 11
977 #define HYPERV_FEAT_EVMCS 12
978 #define HYPERV_FEAT_IPI 13
979 #define HYPERV_FEAT_STIMER_DIRECT 14
980
981 #ifndef HYPERV_SPINLOCK_NEVER_RETRY
982 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
983 #endif
984
985 #define EXCP00_DIVZ 0
986 #define EXCP01_DB 1
987 #define EXCP02_NMI 2
988 #define EXCP03_INT3 3
989 #define EXCP04_INTO 4
990 #define EXCP05_BOUND 5
991 #define EXCP06_ILLOP 6
992 #define EXCP07_PREX 7
993 #define EXCP08_DBLE 8
994 #define EXCP09_XERR 9
995 #define EXCP0A_TSS 10
996 #define EXCP0B_NOSEG 11
997 #define EXCP0C_STACK 12
998 #define EXCP0D_GPF 13
999 #define EXCP0E_PAGE 14
1000 #define EXCP10_COPR 16
1001 #define EXCP11_ALGN 17
1002 #define EXCP12_MCHK 18
1003
1004 #define EXCP_VMEXIT 0x100 /* only for system emulation */
1005 #define EXCP_SYSCALL 0x101 /* only for user emulation */
1006 #define EXCP_VSYSCALL 0x102 /* only for user emulation */
1007
1008 /* i386-specific interrupt pending bits. */
1009 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
1010 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
1011 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
1012 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
1013 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
1014 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
1015 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
1016
1017 /* Use a clearer name for this. */
1018 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
1019
1020 /* Instead of computing the condition codes after each x86 instruction,
1021 * QEMU just stores one operand (called CC_SRC), the result
1022 * (called CC_DST) and the type of operation (called CC_OP). When the
1023 * condition codes are needed, the condition codes can be calculated
1024 * using this information. Condition codes are not generated if they
1025 * are only needed for conditional branches.
1026 */
1027 typedef enum {
1028 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
1029 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
1030
1031 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
1032 CC_OP_MULW,
1033 CC_OP_MULL,
1034 CC_OP_MULQ,
1035
1036 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1037 CC_OP_ADDW,
1038 CC_OP_ADDL,
1039 CC_OP_ADDQ,
1040
1041 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1042 CC_OP_ADCW,
1043 CC_OP_ADCL,
1044 CC_OP_ADCQ,
1045
1046 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1047 CC_OP_SUBW,
1048 CC_OP_SUBL,
1049 CC_OP_SUBQ,
1050
1051 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1052 CC_OP_SBBW,
1053 CC_OP_SBBL,
1054 CC_OP_SBBQ,
1055
1056 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
1057 CC_OP_LOGICW,
1058 CC_OP_LOGICL,
1059 CC_OP_LOGICQ,
1060
1061 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
1062 CC_OP_INCW,
1063 CC_OP_INCL,
1064 CC_OP_INCQ,
1065
1066 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
1067 CC_OP_DECW,
1068 CC_OP_DECL,
1069 CC_OP_DECQ,
1070
1071 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
1072 CC_OP_SHLW,
1073 CC_OP_SHLL,
1074 CC_OP_SHLQ,
1075
1076 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
1077 CC_OP_SARW,
1078 CC_OP_SARL,
1079 CC_OP_SARQ,
1080
1081 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
1082 CC_OP_BMILGW,
1083 CC_OP_BMILGL,
1084 CC_OP_BMILGQ,
1085
1086 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */
1087 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */
1088 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */
1089
1090 CC_OP_CLR, /* Z set, all other flags clear. */
1091 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */
1092
1093 CC_OP_NB,
1094 } CCOp;
1095
1096 typedef struct SegmentCache {
1097 uint32_t selector;
1098 target_ulong base;
1099 uint32_t limit;
1100 uint32_t flags;
1101 } SegmentCache;
1102
1103 #define MMREG_UNION(n, bits) \
1104 union n { \
1105 uint8_t _b_##n[(bits)/8]; \
1106 uint16_t _w_##n[(bits)/16]; \
1107 uint32_t _l_##n[(bits)/32]; \
1108 uint64_t _q_##n[(bits)/64]; \
1109 float32 _s_##n[(bits)/32]; \
1110 float64 _d_##n[(bits)/64]; \
1111 }
1112
1113 typedef union {
1114 uint8_t _b[16];
1115 uint16_t _w[8];
1116 uint32_t _l[4];
1117 uint64_t _q[2];
1118 } XMMReg;
1119
1120 typedef union {
1121 uint8_t _b[32];
1122 uint16_t _w[16];
1123 uint32_t _l[8];
1124 uint64_t _q[4];
1125 } YMMReg;
1126
1127 typedef MMREG_UNION(ZMMReg, 512) ZMMReg;
1128 typedef MMREG_UNION(MMXReg, 64) MMXReg;
1129
1130 typedef struct BNDReg {
1131 uint64_t lb;
1132 uint64_t ub;
1133 } BNDReg;
1134
1135 typedef struct BNDCSReg {
1136 uint64_t cfgu;
1137 uint64_t sts;
1138 } BNDCSReg;
1139
1140 #define BNDCFG_ENABLE 1ULL
1141 #define BNDCFG_BNDPRESERVE 2ULL
1142 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
1143
1144 #ifdef HOST_WORDS_BIGENDIAN
1145 #define ZMM_B(n) _b_ZMMReg[63 - (n)]
1146 #define ZMM_W(n) _w_ZMMReg[31 - (n)]
1147 #define ZMM_L(n) _l_ZMMReg[15 - (n)]
1148 #define ZMM_S(n) _s_ZMMReg[15 - (n)]
1149 #define ZMM_Q(n) _q_ZMMReg[7 - (n)]
1150 #define ZMM_D(n) _d_ZMMReg[7 - (n)]
1151
1152 #define MMX_B(n) _b_MMXReg[7 - (n)]
1153 #define MMX_W(n) _w_MMXReg[3 - (n)]
1154 #define MMX_L(n) _l_MMXReg[1 - (n)]
1155 #define MMX_S(n) _s_MMXReg[1 - (n)]
1156 #else
1157 #define ZMM_B(n) _b_ZMMReg[n]
1158 #define ZMM_W(n) _w_ZMMReg[n]
1159 #define ZMM_L(n) _l_ZMMReg[n]
1160 #define ZMM_S(n) _s_ZMMReg[n]
1161 #define ZMM_Q(n) _q_ZMMReg[n]
1162 #define ZMM_D(n) _d_ZMMReg[n]
1163
1164 #define MMX_B(n) _b_MMXReg[n]
1165 #define MMX_W(n) _w_MMXReg[n]
1166 #define MMX_L(n) _l_MMXReg[n]
1167 #define MMX_S(n) _s_MMXReg[n]
1168 #endif
1169 #define MMX_Q(n) _q_MMXReg[n]
1170
1171 typedef union {
1172 floatx80 d __attribute__((aligned(16)));
1173 MMXReg mmx;
1174 } FPReg;
1175
1176 typedef struct {
1177 uint64_t base;
1178 uint64_t mask;
1179 } MTRRVar;
1180
1181 #define CPU_NB_REGS64 16
1182 #define CPU_NB_REGS32 8
1183
1184 #ifdef TARGET_X86_64
1185 #define CPU_NB_REGS CPU_NB_REGS64
1186 #else
1187 #define CPU_NB_REGS CPU_NB_REGS32
1188 #endif
1189
1190 #define MAX_FIXED_COUNTERS 3
1191 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
1192
1193 #define TARGET_INSN_START_EXTRA_WORDS 1
1194
1195 #define NB_OPMASK_REGS 8
1196
1197 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
1198 * that APIC ID hasn't been set yet
1199 */
1200 #define UNASSIGNED_APIC_ID 0xFFFFFFFF
1201
1202 typedef union X86LegacyXSaveArea {
1203 struct {
1204 uint16_t fcw;
1205 uint16_t fsw;
1206 uint8_t ftw;
1207 uint8_t reserved;
1208 uint16_t fpop;
1209 uint64_t fpip;
1210 uint64_t fpdp;
1211 uint32_t mxcsr;
1212 uint32_t mxcsr_mask;
1213 FPReg fpregs[8];
1214 uint8_t xmm_regs[16][16];
1215 };
1216 uint8_t data[512];
1217 } X86LegacyXSaveArea;
1218
1219 typedef struct X86XSaveHeader {
1220 uint64_t xstate_bv;
1221 uint64_t xcomp_bv;
1222 uint64_t reserve0;
1223 uint8_t reserved[40];
1224 } X86XSaveHeader;
1225
1226 /* Ext. save area 2: AVX State */
1227 typedef struct XSaveAVX {
1228 uint8_t ymmh[16][16];
1229 } XSaveAVX;
1230
1231 /* Ext. save area 3: BNDREG */
1232 typedef struct XSaveBNDREG {
1233 BNDReg bnd_regs[4];
1234 } XSaveBNDREG;
1235
1236 /* Ext. save area 4: BNDCSR */
1237 typedef union XSaveBNDCSR {
1238 BNDCSReg bndcsr;
1239 uint8_t data[64];
1240 } XSaveBNDCSR;
1241
1242 /* Ext. save area 5: Opmask */
1243 typedef struct XSaveOpmask {
1244 uint64_t opmask_regs[NB_OPMASK_REGS];
1245 } XSaveOpmask;
1246
1247 /* Ext. save area 6: ZMM_Hi256 */
1248 typedef struct XSaveZMM_Hi256 {
1249 uint8_t zmm_hi256[16][32];
1250 } XSaveZMM_Hi256;
1251
1252 /* Ext. save area 7: Hi16_ZMM */
1253 typedef struct XSaveHi16_ZMM {
1254 uint8_t hi16_zmm[16][64];
1255 } XSaveHi16_ZMM;
1256
1257 /* Ext. save area 9: PKRU state */
1258 typedef struct XSavePKRU {
1259 uint32_t pkru;
1260 uint32_t padding;
1261 } XSavePKRU;
1262
1263 typedef struct X86XSaveArea {
1264 X86LegacyXSaveArea legacy;
1265 X86XSaveHeader header;
1266
1267 /* Extended save areas: */
1268
1269 /* AVX State: */
1270 XSaveAVX avx_state;
1271 uint8_t padding[960 - 576 - sizeof(XSaveAVX)];
1272 /* MPX State: */
1273 XSaveBNDREG bndreg_state;
1274 XSaveBNDCSR bndcsr_state;
1275 /* AVX-512 State: */
1276 XSaveOpmask opmask_state;
1277 XSaveZMM_Hi256 zmm_hi256_state;
1278 XSaveHi16_ZMM hi16_zmm_state;
1279 /* PKRU State: */
1280 XSavePKRU pkru_state;
1281 } X86XSaveArea;
1282
1283 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240);
1284 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1285 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0);
1286 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1287 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400);
1288 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1289 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440);
1290 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1291 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480);
1292 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1293 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680);
1294 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1295 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80);
1296 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1297
1298 typedef enum TPRAccess {
1299 TPR_ACCESS_READ,
1300 TPR_ACCESS_WRITE,
1301 } TPRAccess;
1302
1303 /* Cache information data structures: */
1304
1305 enum CacheType {
1306 DATA_CACHE,
1307 INSTRUCTION_CACHE,
1308 UNIFIED_CACHE
1309 };
1310
1311 typedef struct CPUCacheInfo {
1312 enum CacheType type;
1313 uint8_t level;
1314 /* Size in bytes */
1315 uint32_t size;
1316 /* Line size, in bytes */
1317 uint16_t line_size;
1318 /*
1319 * Associativity.
1320 * Note: representation of fully-associative caches is not implemented
1321 */
1322 uint8_t associativity;
1323 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
1324 uint8_t partitions;
1325 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
1326 uint32_t sets;
1327 /*
1328 * Lines per tag.
1329 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
1330 * (Is this synonym to @partitions?)
1331 */
1332 uint8_t lines_per_tag;
1333
1334 /* Self-initializing cache */
1335 bool self_init;
1336 /*
1337 * WBINVD/INVD is not guaranteed to act upon lower level caches of
1338 * non-originating threads sharing this cache.
1339 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
1340 */
1341 bool no_invd_sharing;
1342 /*
1343 * Cache is inclusive of lower cache levels.
1344 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
1345 */
1346 bool inclusive;
1347 /*
1348 * A complex function is used to index the cache, potentially using all
1349 * address bits. CPUID[4].EDX[bit 2].
1350 */
1351 bool complex_indexing;
1352 } CPUCacheInfo;
1353
1354
1355 typedef struct CPUCaches {
1356 CPUCacheInfo *l1d_cache;
1357 CPUCacheInfo *l1i_cache;
1358 CPUCacheInfo *l2_cache;
1359 CPUCacheInfo *l3_cache;
1360 } CPUCaches;
1361
1362 typedef struct CPUX86State {
1363 /* standard registers */
1364 target_ulong regs[CPU_NB_REGS];
1365 target_ulong eip;
1366 target_ulong eflags; /* eflags register. During CPU emulation, CC
1367 flags and DF are set to zero because they are
1368 stored elsewhere */
1369
1370 /* emulator internal eflags handling */
1371 target_ulong cc_dst;
1372 target_ulong cc_src;
1373 target_ulong cc_src2;
1374 uint32_t cc_op;
1375 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
1376 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
1377 are known at translation time. */
1378 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
1379
1380 /* segments */
1381 SegmentCache segs[6]; /* selector values */
1382 SegmentCache ldt;
1383 SegmentCache tr;
1384 SegmentCache gdt; /* only base and limit are used */
1385 SegmentCache idt; /* only base and limit are used */
1386
1387 target_ulong cr[5]; /* NOTE: cr1 is unused */
1388 int32_t a20_mask;
1389
1390 BNDReg bnd_regs[4];
1391 BNDCSReg bndcs_regs;
1392 uint64_t msr_bndcfgs;
1393 uint64_t efer;
1394
1395 /* Beginning of state preserved by INIT (dummy marker). */
1396 struct {} start_init_save;
1397
1398 /* FPU state */
1399 unsigned int fpstt; /* top of stack index */
1400 uint16_t fpus;
1401 uint16_t fpuc;
1402 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
1403 FPReg fpregs[8];
1404 /* KVM-only so far */
1405 uint16_t fpop;
1406 uint64_t fpip;
1407 uint64_t fpdp;
1408
1409 /* emulator internal variables */
1410 float_status fp_status;
1411 floatx80 ft0;
1412
1413 float_status mmx_status; /* for 3DNow! float ops */
1414 float_status sse_status;
1415 uint32_t mxcsr;
1416 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
1417 ZMMReg xmm_t0;
1418 MMXReg mmx_t0;
1419
1420 XMMReg ymmh_regs[CPU_NB_REGS];
1421
1422 uint64_t opmask_regs[NB_OPMASK_REGS];
1423 YMMReg zmmh_regs[CPU_NB_REGS];
1424 ZMMReg hi16_zmm_regs[CPU_NB_REGS];
1425
1426 /* sysenter registers */
1427 uint32_t sysenter_cs;
1428 target_ulong sysenter_esp;
1429 target_ulong sysenter_eip;
1430 uint64_t star;
1431
1432 uint64_t vm_hsave;
1433
1434 #ifdef TARGET_X86_64
1435 target_ulong lstar;
1436 target_ulong cstar;
1437 target_ulong fmask;
1438 target_ulong kernelgsbase;
1439 #endif
1440
1441 uint64_t tsc;
1442 uint64_t tsc_adjust;
1443 uint64_t tsc_deadline;
1444 uint64_t tsc_aux;
1445
1446 uint64_t xcr0;
1447
1448 uint64_t mcg_status;
1449 uint64_t msr_ia32_misc_enable;
1450 uint64_t msr_ia32_feature_control;
1451
1452 uint64_t msr_fixed_ctr_ctrl;
1453 uint64_t msr_global_ctrl;
1454 uint64_t msr_global_status;
1455 uint64_t msr_global_ovf_ctrl;
1456 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1457 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1458 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1459
1460 uint64_t pat;
1461 uint32_t smbase;
1462 uint64_t msr_smi_count;
1463
1464 uint32_t pkru;
1465 uint32_t tsx_ctrl;
1466
1467 uint64_t spec_ctrl;
1468 uint64_t virt_ssbd;
1469
1470 /* End of state preserved by INIT (dummy marker). */
1471 struct {} end_init_save;
1472
1473 uint64_t system_time_msr;
1474 uint64_t wall_clock_msr;
1475 uint64_t steal_time_msr;
1476 uint64_t async_pf_en_msr;
1477 uint64_t pv_eoi_en_msr;
1478 uint64_t poll_control_msr;
1479
1480 /* Partition-wide HV MSRs, will be updated only on the first vcpu */
1481 uint64_t msr_hv_hypercall;
1482 uint64_t msr_hv_guest_os_id;
1483 uint64_t msr_hv_tsc;
1484
1485 /* Per-VCPU HV MSRs */
1486 uint64_t msr_hv_vapic;
1487 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1488 uint64_t msr_hv_runtime;
1489 uint64_t msr_hv_synic_control;
1490 uint64_t msr_hv_synic_evt_page;
1491 uint64_t msr_hv_synic_msg_page;
1492 uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
1493 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
1494 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1495 uint64_t msr_hv_reenlightenment_control;
1496 uint64_t msr_hv_tsc_emulation_control;
1497 uint64_t msr_hv_tsc_emulation_status;
1498
1499 uint64_t msr_rtit_ctrl;
1500 uint64_t msr_rtit_status;
1501 uint64_t msr_rtit_output_base;
1502 uint64_t msr_rtit_output_mask;
1503 uint64_t msr_rtit_cr3_match;
1504 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
1505
1506 /* exception/interrupt handling */
1507 int error_code;
1508 int exception_is_int;
1509 target_ulong exception_next_eip;
1510 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */
1511 union {
1512 struct CPUBreakpoint *cpu_breakpoint[4];
1513 struct CPUWatchpoint *cpu_watchpoint[4];
1514 }; /* break/watchpoints for dr[0..3] */
1515 int old_exception; /* exception in flight */
1516
1517 uint64_t vm_vmcb;
1518 uint64_t tsc_offset;
1519 uint64_t intercept;
1520 uint16_t intercept_cr_read;
1521 uint16_t intercept_cr_write;
1522 uint16_t intercept_dr_read;
1523 uint16_t intercept_dr_write;
1524 uint32_t intercept_exceptions;
1525 uint64_t nested_cr3;
1526 uint32_t nested_pg_mode;
1527 uint8_t v_tpr;
1528
1529 /* KVM states, automatically cleared on reset */
1530 uint8_t nmi_injected;
1531 uint8_t nmi_pending;
1532
1533 uintptr_t retaddr;
1534
1535 /* Fields up to this point are cleared by a CPU reset */
1536 struct {} end_reset_fields;
1537
1538 /* Fields after this point are preserved across CPU reset. */
1539
1540 /* processor features (e.g. for CPUID insn) */
1541 /* Minimum cpuid leaf 7 value */
1542 uint32_t cpuid_level_func7;
1543 /* Actual cpuid leaf 7 value */
1544 uint32_t cpuid_min_level_func7;
1545 /* Minimum level/xlevel/xlevel2, based on CPU model + features */
1546 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1547 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */
1548 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1549 /* Actual level/xlevel/xlevel2 value: */
1550 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1551 uint32_t cpuid_vendor1;
1552 uint32_t cpuid_vendor2;
1553 uint32_t cpuid_vendor3;
1554 uint32_t cpuid_version;
1555 FeatureWordArray features;
1556 /* Features that were explicitly enabled/disabled */
1557 FeatureWordArray user_features;
1558 uint32_t cpuid_model[12];
1559 /* Cache information for CPUID. When legacy-cache=on, the cache data
1560 * on each CPUID leaf will be different, because we keep compatibility
1561 * with old QEMU versions.
1562 */
1563 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
1564
1565 /* MTRRs */
1566 uint64_t mtrr_fixed[11];
1567 uint64_t mtrr_deftype;
1568 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1569
1570 /* For KVM */
1571 uint32_t mp_state;
1572 int32_t exception_nr;
1573 int32_t interrupt_injected;
1574 uint8_t soft_interrupt;
1575 uint8_t exception_pending;
1576 uint8_t exception_injected;
1577 uint8_t has_error_code;
1578 uint8_t exception_has_payload;
1579 uint64_t exception_payload;
1580 uint32_t ins_len;
1581 uint32_t sipi_vector;
1582 bool tsc_valid;
1583 int64_t tsc_khz;
1584 int64_t user_tsc_khz; /* for sanity check only */
1585 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1586 void *xsave_buf;
1587 #endif
1588 #if defined(CONFIG_KVM)
1589 struct kvm_nested_state *nested_state;
1590 #endif
1591 #if defined(CONFIG_HVF)
1592 HVFX86EmulatorState *hvf_emul;
1593 #endif
1594
1595 uint64_t mcg_cap;
1596 uint64_t mcg_ctl;
1597 uint64_t mcg_ext_ctl;
1598 uint64_t mce_banks[MCE_BANKS_DEF*4];
1599 uint64_t xstate_bv;
1600
1601 /* vmstate */
1602 uint16_t fpus_vmstate;
1603 uint16_t fptag_vmstate;
1604 uint16_t fpregs_format_vmstate;
1605
1606 uint64_t xss;
1607 uint32_t umwait;
1608
1609 TPRAccess tpr_access_type;
1610
1611 unsigned nr_dies;
1612 unsigned nr_nodes;
1613 } CPUX86State;
1614
1615 struct kvm_msrs;
1616
1617 /**
1618 * X86CPU:
1619 * @env: #CPUX86State
1620 * @migratable: If set, only migratable flags will be accepted when "enforce"
1621 * mode is used, and only migratable flags will be included in the "host"
1622 * CPU model.
1623 *
1624 * An x86 CPU.
1625 */
1626 struct X86CPU {
1627 /*< private >*/
1628 CPUState parent_obj;
1629 /*< public >*/
1630
1631 CPUNegativeOffsetState neg;
1632 CPUX86State env;
1633
1634 uint64_t ucode_rev;
1635
1636 uint32_t hyperv_spinlock_attempts;
1637 char *hyperv_vendor_id;
1638 bool hyperv_synic_kvm_only;
1639 uint64_t hyperv_features;
1640 bool hyperv_passthrough;
1641 OnOffAuto hyperv_no_nonarch_cs;
1642
1643 bool check_cpuid;
1644 bool enforce_cpuid;
1645 /*
1646 * Force features to be enabled even if the host doesn't support them.
1647 * This is dangerous and should be done only for testing CPUID
1648 * compatibility.
1649 */
1650 bool force_features;
1651 bool expose_kvm;
1652 bool expose_tcg;
1653 bool migratable;
1654 bool migrate_smi_count;
1655 bool max_features; /* Enable all supported features automatically */
1656 uint32_t apic_id;
1657
1658 /* Enables publishing of TSC increment and Local APIC bus frequencies to
1659 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */
1660 bool vmware_cpuid_freq;
1661
1662 /* if true the CPUID code directly forward host cache leaves to the guest */
1663 bool cache_info_passthrough;
1664
1665 /* if true the CPUID code directly forwards
1666 * host monitor/mwait leaves to the guest */
1667 struct {
1668 uint32_t eax;
1669 uint32_t ebx;
1670 uint32_t ecx;
1671 uint32_t edx;
1672 } mwait;
1673
1674 /* Features that were filtered out because of missing host capabilities */
1675 FeatureWordArray filtered_features;
1676
1677 /* Enable PMU CPUID bits. This can't be enabled by default yet because
1678 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
1679 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
1680 * capabilities) directly to the guest.
1681 */
1682 bool enable_pmu;
1683
1684 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
1685 * disabled by default to avoid breaking migration between QEMU with
1686 * different LMCE configurations.
1687 */
1688 bool enable_lmce;
1689
1690 /* Compatibility bits for old machine types.
1691 * If true present virtual l3 cache for VM, the vcpus in the same virtual
1692 * socket share an virtual l3 cache.
1693 */
1694 bool enable_l3_cache;
1695
1696 /* Compatibility bits for old machine types.
1697 * If true present the old cache topology information
1698 */
1699 bool legacy_cache;
1700
1701 /* Compatibility bits for old machine types: */
1702 bool enable_cpuid_0xb;
1703
1704 /* Enable auto level-increase for all CPUID leaves */
1705 bool full_cpuid_auto_level;
1706
1707 /* Enable auto level-increase for Intel Processor Trace leave */
1708 bool intel_pt_auto_level;
1709
1710 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */
1711 bool fill_mtrr_mask;
1712
1713 /* if true override the phys_bits value with a value read from the host */
1714 bool host_phys_bits;
1715
1716 /* if set, limit maximum value for phys_bits when host_phys_bits is true */
1717 uint8_t host_phys_bits_limit;
1718
1719 /* Stop SMI delivery for migration compatibility with old machines */
1720 bool kvm_no_smi_migration;
1721
1722 /* Number of physical address bits supported */
1723 uint32_t phys_bits;
1724
1725 /* in order to simplify APIC support, we leave this pointer to the
1726 user */
1727 struct DeviceState *apic_state;
1728 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
1729 Notifier machine_done;
1730
1731 struct kvm_msrs *kvm_msr_buf;
1732
1733 int32_t node_id; /* NUMA node this CPU belongs to */
1734 int32_t socket_id;
1735 int32_t die_id;
1736 int32_t core_id;
1737 int32_t thread_id;
1738
1739 int32_t hv_max_vps;
1740 };
1741
1742
1743 #ifndef CONFIG_USER_ONLY
1744 extern VMStateDescription vmstate_x86_cpu;
1745 #endif
1746
1747 /**
1748 * x86_cpu_do_interrupt:
1749 * @cpu: vCPU the interrupt is to be handled by.
1750 */
1751 void x86_cpu_do_interrupt(CPUState *cpu);
1752 bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
1753 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
1754
1755 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
1756 int cpuid, void *opaque);
1757 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
1758 int cpuid, void *opaque);
1759 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1760 void *opaque);
1761 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1762 void *opaque);
1763
1764 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
1765 Error **errp);
1766
1767 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags);
1768
1769 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1770 MemTxAttrs *attrs);
1771
1772 int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1773 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1774
1775 void x86_cpu_exec_enter(CPUState *cpu);
1776 void x86_cpu_exec_exit(CPUState *cpu);
1777
1778 void x86_cpu_list(void);
1779 int cpu_x86_support_mca_broadcast(CPUX86State *env);
1780
1781 int cpu_get_pic_interrupt(CPUX86State *s);
1782 /* MSDOS compatibility mode FPU exception support */
1783 void x86_register_ferr_irq(qemu_irq irq);
1784 void cpu_set_ignne(void);
1785 /* mpx_helper.c */
1786 void cpu_sync_bndcs_hflags(CPUX86State *env);
1787
1788 /* this function must always be used to load data in the segment
1789 cache: it synchronizes the hflags with the segment cache values */
1790 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
1791 int seg_reg, unsigned int selector,
1792 target_ulong base,
1793 unsigned int limit,
1794 unsigned int flags)
1795 {
1796 SegmentCache *sc;
1797 unsigned int new_hflags;
1798
1799 sc = &env->segs[seg_reg];
1800 sc->selector = selector;
1801 sc->base = base;
1802 sc->limit = limit;
1803 sc->flags = flags;
1804
1805 /* update the hidden flags */
1806 {
1807 if (seg_reg == R_CS) {
1808 #ifdef TARGET_X86_64
1809 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
1810 /* long mode */
1811 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1812 env->hflags &= ~(HF_ADDSEG_MASK);
1813 } else
1814 #endif
1815 {
1816 /* legacy / compatibility case */
1817 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
1818 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
1819 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
1820 new_hflags;
1821 }
1822 }
1823 if (seg_reg == R_SS) {
1824 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
1825 #if HF_CPL_MASK != 3
1826 #error HF_CPL_MASK is hardcoded
1827 #endif
1828 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
1829 /* Possibly switch between BNDCFGS and BNDCFGU */
1830 cpu_sync_bndcs_hflags(env);
1831 }
1832 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
1833 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
1834 if (env->hflags & HF_CS64_MASK) {
1835 /* zero base assumed for DS, ES and SS in long mode */
1836 } else if (!(env->cr[0] & CR0_PE_MASK) ||
1837 (env->eflags & VM_MASK) ||
1838 !(env->hflags & HF_CS32_MASK)) {
1839 /* XXX: try to avoid this test. The problem comes from the
1840 fact that is real mode or vm86 mode we only modify the
1841 'base' and 'selector' fields of the segment cache to go
1842 faster. A solution may be to force addseg to one in
1843 translate-i386.c. */
1844 new_hflags |= HF_ADDSEG_MASK;
1845 } else {
1846 new_hflags |= ((env->segs[R_DS].base |
1847 env->segs[R_ES].base |
1848 env->segs[R_SS].base) != 0) <<
1849 HF_ADDSEG_SHIFT;
1850 }
1851 env->hflags = (env->hflags &
1852 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
1853 }
1854 }
1855
1856 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
1857 uint8_t sipi_vector)
1858 {
1859 CPUState *cs = CPU(cpu);
1860 CPUX86State *env = &cpu->env;
1861
1862 env->eip = 0;
1863 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
1864 sipi_vector << 12,
1865 env->segs[R_CS].limit,
1866 env->segs[R_CS].flags);
1867 cs->halted = 0;
1868 }
1869
1870 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1871 target_ulong *base, unsigned int *limit,
1872 unsigned int *flags);
1873
1874 /* op_helper.c */
1875 /* used for debug or cpu save/restore */
1876
1877 /* cpu-exec.c */
1878 /* the following helpers are only usable in user mode simulation as
1879 they can trigger unexpected exceptions */
1880 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1881 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1882 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1883 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr);
1884 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr);
1885
1886 /* you can call this signal handler from your SIGBUS and SIGSEGV
1887 signal handlers to inform the virtual CPU of exceptions. non zero
1888 is returned if the signal was handled by the virtual CPU. */
1889 int cpu_x86_signal_handler(int host_signum, void *pinfo,
1890 void *puc);
1891
1892 /* cpu.c */
1893 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1894 uint32_t *eax, uint32_t *ebx,
1895 uint32_t *ecx, uint32_t *edx);
1896 void cpu_clear_apic_feature(CPUX86State *env);
1897 void host_cpuid(uint32_t function, uint32_t count,
1898 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1899 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
1900 bool cpu_x86_use_epyc_apic_id_encoding(const char *cpu_type);
1901
1902 /* helper.c */
1903 bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
1904 MMUAccessType access_type, int mmu_idx,
1905 bool probe, uintptr_t retaddr);
1906 void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1907
1908 #ifndef CONFIG_USER_ONLY
1909 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
1910 {
1911 return !!attrs.secure;
1912 }
1913
1914 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
1915 {
1916 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
1917 }
1918
1919 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
1920 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
1921 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
1922 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
1923 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
1924 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
1925 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
1926 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
1927 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
1928 #endif
1929
1930 void breakpoint_handler(CPUState *cs);
1931
1932 /* will be suppressed */
1933 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1934 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1935 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1936 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
1937
1938 /* hw/pc.c */
1939 uint64_t cpu_get_tsc(CPUX86State *env);
1940
1941 /* XXX: This value should match the one returned by CPUID
1942 * and in exec.c */
1943 # if defined(TARGET_X86_64)
1944 # define TCG_PHYS_ADDR_BITS 40
1945 # else
1946 # define TCG_PHYS_ADDR_BITS 36
1947 # endif
1948
1949 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
1950
1951 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
1952 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
1953 #define CPU_RESOLVING_TYPE TYPE_X86_CPU
1954
1955 #ifdef TARGET_X86_64
1956 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
1957 #else
1958 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
1959 #endif
1960
1961 #define cpu_signal_handler cpu_x86_signal_handler
1962 #define cpu_list x86_cpu_list
1963
1964 /* MMU modes definitions */
1965 #define MMU_KSMAP_IDX 0
1966 #define MMU_USER_IDX 1
1967 #define MMU_KNOSMAP_IDX 2
1968 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
1969 {
1970 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1971 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
1972 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1973 }
1974
1975 static inline int cpu_mmu_index_kernel(CPUX86State *env)
1976 {
1977 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
1978 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
1979 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1980 }
1981
1982 #define CC_DST (env->cc_dst)
1983 #define CC_SRC (env->cc_src)
1984 #define CC_SRC2 (env->cc_src2)
1985 #define CC_OP (env->cc_op)
1986
1987 /* n must be a constant to be efficient */
1988 static inline target_long lshift(target_long x, int n)
1989 {
1990 if (n >= 0) {
1991 return x << n;
1992 } else {
1993 return x >> (-n);
1994 }
1995 }
1996
1997 /* float macros */
1998 #define FT0 (env->ft0)
1999 #define ST0 (env->fpregs[env->fpstt].d)
2000 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
2001 #define ST1 ST(1)
2002
2003 /* translate.c */
2004 void tcg_x86_init(void);
2005
2006 typedef CPUX86State CPUArchState;
2007 typedef X86CPU ArchCPU;
2008
2009 #include "exec/cpu-all.h"
2010 #include "svm.h"
2011
2012 #if !defined(CONFIG_USER_ONLY)
2013 #include "hw/i386/apic.h"
2014 #endif
2015
2016 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
2017 target_ulong *cs_base, uint32_t *flags)
2018 {
2019 *cs_base = env->segs[R_CS].base;
2020 *pc = *cs_base + env->eip;
2021 *flags = env->hflags |
2022 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
2023 }
2024
2025 void do_cpu_init(X86CPU *cpu);
2026 void do_cpu_sipi(X86CPU *cpu);
2027
2028 #define MCE_INJECT_BROADCAST 1
2029 #define MCE_INJECT_UNCOND_AO 2
2030
2031 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
2032 uint64_t status, uint64_t mcg_status, uint64_t addr,
2033 uint64_t misc, int flags);
2034
2035 /* excp_helper.c */
2036 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
2037 void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
2038 uintptr_t retaddr);
2039 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
2040 int error_code);
2041 void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
2042 int error_code, uintptr_t retaddr);
2043 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
2044 int error_code, int next_eip_addend);
2045
2046 /* cc_helper.c */
2047 extern const uint8_t parity_table[256];
2048 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
2049
2050 static inline uint32_t cpu_compute_eflags(CPUX86State *env)
2051 {
2052 uint32_t eflags = env->eflags;
2053 if (tcg_enabled()) {
2054 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
2055 }
2056 return eflags;
2057 }
2058
2059 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
2060 * after generating a call to a helper that uses this.
2061 */
2062 static inline void cpu_load_eflags(CPUX86State *env, int eflags,
2063 int update_mask)
2064 {
2065 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
2066 CC_OP = CC_OP_EFLAGS;
2067 env->df = 1 - (2 * ((eflags >> 10) & 1));
2068 env->eflags = (env->eflags & ~update_mask) |
2069 (eflags & update_mask) | 0x2;
2070 }
2071
2072 /* load efer and update the corresponding hflags. XXX: do consistency
2073 checks with cpuid bits? */
2074 static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
2075 {
2076 env->efer = val;
2077 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
2078 if (env->efer & MSR_EFER_LMA) {
2079 env->hflags |= HF_LMA_MASK;
2080 }
2081 if (env->efer & MSR_EFER_SVME) {
2082 env->hflags |= HF_SVME_MASK;
2083 }
2084 }
2085
2086 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
2087 {
2088 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
2089 }
2090
2091 static inline int32_t x86_get_a20_mask(CPUX86State *env)
2092 {
2093 if (env->hflags & HF_SMM_MASK) {
2094 return -1;
2095 } else {
2096 return env->a20_mask;
2097 }
2098 }
2099
2100 static inline bool cpu_has_vmx(CPUX86State *env)
2101 {
2102 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX;
2103 }
2104
2105 /*
2106 * In order for a vCPU to enter VMX operation it must have CR4.VMXE set.
2107 * Since it was set, CR4.VMXE must remain set as long as vCPU is in
2108 * VMX operation. This is because CR4.VMXE is one of the bits set
2109 * in MSR_IA32_VMX_CR4_FIXED1.
2110 *
2111 * There is one exception to above statement when vCPU enters SMM mode.
2112 * When a vCPU enters SMM mode, it temporarily exit VMX operation and
2113 * may also reset CR4.VMXE during execution in SMM mode.
2114 * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation
2115 * and CR4.VMXE is restored to it's original value of being set.
2116 *
2117 * Therefore, when vCPU is not in SMM mode, we can infer whether
2118 * VMX is being used by examining CR4.VMXE. Otherwise, we cannot
2119 * know for certain.
2120 */
2121 static inline bool cpu_vmx_maybe_enabled(CPUX86State *env)
2122 {
2123 return cpu_has_vmx(env) &&
2124 ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK));
2125 }
2126
2127 /* fpu_helper.c */
2128 void update_fp_status(CPUX86State *env);
2129 void update_mxcsr_status(CPUX86State *env);
2130
2131 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
2132 {
2133 env->mxcsr = mxcsr;
2134 if (tcg_enabled()) {
2135 update_mxcsr_status(env);
2136 }
2137 }
2138
2139 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
2140 {
2141 env->fpuc = fpuc;
2142 if (tcg_enabled()) {
2143 update_fp_status(env);
2144 }
2145 }
2146
2147 /* mem_helper.c */
2148 void helper_lock_init(void);
2149
2150 /* svm_helper.c */
2151 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2152 uint64_t param, uintptr_t retaddr);
2153 void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
2154 uint64_t exit_info_1, uintptr_t retaddr);
2155 void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
2156
2157 /* seg_helper.c */
2158 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
2159
2160 /* smm_helper.c */
2161 void do_smm_enter(X86CPU *cpu);
2162
2163 /* apic.c */
2164 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
2165 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
2166 TPRAccess access);
2167
2168
2169 /* Change the value of a KVM-specific default
2170 *
2171 * If value is NULL, no default will be set and the original
2172 * value from the CPU model table will be kept.
2173 *
2174 * It is valid to call this function only for properties that
2175 * are already present in the kvm_default_props table.
2176 */
2177 void x86_cpu_change_kvm_default(const char *prop, const char *value);
2178
2179 /* Special values for X86CPUVersion: */
2180
2181 /* Resolve to latest CPU version */
2182 #define CPU_VERSION_LATEST -1
2183
2184 /*
2185 * Resolve to version defined by current machine type.
2186 * See x86_cpu_set_default_version()
2187 */
2188 #define CPU_VERSION_AUTO -2
2189
2190 /* Don't resolve to any versioned CPU models, like old QEMU versions */
2191 #define CPU_VERSION_LEGACY 0
2192
2193 typedef int X86CPUVersion;
2194
2195 /*
2196 * Set default CPU model version for CPU models having
2197 * version == CPU_VERSION_AUTO.
2198 */
2199 void x86_cpu_set_default_version(X86CPUVersion version);
2200
2201 /* Return name of 32-bit register, from a R_* constant */
2202 const char *get_register_name_32(unsigned int reg);
2203
2204 void enable_compat_apic_id_mode(void);
2205
2206 #define APIC_DEFAULT_ADDRESS 0xfee00000
2207 #define APIC_SPACE_SIZE 0x100000
2208
2209 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
2210
2211 /* cpu.c */
2212 bool cpu_is_bsp(X86CPU *cpu);
2213
2214 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf);
2215 void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf);
2216 void x86_update_hflags(CPUX86State* env);
2217
2218 static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat)
2219 {
2220 return !!(cpu->hyperv_features & BIT(feat));
2221 }
2222
2223 #if defined(TARGET_X86_64) && \
2224 defined(CONFIG_USER_ONLY) && \
2225 defined(CONFIG_LINUX)
2226 # define TARGET_VSYSCALL_PAGE (UINT64_C(-10) << 20)
2227 #endif
2228
2229 #endif /* I386_CPU_H */