gdbstub: extend GByteArray to read register helpers
[qemu.git] / target / i386 / cpu.h
1 /*
2 * i386 virtual CPU header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef I386_CPU_H
21 #define I386_CPU_H
22
23 #include "sysemu/tcg.h"
24 #include "cpu-qom.h"
25 #include "hyperv-proto.h"
26 #include "exec/cpu-defs.h"
27 #include "qapi/qapi-types-common.h"
28
29 /* The x86 has a strong memory model with some store-after-load re-ordering */
30 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
31
32 /* Maximum instruction code size */
33 #define TARGET_MAX_INSN_SIZE 16
34
35 /* support for self modifying code even if the modified instruction is
36 close to the modifying instruction */
37 #define TARGET_HAS_PRECISE_SMC
38
39 #ifdef TARGET_X86_64
40 #define I386_ELF_MACHINE EM_X86_64
41 #define ELF_MACHINE_UNAME "x86_64"
42 #else
43 #define I386_ELF_MACHINE EM_386
44 #define ELF_MACHINE_UNAME "i686"
45 #endif
46
47 enum {
48 R_EAX = 0,
49 R_ECX = 1,
50 R_EDX = 2,
51 R_EBX = 3,
52 R_ESP = 4,
53 R_EBP = 5,
54 R_ESI = 6,
55 R_EDI = 7,
56 R_R8 = 8,
57 R_R9 = 9,
58 R_R10 = 10,
59 R_R11 = 11,
60 R_R12 = 12,
61 R_R13 = 13,
62 R_R14 = 14,
63 R_R15 = 15,
64
65 R_AL = 0,
66 R_CL = 1,
67 R_DL = 2,
68 R_BL = 3,
69 R_AH = 4,
70 R_CH = 5,
71 R_DH = 6,
72 R_BH = 7,
73 };
74
75 typedef enum X86Seg {
76 R_ES = 0,
77 R_CS = 1,
78 R_SS = 2,
79 R_DS = 3,
80 R_FS = 4,
81 R_GS = 5,
82 R_LDTR = 6,
83 R_TR = 7,
84 } X86Seg;
85
86 /* segment descriptor fields */
87 #define DESC_G_SHIFT 23
88 #define DESC_G_MASK (1 << DESC_G_SHIFT)
89 #define DESC_B_SHIFT 22
90 #define DESC_B_MASK (1 << DESC_B_SHIFT)
91 #define DESC_L_SHIFT 21 /* x86_64 only : 64 bit code segment */
92 #define DESC_L_MASK (1 << DESC_L_SHIFT)
93 #define DESC_AVL_SHIFT 20
94 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT)
95 #define DESC_P_SHIFT 15
96 #define DESC_P_MASK (1 << DESC_P_SHIFT)
97 #define DESC_DPL_SHIFT 13
98 #define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
99 #define DESC_S_SHIFT 12
100 #define DESC_S_MASK (1 << DESC_S_SHIFT)
101 #define DESC_TYPE_SHIFT 8
102 #define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
103 #define DESC_A_MASK (1 << 8)
104
105 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
106 #define DESC_C_MASK (1 << 10) /* code: conforming */
107 #define DESC_R_MASK (1 << 9) /* code: readable */
108
109 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
110 #define DESC_W_MASK (1 << 9) /* data: writable */
111
112 #define DESC_TSS_BUSY_MASK (1 << 9)
113
114 /* eflags masks */
115 #define CC_C 0x0001
116 #define CC_P 0x0004
117 #define CC_A 0x0010
118 #define CC_Z 0x0040
119 #define CC_S 0x0080
120 #define CC_O 0x0800
121
122 #define TF_SHIFT 8
123 #define IOPL_SHIFT 12
124 #define VM_SHIFT 17
125
126 #define TF_MASK 0x00000100
127 #define IF_MASK 0x00000200
128 #define DF_MASK 0x00000400
129 #define IOPL_MASK 0x00003000
130 #define NT_MASK 0x00004000
131 #define RF_MASK 0x00010000
132 #define VM_MASK 0x00020000
133 #define AC_MASK 0x00040000
134 #define VIF_MASK 0x00080000
135 #define VIP_MASK 0x00100000
136 #define ID_MASK 0x00200000
137
138 /* hidden flags - used internally by qemu to represent additional cpu
139 states. Only the INHIBIT_IRQ, SMM and SVMI are not redundant. We
140 avoid using the IOPL_MASK, TF_MASK, VM_MASK and AC_MASK bit
141 positions to ease oring with eflags. */
142 /* current cpl */
143 #define HF_CPL_SHIFT 0
144 /* true if hardware interrupts must be disabled for next instruction */
145 #define HF_INHIBIT_IRQ_SHIFT 3
146 /* 16 or 32 segments */
147 #define HF_CS32_SHIFT 4
148 #define HF_SS32_SHIFT 5
149 /* zero base for DS, ES and SS : can be '0' only in 32 bit CS segment */
150 #define HF_ADDSEG_SHIFT 6
151 /* copy of CR0.PE (protected mode) */
152 #define HF_PE_SHIFT 7
153 #define HF_TF_SHIFT 8 /* must be same as eflags */
154 #define HF_MP_SHIFT 9 /* the order must be MP, EM, TS */
155 #define HF_EM_SHIFT 10
156 #define HF_TS_SHIFT 11
157 #define HF_IOPL_SHIFT 12 /* must be same as eflags */
158 #define HF_LMA_SHIFT 14 /* only used on x86_64: long mode active */
159 #define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
160 #define HF_RF_SHIFT 16 /* must be same as eflags */
161 #define HF_VM_SHIFT 17 /* must be same as eflags */
162 #define HF_AC_SHIFT 18 /* must be same as eflags */
163 #define HF_SMM_SHIFT 19 /* CPU in SMM mode */
164 #define HF_SVME_SHIFT 20 /* SVME enabled (copy of EFER.SVME) */
165 #define HF_GUEST_SHIFT 21 /* SVM intercepts are active */
166 #define HF_OSFXSR_SHIFT 22 /* CR4.OSFXSR */
167 #define HF_SMAP_SHIFT 23 /* CR4.SMAP */
168 #define HF_IOBPT_SHIFT 24 /* an io breakpoint enabled */
169 #define HF_MPX_EN_SHIFT 25 /* MPX Enabled (CR4+XCR0+BNDCFGx) */
170 #define HF_MPX_IU_SHIFT 26 /* BND registers in-use */
171
172 #define HF_CPL_MASK (3 << HF_CPL_SHIFT)
173 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
174 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
175 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
176 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
177 #define HF_PE_MASK (1 << HF_PE_SHIFT)
178 #define HF_TF_MASK (1 << HF_TF_SHIFT)
179 #define HF_MP_MASK (1 << HF_MP_SHIFT)
180 #define HF_EM_MASK (1 << HF_EM_SHIFT)
181 #define HF_TS_MASK (1 << HF_TS_SHIFT)
182 #define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
183 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
184 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
185 #define HF_RF_MASK (1 << HF_RF_SHIFT)
186 #define HF_VM_MASK (1 << HF_VM_SHIFT)
187 #define HF_AC_MASK (1 << HF_AC_SHIFT)
188 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
189 #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
190 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT)
191 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
192 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
193 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
194 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
195 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
196
197 /* hflags2 */
198
199 #define HF2_GIF_SHIFT 0 /* if set CPU takes interrupts */
200 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
201 #define HF2_NMI_SHIFT 2 /* CPU serving NMI */
202 #define HF2_VINTR_SHIFT 3 /* value of V_INTR_MASKING bit */
203 #define HF2_SMM_INSIDE_NMI_SHIFT 4 /* CPU serving SMI nested inside NMI */
204 #define HF2_MPX_PR_SHIFT 5 /* BNDCFGx.BNDPRESERVE */
205 #define HF2_NPT_SHIFT 6 /* Nested Paging enabled */
206 #define HF2_IGNNE_SHIFT 7 /* Ignore CR0.NE=0 */
207
208 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
209 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
210 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
211 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
212 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
213 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
214 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
215 #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT)
216
217 #define CR0_PE_SHIFT 0
218 #define CR0_MP_SHIFT 1
219
220 #define CR0_PE_MASK (1U << 0)
221 #define CR0_MP_MASK (1U << 1)
222 #define CR0_EM_MASK (1U << 2)
223 #define CR0_TS_MASK (1U << 3)
224 #define CR0_ET_MASK (1U << 4)
225 #define CR0_NE_MASK (1U << 5)
226 #define CR0_WP_MASK (1U << 16)
227 #define CR0_AM_MASK (1U << 18)
228 #define CR0_PG_MASK (1U << 31)
229
230 #define CR4_VME_MASK (1U << 0)
231 #define CR4_PVI_MASK (1U << 1)
232 #define CR4_TSD_MASK (1U << 2)
233 #define CR4_DE_MASK (1U << 3)
234 #define CR4_PSE_MASK (1U << 4)
235 #define CR4_PAE_MASK (1U << 5)
236 #define CR4_MCE_MASK (1U << 6)
237 #define CR4_PGE_MASK (1U << 7)
238 #define CR4_PCE_MASK (1U << 8)
239 #define CR4_OSFXSR_SHIFT 9
240 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
241 #define CR4_OSXMMEXCPT_MASK (1U << 10)
242 #define CR4_LA57_MASK (1U << 12)
243 #define CR4_VMXE_MASK (1U << 13)
244 #define CR4_SMXE_MASK (1U << 14)
245 #define CR4_FSGSBASE_MASK (1U << 16)
246 #define CR4_PCIDE_MASK (1U << 17)
247 #define CR4_OSXSAVE_MASK (1U << 18)
248 #define CR4_SMEP_MASK (1U << 20)
249 #define CR4_SMAP_MASK (1U << 21)
250 #define CR4_PKE_MASK (1U << 22)
251
252 #define DR6_BD (1 << 13)
253 #define DR6_BS (1 << 14)
254 #define DR6_BT (1 << 15)
255 #define DR6_FIXED_1 0xffff0ff0
256
257 #define DR7_GD (1 << 13)
258 #define DR7_TYPE_SHIFT 16
259 #define DR7_LEN_SHIFT 18
260 #define DR7_FIXED_1 0x00000400
261 #define DR7_GLOBAL_BP_MASK 0xaa
262 #define DR7_LOCAL_BP_MASK 0x55
263 #define DR7_MAX_BP 4
264 #define DR7_TYPE_BP_INST 0x0
265 #define DR7_TYPE_DATA_WR 0x1
266 #define DR7_TYPE_IO_RW 0x2
267 #define DR7_TYPE_DATA_RW 0x3
268
269 #define PG_PRESENT_BIT 0
270 #define PG_RW_BIT 1
271 #define PG_USER_BIT 2
272 #define PG_PWT_BIT 3
273 #define PG_PCD_BIT 4
274 #define PG_ACCESSED_BIT 5
275 #define PG_DIRTY_BIT 6
276 #define PG_PSE_BIT 7
277 #define PG_GLOBAL_BIT 8
278 #define PG_PSE_PAT_BIT 12
279 #define PG_PKRU_BIT 59
280 #define PG_NX_BIT 63
281
282 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
283 #define PG_RW_MASK (1 << PG_RW_BIT)
284 #define PG_USER_MASK (1 << PG_USER_BIT)
285 #define PG_PWT_MASK (1 << PG_PWT_BIT)
286 #define PG_PCD_MASK (1 << PG_PCD_BIT)
287 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
288 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
289 #define PG_PSE_MASK (1 << PG_PSE_BIT)
290 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
291 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
292 #define PG_ADDRESS_MASK 0x000ffffffffff000LL
293 #define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
294 #define PG_HI_USER_MASK 0x7ff0000000000000LL
295 #define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
296 #define PG_NX_MASK (1ULL << PG_NX_BIT)
297
298 #define PG_ERROR_W_BIT 1
299
300 #define PG_ERROR_P_MASK 0x01
301 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
302 #define PG_ERROR_U_MASK 0x04
303 #define PG_ERROR_RSVD_MASK 0x08
304 #define PG_ERROR_I_D_MASK 0x10
305 #define PG_ERROR_PK_MASK 0x20
306
307 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
308 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
309 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */
310
311 #define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
312 #define MCE_BANKS_DEF 10
313
314 #define MCG_CAP_BANKS_MASK 0xff
315
316 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
317 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
318 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
319 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */
320
321 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
322
323 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
324 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
325 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
326 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
327 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
328 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
329 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
330 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
331 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
332
333 /* MISC register defines */
334 #define MCM_ADDR_SEGOFF 0 /* segment offset */
335 #define MCM_ADDR_LINEAR 1 /* linear address */
336 #define MCM_ADDR_PHYS 2 /* physical address */
337 #define MCM_ADDR_MEM 3 /* memory address */
338 #define MCM_ADDR_GENERIC 7 /* generic */
339
340 #define MSR_IA32_TSC 0x10
341 #define MSR_IA32_APICBASE 0x1b
342 #define MSR_IA32_APICBASE_BSP (1<<8)
343 #define MSR_IA32_APICBASE_ENABLE (1<<11)
344 #define MSR_IA32_APICBASE_EXTD (1 << 10)
345 #define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
346 #define MSR_IA32_FEATURE_CONTROL 0x0000003a
347 #define MSR_TSC_ADJUST 0x0000003b
348 #define MSR_IA32_SPEC_CTRL 0x48
349 #define MSR_VIRT_SSBD 0xc001011f
350 #define MSR_IA32_PRED_CMD 0x49
351 #define MSR_IA32_UCODE_REV 0x8b
352 #define MSR_IA32_CORE_CAPABILITY 0xcf
353
354 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
355 #define ARCH_CAP_TSX_CTRL_MSR (1<<7)
356
357 #define MSR_IA32_TSX_CTRL 0x122
358 #define MSR_IA32_TSCDEADLINE 0x6e0
359
360 #define FEATURE_CONTROL_LOCKED (1<<0)
361 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
362 #define FEATURE_CONTROL_LMCE (1<<20)
363
364 #define MSR_P6_PERFCTR0 0xc1
365
366 #define MSR_IA32_SMBASE 0x9e
367 #define MSR_SMI_COUNT 0x34
368 #define MSR_MTRRcap 0xfe
369 #define MSR_MTRRcap_VCNT 8
370 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
371 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
372
373 #define MSR_IA32_SYSENTER_CS 0x174
374 #define MSR_IA32_SYSENTER_ESP 0x175
375 #define MSR_IA32_SYSENTER_EIP 0x176
376
377 #define MSR_MCG_CAP 0x179
378 #define MSR_MCG_STATUS 0x17a
379 #define MSR_MCG_CTL 0x17b
380 #define MSR_MCG_EXT_CTL 0x4d0
381
382 #define MSR_P6_EVNTSEL0 0x186
383
384 #define MSR_IA32_PERF_STATUS 0x198
385
386 #define MSR_IA32_MISC_ENABLE 0x1a0
387 /* Indicates good rep/movs microcode on some processors: */
388 #define MSR_IA32_MISC_ENABLE_DEFAULT 1
389 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
390
391 #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
392 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
393
394 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
395
396 #define MSR_MTRRfix64K_00000 0x250
397 #define MSR_MTRRfix16K_80000 0x258
398 #define MSR_MTRRfix16K_A0000 0x259
399 #define MSR_MTRRfix4K_C0000 0x268
400 #define MSR_MTRRfix4K_C8000 0x269
401 #define MSR_MTRRfix4K_D0000 0x26a
402 #define MSR_MTRRfix4K_D8000 0x26b
403 #define MSR_MTRRfix4K_E0000 0x26c
404 #define MSR_MTRRfix4K_E8000 0x26d
405 #define MSR_MTRRfix4K_F0000 0x26e
406 #define MSR_MTRRfix4K_F8000 0x26f
407
408 #define MSR_PAT 0x277
409
410 #define MSR_MTRRdefType 0x2ff
411
412 #define MSR_CORE_PERF_FIXED_CTR0 0x309
413 #define MSR_CORE_PERF_FIXED_CTR1 0x30a
414 #define MSR_CORE_PERF_FIXED_CTR2 0x30b
415 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
416 #define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
417 #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
418 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
419
420 #define MSR_MC0_CTL 0x400
421 #define MSR_MC0_STATUS 0x401
422 #define MSR_MC0_ADDR 0x402
423 #define MSR_MC0_MISC 0x403
424
425 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560
426 #define MSR_IA32_RTIT_OUTPUT_MASK 0x561
427 #define MSR_IA32_RTIT_CTL 0x570
428 #define MSR_IA32_RTIT_STATUS 0x571
429 #define MSR_IA32_RTIT_CR3_MATCH 0x572
430 #define MSR_IA32_RTIT_ADDR0_A 0x580
431 #define MSR_IA32_RTIT_ADDR0_B 0x581
432 #define MSR_IA32_RTIT_ADDR1_A 0x582
433 #define MSR_IA32_RTIT_ADDR1_B 0x583
434 #define MSR_IA32_RTIT_ADDR2_A 0x584
435 #define MSR_IA32_RTIT_ADDR2_B 0x585
436 #define MSR_IA32_RTIT_ADDR3_A 0x586
437 #define MSR_IA32_RTIT_ADDR3_B 0x587
438 #define MAX_RTIT_ADDRS 8
439
440 #define MSR_EFER 0xc0000080
441
442 #define MSR_EFER_SCE (1 << 0)
443 #define MSR_EFER_LME (1 << 8)
444 #define MSR_EFER_LMA (1 << 10)
445 #define MSR_EFER_NXE (1 << 11)
446 #define MSR_EFER_SVME (1 << 12)
447 #define MSR_EFER_FFXSR (1 << 14)
448
449 #define MSR_STAR 0xc0000081
450 #define MSR_LSTAR 0xc0000082
451 #define MSR_CSTAR 0xc0000083
452 #define MSR_FMASK 0xc0000084
453 #define MSR_FSBASE 0xc0000100
454 #define MSR_GSBASE 0xc0000101
455 #define MSR_KERNELGSBASE 0xc0000102
456 #define MSR_TSC_AUX 0xc0000103
457
458 #define MSR_VM_HSAVE_PA 0xc0010117
459
460 #define MSR_IA32_BNDCFGS 0x00000d90
461 #define MSR_IA32_XSS 0x00000da0
462 #define MSR_IA32_UMWAIT_CONTROL 0xe1
463
464 #define MSR_IA32_VMX_BASIC 0x00000480
465 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
466 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
467 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
468 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
469 #define MSR_IA32_VMX_MISC 0x00000485
470 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
471 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
472 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
473 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
474 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
475 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
476 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
477 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
478 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
479 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
480 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
481 #define MSR_IA32_VMX_VMFUNC 0x00000491
482
483 #define XSTATE_FP_BIT 0
484 #define XSTATE_SSE_BIT 1
485 #define XSTATE_YMM_BIT 2
486 #define XSTATE_BNDREGS_BIT 3
487 #define XSTATE_BNDCSR_BIT 4
488 #define XSTATE_OPMASK_BIT 5
489 #define XSTATE_ZMM_Hi256_BIT 6
490 #define XSTATE_Hi16_ZMM_BIT 7
491 #define XSTATE_PKRU_BIT 9
492
493 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
494 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
495 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
496 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
497 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
498 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
499 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
500 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
501 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
502
503 /* CPUID feature words */
504 typedef enum FeatureWord {
505 FEAT_1_EDX, /* CPUID[1].EDX */
506 FEAT_1_ECX, /* CPUID[1].ECX */
507 FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
508 FEAT_7_0_ECX, /* CPUID[EAX=7,ECX=0].ECX */
509 FEAT_7_0_EDX, /* CPUID[EAX=7,ECX=0].EDX */
510 FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */
511 FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
512 FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
513 FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
514 FEAT_8000_0008_EBX, /* CPUID[8000_0008].EBX */
515 FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
516 FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
517 FEAT_KVM_HINTS, /* CPUID[4000_0001].EDX */
518 FEAT_HYPERV_EAX, /* CPUID[4000_0003].EAX */
519 FEAT_HYPERV_EBX, /* CPUID[4000_0003].EBX */
520 FEAT_HYPERV_EDX, /* CPUID[4000_0003].EDX */
521 FEAT_HV_RECOMM_EAX, /* CPUID[4000_0004].EAX */
522 FEAT_HV_NESTED_EAX, /* CPUID[4000_000A].EAX */
523 FEAT_SVM, /* CPUID[8000_000A].EDX */
524 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */
525 FEAT_6_EAX, /* CPUID[6].EAX */
526 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
527 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
528 FEAT_ARCH_CAPABILITIES,
529 FEAT_CORE_CAPABILITY,
530 FEAT_VMX_PROCBASED_CTLS,
531 FEAT_VMX_SECONDARY_CTLS,
532 FEAT_VMX_PINBASED_CTLS,
533 FEAT_VMX_EXIT_CTLS,
534 FEAT_VMX_ENTRY_CTLS,
535 FEAT_VMX_MISC,
536 FEAT_VMX_EPT_VPID_CAPS,
537 FEAT_VMX_BASIC,
538 FEAT_VMX_VMFUNC,
539 FEATURE_WORDS,
540 } FeatureWord;
541
542 typedef uint64_t FeatureWordArray[FEATURE_WORDS];
543
544 /* cpuid_features bits */
545 #define CPUID_FP87 (1U << 0)
546 #define CPUID_VME (1U << 1)
547 #define CPUID_DE (1U << 2)
548 #define CPUID_PSE (1U << 3)
549 #define CPUID_TSC (1U << 4)
550 #define CPUID_MSR (1U << 5)
551 #define CPUID_PAE (1U << 6)
552 #define CPUID_MCE (1U << 7)
553 #define CPUID_CX8 (1U << 8)
554 #define CPUID_APIC (1U << 9)
555 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */
556 #define CPUID_MTRR (1U << 12)
557 #define CPUID_PGE (1U << 13)
558 #define CPUID_MCA (1U << 14)
559 #define CPUID_CMOV (1U << 15)
560 #define CPUID_PAT (1U << 16)
561 #define CPUID_PSE36 (1U << 17)
562 #define CPUID_PN (1U << 18)
563 #define CPUID_CLFLUSH (1U << 19)
564 #define CPUID_DTS (1U << 21)
565 #define CPUID_ACPI (1U << 22)
566 #define CPUID_MMX (1U << 23)
567 #define CPUID_FXSR (1U << 24)
568 #define CPUID_SSE (1U << 25)
569 #define CPUID_SSE2 (1U << 26)
570 #define CPUID_SS (1U << 27)
571 #define CPUID_HT (1U << 28)
572 #define CPUID_TM (1U << 29)
573 #define CPUID_IA64 (1U << 30)
574 #define CPUID_PBE (1U << 31)
575
576 #define CPUID_EXT_SSE3 (1U << 0)
577 #define CPUID_EXT_PCLMULQDQ (1U << 1)
578 #define CPUID_EXT_DTES64 (1U << 2)
579 #define CPUID_EXT_MONITOR (1U << 3)
580 #define CPUID_EXT_DSCPL (1U << 4)
581 #define CPUID_EXT_VMX (1U << 5)
582 #define CPUID_EXT_SMX (1U << 6)
583 #define CPUID_EXT_EST (1U << 7)
584 #define CPUID_EXT_TM2 (1U << 8)
585 #define CPUID_EXT_SSSE3 (1U << 9)
586 #define CPUID_EXT_CID (1U << 10)
587 #define CPUID_EXT_FMA (1U << 12)
588 #define CPUID_EXT_CX16 (1U << 13)
589 #define CPUID_EXT_XTPR (1U << 14)
590 #define CPUID_EXT_PDCM (1U << 15)
591 #define CPUID_EXT_PCID (1U << 17)
592 #define CPUID_EXT_DCA (1U << 18)
593 #define CPUID_EXT_SSE41 (1U << 19)
594 #define CPUID_EXT_SSE42 (1U << 20)
595 #define CPUID_EXT_X2APIC (1U << 21)
596 #define CPUID_EXT_MOVBE (1U << 22)
597 #define CPUID_EXT_POPCNT (1U << 23)
598 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
599 #define CPUID_EXT_AES (1U << 25)
600 #define CPUID_EXT_XSAVE (1U << 26)
601 #define CPUID_EXT_OSXSAVE (1U << 27)
602 #define CPUID_EXT_AVX (1U << 28)
603 #define CPUID_EXT_F16C (1U << 29)
604 #define CPUID_EXT_RDRAND (1U << 30)
605 #define CPUID_EXT_HYPERVISOR (1U << 31)
606
607 #define CPUID_EXT2_FPU (1U << 0)
608 #define CPUID_EXT2_VME (1U << 1)
609 #define CPUID_EXT2_DE (1U << 2)
610 #define CPUID_EXT2_PSE (1U << 3)
611 #define CPUID_EXT2_TSC (1U << 4)
612 #define CPUID_EXT2_MSR (1U << 5)
613 #define CPUID_EXT2_PAE (1U << 6)
614 #define CPUID_EXT2_MCE (1U << 7)
615 #define CPUID_EXT2_CX8 (1U << 8)
616 #define CPUID_EXT2_APIC (1U << 9)
617 #define CPUID_EXT2_SYSCALL (1U << 11)
618 #define CPUID_EXT2_MTRR (1U << 12)
619 #define CPUID_EXT2_PGE (1U << 13)
620 #define CPUID_EXT2_MCA (1U << 14)
621 #define CPUID_EXT2_CMOV (1U << 15)
622 #define CPUID_EXT2_PAT (1U << 16)
623 #define CPUID_EXT2_PSE36 (1U << 17)
624 #define CPUID_EXT2_MP (1U << 19)
625 #define CPUID_EXT2_NX (1U << 20)
626 #define CPUID_EXT2_MMXEXT (1U << 22)
627 #define CPUID_EXT2_MMX (1U << 23)
628 #define CPUID_EXT2_FXSR (1U << 24)
629 #define CPUID_EXT2_FFXSR (1U << 25)
630 #define CPUID_EXT2_PDPE1GB (1U << 26)
631 #define CPUID_EXT2_RDTSCP (1U << 27)
632 #define CPUID_EXT2_LM (1U << 29)
633 #define CPUID_EXT2_3DNOWEXT (1U << 30)
634 #define CPUID_EXT2_3DNOW (1U << 31)
635
636 /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */
637 #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
638 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
639 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
640 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
641 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
642 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
643 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
644 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
645 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
646
647 #define CPUID_EXT3_LAHF_LM (1U << 0)
648 #define CPUID_EXT3_CMP_LEG (1U << 1)
649 #define CPUID_EXT3_SVM (1U << 2)
650 #define CPUID_EXT3_EXTAPIC (1U << 3)
651 #define CPUID_EXT3_CR8LEG (1U << 4)
652 #define CPUID_EXT3_ABM (1U << 5)
653 #define CPUID_EXT3_SSE4A (1U << 6)
654 #define CPUID_EXT3_MISALIGNSSE (1U << 7)
655 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
656 #define CPUID_EXT3_OSVW (1U << 9)
657 #define CPUID_EXT3_IBS (1U << 10)
658 #define CPUID_EXT3_XOP (1U << 11)
659 #define CPUID_EXT3_SKINIT (1U << 12)
660 #define CPUID_EXT3_WDT (1U << 13)
661 #define CPUID_EXT3_LWP (1U << 15)
662 #define CPUID_EXT3_FMA4 (1U << 16)
663 #define CPUID_EXT3_TCE (1U << 17)
664 #define CPUID_EXT3_NODEID (1U << 19)
665 #define CPUID_EXT3_TBM (1U << 21)
666 #define CPUID_EXT3_TOPOEXT (1U << 22)
667 #define CPUID_EXT3_PERFCORE (1U << 23)
668 #define CPUID_EXT3_PERFNB (1U << 24)
669
670 #define CPUID_SVM_NPT (1U << 0)
671 #define CPUID_SVM_LBRV (1U << 1)
672 #define CPUID_SVM_SVMLOCK (1U << 2)
673 #define CPUID_SVM_NRIPSAVE (1U << 3)
674 #define CPUID_SVM_TSCSCALE (1U << 4)
675 #define CPUID_SVM_VMCBCLEAN (1U << 5)
676 #define CPUID_SVM_FLUSHASID (1U << 6)
677 #define CPUID_SVM_DECODEASSIST (1U << 7)
678 #define CPUID_SVM_PAUSEFILTER (1U << 10)
679 #define CPUID_SVM_PFTHRESHOLD (1U << 12)
680
681 /* Support RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE */
682 #define CPUID_7_0_EBX_FSGSBASE (1U << 0)
683 /* 1st Group of Advanced Bit Manipulation Extensions */
684 #define CPUID_7_0_EBX_BMI1 (1U << 3)
685 /* Hardware Lock Elision */
686 #define CPUID_7_0_EBX_HLE (1U << 4)
687 /* Intel Advanced Vector Extensions 2 */
688 #define CPUID_7_0_EBX_AVX2 (1U << 5)
689 /* Supervisor-mode Execution Prevention */
690 #define CPUID_7_0_EBX_SMEP (1U << 7)
691 /* 2nd Group of Advanced Bit Manipulation Extensions */
692 #define CPUID_7_0_EBX_BMI2 (1U << 8)
693 /* Enhanced REP MOVSB/STOSB */
694 #define CPUID_7_0_EBX_ERMS (1U << 9)
695 /* Invalidate Process-Context Identifier */
696 #define CPUID_7_0_EBX_INVPCID (1U << 10)
697 /* Restricted Transactional Memory */
698 #define CPUID_7_0_EBX_RTM (1U << 11)
699 /* Memory Protection Extension */
700 #define CPUID_7_0_EBX_MPX (1U << 14)
701 /* AVX-512 Foundation */
702 #define CPUID_7_0_EBX_AVX512F (1U << 16)
703 /* AVX-512 Doubleword & Quadword Instruction */
704 #define CPUID_7_0_EBX_AVX512DQ (1U << 17)
705 /* Read Random SEED */
706 #define CPUID_7_0_EBX_RDSEED (1U << 18)
707 /* ADCX and ADOX instructions */
708 #define CPUID_7_0_EBX_ADX (1U << 19)
709 /* Supervisor Mode Access Prevention */
710 #define CPUID_7_0_EBX_SMAP (1U << 20)
711 /* AVX-512 Integer Fused Multiply Add */
712 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
713 /* Persistent Commit */
714 #define CPUID_7_0_EBX_PCOMMIT (1U << 22)
715 /* Flush a Cache Line Optimized */
716 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
717 /* Cache Line Write Back */
718 #define CPUID_7_0_EBX_CLWB (1U << 24)
719 /* Intel Processor Trace */
720 #define CPUID_7_0_EBX_INTEL_PT (1U << 25)
721 /* AVX-512 Prefetch */
722 #define CPUID_7_0_EBX_AVX512PF (1U << 26)
723 /* AVX-512 Exponential and Reciprocal */
724 #define CPUID_7_0_EBX_AVX512ER (1U << 27)
725 /* AVX-512 Conflict Detection */
726 #define CPUID_7_0_EBX_AVX512CD (1U << 28)
727 /* SHA1/SHA256 Instruction Extensions */
728 #define CPUID_7_0_EBX_SHA_NI (1U << 29)
729 /* AVX-512 Byte and Word Instructions */
730 #define CPUID_7_0_EBX_AVX512BW (1U << 30)
731 /* AVX-512 Vector Length Extensions */
732 #define CPUID_7_0_EBX_AVX512VL (1U << 31)
733
734 /* AVX-512 Vector Byte Manipulation Instruction */
735 #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1)
736 /* User-Mode Instruction Prevention */
737 #define CPUID_7_0_ECX_UMIP (1U << 2)
738 /* Protection Keys for User-mode Pages */
739 #define CPUID_7_0_ECX_PKU (1U << 3)
740 /* OS Enable Protection Keys */
741 #define CPUID_7_0_ECX_OSPKE (1U << 4)
742 /* UMONITOR/UMWAIT/TPAUSE Instructions */
743 #define CPUID_7_0_ECX_WAITPKG (1U << 5)
744 /* Additional AVX-512 Vector Byte Manipulation Instruction */
745 #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6)
746 /* Galois Field New Instructions */
747 #define CPUID_7_0_ECX_GFNI (1U << 8)
748 /* Vector AES Instructions */
749 #define CPUID_7_0_ECX_VAES (1U << 9)
750 /* Carry-Less Multiplication Quadword */
751 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
752 /* Vector Neural Network Instructions */
753 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
754 /* Support for VPOPCNT[B,W] and VPSHUFBITQMB */
755 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
756 /* POPCNT for vectors of DW/QW */
757 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
758 /* 5-level Page Tables */
759 #define CPUID_7_0_ECX_LA57 (1U << 16)
760 /* Read Processor ID */
761 #define CPUID_7_0_ECX_RDPID (1U << 22)
762 /* Cache Line Demote Instruction */
763 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
764 /* Move Doubleword as Direct Store Instruction */
765 #define CPUID_7_0_ECX_MOVDIRI (1U << 27)
766 /* Move 64 Bytes as Direct Store Instruction */
767 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28)
768
769 /* AVX512 Neural Network Instructions */
770 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
771 /* AVX512 Multiply Accumulation Single Precision */
772 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
773 /* Speculation Control */
774 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
775 /* Single Thread Indirect Branch Predictors */
776 #define CPUID_7_0_EDX_STIBP (1U << 27)
777 /* Arch Capabilities */
778 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
779 /* Core Capability */
780 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30)
781 /* Speculative Store Bypass Disable */
782 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
783
784 /* AVX512 BFloat16 Instruction */
785 #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
786
787 /* CLZERO instruction */
788 #define CPUID_8000_0008_EBX_CLZERO (1U << 0)
789 /* Always save/restore FP error pointers */
790 #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2)
791 /* Write back and do not invalidate cache */
792 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
793 /* Indirect Branch Prediction Barrier */
794 #define CPUID_8000_0008_EBX_IBPB (1U << 12)
795
796 #define CPUID_XSAVE_XSAVEOPT (1U << 0)
797 #define CPUID_XSAVE_XSAVEC (1U << 1)
798 #define CPUID_XSAVE_XGETBV1 (1U << 2)
799 #define CPUID_XSAVE_XSAVES (1U << 3)
800
801 #define CPUID_6_EAX_ARAT (1U << 2)
802
803 /* CPUID[0x80000007].EDX flags: */
804 #define CPUID_APM_INVTSC (1U << 8)
805
806 #define CPUID_VENDOR_SZ 12
807
808 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
809 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
810 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
811 #define CPUID_VENDOR_INTEL "GenuineIntel"
812
813 #define CPUID_VENDOR_AMD_1 0x68747541 /* "Auth" */
814 #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */
815 #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */
816 #define CPUID_VENDOR_AMD "AuthenticAMD"
817
818 #define CPUID_VENDOR_VIA "CentaurHauls"
819
820 #define CPUID_VENDOR_HYGON "HygonGenuine"
821
822 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
823 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
824 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
825 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
826 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
827 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
828
829 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */
830 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
831
832 /* CPUID[0xB].ECX level types */
833 #define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
834 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
835 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
836 #define CPUID_TOPOLOGY_LEVEL_DIE (5U << 8)
837
838 /* MSR Feature Bits */
839 #define MSR_ARCH_CAP_RDCL_NO (1U << 0)
840 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
841 #define MSR_ARCH_CAP_RSBA (1U << 2)
842 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
843 #define MSR_ARCH_CAP_SSB_NO (1U << 4)
844 #define MSR_ARCH_CAP_MDS_NO (1U << 5)
845 #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
846 #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
847 #define MSR_ARCH_CAP_TAA_NO (1U << 8)
848
849 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
850
851 /* VMX MSR features */
852 #define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull
853 #define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32)
854 #define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32)
855 #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49)
856 #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54)
857 #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55)
858
859 #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full
860 #define MSR_VMX_MISC_STORE_LMA (1ULL << 5)
861 #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6)
862 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7)
863 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8)
864 #define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull
865 #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29)
866 #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30)
867
868 #define MSR_VMX_EPT_EXECONLY (1ULL << 0)
869 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6)
870 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7)
871 #define MSR_VMX_EPT_UC (1ULL << 8)
872 #define MSR_VMX_EPT_WB (1ULL << 14)
873 #define MSR_VMX_EPT_2MB (1ULL << 16)
874 #define MSR_VMX_EPT_1GB (1ULL << 17)
875 #define MSR_VMX_EPT_INVEPT (1ULL << 20)
876 #define MSR_VMX_EPT_AD_BITS (1ULL << 21)
877 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22)
878 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25)
879 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26)
880 #define MSR_VMX_EPT_INVVPID (1ULL << 32)
881 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40)
882 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41)
883 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42)
884 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43)
885
886 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0)
887
888
889 /* VMX controls */
890 #define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
891 #define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008
892 #define VMX_CPU_BASED_HLT_EXITING 0x00000080
893 #define VMX_CPU_BASED_INVLPG_EXITING 0x00000200
894 #define VMX_CPU_BASED_MWAIT_EXITING 0x00000400
895 #define VMX_CPU_BASED_RDPMC_EXITING 0x00000800
896 #define VMX_CPU_BASED_RDTSC_EXITING 0x00001000
897 #define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000
898 #define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000
899 #define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000
900 #define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000
901 #define VMX_CPU_BASED_TPR_SHADOW 0x00200000
902 #define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
903 #define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000
904 #define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000
905 #define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000
906 #define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
907 #define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000
908 #define VMX_CPU_BASED_MONITOR_EXITING 0x20000000
909 #define VMX_CPU_BASED_PAUSE_EXITING 0x40000000
910 #define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
911
912 #define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
913 #define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002
914 #define VMX_SECONDARY_EXEC_DESC 0x00000004
915 #define VMX_SECONDARY_EXEC_RDTSCP 0x00000008
916 #define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
917 #define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020
918 #define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040
919 #define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
920 #define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
921 #define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
922 #define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
923 #define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800
924 #define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
925 #define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000
926 #define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000
927 #define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000
928 #define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000
929 #define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000
930 #define VMX_SECONDARY_EXEC_XSAVES 0x00100000
931
932 #define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001
933 #define VMX_PIN_BASED_NMI_EXITING 0x00000008
934 #define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020
935 #define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
936 #define VMX_PIN_BASED_POSTED_INTR 0x00000080
937
938 #define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
939 #define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
940 #define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
941 #define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
942 #define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000
943 #define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000
944 #define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000
945 #define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000
946 #define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
947 #define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000
948 #define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000
949 #define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
950
951 #define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
952 #define VMX_VM_ENTRY_IA32E_MODE 0x00000200
953 #define VMX_VM_ENTRY_SMM 0x00000400
954 #define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
955 #define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
956 #define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000
957 #define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000
958 #define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000
959 #define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000
960 #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
961
962 /* Supported Hyper-V Enlightenments */
963 #define HYPERV_FEAT_RELAXED 0
964 #define HYPERV_FEAT_VAPIC 1
965 #define HYPERV_FEAT_TIME 2
966 #define HYPERV_FEAT_CRASH 3
967 #define HYPERV_FEAT_RESET 4
968 #define HYPERV_FEAT_VPINDEX 5
969 #define HYPERV_FEAT_RUNTIME 6
970 #define HYPERV_FEAT_SYNIC 7
971 #define HYPERV_FEAT_STIMER 8
972 #define HYPERV_FEAT_FREQUENCIES 9
973 #define HYPERV_FEAT_REENLIGHTENMENT 10
974 #define HYPERV_FEAT_TLBFLUSH 11
975 #define HYPERV_FEAT_EVMCS 12
976 #define HYPERV_FEAT_IPI 13
977 #define HYPERV_FEAT_STIMER_DIRECT 14
978
979 #ifndef HYPERV_SPINLOCK_NEVER_RETRY
980 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
981 #endif
982
983 #define EXCP00_DIVZ 0
984 #define EXCP01_DB 1
985 #define EXCP02_NMI 2
986 #define EXCP03_INT3 3
987 #define EXCP04_INTO 4
988 #define EXCP05_BOUND 5
989 #define EXCP06_ILLOP 6
990 #define EXCP07_PREX 7
991 #define EXCP08_DBLE 8
992 #define EXCP09_XERR 9
993 #define EXCP0A_TSS 10
994 #define EXCP0B_NOSEG 11
995 #define EXCP0C_STACK 12
996 #define EXCP0D_GPF 13
997 #define EXCP0E_PAGE 14
998 #define EXCP10_COPR 16
999 #define EXCP11_ALGN 17
1000 #define EXCP12_MCHK 18
1001
1002 #define EXCP_SYSCALL 0x100 /* only happens in user only emulation
1003 for syscall instruction */
1004 #define EXCP_VMEXIT 0x100
1005
1006 /* i386-specific interrupt pending bits. */
1007 #define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
1008 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
1009 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
1010 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
1011 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
1012 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
1013 #define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
1014
1015 /* Use a clearer name for this. */
1016 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
1017
1018 /* Instead of computing the condition codes after each x86 instruction,
1019 * QEMU just stores one operand (called CC_SRC), the result
1020 * (called CC_DST) and the type of operation (called CC_OP). When the
1021 * condition codes are needed, the condition codes can be calculated
1022 * using this information. Condition codes are not generated if they
1023 * are only needed for conditional branches.
1024 */
1025 typedef enum {
1026 CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
1027 CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */
1028
1029 CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */
1030 CC_OP_MULW,
1031 CC_OP_MULL,
1032 CC_OP_MULQ,
1033
1034 CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1035 CC_OP_ADDW,
1036 CC_OP_ADDL,
1037 CC_OP_ADDQ,
1038
1039 CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1040 CC_OP_ADCW,
1041 CC_OP_ADCL,
1042 CC_OP_ADCQ,
1043
1044 CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1045 CC_OP_SUBW,
1046 CC_OP_SUBL,
1047 CC_OP_SUBQ,
1048
1049 CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
1050 CC_OP_SBBW,
1051 CC_OP_SBBL,
1052 CC_OP_SBBQ,
1053
1054 CC_OP_LOGICB, /* modify all flags, CC_DST = res */
1055 CC_OP_LOGICW,
1056 CC_OP_LOGICL,
1057 CC_OP_LOGICQ,
1058
1059 CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
1060 CC_OP_INCW,
1061 CC_OP_INCL,
1062 CC_OP_INCQ,
1063
1064 CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */
1065 CC_OP_DECW,
1066 CC_OP_DECL,
1067 CC_OP_DECQ,
1068
1069 CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */
1070 CC_OP_SHLW,
1071 CC_OP_SHLL,
1072 CC_OP_SHLQ,
1073
1074 CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
1075 CC_OP_SARW,
1076 CC_OP_SARL,
1077 CC_OP_SARQ,
1078
1079 CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */
1080 CC_OP_BMILGW,
1081 CC_OP_BMILGL,
1082 CC_OP_BMILGQ,
1083
1084 CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */
1085 CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */
1086 CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */
1087
1088 CC_OP_CLR, /* Z set, all other flags clear. */
1089 CC_OP_POPCNT, /* Z via CC_SRC, all other flags clear. */
1090
1091 CC_OP_NB,
1092 } CCOp;
1093
1094 typedef struct SegmentCache {
1095 uint32_t selector;
1096 target_ulong base;
1097 uint32_t limit;
1098 uint32_t flags;
1099 } SegmentCache;
1100
1101 #define MMREG_UNION(n, bits) \
1102 union n { \
1103 uint8_t _b_##n[(bits)/8]; \
1104 uint16_t _w_##n[(bits)/16]; \
1105 uint32_t _l_##n[(bits)/32]; \
1106 uint64_t _q_##n[(bits)/64]; \
1107 float32 _s_##n[(bits)/32]; \
1108 float64 _d_##n[(bits)/64]; \
1109 }
1110
1111 typedef union {
1112 uint8_t _b[16];
1113 uint16_t _w[8];
1114 uint32_t _l[4];
1115 uint64_t _q[2];
1116 } XMMReg;
1117
1118 typedef union {
1119 uint8_t _b[32];
1120 uint16_t _w[16];
1121 uint32_t _l[8];
1122 uint64_t _q[4];
1123 } YMMReg;
1124
1125 typedef MMREG_UNION(ZMMReg, 512) ZMMReg;
1126 typedef MMREG_UNION(MMXReg, 64) MMXReg;
1127
1128 typedef struct BNDReg {
1129 uint64_t lb;
1130 uint64_t ub;
1131 } BNDReg;
1132
1133 typedef struct BNDCSReg {
1134 uint64_t cfgu;
1135 uint64_t sts;
1136 } BNDCSReg;
1137
1138 #define BNDCFG_ENABLE 1ULL
1139 #define BNDCFG_BNDPRESERVE 2ULL
1140 #define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
1141
1142 #ifdef HOST_WORDS_BIGENDIAN
1143 #define ZMM_B(n) _b_ZMMReg[63 - (n)]
1144 #define ZMM_W(n) _w_ZMMReg[31 - (n)]
1145 #define ZMM_L(n) _l_ZMMReg[15 - (n)]
1146 #define ZMM_S(n) _s_ZMMReg[15 - (n)]
1147 #define ZMM_Q(n) _q_ZMMReg[7 - (n)]
1148 #define ZMM_D(n) _d_ZMMReg[7 - (n)]
1149
1150 #define MMX_B(n) _b_MMXReg[7 - (n)]
1151 #define MMX_W(n) _w_MMXReg[3 - (n)]
1152 #define MMX_L(n) _l_MMXReg[1 - (n)]
1153 #define MMX_S(n) _s_MMXReg[1 - (n)]
1154 #else
1155 #define ZMM_B(n) _b_ZMMReg[n]
1156 #define ZMM_W(n) _w_ZMMReg[n]
1157 #define ZMM_L(n) _l_ZMMReg[n]
1158 #define ZMM_S(n) _s_ZMMReg[n]
1159 #define ZMM_Q(n) _q_ZMMReg[n]
1160 #define ZMM_D(n) _d_ZMMReg[n]
1161
1162 #define MMX_B(n) _b_MMXReg[n]
1163 #define MMX_W(n) _w_MMXReg[n]
1164 #define MMX_L(n) _l_MMXReg[n]
1165 #define MMX_S(n) _s_MMXReg[n]
1166 #endif
1167 #define MMX_Q(n) _q_MMXReg[n]
1168
1169 typedef union {
1170 floatx80 d __attribute__((aligned(16)));
1171 MMXReg mmx;
1172 } FPReg;
1173
1174 typedef struct {
1175 uint64_t base;
1176 uint64_t mask;
1177 } MTRRVar;
1178
1179 #define CPU_NB_REGS64 16
1180 #define CPU_NB_REGS32 8
1181
1182 #ifdef TARGET_X86_64
1183 #define CPU_NB_REGS CPU_NB_REGS64
1184 #else
1185 #define CPU_NB_REGS CPU_NB_REGS32
1186 #endif
1187
1188 #define MAX_FIXED_COUNTERS 3
1189 #define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
1190
1191 #define TARGET_INSN_START_EXTRA_WORDS 1
1192
1193 #define NB_OPMASK_REGS 8
1194
1195 /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish
1196 * that APIC ID hasn't been set yet
1197 */
1198 #define UNASSIGNED_APIC_ID 0xFFFFFFFF
1199
1200 typedef union X86LegacyXSaveArea {
1201 struct {
1202 uint16_t fcw;
1203 uint16_t fsw;
1204 uint8_t ftw;
1205 uint8_t reserved;
1206 uint16_t fpop;
1207 uint64_t fpip;
1208 uint64_t fpdp;
1209 uint32_t mxcsr;
1210 uint32_t mxcsr_mask;
1211 FPReg fpregs[8];
1212 uint8_t xmm_regs[16][16];
1213 };
1214 uint8_t data[512];
1215 } X86LegacyXSaveArea;
1216
1217 typedef struct X86XSaveHeader {
1218 uint64_t xstate_bv;
1219 uint64_t xcomp_bv;
1220 uint64_t reserve0;
1221 uint8_t reserved[40];
1222 } X86XSaveHeader;
1223
1224 /* Ext. save area 2: AVX State */
1225 typedef struct XSaveAVX {
1226 uint8_t ymmh[16][16];
1227 } XSaveAVX;
1228
1229 /* Ext. save area 3: BNDREG */
1230 typedef struct XSaveBNDREG {
1231 BNDReg bnd_regs[4];
1232 } XSaveBNDREG;
1233
1234 /* Ext. save area 4: BNDCSR */
1235 typedef union XSaveBNDCSR {
1236 BNDCSReg bndcsr;
1237 uint8_t data[64];
1238 } XSaveBNDCSR;
1239
1240 /* Ext. save area 5: Opmask */
1241 typedef struct XSaveOpmask {
1242 uint64_t opmask_regs[NB_OPMASK_REGS];
1243 } XSaveOpmask;
1244
1245 /* Ext. save area 6: ZMM_Hi256 */
1246 typedef struct XSaveZMM_Hi256 {
1247 uint8_t zmm_hi256[16][32];
1248 } XSaveZMM_Hi256;
1249
1250 /* Ext. save area 7: Hi16_ZMM */
1251 typedef struct XSaveHi16_ZMM {
1252 uint8_t hi16_zmm[16][64];
1253 } XSaveHi16_ZMM;
1254
1255 /* Ext. save area 9: PKRU state */
1256 typedef struct XSavePKRU {
1257 uint32_t pkru;
1258 uint32_t padding;
1259 } XSavePKRU;
1260
1261 typedef struct X86XSaveArea {
1262 X86LegacyXSaveArea legacy;
1263 X86XSaveHeader header;
1264
1265 /* Extended save areas: */
1266
1267 /* AVX State: */
1268 XSaveAVX avx_state;
1269 uint8_t padding[960 - 576 - sizeof(XSaveAVX)];
1270 /* MPX State: */
1271 XSaveBNDREG bndreg_state;
1272 XSaveBNDCSR bndcsr_state;
1273 /* AVX-512 State: */
1274 XSaveOpmask opmask_state;
1275 XSaveZMM_Hi256 zmm_hi256_state;
1276 XSaveHi16_ZMM hi16_zmm_state;
1277 /* PKRU State: */
1278 XSavePKRU pkru_state;
1279 } X86XSaveArea;
1280
1281 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240);
1282 QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
1283 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0);
1284 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
1285 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400);
1286 QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
1287 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440);
1288 QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
1289 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480);
1290 QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
1291 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680);
1292 QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
1293 QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80);
1294 QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
1295
1296 typedef enum TPRAccess {
1297 TPR_ACCESS_READ,
1298 TPR_ACCESS_WRITE,
1299 } TPRAccess;
1300
1301 /* Cache information data structures: */
1302
1303 enum CacheType {
1304 DATA_CACHE,
1305 INSTRUCTION_CACHE,
1306 UNIFIED_CACHE
1307 };
1308
1309 typedef struct CPUCacheInfo {
1310 enum CacheType type;
1311 uint8_t level;
1312 /* Size in bytes */
1313 uint32_t size;
1314 /* Line size, in bytes */
1315 uint16_t line_size;
1316 /*
1317 * Associativity.
1318 * Note: representation of fully-associative caches is not implemented
1319 */
1320 uint8_t associativity;
1321 /* Physical line partitions. CPUID[0x8000001D].EBX, CPUID[4].EBX */
1322 uint8_t partitions;
1323 /* Number of sets. CPUID[0x8000001D].ECX, CPUID[4].ECX */
1324 uint32_t sets;
1325 /*
1326 * Lines per tag.
1327 * AMD-specific: CPUID[0x80000005], CPUID[0x80000006].
1328 * (Is this synonym to @partitions?)
1329 */
1330 uint8_t lines_per_tag;
1331
1332 /* Self-initializing cache */
1333 bool self_init;
1334 /*
1335 * WBINVD/INVD is not guaranteed to act upon lower level caches of
1336 * non-originating threads sharing this cache.
1337 * CPUID[4].EDX[bit 0], CPUID[0x8000001D].EDX[bit 0]
1338 */
1339 bool no_invd_sharing;
1340 /*
1341 * Cache is inclusive of lower cache levels.
1342 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
1343 */
1344 bool inclusive;
1345 /*
1346 * A complex function is used to index the cache, potentially using all
1347 * address bits. CPUID[4].EDX[bit 2].
1348 */
1349 bool complex_indexing;
1350 } CPUCacheInfo;
1351
1352
1353 typedef struct CPUCaches {
1354 CPUCacheInfo *l1d_cache;
1355 CPUCacheInfo *l1i_cache;
1356 CPUCacheInfo *l2_cache;
1357 CPUCacheInfo *l3_cache;
1358 } CPUCaches;
1359
1360 typedef struct CPUX86State {
1361 /* standard registers */
1362 target_ulong regs[CPU_NB_REGS];
1363 target_ulong eip;
1364 target_ulong eflags; /* eflags register. During CPU emulation, CC
1365 flags and DF are set to zero because they are
1366 stored elsewhere */
1367
1368 /* emulator internal eflags handling */
1369 target_ulong cc_dst;
1370 target_ulong cc_src;
1371 target_ulong cc_src2;
1372 uint32_t cc_op;
1373 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
1374 uint32_t hflags; /* TB flags, see HF_xxx constants. These flags
1375 are known at translation time. */
1376 uint32_t hflags2; /* various other flags, see HF2_xxx constants. */
1377
1378 /* segments */
1379 SegmentCache segs[6]; /* selector values */
1380 SegmentCache ldt;
1381 SegmentCache tr;
1382 SegmentCache gdt; /* only base and limit are used */
1383 SegmentCache idt; /* only base and limit are used */
1384
1385 target_ulong cr[5]; /* NOTE: cr1 is unused */
1386 int32_t a20_mask;
1387
1388 BNDReg bnd_regs[4];
1389 BNDCSReg bndcs_regs;
1390 uint64_t msr_bndcfgs;
1391 uint64_t efer;
1392
1393 /* Beginning of state preserved by INIT (dummy marker). */
1394 struct {} start_init_save;
1395
1396 /* FPU state */
1397 unsigned int fpstt; /* top of stack index */
1398 uint16_t fpus;
1399 uint16_t fpuc;
1400 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
1401 FPReg fpregs[8];
1402 /* KVM-only so far */
1403 uint16_t fpop;
1404 uint64_t fpip;
1405 uint64_t fpdp;
1406
1407 /* emulator internal variables */
1408 float_status fp_status;
1409 floatx80 ft0;
1410
1411 float_status mmx_status; /* for 3DNow! float ops */
1412 float_status sse_status;
1413 uint32_t mxcsr;
1414 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
1415 ZMMReg xmm_t0;
1416 MMXReg mmx_t0;
1417
1418 XMMReg ymmh_regs[CPU_NB_REGS];
1419
1420 uint64_t opmask_regs[NB_OPMASK_REGS];
1421 YMMReg zmmh_regs[CPU_NB_REGS];
1422 ZMMReg hi16_zmm_regs[CPU_NB_REGS];
1423
1424 /* sysenter registers */
1425 uint32_t sysenter_cs;
1426 target_ulong sysenter_esp;
1427 target_ulong sysenter_eip;
1428 uint64_t star;
1429
1430 uint64_t vm_hsave;
1431
1432 #ifdef TARGET_X86_64
1433 target_ulong lstar;
1434 target_ulong cstar;
1435 target_ulong fmask;
1436 target_ulong kernelgsbase;
1437 #endif
1438
1439 uint64_t tsc;
1440 uint64_t tsc_adjust;
1441 uint64_t tsc_deadline;
1442 uint64_t tsc_aux;
1443
1444 uint64_t xcr0;
1445
1446 uint64_t mcg_status;
1447 uint64_t msr_ia32_misc_enable;
1448 uint64_t msr_ia32_feature_control;
1449
1450 uint64_t msr_fixed_ctr_ctrl;
1451 uint64_t msr_global_ctrl;
1452 uint64_t msr_global_status;
1453 uint64_t msr_global_ovf_ctrl;
1454 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1455 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1456 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1457
1458 uint64_t pat;
1459 uint32_t smbase;
1460 uint64_t msr_smi_count;
1461
1462 uint32_t pkru;
1463 uint32_t tsx_ctrl;
1464
1465 uint64_t spec_ctrl;
1466 uint64_t virt_ssbd;
1467
1468 /* End of state preserved by INIT (dummy marker). */
1469 struct {} end_init_save;
1470
1471 uint64_t system_time_msr;
1472 uint64_t wall_clock_msr;
1473 uint64_t steal_time_msr;
1474 uint64_t async_pf_en_msr;
1475 uint64_t pv_eoi_en_msr;
1476 uint64_t poll_control_msr;
1477
1478 /* Partition-wide HV MSRs, will be updated only on the first vcpu */
1479 uint64_t msr_hv_hypercall;
1480 uint64_t msr_hv_guest_os_id;
1481 uint64_t msr_hv_tsc;
1482
1483 /* Per-VCPU HV MSRs */
1484 uint64_t msr_hv_vapic;
1485 uint64_t msr_hv_crash_params[HV_CRASH_PARAMS];
1486 uint64_t msr_hv_runtime;
1487 uint64_t msr_hv_synic_control;
1488 uint64_t msr_hv_synic_evt_page;
1489 uint64_t msr_hv_synic_msg_page;
1490 uint64_t msr_hv_synic_sint[HV_SINT_COUNT];
1491 uint64_t msr_hv_stimer_config[HV_STIMER_COUNT];
1492 uint64_t msr_hv_stimer_count[HV_STIMER_COUNT];
1493 uint64_t msr_hv_reenlightenment_control;
1494 uint64_t msr_hv_tsc_emulation_control;
1495 uint64_t msr_hv_tsc_emulation_status;
1496
1497 uint64_t msr_rtit_ctrl;
1498 uint64_t msr_rtit_status;
1499 uint64_t msr_rtit_output_base;
1500 uint64_t msr_rtit_output_mask;
1501 uint64_t msr_rtit_cr3_match;
1502 uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS];
1503
1504 /* exception/interrupt handling */
1505 int error_code;
1506 int exception_is_int;
1507 target_ulong exception_next_eip;
1508 target_ulong dr[8]; /* debug registers; note dr4 and dr5 are unused */
1509 union {
1510 struct CPUBreakpoint *cpu_breakpoint[4];
1511 struct CPUWatchpoint *cpu_watchpoint[4];
1512 }; /* break/watchpoints for dr[0..3] */
1513 int old_exception; /* exception in flight */
1514
1515 uint64_t vm_vmcb;
1516 uint64_t tsc_offset;
1517 uint64_t intercept;
1518 uint16_t intercept_cr_read;
1519 uint16_t intercept_cr_write;
1520 uint16_t intercept_dr_read;
1521 uint16_t intercept_dr_write;
1522 uint32_t intercept_exceptions;
1523 uint64_t nested_cr3;
1524 uint32_t nested_pg_mode;
1525 uint8_t v_tpr;
1526
1527 /* KVM states, automatically cleared on reset */
1528 uint8_t nmi_injected;
1529 uint8_t nmi_pending;
1530
1531 uintptr_t retaddr;
1532
1533 /* Fields up to this point are cleared by a CPU reset */
1534 struct {} end_reset_fields;
1535
1536 /* Fields after this point are preserved across CPU reset. */
1537
1538 /* processor features (e.g. for CPUID insn) */
1539 /* Minimum cpuid leaf 7 value */
1540 uint32_t cpuid_level_func7;
1541 /* Actual cpuid leaf 7 value */
1542 uint32_t cpuid_min_level_func7;
1543 /* Minimum level/xlevel/xlevel2, based on CPU model + features */
1544 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1545 /* Maximum level/xlevel/xlevel2 value for auto-assignment: */
1546 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1547 /* Actual level/xlevel/xlevel2 value: */
1548 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1549 uint32_t cpuid_vendor1;
1550 uint32_t cpuid_vendor2;
1551 uint32_t cpuid_vendor3;
1552 uint32_t cpuid_version;
1553 FeatureWordArray features;
1554 /* Features that were explicitly enabled/disabled */
1555 FeatureWordArray user_features;
1556 uint32_t cpuid_model[12];
1557 /* Cache information for CPUID. When legacy-cache=on, the cache data
1558 * on each CPUID leaf will be different, because we keep compatibility
1559 * with old QEMU versions.
1560 */
1561 CPUCaches cache_info_cpuid2, cache_info_cpuid4, cache_info_amd;
1562
1563 /* MTRRs */
1564 uint64_t mtrr_fixed[11];
1565 uint64_t mtrr_deftype;
1566 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1567
1568 /* For KVM */
1569 uint32_t mp_state;
1570 int32_t exception_nr;
1571 int32_t interrupt_injected;
1572 uint8_t soft_interrupt;
1573 uint8_t exception_pending;
1574 uint8_t exception_injected;
1575 uint8_t has_error_code;
1576 uint8_t exception_has_payload;
1577 uint64_t exception_payload;
1578 uint32_t ins_len;
1579 uint32_t sipi_vector;
1580 bool tsc_valid;
1581 int64_t tsc_khz;
1582 int64_t user_tsc_khz; /* for sanity check only */
1583 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1584 void *xsave_buf;
1585 #endif
1586 #if defined(CONFIG_KVM)
1587 struct kvm_nested_state *nested_state;
1588 #endif
1589 #if defined(CONFIG_HVF)
1590 HVFX86EmulatorState *hvf_emul;
1591 #endif
1592
1593 uint64_t mcg_cap;
1594 uint64_t mcg_ctl;
1595 uint64_t mcg_ext_ctl;
1596 uint64_t mce_banks[MCE_BANKS_DEF*4];
1597 uint64_t xstate_bv;
1598
1599 /* vmstate */
1600 uint16_t fpus_vmstate;
1601 uint16_t fptag_vmstate;
1602 uint16_t fpregs_format_vmstate;
1603
1604 uint64_t xss;
1605 uint32_t umwait;
1606
1607 TPRAccess tpr_access_type;
1608
1609 unsigned nr_dies;
1610 } CPUX86State;
1611
1612 struct kvm_msrs;
1613
1614 /**
1615 * X86CPU:
1616 * @env: #CPUX86State
1617 * @migratable: If set, only migratable flags will be accepted when "enforce"
1618 * mode is used, and only migratable flags will be included in the "host"
1619 * CPU model.
1620 *
1621 * An x86 CPU.
1622 */
1623 struct X86CPU {
1624 /*< private >*/
1625 CPUState parent_obj;
1626 /*< public >*/
1627
1628 CPUNegativeOffsetState neg;
1629 CPUX86State env;
1630
1631 uint64_t ucode_rev;
1632
1633 uint32_t hyperv_spinlock_attempts;
1634 char *hyperv_vendor_id;
1635 bool hyperv_synic_kvm_only;
1636 uint64_t hyperv_features;
1637 bool hyperv_passthrough;
1638 OnOffAuto hyperv_no_nonarch_cs;
1639
1640 bool check_cpuid;
1641 bool enforce_cpuid;
1642 /*
1643 * Force features to be enabled even if the host doesn't support them.
1644 * This is dangerous and should be done only for testing CPUID
1645 * compatibility.
1646 */
1647 bool force_features;
1648 bool expose_kvm;
1649 bool expose_tcg;
1650 bool migratable;
1651 bool migrate_smi_count;
1652 bool max_features; /* Enable all supported features automatically */
1653 uint32_t apic_id;
1654
1655 /* Enables publishing of TSC increment and Local APIC bus frequencies to
1656 * the guest OS in CPUID page 0x40000010, the same way that VMWare does. */
1657 bool vmware_cpuid_freq;
1658
1659 /* if true the CPUID code directly forward host cache leaves to the guest */
1660 bool cache_info_passthrough;
1661
1662 /* if true the CPUID code directly forwards
1663 * host monitor/mwait leaves to the guest */
1664 struct {
1665 uint32_t eax;
1666 uint32_t ebx;
1667 uint32_t ecx;
1668 uint32_t edx;
1669 } mwait;
1670
1671 /* Features that were filtered out because of missing host capabilities */
1672 FeatureWordArray filtered_features;
1673
1674 /* Enable PMU CPUID bits. This can't be enabled by default yet because
1675 * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
1676 * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
1677 * capabilities) directly to the guest.
1678 */
1679 bool enable_pmu;
1680
1681 /* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
1682 * disabled by default to avoid breaking migration between QEMU with
1683 * different LMCE configurations.
1684 */
1685 bool enable_lmce;
1686
1687 /* Compatibility bits for old machine types.
1688 * If true present virtual l3 cache for VM, the vcpus in the same virtual
1689 * socket share an virtual l3 cache.
1690 */
1691 bool enable_l3_cache;
1692
1693 /* Compatibility bits for old machine types.
1694 * If true present the old cache topology information
1695 */
1696 bool legacy_cache;
1697
1698 /* Compatibility bits for old machine types: */
1699 bool enable_cpuid_0xb;
1700
1701 /* Enable auto level-increase for all CPUID leaves */
1702 bool full_cpuid_auto_level;
1703
1704 /* Enable auto level-increase for Intel Processor Trace leave */
1705 bool intel_pt_auto_level;
1706
1707 /* if true fill the top bits of the MTRR_PHYSMASKn variable range */
1708 bool fill_mtrr_mask;
1709
1710 /* if true override the phys_bits value with a value read from the host */
1711 bool host_phys_bits;
1712
1713 /* if set, limit maximum value for phys_bits when host_phys_bits is true */
1714 uint8_t host_phys_bits_limit;
1715
1716 /* Stop SMI delivery for migration compatibility with old machines */
1717 bool kvm_no_smi_migration;
1718
1719 /* Number of physical address bits supported */
1720 uint32_t phys_bits;
1721
1722 /* in order to simplify APIC support, we leave this pointer to the
1723 user */
1724 struct DeviceState *apic_state;
1725 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
1726 Notifier machine_done;
1727
1728 struct kvm_msrs *kvm_msr_buf;
1729
1730 int32_t node_id; /* NUMA node this CPU belongs to */
1731 int32_t socket_id;
1732 int32_t die_id;
1733 int32_t core_id;
1734 int32_t thread_id;
1735
1736 int32_t hv_max_vps;
1737 };
1738
1739
1740 #ifndef CONFIG_USER_ONLY
1741 extern VMStateDescription vmstate_x86_cpu;
1742 #endif
1743
1744 /**
1745 * x86_cpu_do_interrupt:
1746 * @cpu: vCPU the interrupt is to be handled by.
1747 */
1748 void x86_cpu_do_interrupt(CPUState *cpu);
1749 bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
1750 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
1751
1752 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
1753 int cpuid, void *opaque);
1754 int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
1755 int cpuid, void *opaque);
1756 int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1757 void *opaque);
1758 int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1759 void *opaque);
1760
1761 void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
1762 Error **errp);
1763
1764 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags);
1765
1766 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
1767 MemTxAttrs *attrs);
1768
1769 int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
1770 int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1771
1772 void x86_cpu_exec_enter(CPUState *cpu);
1773 void x86_cpu_exec_exit(CPUState *cpu);
1774
1775 void x86_cpu_list(void);
1776 int cpu_x86_support_mca_broadcast(CPUX86State *env);
1777
1778 int cpu_get_pic_interrupt(CPUX86State *s);
1779 /* MSDOS compatibility mode FPU exception support */
1780 void x86_register_ferr_irq(qemu_irq irq);
1781 void cpu_set_ignne(void);
1782 /* mpx_helper.c */
1783 void cpu_sync_bndcs_hflags(CPUX86State *env);
1784
1785 /* this function must always be used to load data in the segment
1786 cache: it synchronizes the hflags with the segment cache values */
1787 static inline void cpu_x86_load_seg_cache(CPUX86State *env,
1788 int seg_reg, unsigned int selector,
1789 target_ulong base,
1790 unsigned int limit,
1791 unsigned int flags)
1792 {
1793 SegmentCache *sc;
1794 unsigned int new_hflags;
1795
1796 sc = &env->segs[seg_reg];
1797 sc->selector = selector;
1798 sc->base = base;
1799 sc->limit = limit;
1800 sc->flags = flags;
1801
1802 /* update the hidden flags */
1803 {
1804 if (seg_reg == R_CS) {
1805 #ifdef TARGET_X86_64
1806 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
1807 /* long mode */
1808 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1809 env->hflags &= ~(HF_ADDSEG_MASK);
1810 } else
1811 #endif
1812 {
1813 /* legacy / compatibility case */
1814 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
1815 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
1816 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
1817 new_hflags;
1818 }
1819 }
1820 if (seg_reg == R_SS) {
1821 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
1822 #if HF_CPL_MASK != 3
1823 #error HF_CPL_MASK is hardcoded
1824 #endif
1825 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
1826 /* Possibly switch between BNDCFGS and BNDCFGU */
1827 cpu_sync_bndcs_hflags(env);
1828 }
1829 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
1830 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
1831 if (env->hflags & HF_CS64_MASK) {
1832 /* zero base assumed for DS, ES and SS in long mode */
1833 } else if (!(env->cr[0] & CR0_PE_MASK) ||
1834 (env->eflags & VM_MASK) ||
1835 !(env->hflags & HF_CS32_MASK)) {
1836 /* XXX: try to avoid this test. The problem comes from the
1837 fact that is real mode or vm86 mode we only modify the
1838 'base' and 'selector' fields of the segment cache to go
1839 faster. A solution may be to force addseg to one in
1840 translate-i386.c. */
1841 new_hflags |= HF_ADDSEG_MASK;
1842 } else {
1843 new_hflags |= ((env->segs[R_DS].base |
1844 env->segs[R_ES].base |
1845 env->segs[R_SS].base) != 0) <<
1846 HF_ADDSEG_SHIFT;
1847 }
1848 env->hflags = (env->hflags &
1849 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
1850 }
1851 }
1852
1853 static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
1854 uint8_t sipi_vector)
1855 {
1856 CPUState *cs = CPU(cpu);
1857 CPUX86State *env = &cpu->env;
1858
1859 env->eip = 0;
1860 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
1861 sipi_vector << 12,
1862 env->segs[R_CS].limit,
1863 env->segs[R_CS].flags);
1864 cs->halted = 0;
1865 }
1866
1867 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1868 target_ulong *base, unsigned int *limit,
1869 unsigned int *flags);
1870
1871 /* op_helper.c */
1872 /* used for debug or cpu save/restore */
1873
1874 /* cpu-exec.c */
1875 /* the following helpers are only usable in user mode simulation as
1876 they can trigger unexpected exceptions */
1877 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1878 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1879 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1880 void cpu_x86_fxsave(CPUX86State *s, target_ulong ptr);
1881 void cpu_x86_fxrstor(CPUX86State *s, target_ulong ptr);
1882
1883 /* you can call this signal handler from your SIGBUS and SIGSEGV
1884 signal handlers to inform the virtual CPU of exceptions. non zero
1885 is returned if the signal was handled by the virtual CPU. */
1886 int cpu_x86_signal_handler(int host_signum, void *pinfo,
1887 void *puc);
1888
1889 /* cpu.c */
1890 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1891 uint32_t *eax, uint32_t *ebx,
1892 uint32_t *ecx, uint32_t *edx);
1893 void cpu_clear_apic_feature(CPUX86State *env);
1894 void host_cpuid(uint32_t function, uint32_t count,
1895 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1896 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping);
1897
1898 /* helper.c */
1899 bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
1900 MMUAccessType access_type, int mmu_idx,
1901 bool probe, uintptr_t retaddr);
1902 void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1903
1904 #ifndef CONFIG_USER_ONLY
1905 static inline int x86_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
1906 {
1907 return !!attrs.secure;
1908 }
1909
1910 static inline AddressSpace *cpu_addressspace(CPUState *cs, MemTxAttrs attrs)
1911 {
1912 return cpu_get_address_space(cs, cpu_asidx_from_attrs(cs, attrs));
1913 }
1914
1915 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
1916 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
1917 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
1918 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
1919 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
1920 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
1921 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
1922 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
1923 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
1924 #endif
1925
1926 void breakpoint_handler(CPUState *cs);
1927
1928 /* will be suppressed */
1929 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1930 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1931 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1932 void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
1933
1934 /* hw/pc.c */
1935 uint64_t cpu_get_tsc(CPUX86State *env);
1936
1937 /* XXX: This value should match the one returned by CPUID
1938 * and in exec.c */
1939 # if defined(TARGET_X86_64)
1940 # define TCG_PHYS_ADDR_BITS 40
1941 # else
1942 # define TCG_PHYS_ADDR_BITS 36
1943 # endif
1944
1945 #define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
1946
1947 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
1948 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
1949 #define CPU_RESOLVING_TYPE TYPE_X86_CPU
1950
1951 #ifdef TARGET_X86_64
1952 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64")
1953 #else
1954 #define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32")
1955 #endif
1956
1957 #define cpu_signal_handler cpu_x86_signal_handler
1958 #define cpu_list x86_cpu_list
1959
1960 /* MMU modes definitions */
1961 #define MMU_KSMAP_IDX 0
1962 #define MMU_USER_IDX 1
1963 #define MMU_KNOSMAP_IDX 2
1964 static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
1965 {
1966 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1967 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
1968 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1969 }
1970
1971 static inline int cpu_mmu_index_kernel(CPUX86State *env)
1972 {
1973 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
1974 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
1975 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1976 }
1977
1978 #define CC_DST (env->cc_dst)
1979 #define CC_SRC (env->cc_src)
1980 #define CC_SRC2 (env->cc_src2)
1981 #define CC_OP (env->cc_op)
1982
1983 /* n must be a constant to be efficient */
1984 static inline target_long lshift(target_long x, int n)
1985 {
1986 if (n >= 0) {
1987 return x << n;
1988 } else {
1989 return x >> (-n);
1990 }
1991 }
1992
1993 /* float macros */
1994 #define FT0 (env->ft0)
1995 #define ST0 (env->fpregs[env->fpstt].d)
1996 #define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
1997 #define ST1 ST(1)
1998
1999 /* translate.c */
2000 void tcg_x86_init(void);
2001
2002 typedef CPUX86State CPUArchState;
2003 typedef X86CPU ArchCPU;
2004
2005 #include "exec/cpu-all.h"
2006 #include "svm.h"
2007
2008 #if !defined(CONFIG_USER_ONLY)
2009 #include "hw/i386/apic.h"
2010 #endif
2011
2012 static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
2013 target_ulong *cs_base, uint32_t *flags)
2014 {
2015 *cs_base = env->segs[R_CS].base;
2016 *pc = *cs_base + env->eip;
2017 *flags = env->hflags |
2018 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
2019 }
2020
2021 void do_cpu_init(X86CPU *cpu);
2022 void do_cpu_sipi(X86CPU *cpu);
2023
2024 #define MCE_INJECT_BROADCAST 1
2025 #define MCE_INJECT_UNCOND_AO 2
2026
2027 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
2028 uint64_t status, uint64_t mcg_status, uint64_t addr,
2029 uint64_t misc, int flags);
2030
2031 /* excp_helper.c */
2032 void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
2033 void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
2034 uintptr_t retaddr);
2035 void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
2036 int error_code);
2037 void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
2038 int error_code, uintptr_t retaddr);
2039 void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
2040 int error_code, int next_eip_addend);
2041
2042 /* cc_helper.c */
2043 extern const uint8_t parity_table[256];
2044 uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
2045
2046 static inline uint32_t cpu_compute_eflags(CPUX86State *env)
2047 {
2048 uint32_t eflags = env->eflags;
2049 if (tcg_enabled()) {
2050 eflags |= cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
2051 }
2052 return eflags;
2053 }
2054
2055 /* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS
2056 * after generating a call to a helper that uses this.
2057 */
2058 static inline void cpu_load_eflags(CPUX86State *env, int eflags,
2059 int update_mask)
2060 {
2061 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
2062 CC_OP = CC_OP_EFLAGS;
2063 env->df = 1 - (2 * ((eflags >> 10) & 1));
2064 env->eflags = (env->eflags & ~update_mask) |
2065 (eflags & update_mask) | 0x2;
2066 }
2067
2068 /* load efer and update the corresponding hflags. XXX: do consistency
2069 checks with cpuid bits? */
2070 static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
2071 {
2072 env->efer = val;
2073 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
2074 if (env->efer & MSR_EFER_LMA) {
2075 env->hflags |= HF_LMA_MASK;
2076 }
2077 if (env->efer & MSR_EFER_SVME) {
2078 env->hflags |= HF_SVME_MASK;
2079 }
2080 }
2081
2082 static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
2083 {
2084 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
2085 }
2086
2087 static inline int32_t x86_get_a20_mask(CPUX86State *env)
2088 {
2089 if (env->hflags & HF_SMM_MASK) {
2090 return -1;
2091 } else {
2092 return env->a20_mask;
2093 }
2094 }
2095
2096 static inline bool cpu_has_vmx(CPUX86State *env)
2097 {
2098 return env->features[FEAT_1_ECX] & CPUID_EXT_VMX;
2099 }
2100
2101 /*
2102 * In order for a vCPU to enter VMX operation it must have CR4.VMXE set.
2103 * Since it was set, CR4.VMXE must remain set as long as vCPU is in
2104 * VMX operation. This is because CR4.VMXE is one of the bits set
2105 * in MSR_IA32_VMX_CR4_FIXED1.
2106 *
2107 * There is one exception to above statement when vCPU enters SMM mode.
2108 * When a vCPU enters SMM mode, it temporarily exit VMX operation and
2109 * may also reset CR4.VMXE during execution in SMM mode.
2110 * When vCPU exits SMM mode, vCPU state is restored to be in VMX operation
2111 * and CR4.VMXE is restored to it's original value of being set.
2112 *
2113 * Therefore, when vCPU is not in SMM mode, we can infer whether
2114 * VMX is being used by examining CR4.VMXE. Otherwise, we cannot
2115 * know for certain.
2116 */
2117 static inline bool cpu_vmx_maybe_enabled(CPUX86State *env)
2118 {
2119 return cpu_has_vmx(env) &&
2120 ((env->cr[4] & CR4_VMXE_MASK) || (env->hflags & HF_SMM_MASK));
2121 }
2122
2123 /* fpu_helper.c */
2124 void update_fp_status(CPUX86State *env);
2125 void update_mxcsr_status(CPUX86State *env);
2126
2127 static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
2128 {
2129 env->mxcsr = mxcsr;
2130 if (tcg_enabled()) {
2131 update_mxcsr_status(env);
2132 }
2133 }
2134
2135 static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
2136 {
2137 env->fpuc = fpuc;
2138 if (tcg_enabled()) {
2139 update_fp_status(env);
2140 }
2141 }
2142
2143 /* mem_helper.c */
2144 void helper_lock_init(void);
2145
2146 /* svm_helper.c */
2147 void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
2148 uint64_t param, uintptr_t retaddr);
2149 void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code,
2150 uint64_t exit_info_1, uintptr_t retaddr);
2151 void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1);
2152
2153 /* seg_helper.c */
2154 void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
2155
2156 /* smm_helper.c */
2157 void do_smm_enter(X86CPU *cpu);
2158
2159 /* apic.c */
2160 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
2161 void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
2162 TPRAccess access);
2163
2164
2165 /* Change the value of a KVM-specific default
2166 *
2167 * If value is NULL, no default will be set and the original
2168 * value from the CPU model table will be kept.
2169 *
2170 * It is valid to call this function only for properties that
2171 * are already present in the kvm_default_props table.
2172 */
2173 void x86_cpu_change_kvm_default(const char *prop, const char *value);
2174
2175 /* Special values for X86CPUVersion: */
2176
2177 /* Resolve to latest CPU version */
2178 #define CPU_VERSION_LATEST -1
2179
2180 /*
2181 * Resolve to version defined by current machine type.
2182 * See x86_cpu_set_default_version()
2183 */
2184 #define CPU_VERSION_AUTO -2
2185
2186 /* Don't resolve to any versioned CPU models, like old QEMU versions */
2187 #define CPU_VERSION_LEGACY 0
2188
2189 typedef int X86CPUVersion;
2190
2191 /*
2192 * Set default CPU model version for CPU models having
2193 * version == CPU_VERSION_AUTO.
2194 */
2195 void x86_cpu_set_default_version(X86CPUVersion version);
2196
2197 /* Return name of 32-bit register, from a R_* constant */
2198 const char *get_register_name_32(unsigned int reg);
2199
2200 void enable_compat_apic_id_mode(void);
2201
2202 #define APIC_DEFAULT_ADDRESS 0xfee00000
2203 #define APIC_SPACE_SIZE 0x100000
2204
2205 void x86_cpu_dump_local_apic_state(CPUState *cs, int flags);
2206
2207 /* cpu.c */
2208 bool cpu_is_bsp(X86CPU *cpu);
2209
2210 void x86_cpu_xrstor_all_areas(X86CPU *cpu, const X86XSaveArea *buf);
2211 void x86_cpu_xsave_all_areas(X86CPU *cpu, X86XSaveArea *buf);
2212 void x86_update_hflags(CPUX86State* env);
2213
2214 static inline bool hyperv_feat_enabled(X86CPU *cpu, int feat)
2215 {
2216 return !!(cpu->hyperv_features & BIT(feat));
2217 }
2218
2219 #endif /* I386_CPU_H */