target/arm: Convert Neon VCVT fixed-point to gvec
[qemu.git] / target / i386 / hax-interface.h
1 /*
2 * QEMU HAXM support
3 *
4 * Copyright (c) 2011 Intel Corporation
5 * Written by:
6 * Jiang Yunhong<yunhong.jiang@intel.com>
7 * Xin Xiaohui<xiaohui.xin@intel.com>
8 * Zhang Xiantao<xiantao.zhang@intel.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 /* Interface with HAX kernel module */
16
17 #ifndef HAX_INTERFACE_H
18 #define HAX_INTERFACE_H
19
20 /* fx_layout has 3 formats table 3-56, 512bytes */
21 struct fx_layout {
22 uint16_t fcw;
23 uint16_t fsw;
24 uint8_t ftw;
25 uint8_t res1;
26 uint16_t fop;
27 union {
28 struct {
29 uint32_t fip;
30 uint16_t fcs;
31 uint16_t res2;
32 };
33 uint64_t fpu_ip;
34 };
35 union {
36 struct {
37 uint32_t fdp;
38 uint16_t fds;
39 uint16_t res3;
40 };
41 uint64_t fpu_dp;
42 };
43 uint32_t mxcsr;
44 uint32_t mxcsr_mask;
45 uint8_t st_mm[8][16];
46 uint8_t mmx_1[8][16];
47 uint8_t mmx_2[8][16];
48 uint8_t pad[96];
49 } __attribute__ ((aligned(8)));
50
51 struct vmx_msr {
52 uint64_t entry;
53 uint64_t value;
54 } __attribute__ ((__packed__));
55
56 /*
57 * Fixed array is not good, but it makes Mac support a bit easier by avoiding
58 * memory map or copyin staff.
59 */
60 #define HAX_MAX_MSR_ARRAY 0x20
61 struct hax_msr_data {
62 uint16_t nr_msr;
63 uint16_t done;
64 uint16_t pad[2];
65 struct vmx_msr entries[HAX_MAX_MSR_ARRAY];
66 } __attribute__ ((__packed__));
67
68 union interruptibility_state_t {
69 uint32_t raw;
70 struct {
71 uint32_t sti_blocking:1;
72 uint32_t movss_blocking:1;
73 uint32_t smi_blocking:1;
74 uint32_t nmi_blocking:1;
75 uint32_t reserved:28;
76 };
77 uint64_t pad;
78 };
79
80 typedef union interruptibility_state_t interruptibility_state_t;
81
82 /* Segment descriptor */
83 struct segment_desc_t {
84 uint16_t selector;
85 uint16_t _dummy;
86 uint32_t limit;
87 uint64_t base;
88 union {
89 struct {
90 uint32_t type:4;
91 uint32_t desc:1;
92 uint32_t dpl:2;
93 uint32_t present:1;
94 uint32_t:4;
95 uint32_t available:1;
96 uint32_t long_mode:1;
97 uint32_t operand_size:1;
98 uint32_t granularity:1;
99 uint32_t null:1;
100 uint32_t:15;
101 };
102 uint32_t ar;
103 };
104 uint32_t ipad;
105 };
106
107 typedef struct segment_desc_t segment_desc_t;
108
109 struct vcpu_state_t {
110 union {
111 uint64_t _regs[16];
112 struct {
113 union {
114 struct {
115 uint8_t _al, _ah;
116 };
117 uint16_t _ax;
118 uint32_t _eax;
119 uint64_t _rax;
120 };
121 union {
122 struct {
123 uint8_t _cl, _ch;
124 };
125 uint16_t _cx;
126 uint32_t _ecx;
127 uint64_t _rcx;
128 };
129 union {
130 struct {
131 uint8_t _dl, _dh;
132 };
133 uint16_t _dx;
134 uint32_t _edx;
135 uint64_t _rdx;
136 };
137 union {
138 struct {
139 uint8_t _bl, _bh;
140 };
141 uint16_t _bx;
142 uint32_t _ebx;
143 uint64_t _rbx;
144 };
145 union {
146 uint16_t _sp;
147 uint32_t _esp;
148 uint64_t _rsp;
149 };
150 union {
151 uint16_t _bp;
152 uint32_t _ebp;
153 uint64_t _rbp;
154 };
155 union {
156 uint16_t _si;
157 uint32_t _esi;
158 uint64_t _rsi;
159 };
160 union {
161 uint16_t _di;
162 uint32_t _edi;
163 uint64_t _rdi;
164 };
165
166 uint64_t _r8;
167 uint64_t _r9;
168 uint64_t _r10;
169 uint64_t _r11;
170 uint64_t _r12;
171 uint64_t _r13;
172 uint64_t _r14;
173 uint64_t _r15;
174 };
175 };
176
177 union {
178 uint32_t _eip;
179 uint64_t _rip;
180 };
181
182 union {
183 uint32_t _eflags;
184 uint64_t _rflags;
185 };
186
187 segment_desc_t _cs;
188 segment_desc_t _ss;
189 segment_desc_t _ds;
190 segment_desc_t _es;
191 segment_desc_t _fs;
192 segment_desc_t _gs;
193 segment_desc_t _ldt;
194 segment_desc_t _tr;
195
196 segment_desc_t _gdt;
197 segment_desc_t _idt;
198
199 uint64_t _cr0;
200 uint64_t _cr2;
201 uint64_t _cr3;
202 uint64_t _cr4;
203
204 uint64_t _dr0;
205 uint64_t _dr1;
206 uint64_t _dr2;
207 uint64_t _dr3;
208 uint64_t _dr6;
209 uint64_t _dr7;
210 uint64_t _pde;
211
212 uint32_t _efer;
213
214 uint32_t _sysenter_cs;
215 uint64_t _sysenter_eip;
216 uint64_t _sysenter_esp;
217
218 uint32_t _activity_state;
219 uint32_t pad;
220 interruptibility_state_t _interruptibility_state;
221 };
222
223 /* HAX exit status */
224 enum exit_status {
225 /* IO port request */
226 HAX_EXIT_IO = 1,
227 /* MMIO instruction emulation */
228 HAX_EXIT_MMIO,
229 /* QEMU emulation mode request, currently means guest enter non-PG mode */
230 HAX_EXIT_REAL,
231 /*
232 * Interrupt window open, qemu can inject interrupt now
233 * Also used when signal pending since at that time qemu usually need
234 * check interrupt
235 */
236 HAX_EXIT_INTERRUPT,
237 /* Unknown vmexit, mostly trigger reboot */
238 HAX_EXIT_UNKNOWN_VMEXIT,
239 /* HALT from guest */
240 HAX_EXIT_HLT,
241 /* Reboot request, like because of tripple fault in guest */
242 HAX_EXIT_STATECHANGE,
243 /* the vcpu is now only paused when destroy, so simply return to hax */
244 HAX_EXIT_PAUSED,
245 HAX_EXIT_FAST_MMIO,
246 };
247
248 /*
249 * The interface definition:
250 * 1. vcpu_run execute will return 0 on success, otherwise mean failed
251 * 2. exit_status return the exit reason, as stated in enum exit_status
252 * 3. exit_reason is the vmx exit reason
253 */
254 struct hax_tunnel {
255 uint32_t _exit_reason;
256 uint32_t _exit_flag;
257 uint32_t _exit_status;
258 uint32_t user_event_pending;
259 int ready_for_interrupt_injection;
260 int request_interrupt_window;
261 union {
262 struct {
263 /* 0: read, 1: write */
264 #define HAX_EXIT_IO_IN 1
265 #define HAX_EXIT_IO_OUT 0
266 uint8_t _direction;
267 uint8_t _df;
268 uint16_t _size;
269 uint16_t _port;
270 uint16_t _count;
271 uint8_t _flags;
272 uint8_t _pad0;
273 uint16_t _pad1;
274 uint32_t _pad2;
275 uint64_t _vaddr;
276 } pio;
277 struct {
278 uint64_t gla;
279 } mmio;
280 struct {
281 } state;
282 };
283 } __attribute__ ((__packed__));
284
285 struct hax_module_version {
286 uint32_t compat_version;
287 uint32_t cur_version;
288 } __attribute__ ((__packed__));
289
290 /* This interface is support only after API version 2 */
291 struct hax_qemu_version {
292 /* Current API version in QEMU */
293 uint32_t cur_version;
294 /* The minimum API version supported by QEMU */
295 uint32_t min_version;
296 } __attribute__ ((__packed__));
297
298 /* The mac specfic interface to qemu, mostly is ioctl related */
299 struct hax_tunnel_info {
300 uint64_t va;
301 uint64_t io_va;
302 uint16_t size;
303 uint16_t pad[3];
304 } __attribute__ ((__packed__));
305
306 struct hax_alloc_ram_info {
307 uint32_t size;
308 uint32_t pad;
309 uint64_t va;
310 } __attribute__ ((__packed__));
311
312 struct hax_ramblock_info {
313 uint64_t start_va;
314 uint64_t size;
315 uint64_t reserved;
316 } __attribute__ ((__packed__));
317
318 #define HAX_RAM_INFO_ROM 0x01 /* Read-Only */
319 #define HAX_RAM_INFO_INVALID 0x80 /* Unmapped, usually used for MMIO */
320 struct hax_set_ram_info {
321 uint64_t pa_start;
322 uint32_t size;
323 uint8_t flags;
324 uint8_t pad[3];
325 uint64_t va;
326 } __attribute__ ((__packed__));
327
328 #define HAX_CAP_STATUS_WORKING 0x1
329 #define HAX_CAP_STATUS_NOTWORKING 0x0
330 #define HAX_CAP_WORKSTATUS_MASK 0x1
331
332 #define HAX_CAP_FAILREASON_VT 0x1
333 #define HAX_CAP_FAILREASON_NX 0x2
334
335 #define HAX_CAP_MEMQUOTA 0x2
336 #define HAX_CAP_UG 0x4
337 #define HAX_CAP_64BIT_RAMBLOCK 0x8
338
339 struct hax_capabilityinfo {
340 /* bit 0: 1 - working
341 * 0 - not working, possibly because NT/NX disabled
342 * bit 1: 1 - memory limitation working
343 * 0 - no memory limitation
344 */
345 uint16_t wstatus;
346 /* valid when not working
347 * bit 0: VT not enabeld
348 * bit 1: NX not enabled*/
349 uint16_t winfo;
350 uint32_t pad;
351 uint64_t mem_quota;
352 } __attribute__ ((__packed__));
353
354 struct hax_fastmmio {
355 uint64_t gpa;
356 union {
357 uint64_t value;
358 uint64_t gpa2; /* since HAX API v4 */
359 };
360 uint8_t size;
361 uint8_t direction;
362 uint16_t reg_index;
363 uint32_t pad0;
364 uint64_t _cr0;
365 uint64_t _cr2;
366 uint64_t _cr3;
367 uint64_t _cr4;
368 } __attribute__ ((__packed__));
369 #endif