Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.2-pull-request...
[qemu.git] / target / lm32 / cpu.c
1 /*
2 * QEMU LatticeMico32 CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu/qemu-print.h"
24 #include "cpu.h"
25
26
27 static void lm32_cpu_set_pc(CPUState *cs, vaddr value)
28 {
29 LM32CPU *cpu = LM32_CPU(cs);
30
31 cpu->env.pc = value;
32 }
33
34 static void lm32_cpu_list_entry(gpointer data, gpointer user_data)
35 {
36 ObjectClass *oc = data;
37 const char *typename = object_class_get_name(oc);
38 char *name;
39
40 name = g_strndup(typename, strlen(typename) - strlen(LM32_CPU_TYPE_SUFFIX));
41 qemu_printf(" %s\n", name);
42 g_free(name);
43 }
44
45
46 void lm32_cpu_list(void)
47 {
48 GSList *list;
49
50 list = object_class_get_list_sorted(TYPE_LM32_CPU, false);
51 qemu_printf("Available CPUs:\n");
52 g_slist_foreach(list, lm32_cpu_list_entry, NULL);
53 g_slist_free(list);
54 }
55
56 static void lm32_cpu_init_cfg_reg(LM32CPU *cpu)
57 {
58 CPULM32State *env = &cpu->env;
59 uint32_t cfg = 0;
60
61 if (cpu->features & LM32_FEATURE_MULTIPLY) {
62 cfg |= CFG_M;
63 }
64
65 if (cpu->features & LM32_FEATURE_DIVIDE) {
66 cfg |= CFG_D;
67 }
68
69 if (cpu->features & LM32_FEATURE_SHIFT) {
70 cfg |= CFG_S;
71 }
72
73 if (cpu->features & LM32_FEATURE_SIGN_EXTEND) {
74 cfg |= CFG_X;
75 }
76
77 if (cpu->features & LM32_FEATURE_I_CACHE) {
78 cfg |= CFG_IC;
79 }
80
81 if (cpu->features & LM32_FEATURE_D_CACHE) {
82 cfg |= CFG_DC;
83 }
84
85 if (cpu->features & LM32_FEATURE_CYCLE_COUNT) {
86 cfg |= CFG_CC;
87 }
88
89 cfg |= (cpu->num_interrupts << CFG_INT_SHIFT);
90 cfg |= (cpu->num_breakpoints << CFG_BP_SHIFT);
91 cfg |= (cpu->num_watchpoints << CFG_WP_SHIFT);
92 cfg |= (cpu->revision << CFG_REV_SHIFT);
93
94 env->cfg = cfg;
95 }
96
97 static bool lm32_cpu_has_work(CPUState *cs)
98 {
99 return cs->interrupt_request & CPU_INTERRUPT_HARD;
100 }
101
102 static void lm32_cpu_reset(DeviceState *dev)
103 {
104 CPUState *s = CPU(dev);
105 LM32CPU *cpu = LM32_CPU(s);
106 LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu);
107 CPULM32State *env = &cpu->env;
108
109 lcc->parent_reset(dev);
110
111 /* reset cpu state */
112 memset(env, 0, offsetof(CPULM32State, end_reset_fields));
113
114 lm32_cpu_init_cfg_reg(cpu);
115 }
116
117 static void lm32_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
118 {
119 info->mach = bfd_mach_lm32;
120 info->print_insn = print_insn_lm32;
121 }
122
123 static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
124 {
125 CPUState *cs = CPU(dev);
126 LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev);
127 Error *local_err = NULL;
128
129 cpu_exec_realizefn(cs, &local_err);
130 if (local_err != NULL) {
131 error_propagate(errp, local_err);
132 return;
133 }
134
135 cpu_reset(cs);
136
137 qemu_init_vcpu(cs);
138
139 lcc->parent_realize(dev, errp);
140 }
141
142 static void lm32_cpu_initfn(Object *obj)
143 {
144 LM32CPU *cpu = LM32_CPU(obj);
145 CPULM32State *env = &cpu->env;
146
147 cpu_set_cpustate_pointers(cpu);
148
149 env->flags = 0;
150 }
151
152 static void lm32_basic_cpu_initfn(Object *obj)
153 {
154 LM32CPU *cpu = LM32_CPU(obj);
155
156 cpu->revision = 3;
157 cpu->num_interrupts = 32;
158 cpu->num_breakpoints = 4;
159 cpu->num_watchpoints = 4;
160 cpu->features = LM32_FEATURE_SHIFT
161 | LM32_FEATURE_SIGN_EXTEND
162 | LM32_FEATURE_CYCLE_COUNT;
163 }
164
165 static void lm32_standard_cpu_initfn(Object *obj)
166 {
167 LM32CPU *cpu = LM32_CPU(obj);
168
169 cpu->revision = 3;
170 cpu->num_interrupts = 32;
171 cpu->num_breakpoints = 4;
172 cpu->num_watchpoints = 4;
173 cpu->features = LM32_FEATURE_MULTIPLY
174 | LM32_FEATURE_DIVIDE
175 | LM32_FEATURE_SHIFT
176 | LM32_FEATURE_SIGN_EXTEND
177 | LM32_FEATURE_I_CACHE
178 | LM32_FEATURE_CYCLE_COUNT;
179 }
180
181 static void lm32_full_cpu_initfn(Object *obj)
182 {
183 LM32CPU *cpu = LM32_CPU(obj);
184
185 cpu->revision = 3;
186 cpu->num_interrupts = 32;
187 cpu->num_breakpoints = 4;
188 cpu->num_watchpoints = 4;
189 cpu->features = LM32_FEATURE_MULTIPLY
190 | LM32_FEATURE_DIVIDE
191 | LM32_FEATURE_SHIFT
192 | LM32_FEATURE_SIGN_EXTEND
193 | LM32_FEATURE_I_CACHE
194 | LM32_FEATURE_D_CACHE
195 | LM32_FEATURE_CYCLE_COUNT;
196 }
197
198 static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
199 {
200 ObjectClass *oc;
201 char *typename;
202
203 typename = g_strdup_printf(LM32_CPU_TYPE_NAME("%s"), cpu_model);
204 oc = object_class_by_name(typename);
205 g_free(typename);
206 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_LM32_CPU) ||
207 object_class_is_abstract(oc))) {
208 oc = NULL;
209 }
210 return oc;
211 }
212
213 static void lm32_cpu_class_init(ObjectClass *oc, void *data)
214 {
215 LM32CPUClass *lcc = LM32_CPU_CLASS(oc);
216 CPUClass *cc = CPU_CLASS(oc);
217 DeviceClass *dc = DEVICE_CLASS(oc);
218
219 device_class_set_parent_realize(dc, lm32_cpu_realizefn,
220 &lcc->parent_realize);
221 device_class_set_parent_reset(dc, lm32_cpu_reset, &lcc->parent_reset);
222
223 cc->class_by_name = lm32_cpu_class_by_name;
224 cc->has_work = lm32_cpu_has_work;
225 cc->do_interrupt = lm32_cpu_do_interrupt;
226 cc->cpu_exec_interrupt = lm32_cpu_exec_interrupt;
227 cc->dump_state = lm32_cpu_dump_state;
228 cc->set_pc = lm32_cpu_set_pc;
229 cc->gdb_read_register = lm32_cpu_gdb_read_register;
230 cc->gdb_write_register = lm32_cpu_gdb_write_register;
231 cc->tlb_fill = lm32_cpu_tlb_fill;
232 #ifndef CONFIG_USER_ONLY
233 cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
234 cc->vmsd = &vmstate_lm32_cpu;
235 #endif
236 cc->gdb_num_core_regs = 32 + 7;
237 cc->gdb_stop_before_watchpoint = true;
238 cc->debug_excp_handler = lm32_debug_excp_handler;
239 cc->disas_set_info = lm32_cpu_disas_set_info;
240 cc->tcg_initialize = lm32_translate_init;
241 }
242
243 #define DEFINE_LM32_CPU_TYPE(cpu_model, initfn) \
244 { \
245 .parent = TYPE_LM32_CPU, \
246 .name = LM32_CPU_TYPE_NAME(cpu_model), \
247 .instance_init = initfn, \
248 }
249
250 static const TypeInfo lm32_cpus_type_infos[] = {
251 { /* base class should be registered first */
252 .name = TYPE_LM32_CPU,
253 .parent = TYPE_CPU,
254 .instance_size = sizeof(LM32CPU),
255 .instance_init = lm32_cpu_initfn,
256 .abstract = true,
257 .class_size = sizeof(LM32CPUClass),
258 .class_init = lm32_cpu_class_init,
259 },
260 DEFINE_LM32_CPU_TYPE("lm32-basic", lm32_basic_cpu_initfn),
261 DEFINE_LM32_CPU_TYPE("lm32-standard", lm32_standard_cpu_initfn),
262 DEFINE_LM32_CPU_TYPE("lm32-full", lm32_full_cpu_initfn),
263 };
264
265 DEFINE_TYPES(lm32_cpus_type_infos)