Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.2-pull-request...
[qemu.git] / target / lm32 / helper.c
1 /*
2 * LatticeMico32 helper routines.
3 *
4 * Copyright (c) 2010-2014 Michael Walle <michael@walle.cc>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/exec-all.h"
23 #include "qemu/host-utils.h"
24 #include "hw/semihosting/semihost.h"
25 #include "exec/log.h"
26
27 bool lm32_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
28 MMUAccessType access_type, int mmu_idx,
29 bool probe, uintptr_t retaddr)
30 {
31 LM32CPU *cpu = LM32_CPU(cs);
32 CPULM32State *env = &cpu->env;
33 int prot;
34
35 address &= TARGET_PAGE_MASK;
36 prot = PAGE_BITS;
37 if (env->flags & LM32_FLAG_IGNORE_MSB) {
38 tlb_set_page(cs, address, address & 0x7fffffff, prot, mmu_idx,
39 TARGET_PAGE_SIZE);
40 } else {
41 tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
42 }
43 return true;
44 }
45
46 hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
47 {
48 LM32CPU *cpu = LM32_CPU(cs);
49
50 addr &= TARGET_PAGE_MASK;
51 if (cpu->env.flags & LM32_FLAG_IGNORE_MSB) {
52 return addr & 0x7fffffff;
53 } else {
54 return addr;
55 }
56 }
57
58 void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address)
59 {
60 cpu_breakpoint_insert(env_cpu(env), address, BP_CPU,
61 &env->cpu_breakpoint[idx]);
62 }
63
64 void lm32_breakpoint_remove(CPULM32State *env, int idx)
65 {
66 if (!env->cpu_breakpoint[idx]) {
67 return;
68 }
69
70 cpu_breakpoint_remove_by_ref(env_cpu(env), env->cpu_breakpoint[idx]);
71 env->cpu_breakpoint[idx] = NULL;
72 }
73
74 void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address,
75 lm32_wp_t wp_type)
76 {
77 int flags = 0;
78
79 switch (wp_type) {
80 case LM32_WP_DISABLED:
81 /* nothing to do */
82 break;
83 case LM32_WP_READ:
84 flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_READ;
85 break;
86 case LM32_WP_WRITE:
87 flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_WRITE;
88 break;
89 case LM32_WP_READ_WRITE:
90 flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_ACCESS;
91 break;
92 }
93
94 if (flags != 0) {
95 cpu_watchpoint_insert(env_cpu(env), address, 1, flags,
96 &env->cpu_watchpoint[idx]);
97 }
98 }
99
100 void lm32_watchpoint_remove(CPULM32State *env, int idx)
101 {
102 if (!env->cpu_watchpoint[idx]) {
103 return;
104 }
105
106 cpu_watchpoint_remove_by_ref(env_cpu(env), env->cpu_watchpoint[idx]);
107 env->cpu_watchpoint[idx] = NULL;
108 }
109
110 static bool check_watchpoints(CPULM32State *env)
111 {
112 LM32CPU *cpu = env_archcpu(env);
113 int i;
114
115 for (i = 0; i < cpu->num_watchpoints; i++) {
116 if (env->cpu_watchpoint[i] &&
117 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
118 return true;
119 }
120 }
121 return false;
122 }
123
124 void lm32_debug_excp_handler(CPUState *cs)
125 {
126 LM32CPU *cpu = LM32_CPU(cs);
127 CPULM32State *env = &cpu->env;
128 CPUBreakpoint *bp;
129
130 if (cs->watchpoint_hit) {
131 if (cs->watchpoint_hit->flags & BP_CPU) {
132 cs->watchpoint_hit = NULL;
133 if (check_watchpoints(env)) {
134 raise_exception(env, EXCP_WATCHPOINT);
135 } else {
136 cpu_loop_exit_noexc(cs);
137 }
138 }
139 } else {
140 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
141 if (bp->pc == env->pc) {
142 if (bp->flags & BP_CPU) {
143 raise_exception(env, EXCP_BREAKPOINT);
144 }
145 break;
146 }
147 }
148 }
149 }
150
151 void lm32_cpu_do_interrupt(CPUState *cs)
152 {
153 LM32CPU *cpu = LM32_CPU(cs);
154 CPULM32State *env = &cpu->env;
155
156 qemu_log_mask(CPU_LOG_INT,
157 "exception at pc=%x type=%x\n", env->pc, cs->exception_index);
158
159 switch (cs->exception_index) {
160 case EXCP_SYSTEMCALL:
161 if (unlikely(semihosting_enabled())) {
162 /* do_semicall() returns true if call was handled. Otherwise
163 * do the normal exception handling. */
164 if (lm32_cpu_do_semihosting(cs)) {
165 env->pc += 4;
166 break;
167 }
168 }
169 /* fall through */
170 case EXCP_INSN_BUS_ERROR:
171 case EXCP_DATA_BUS_ERROR:
172 case EXCP_DIVIDE_BY_ZERO:
173 case EXCP_IRQ:
174 /* non-debug exceptions */
175 env->regs[R_EA] = env->pc;
176 env->ie |= (env->ie & IE_IE) ? IE_EIE : 0;
177 env->ie &= ~IE_IE;
178 if (env->dc & DC_RE) {
179 env->pc = env->deba + (cs->exception_index * 32);
180 } else {
181 env->pc = env->eba + (cs->exception_index * 32);
182 }
183 log_cpu_state_mask(CPU_LOG_INT, cs, 0);
184 break;
185 case EXCP_BREAKPOINT:
186 case EXCP_WATCHPOINT:
187 /* debug exceptions */
188 env->regs[R_BA] = env->pc;
189 env->ie |= (env->ie & IE_IE) ? IE_BIE : 0;
190 env->ie &= ~IE_IE;
191 env->pc = env->deba + (cs->exception_index * 32);
192 log_cpu_state_mask(CPU_LOG_INT, cs, 0);
193 break;
194 default:
195 cpu_abort(cs, "unhandled exception type=%d\n",
196 cs->exception_index);
197 break;
198 }
199 }
200
201 bool lm32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
202 {
203 LM32CPU *cpu = LM32_CPU(cs);
204 CPULM32State *env = &cpu->env;
205
206 if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->ie & IE_IE)) {
207 cs->exception_index = EXCP_IRQ;
208 lm32_cpu_do_interrupt(cs);
209 return true;
210 }
211 return false;
212 }
213
214 /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory
215 * area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
216 * 0x80000000-0xffffffff is not cached and used to access IO devices. */
217 void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value)
218 {
219 if (value) {
220 env->flags |= LM32_FLAG_IGNORE_MSB;
221 } else {
222 env->flags &= ~LM32_FLAG_IGNORE_MSB;
223 }
224 }