hw/arm/virt: Merge VirtBoardInfo and VirtMachineState
[qemu.git] / target / microblaze / cpu.c
1 /*
2 * QEMU MicroBlaze CPU
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 * Copyright (c) 2012 SUSE LINUX Products GmbH
7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2.1 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see
21 * <http://www.gnu.org/licenses/lgpl-2.1.html>
22 */
23
24 #include "qemu/osdep.h"
25 #include "qapi/error.h"
26 #include "cpu.h"
27 #include "qemu-common.h"
28 #include "hw/qdev-properties.h"
29 #include "migration/vmstate.h"
30 #include "exec/exec-all.h"
31
32 static const struct {
33 const char *name;
34 uint8_t version_id;
35 } mb_cpu_lookup[] = {
36 /* These key value are as per MBV field in PVR0 */
37 {"5.00.a", 0x01},
38 {"5.00.b", 0x02},
39 {"5.00.c", 0x03},
40 {"6.00.a", 0x04},
41 {"6.00.b", 0x06},
42 {"7.00.a", 0x05},
43 {"7.00.b", 0x07},
44 {"7.10.a", 0x08},
45 {"7.10.b", 0x09},
46 {"7.10.c", 0x0a},
47 {"7.10.d", 0x0b},
48 {"7.20.a", 0x0c},
49 {"7.20.b", 0x0d},
50 {"7.20.c", 0x0e},
51 {"7.20.d", 0x0f},
52 {"7.30.a", 0x10},
53 {"7.30.b", 0x11},
54 {"8.00.a", 0x12},
55 {"8.00.b", 0x13},
56 {"8.10.a", 0x14},
57 {"8.20.a", 0x15},
58 {"8.20.b", 0x16},
59 {"8.30.a", 0x17},
60 {"8.40.a", 0x18},
61 {"8.40.b", 0x19},
62 {"8.50.a", 0x1A},
63 {"9.0", 0x1B},
64 {"9.1", 0x1D},
65 {"9.2", 0x1F},
66 {"9.3", 0x20},
67 {NULL, 0},
68 };
69
70 static void mb_cpu_set_pc(CPUState *cs, vaddr value)
71 {
72 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
73
74 cpu->env.sregs[SR_PC] = value;
75 }
76
77 static bool mb_cpu_has_work(CPUState *cs)
78 {
79 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
80 }
81
82 #ifndef CONFIG_USER_ONLY
83 static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
84 {
85 MicroBlazeCPU *cpu = opaque;
86 CPUState *cs = CPU(cpu);
87 int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
88
89 if (level) {
90 cpu_interrupt(cs, type);
91 } else {
92 cpu_reset_interrupt(cs, type);
93 }
94 }
95 #endif
96
97 /* CPUClass::reset() */
98 static void mb_cpu_reset(CPUState *s)
99 {
100 MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
101 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
102 CPUMBState *env = &cpu->env;
103
104 mcc->parent_reset(s);
105
106 memset(env, 0, offsetof(CPUMBState, pvr));
107 env->res_addr = RES_ADDR_NONE;
108 tlb_flush(s, 1);
109
110 /* Disable stack protector. */
111 env->shr = ~0;
112
113 env->sregs[SR_PC] = cpu->cfg.base_vectors;
114
115 #if defined(CONFIG_USER_ONLY)
116 /* start in user mode with interrupts enabled. */
117 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
118 #else
119 env->sregs[SR_MSR] = 0;
120 mmu_init(&env->mmu);
121 env->mmu.c_mmu = 3;
122 env->mmu.c_mmu_tlb_access = 3;
123 env->mmu.c_mmu_zones = 16;
124 #endif
125 }
126
127 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
128 {
129 info->mach = bfd_arch_microblaze;
130 info->print_insn = print_insn_microblaze;
131 }
132
133 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
134 {
135 CPUState *cs = CPU(dev);
136 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
137 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
138 CPUMBState *env = &cpu->env;
139 uint8_t version_code = 0;
140 int i = 0;
141 Error *local_err = NULL;
142
143 cpu_exec_realizefn(cs, &local_err);
144 if (local_err != NULL) {
145 error_propagate(errp, local_err);
146 return;
147 }
148
149 qemu_init_vcpu(cs);
150
151 env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
152 | PVR0_USE_DIV_MASK \
153 | PVR0_USE_HW_MUL_MASK \
154 | PVR0_USE_EXC_MASK \
155 | PVR0_USE_ICACHE_MASK \
156 | PVR0_USE_DCACHE_MASK \
157 | (0xb << 8);
158 env->pvr.regs[2] = PVR2_D_OPB_MASK \
159 | PVR2_D_LMB_MASK \
160 | PVR2_I_OPB_MASK \
161 | PVR2_I_LMB_MASK \
162 | PVR2_USE_MSR_INSTR \
163 | PVR2_USE_PCMP_INSTR \
164 | PVR2_USE_BARREL_MASK \
165 | PVR2_USE_DIV_MASK \
166 | PVR2_USE_HW_MUL_MASK \
167 | PVR2_USE_MUL64_MASK \
168 | PVR2_FPU_EXC_MASK \
169 | 0;
170
171 for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) {
172 if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) {
173 version_code = mb_cpu_lookup[i].version_id;
174 break;
175 }
176 }
177
178 if (!version_code) {
179 qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
180 }
181
182 env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
183 (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
184 (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
185 (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
186 (version_code << 16) |
187 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
188
189 env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
190 (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
191
192 env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
193 PVR5_DCACHE_WRITEBACK_MASK : 0;
194
195 env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
196 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
197
198 mcc->parent_realize(dev, errp);
199 }
200
201 static void mb_cpu_initfn(Object *obj)
202 {
203 CPUState *cs = CPU(obj);
204 MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
205 CPUMBState *env = &cpu->env;
206 static bool tcg_initialized;
207
208 cs->env_ptr = env;
209
210 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
211
212 #ifndef CONFIG_USER_ONLY
213 /* Inbound IRQ and FIR lines */
214 qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
215 #endif
216
217 if (tcg_enabled() && !tcg_initialized) {
218 tcg_initialized = true;
219 mb_tcg_init();
220 }
221 }
222
223 static const VMStateDescription vmstate_mb_cpu = {
224 .name = "cpu",
225 .unmigratable = 1,
226 };
227
228 static Property mb_properties[] = {
229 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
230 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
231 false),
232 /* If use-fpu > 0 - FPU is enabled
233 * If use-fpu = 2 - Floating point conversion and square root instructions
234 * are enabled
235 */
236 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
237 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
238 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
239 false),
240 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
241 DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
242 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
243 DEFINE_PROP_END_OF_LIST(),
244 };
245
246 static void mb_cpu_class_init(ObjectClass *oc, void *data)
247 {
248 DeviceClass *dc = DEVICE_CLASS(oc);
249 CPUClass *cc = CPU_CLASS(oc);
250 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
251
252 mcc->parent_realize = dc->realize;
253 dc->realize = mb_cpu_realizefn;
254
255 mcc->parent_reset = cc->reset;
256 cc->reset = mb_cpu_reset;
257
258 cc->has_work = mb_cpu_has_work;
259 cc->do_interrupt = mb_cpu_do_interrupt;
260 cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
261 cc->dump_state = mb_cpu_dump_state;
262 cc->set_pc = mb_cpu_set_pc;
263 cc->gdb_read_register = mb_cpu_gdb_read_register;
264 cc->gdb_write_register = mb_cpu_gdb_write_register;
265 #ifdef CONFIG_USER_ONLY
266 cc->handle_mmu_fault = mb_cpu_handle_mmu_fault;
267 #else
268 cc->do_unassigned_access = mb_cpu_unassigned_access;
269 cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
270 #endif
271 dc->vmsd = &vmstate_mb_cpu;
272 dc->props = mb_properties;
273 cc->gdb_num_core_regs = 32 + 5;
274
275 cc->disas_set_info = mb_disas_set_info;
276 }
277
278 static const TypeInfo mb_cpu_type_info = {
279 .name = TYPE_MICROBLAZE_CPU,
280 .parent = TYPE_CPU,
281 .instance_size = sizeof(MicroBlazeCPU),
282 .instance_init = mb_cpu_initfn,
283 .class_size = sizeof(MicroBlazeCPUClass),
284 .class_init = mb_cpu_class_init,
285 };
286
287 static void mb_cpu_register_types(void)
288 {
289 type_register_static(&mb_cpu_type_info);
290 }
291
292 type_init(mb_cpu_register_types)