target/microblaze: Fix width of PC and BTARGET
[qemu.git] / target / microblaze / helper.c
1 /*
2 * MicroBlaze helper routines.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "exec/exec-all.h"
24 #include "qemu/host-utils.h"
25 #include "exec/log.h"
26
27 #define D(x)
28
29 #if defined(CONFIG_USER_ONLY)
30
31 void mb_cpu_do_interrupt(CPUState *cs)
32 {
33 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
34 CPUMBState *env = &cpu->env;
35
36 cs->exception_index = -1;
37 env->res_addr = RES_ADDR_NONE;
38 env->regs[14] = env->pc;
39 }
40
41 bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
42 MMUAccessType access_type, int mmu_idx,
43 bool probe, uintptr_t retaddr)
44 {
45 cs->exception_index = 0xaa;
46 cpu_loop_exit_restore(cs, retaddr);
47 }
48
49 #else /* !CONFIG_USER_ONLY */
50
51 bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
52 MMUAccessType access_type, int mmu_idx,
53 bool probe, uintptr_t retaddr)
54 {
55 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
56 CPUMBState *env = &cpu->env;
57 struct microblaze_mmu_lookup lu;
58 unsigned int hit;
59 int prot;
60
61 if (mmu_idx == MMU_NOMMU_IDX) {
62 /* MMU disabled or not available. */
63 address &= TARGET_PAGE_MASK;
64 prot = PAGE_BITS;
65 tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
66 return true;
67 }
68
69 hit = mmu_translate(&env->mmu, &lu, address, access_type, mmu_idx);
70 if (likely(hit)) {
71 uint32_t vaddr = address & TARGET_PAGE_MASK;
72 uint32_t paddr = lu.paddr + vaddr - lu.vaddr;
73
74 qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n",
75 mmu_idx, vaddr, paddr, lu.prot);
76 tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
77 return true;
78 }
79
80 /* TLB miss. */
81 if (probe) {
82 return false;
83 }
84
85 qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n",
86 mmu_idx, address);
87
88 env->ear = address;
89 switch (lu.err) {
90 case ERR_PROT:
91 env->esr = access_type == MMU_INST_FETCH ? 17 : 16;
92 env->esr |= (access_type == MMU_DATA_STORE) << 10;
93 break;
94 case ERR_MISS:
95 env->esr = access_type == MMU_INST_FETCH ? 19 : 18;
96 env->esr |= (access_type == MMU_DATA_STORE) << 10;
97 break;
98 default:
99 abort();
100 }
101
102 if (cs->exception_index == EXCP_MMU) {
103 cpu_abort(cs, "recursive faults\n");
104 }
105
106 /* TLB miss. */
107 cs->exception_index = EXCP_MMU;
108 cpu_loop_exit_restore(cs, retaddr);
109 }
110
111 void mb_cpu_do_interrupt(CPUState *cs)
112 {
113 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
114 CPUMBState *env = &cpu->env;
115 uint32_t t;
116
117 /* IMM flag cannot propagate across a branch and into the dslot. */
118 assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
119 assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
120 /* assert(env->msr & (MSR_EE)); Only for HW exceptions. */
121 env->res_addr = RES_ADDR_NONE;
122 switch (cs->exception_index) {
123 case EXCP_HW_EXCP:
124 if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
125 qemu_log_mask(LOG_GUEST_ERROR, "Exception raised on system without exceptions!\n");
126 return;
127 }
128
129 env->regs[17] = env->pc + 4;
130 env->esr &= ~(1 << 12);
131
132 /* Exception breaks branch + dslot sequence? */
133 if (env->iflags & D_FLAG) {
134 env->esr |= 1 << 12 ;
135 env->btr = env->btarget;
136 }
137
138 /* Disable the MMU. */
139 t = (env->msr & (MSR_VM | MSR_UM)) << 1;
140 env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
141 env->msr |= t;
142 /* Exception in progress. */
143 env->msr |= MSR_EIP;
144
145 qemu_log_mask(CPU_LOG_INT,
146 "hw exception at pc=%x ear=%" PRIx64 " "
147 "esr=%" PRIx64 " iflags=%x\n",
148 env->pc, env->ear,
149 env->esr, env->iflags);
150 log_cpu_state_mask(CPU_LOG_INT, cs, 0);
151 env->iflags &= ~(IMM_FLAG | D_FLAG);
152 env->pc = cpu->cfg.base_vectors + 0x20;
153 break;
154
155 case EXCP_MMU:
156 env->regs[17] = env->pc;
157
158 env->esr &= ~(1 << 12);
159 /* Exception breaks branch + dslot sequence? */
160 if (env->iflags & D_FLAG) {
161 D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
162 env->esr |= 1 << 12 ;
163 env->btr = env->btarget;
164
165 /* Reexecute the branch. */
166 env->regs[17] -= 4;
167 /* was the branch immprefixed?. */
168 if (env->bimm) {
169 qemu_log_mask(CPU_LOG_INT,
170 "bimm exception at pc=%x iflags=%x\n",
171 env->pc, env->iflags);
172 env->regs[17] -= 4;
173 log_cpu_state_mask(CPU_LOG_INT, cs, 0);
174 }
175 } else if (env->iflags & IMM_FLAG) {
176 D(qemu_log("IMM_FLAG set at exception\n"));
177 env->regs[17] -= 4;
178 }
179
180 /* Disable the MMU. */
181 t = (env->msr & (MSR_VM | MSR_UM)) << 1;
182 env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
183 env->msr |= t;
184 /* Exception in progress. */
185 env->msr |= MSR_EIP;
186
187 qemu_log_mask(CPU_LOG_INT,
188 "exception at pc=%x ear=%" PRIx64 " iflags=%x\n",
189 env->pc, env->ear, env->iflags);
190 log_cpu_state_mask(CPU_LOG_INT, cs, 0);
191 env->iflags &= ~(IMM_FLAG | D_FLAG);
192 env->pc = cpu->cfg.base_vectors + 0x20;
193 break;
194
195 case EXCP_IRQ:
196 assert(!(env->msr & (MSR_EIP | MSR_BIP)));
197 assert(env->msr & MSR_IE);
198 assert(!(env->iflags & D_FLAG));
199
200 t = (env->msr & (MSR_VM | MSR_UM)) << 1;
201
202 #if 0
203 #include "disas/disas.h"
204
205 /* Useful instrumentation when debugging interrupt issues in either
206 the models or in sw. */
207 {
208 const char *sym;
209
210 sym = lookup_symbol(env->pc);
211 if (sym
212 && (!strcmp("netif_rx", sym)
213 || !strcmp("process_backlog", sym))) {
214
215 qemu_log(
216 "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
217 env->pc, env->msr, t, env->iflags,
218 sym);
219
220 log_cpu_state(cs, 0);
221 }
222 }
223 #endif
224 qemu_log_mask(CPU_LOG_INT,
225 "interrupt at pc=%x msr=%" PRIx64 " %x iflags=%x\n",
226 env->pc, env->msr, t, env->iflags);
227
228 env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM | MSR_IE);
229 env->msr |= t;
230
231 env->regs[14] = env->pc;
232 env->pc = cpu->cfg.base_vectors + 0x10;
233 //log_cpu_state_mask(CPU_LOG_INT, cs, 0);
234 break;
235
236 case EXCP_BREAK:
237 case EXCP_HW_BREAK:
238 assert(!(env->iflags & IMM_FLAG));
239 assert(!(env->iflags & D_FLAG));
240 t = (env->msr & (MSR_VM | MSR_UM)) << 1;
241 qemu_log_mask(CPU_LOG_INT,
242 "break at pc=%x msr=%" PRIx64 " %x iflags=%x\n",
243 env->pc, env->msr, t, env->iflags);
244 log_cpu_state_mask(CPU_LOG_INT, cs, 0);
245 env->msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
246 env->msr |= t;
247 env->msr |= MSR_BIP;
248 if (cs->exception_index == EXCP_HW_BREAK) {
249 env->regs[16] = env->pc;
250 env->msr |= MSR_BIP;
251 env->pc = cpu->cfg.base_vectors + 0x18;
252 } else
253 env->pc = env->btarget;
254 break;
255 default:
256 cpu_abort(cs, "unhandled exception type=%d\n",
257 cs->exception_index);
258 break;
259 }
260 }
261
262 hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
263 {
264 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
265 CPUMBState *env = &cpu->env;
266 target_ulong vaddr, paddr = 0;
267 struct microblaze_mmu_lookup lu;
268 int mmu_idx = cpu_mmu_index(env, false);
269 unsigned int hit;
270
271 if (mmu_idx != MMU_NOMMU_IDX) {
272 hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
273 if (hit) {
274 vaddr = addr & TARGET_PAGE_MASK;
275 paddr = lu.paddr + vaddr - lu.vaddr;
276 } else
277 paddr = 0; /* ???. */
278 } else
279 paddr = addr & TARGET_PAGE_MASK;
280
281 return paddr;
282 }
283 #endif
284
285 bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
286 {
287 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
288 CPUMBState *env = &cpu->env;
289
290 if ((interrupt_request & CPU_INTERRUPT_HARD)
291 && (env->msr & MSR_IE)
292 && !(env->msr & (MSR_EIP | MSR_BIP))
293 && !(env->iflags & (D_FLAG | IMM_FLAG))) {
294 cs->exception_index = EXCP_IRQ;
295 mb_cpu_do_interrupt(cs);
296 return true;
297 }
298 return false;
299 }