hmp: Ignore Error objects where the return value suffices
[qemu.git] / target / mips / mips-defs.h
1 #ifndef QEMU_MIPS_DEFS_H
2 #define QEMU_MIPS_DEFS_H
3
4 /*
5 * If we want to use host float regs...
6 *
7 * #define USE_HOST_FLOAT_REGS
8 */
9
10 /* Real pages are variable size... */
11 #define MIPS_TLB_MAX 128
12
13 /*
14 * bit definitions for insn_flags (ISAs/ASEs flags)
15 * ------------------------------------------------
16 */
17 /*
18 * bits 0-23: MIPS base instruction sets
19 */
20 #define ISA_MIPS1 0x0000000000000001ULL
21 #define ISA_MIPS2 0x0000000000000002ULL
22 #define ISA_MIPS3 0x0000000000000004ULL
23 #define ISA_MIPS4 0x0000000000000008ULL
24 #define ISA_MIPS5 0x0000000000000010ULL
25 #define ISA_MIPS32 0x0000000000000020ULL
26 #define ISA_MIPS32R2 0x0000000000000040ULL
27 #define ISA_MIPS64 0x0000000000000080ULL
28 #define ISA_MIPS64R2 0x0000000000000100ULL
29 #define ISA_MIPS32R3 0x0000000000000200ULL
30 #define ISA_MIPS64R3 0x0000000000000400ULL
31 #define ISA_MIPS32R5 0x0000000000000800ULL
32 #define ISA_MIPS64R5 0x0000000000001000ULL
33 #define ISA_MIPS32R6 0x0000000000002000ULL
34 #define ISA_MIPS64R6 0x0000000000004000ULL
35 #define ISA_NANOMIPS32 0x0000000000008000ULL
36 /*
37 * bits 24-39: MIPS ASEs
38 */
39 #define ASE_MIPS16 0x0000000001000000ULL
40 #define ASE_MIPS3D 0x0000000002000000ULL
41 #define ASE_MDMX 0x0000000004000000ULL
42 #define ASE_DSP 0x0000000008000000ULL
43 #define ASE_DSP_R2 0x0000000010000000ULL
44 #define ASE_DSP_R3 0x0000000020000000ULL
45 #define ASE_MT 0x0000000040000000ULL
46 #define ASE_SMARTMIPS 0x0000000080000000ULL
47 #define ASE_MICROMIPS 0x0000000100000000ULL
48 #define ASE_MSA 0x0000000200000000ULL
49 /*
50 * bits 40-51: vendor-specific base instruction sets
51 */
52 #define INSN_VR54XX 0x0000010000000000ULL
53 #define INSN_R5900 0x0000020000000000ULL
54 #define INSN_LOONGSON2E 0x0000040000000000ULL
55 #define INSN_LOONGSON2F 0x0000080000000000ULL
56 #define INSN_LOONGSON3A 0x0000100000000000ULL
57 /*
58 * bits 52-63: vendor-specific ASEs
59 */
60 /* MultiMedia Instructions defined by R5900 */
61 #define ASE_MMI 0x0010000000000000ULL
62 /* MIPS eXtension/enhanced Unit defined by Ingenic */
63 #define ASE_MXU 0x0020000000000000ULL
64 /* Loongson MultiMedia Instructions */
65 #define ASE_LMMI 0x0040000000000000ULL
66 /* Loongson EXTensions */
67 #define ASE_LEXT 0x0080000000000000ULL
68
69 /* MIPS CPU defines. */
70 #define CPU_MIPS1 (ISA_MIPS1)
71 #define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2)
72 #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
73 #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
74 #define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
75 #define CPU_R5900 (CPU_MIPS3 | INSN_R5900)
76 #define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
77 #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
78
79 #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
80
81 /* MIPS Technologies "Release 1" */
82 #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
83 #define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
84
85 /* MIPS Technologies "Release 2" */
86 #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
87 #define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
88
89 /* MIPS Technologies "Release 3" */
90 #define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
91 #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
92
93 /* MIPS Technologies "Release 5" */
94 #define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
95 #define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
96
97 /* MIPS Technologies "Release 6" */
98 #define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
99 #define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
100
101 /* Wave Computing: "nanoMIPS" */
102 #define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
103
104 #define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT)
105
106 /*
107 * Strictly follow the architecture standard:
108 * - Disallow "special" instruction handling for PMON/SPIM.
109 * Note that we still maintain Count/Compare to match the host clock.
110 *
111 * #define MIPS_STRICT_STANDARD 1
112 */
113
114 #endif /* QEMU_MIPS_DEFS_H */