Merge tag 'pull-qapi-2022-05-16' of git://repo.or.cz/qemu/armbru into staging
[qemu.git] / target / ppc / cpu-qom.h
1 /*
2 * QEMU PowerPC CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20 #ifndef QEMU_PPC_CPU_QOM_H
21 #define QEMU_PPC_CPU_QOM_H
22
23 #include "hw/core/cpu.h"
24 #include "qom/object.h"
25
26 #ifdef TARGET_PPC64
27 #define TYPE_POWERPC_CPU "powerpc64-cpu"
28 #else
29 #define TYPE_POWERPC_CPU "powerpc-cpu"
30 #endif
31
32 OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU)
33
34 typedef struct CPUArchState CPUPPCState;
35 typedef struct ppc_tb_t ppc_tb_t;
36 typedef struct ppc_dcr_t ppc_dcr_t;
37
38 /*****************************************************************************/
39 /* MMU model */
40 typedef enum powerpc_mmu_t powerpc_mmu_t;
41 enum powerpc_mmu_t {
42 POWERPC_MMU_UNKNOWN = 0x00000000,
43 /* Standard 32 bits PowerPC MMU */
44 POWERPC_MMU_32B = 0x00000001,
45 /* PowerPC 6xx MMU with software TLB */
46 POWERPC_MMU_SOFT_6xx = 0x00000002,
47 /*
48 * PowerPC 74xx MMU with software TLB (this has been
49 * disabled, see git history for more information.
50 * keywords: tlbld tlbli TLBMISS PTEHI PTELO)
51 */
52 POWERPC_MMU_SOFT_74xx = 0x00000003,
53 /* PowerPC 4xx MMU with software TLB */
54 POWERPC_MMU_SOFT_4xx = 0x00000004,
55 /* PowerPC MMU in real mode only */
56 POWERPC_MMU_REAL = 0x00000006,
57 /* Freescale MPC8xx MMU model */
58 POWERPC_MMU_MPC8xx = 0x00000007,
59 /* BookE MMU model */
60 POWERPC_MMU_BOOKE = 0x00000008,
61 /* BookE 2.06 MMU model */
62 POWERPC_MMU_BOOKE206 = 0x00000009,
63 #define POWERPC_MMU_64 0x00010000
64 /* 64 bits PowerPC MMU */
65 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
66 /* Architecture 2.03 and later (has LPCR) */
67 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
68 /* Architecture 2.06 variant */
69 POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003,
70 /* Architecture 2.07 variant */
71 POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004,
72 /* Architecture 3.00 variant */
73 POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005,
74 };
75
76 static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model)
77 {
78 return mmu_model & POWERPC_MMU_64;
79 }
80
81 /*****************************************************************************/
82 /* Exception model */
83 typedef enum powerpc_excp_t powerpc_excp_t;
84 enum powerpc_excp_t {
85 POWERPC_EXCP_UNKNOWN = 0,
86 /* Standard PowerPC exception model */
87 POWERPC_EXCP_STD,
88 /* PowerPC 40x exception model */
89 POWERPC_EXCP_40x,
90 /* PowerPC 603/604/G2 exception model */
91 POWERPC_EXCP_6xx,
92 /* PowerPC 7xx exception model */
93 POWERPC_EXCP_7xx,
94 /* PowerPC 74xx exception model */
95 POWERPC_EXCP_74xx,
96 /* BookE exception model */
97 POWERPC_EXCP_BOOKE,
98 /* PowerPC 970 exception model */
99 POWERPC_EXCP_970,
100 /* POWER7 exception model */
101 POWERPC_EXCP_POWER7,
102 /* POWER8 exception model */
103 POWERPC_EXCP_POWER8,
104 /* POWER9 exception model */
105 POWERPC_EXCP_POWER9,
106 /* POWER10 exception model */
107 POWERPC_EXCP_POWER10,
108 };
109
110 /*****************************************************************************/
111 /* PM instructions */
112 typedef enum {
113 PPC_PM_DOZE,
114 PPC_PM_NAP,
115 PPC_PM_SLEEP,
116 PPC_PM_RVWINKLE,
117 PPC_PM_STOP,
118 } powerpc_pm_insn_t;
119
120 /*****************************************************************************/
121 /* Input pins model */
122 typedef enum powerpc_input_t powerpc_input_t;
123 enum powerpc_input_t {
124 PPC_FLAGS_INPUT_UNKNOWN = 0,
125 /* PowerPC 6xx bus */
126 PPC_FLAGS_INPUT_6xx,
127 /* BookE bus */
128 PPC_FLAGS_INPUT_BookE,
129 /* PowerPC 405 bus */
130 PPC_FLAGS_INPUT_405,
131 /* PowerPC 970 bus */
132 PPC_FLAGS_INPUT_970,
133 /* PowerPC POWER7 bus */
134 PPC_FLAGS_INPUT_POWER7,
135 /* PowerPC POWER9 bus */
136 PPC_FLAGS_INPUT_POWER9,
137 /* Freescale RCPU bus */
138 PPC_FLAGS_INPUT_RCPU,
139 };
140
141 typedef struct PPCHash64Options PPCHash64Options;
142
143 /**
144 * PowerPCCPUClass:
145 * @parent_realize: The parent class' realize handler.
146 * @parent_reset: The parent class' reset handler.
147 *
148 * A PowerPC CPU model.
149 */
150 struct PowerPCCPUClass {
151 /*< private >*/
152 CPUClass parent_class;
153 /*< public >*/
154
155 DeviceRealize parent_realize;
156 DeviceUnrealize parent_unrealize;
157 DeviceReset parent_reset;
158 void (*parent_parse_features)(const char *type, char *str, Error **errp);
159
160 uint32_t pvr;
161 bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr);
162 uint64_t pcr_mask; /* Available bits in PCR register */
163 uint64_t pcr_supported; /* Bits for supported PowerISA versions */
164 uint32_t svr;
165 uint64_t insns_flags;
166 uint64_t insns_flags2;
167 uint64_t msr_mask;
168 uint64_t lpcr_mask; /* Available bits in the LPCR */
169 uint64_t lpcr_pm; /* Power-saving mode Exit Cause Enable bits */
170 powerpc_mmu_t mmu_model;
171 powerpc_excp_t excp_model;
172 powerpc_input_t bus_model;
173 uint32_t flags;
174 int bfd_mach;
175 uint32_t l1_dcache_size, l1_icache_size;
176 #ifndef CONFIG_USER_ONLY
177 unsigned int gdb_num_sprs;
178 const char *gdb_spr_xml;
179 #endif
180 const PPCHash64Options *hash64_opts;
181 struct ppc_radix_page_info *radix_page_info;
182 uint32_t lrg_decr_bits;
183 int n_host_threads;
184 void (*init_proc)(CPUPPCState *env);
185 int (*check_pow)(CPUPPCState *env);
186 };
187
188 #ifndef CONFIG_USER_ONLY
189 typedef struct PPCTimebase {
190 uint64_t guest_timebase;
191 int64_t time_of_the_day_ns;
192 bool runstate_paused;
193 } PPCTimebase;
194
195 extern const VMStateDescription vmstate_ppc_timebase;
196
197 #define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \
198 .name = (stringify(_field)), \
199 .version_id = (_version), \
200 .size = sizeof(PPCTimebase), \
201 .vmsd = &vmstate_ppc_timebase, \
202 .flags = VMS_STRUCT, \
203 .offset = vmstate_offset_value(_state, _field, PPCTimebase), \
204 }
205
206 void cpu_ppc_clock_vm_state_change(void *opaque, bool running,
207 RunState state);
208 #endif
209
210 #endif