tmp105: Correct handling of temperature limit checks
[qemu.git] / target / ppc / gdbstub.c
1 /*
2 * PowerPC gdb server stub
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2013 SUSE LINUX Products GmbH
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20 #include "qemu/osdep.h"
21 #include "cpu.h"
22 #include "exec/gdbstub.h"
23
24 static int ppc_gdb_register_len_apple(int n)
25 {
26 switch (n) {
27 case 0 ... 31:
28 /* gprs */
29 return 8;
30 case 32 ... 63:
31 /* fprs */
32 return 8;
33 case 64 ... 95:
34 return 16;
35 case 64 + 32: /* nip */
36 case 65 + 32: /* msr */
37 case 67 + 32: /* lr */
38 case 68 + 32: /* ctr */
39 case 70 + 32: /* fpscr */
40 return 8;
41 case 66 + 32: /* cr */
42 case 69 + 32: /* xer */
43 return 4;
44 default:
45 return 0;
46 }
47 }
48
49 static int ppc_gdb_register_len(int n)
50 {
51 switch (n) {
52 case 0 ... 31:
53 /* gprs */
54 return sizeof(target_ulong);
55 case 32 ... 63:
56 /* fprs */
57 if (gdb_has_xml) {
58 return 0;
59 }
60 return 8;
61 case 66:
62 /* cr */
63 case 69:
64 /* xer */
65 return 4;
66 case 64:
67 /* nip */
68 case 65:
69 /* msr */
70 case 67:
71 /* lr */
72 case 68:
73 /* ctr */
74 return sizeof(target_ulong);
75 case 70:
76 /* fpscr */
77 if (gdb_has_xml) {
78 return 0;
79 }
80 return sizeof(target_ulong);
81 default:
82 return 0;
83 }
84 }
85
86 /*
87 * We need to present the registers to gdb in the "current" memory
88 * ordering. For user-only mode we get this for free;
89 * TARGET_WORDS_BIGENDIAN is set to the proper ordering for the
90 * binary, and cannot be changed. For system mode,
91 * TARGET_WORDS_BIGENDIAN is always set, and we must check the current
92 * mode of the chip to see if we're running in little-endian.
93 */
94 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
95 {
96 #ifndef CONFIG_USER_ONLY
97 if (!msr_le) {
98 /* do nothing */
99 } else if (len == 4) {
100 bswap32s((uint32_t *)mem_buf);
101 } else if (len == 8) {
102 bswap64s((uint64_t *)mem_buf);
103 } else {
104 g_assert_not_reached();
105 }
106 #endif
107 }
108
109 /*
110 * Old gdb always expects FP registers. Newer (xml-aware) gdb only
111 * expects whatever the target description contains. Due to a
112 * historical mishap the FP registers appear in between core integer
113 * regs and PC, MSR, CR, and so forth. We hack round this by giving
114 * the FP regs zero size when talking to a newer gdb.
115 */
116
117 int ppc_cpu_gdb_read_register(CPUState *cs, GByteArray *buf, int n)
118 {
119 PowerPCCPU *cpu = POWERPC_CPU(cs);
120 CPUPPCState *env = &cpu->env;
121 uint8_t *mem_buf;
122 int r = ppc_gdb_register_len(n);
123
124 if (!r) {
125 return r;
126 }
127
128 if (n < 32) {
129 /* gprs */
130 gdb_get_regl(buf, env->gpr[n]);
131 } else if (n < 64) {
132 /* fprs */
133 gdb_get_float64(buf, *cpu_fpr_ptr(env, n - 32));
134 } else {
135 switch (n) {
136 case 64:
137 gdb_get_regl(buf, env->nip);
138 break;
139 case 65:
140 gdb_get_regl(buf, env->msr);
141 break;
142 case 66:
143 {
144 uint32_t cr = 0;
145 int i;
146 for (i = 0; i < 8; i++) {
147 cr |= env->crf[i] << (32 - ((i + 1) * 4));
148 }
149 gdb_get_reg32(buf, cr);
150 break;
151 }
152 case 67:
153 gdb_get_regl(buf, env->lr);
154 break;
155 case 68:
156 gdb_get_regl(buf, env->ctr);
157 break;
158 case 69:
159 gdb_get_reg32(buf, env->xer);
160 break;
161 case 70:
162 gdb_get_reg32(buf, env->fpscr);
163 break;
164 }
165 }
166 mem_buf = buf->data + buf->len - r;
167 ppc_maybe_bswap_register(env, mem_buf, r);
168 return r;
169 }
170
171 int ppc_cpu_gdb_read_register_apple(CPUState *cs, GByteArray *buf, int n)
172 {
173 PowerPCCPU *cpu = POWERPC_CPU(cs);
174 CPUPPCState *env = &cpu->env;
175 uint8_t *mem_buf;
176 int r = ppc_gdb_register_len_apple(n);
177
178 if (!r) {
179 return r;
180 }
181
182 if (n < 32) {
183 /* gprs */
184 gdb_get_reg64(buf, env->gpr[n]);
185 } else if (n < 64) {
186 /* fprs */
187 gdb_get_float64(buf, *cpu_fpr_ptr(env, n - 32));
188 } else if (n < 96) {
189 /* Altivec */
190 gdb_get_reg64(buf, n - 64);
191 gdb_get_reg64(buf, 0);
192 } else {
193 switch (n) {
194 case 64 + 32:
195 gdb_get_reg64(buf, env->nip);
196 break;
197 case 65 + 32:
198 gdb_get_reg64(buf, env->msr);
199 break;
200 case 66 + 32:
201 {
202 uint32_t cr = 0;
203 int i;
204 for (i = 0; i < 8; i++) {
205 cr |= env->crf[i] << (32 - ((i + 1) * 4));
206 }
207 gdb_get_reg32(buf, cr);
208 break;
209 }
210 case 67 + 32:
211 gdb_get_reg64(buf, env->lr);
212 break;
213 case 68 + 32:
214 gdb_get_reg64(buf, env->ctr);
215 break;
216 case 69 + 32:
217 gdb_get_reg32(buf, env->xer);
218 break;
219 case 70 + 32:
220 gdb_get_reg64(buf, env->fpscr);
221 break;
222 }
223 }
224 mem_buf = buf->data + buf->len - r;
225 ppc_maybe_bswap_register(env, mem_buf, r);
226 return r;
227 }
228
229 int ppc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
230 {
231 PowerPCCPU *cpu = POWERPC_CPU(cs);
232 CPUPPCState *env = &cpu->env;
233 int r = ppc_gdb_register_len(n);
234
235 if (!r) {
236 return r;
237 }
238 ppc_maybe_bswap_register(env, mem_buf, r);
239 if (n < 32) {
240 /* gprs */
241 env->gpr[n] = ldtul_p(mem_buf);
242 } else if (n < 64) {
243 /* fprs */
244 *cpu_fpr_ptr(env, n - 32) = ldfq_p(mem_buf);
245 } else {
246 switch (n) {
247 case 64:
248 env->nip = ldtul_p(mem_buf);
249 break;
250 case 65:
251 ppc_store_msr(env, ldtul_p(mem_buf));
252 break;
253 case 66:
254 {
255 uint32_t cr = ldl_p(mem_buf);
256 int i;
257 for (i = 0; i < 8; i++) {
258 env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
259 }
260 break;
261 }
262 case 67:
263 env->lr = ldtul_p(mem_buf);
264 break;
265 case 68:
266 env->ctr = ldtul_p(mem_buf);
267 break;
268 case 69:
269 env->xer = ldl_p(mem_buf);
270 break;
271 case 70:
272 /* fpscr */
273 store_fpscr(env, ldtul_p(mem_buf), 0xffffffff);
274 break;
275 }
276 }
277 return r;
278 }
279 int ppc_cpu_gdb_write_register_apple(CPUState *cs, uint8_t *mem_buf, int n)
280 {
281 PowerPCCPU *cpu = POWERPC_CPU(cs);
282 CPUPPCState *env = &cpu->env;
283 int r = ppc_gdb_register_len_apple(n);
284
285 if (!r) {
286 return r;
287 }
288 ppc_maybe_bswap_register(env, mem_buf, r);
289 if (n < 32) {
290 /* gprs */
291 env->gpr[n] = ldq_p(mem_buf);
292 } else if (n < 64) {
293 /* fprs */
294 *cpu_fpr_ptr(env, n - 32) = ldfq_p(mem_buf);
295 } else {
296 switch (n) {
297 case 64 + 32:
298 env->nip = ldq_p(mem_buf);
299 break;
300 case 65 + 32:
301 ppc_store_msr(env, ldq_p(mem_buf));
302 break;
303 case 66 + 32:
304 {
305 uint32_t cr = ldl_p(mem_buf);
306 int i;
307 for (i = 0; i < 8; i++) {
308 env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
309 }
310 break;
311 }
312 case 67 + 32:
313 env->lr = ldq_p(mem_buf);
314 break;
315 case 68 + 32:
316 env->ctr = ldq_p(mem_buf);
317 break;
318 case 69 + 32:
319 env->xer = ldl_p(mem_buf);
320 break;
321 case 70 + 32:
322 /* fpscr */
323 store_fpscr(env, ldq_p(mem_buf), 0xffffffff);
324 break;
325 }
326 }
327 return r;
328 }
329
330 #ifndef CONFIG_USER_ONLY
331 void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu)
332 {
333 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
334 CPUPPCState *env = &cpu->env;
335 GString *xml;
336 char *spr_name;
337 unsigned int num_regs = 0;
338 int i;
339
340 if (pcc->gdb_spr_xml) {
341 return;
342 }
343
344 xml = g_string_new("<?xml version=\"1.0\"?>");
345 g_string_append(xml, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
346 g_string_append(xml, "<feature name=\"org.qemu.power.spr\">");
347
348 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
349 ppc_spr_t *spr = &env->spr_cb[i];
350
351 if (!spr->name) {
352 continue;
353 }
354
355 spr_name = g_ascii_strdown(spr->name, -1);
356 g_string_append_printf(xml, "<reg name=\"%s\"", spr_name);
357 g_free(spr_name);
358
359 g_string_append_printf(xml, " bitsize=\"%d\"", TARGET_LONG_BITS);
360 g_string_append(xml, " group=\"spr\"/>");
361
362 /*
363 * GDB identifies registers based on the order they are
364 * presented in the XML. These ids will not match QEMU's
365 * representation (which follows the PowerISA).
366 *
367 * Store the position of the current register description so
368 * we can make the correspondence later.
369 */
370 spr->gdb_id = num_regs;
371 num_regs++;
372 }
373
374 g_string_append(xml, "</feature>");
375
376 pcc->gdb_num_sprs = num_regs;
377 pcc->gdb_spr_xml = g_string_free(xml, false);
378 }
379
380 const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name)
381 {
382 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
383
384 if (strcmp(xml_name, "power-spr.xml") == 0) {
385 return pcc->gdb_spr_xml;
386 }
387 return NULL;
388 }
389 #endif