tests: virtio-9p: rename PCI configuration test
[qemu.git] / target / ppc / misc_helper.c
1 /*
2 * Miscellaneous PowerPC emulation helpers for QEMU.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "exec/exec-all.h"
22 #include "exec/helper-proto.h"
23
24 #include "helper_regs.h"
25
26 /*****************************************************************************/
27 /* SPR accesses */
28 void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn)
29 {
30 qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
31 env->spr[sprn]);
32 }
33
34 void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
35 {
36 qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
37 env->spr[sprn]);
38 }
39
40 #ifdef TARGET_PPC64
41 static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
42 uint32_t sprn, uint32_t cause,
43 uintptr_t raddr)
44 {
45 qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit);
46
47 env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
48 cause &= FSCR_IC_MASK;
49 env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS;
50
51 raise_exception_err_ra(env, POWERPC_EXCP_FU, 0, raddr);
52 }
53 #endif
54
55 void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
56 uint32_t sprn, uint32_t cause)
57 {
58 #ifdef TARGET_PPC64
59 if (env->spr[SPR_FSCR] & (1ULL << bit)) {
60 /* Facility is enabled, continue */
61 return;
62 }
63 raise_fu_exception(env, bit, sprn, cause, GETPC());
64 #endif
65 }
66
67 void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
68 uint32_t sprn, uint32_t cause)
69 {
70 #ifdef TARGET_PPC64
71 if (env->msr & (1ULL << bit)) {
72 /* Facility is enabled, continue */
73 return;
74 }
75 raise_fu_exception(env, bit, sprn, cause, GETPC());
76 #endif
77 }
78
79 #if !defined(CONFIG_USER_ONLY)
80
81 void helper_store_sdr1(CPUPPCState *env, target_ulong val)
82 {
83 PowerPCCPU *cpu = ppc_env_get_cpu(env);
84
85 if (!env->external_htab) {
86 if (env->spr[SPR_SDR1] != val) {
87 ppc_store_sdr1(env, val);
88 tlb_flush(CPU(cpu), 1);
89 }
90 }
91 }
92
93 void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
94 {
95 target_ulong hid0;
96
97 hid0 = env->spr[SPR_HID0];
98 if ((val ^ hid0) & 0x00000008) {
99 /* Change current endianness */
100 env->hflags &= ~(1 << MSR_LE);
101 env->hflags_nmsr &= ~(1 << MSR_LE);
102 env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
103 env->hflags |= env->hflags_nmsr;
104 qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
105 val & 0x8 ? 'l' : 'b', env->hflags);
106 }
107 env->spr[SPR_HID0] = (uint32_t)val;
108 }
109
110 void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
111 {
112 PowerPCCPU *cpu = ppc_env_get_cpu(env);
113
114 if (likely(env->pb[num] != value)) {
115 env->pb[num] = value;
116 /* Should be optimized */
117 tlb_flush(CPU(cpu), 1);
118 }
119 }
120
121 void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
122 {
123 store_40x_dbcr0(env, val);
124 }
125
126 void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
127 {
128 store_40x_sler(env, val);
129 }
130 #endif
131 /*****************************************************************************/
132 /* PowerPC 601 specific instructions (POWER bridge) */
133
134 target_ulong helper_clcs(CPUPPCState *env, uint32_t arg)
135 {
136 switch (arg) {
137 case 0x0CUL:
138 /* Instruction cache line size */
139 return env->icache_line_size;
140 break;
141 case 0x0DUL:
142 /* Data cache line size */
143 return env->dcache_line_size;
144 break;
145 case 0x0EUL:
146 /* Minimum cache line size */
147 return (env->icache_line_size < env->dcache_line_size) ?
148 env->icache_line_size : env->dcache_line_size;
149 break;
150 case 0x0FUL:
151 /* Maximum cache line size */
152 return (env->icache_line_size > env->dcache_line_size) ?
153 env->icache_line_size : env->dcache_line_size;
154 break;
155 default:
156 /* Undefined */
157 return 0;
158 break;
159 }
160 }
161
162 /*****************************************************************************/
163 /* Special registers manipulation */
164
165 /* GDBstub can read and write MSR... */
166 void ppc_store_msr(CPUPPCState *env, target_ulong value)
167 {
168 hreg_store_msr(env, value, 0);
169 }
170
171 /* This code is lifted from MacOnLinux. It is called whenever
172 * THRM1,2 or 3 is read an fixes up the values in such a way
173 * that will make MacOS not hang. These registers exist on some
174 * 75x and 74xx processors.
175 */
176 void helper_fixup_thrm(CPUPPCState *env)
177 {
178 target_ulong v, t;
179 int i;
180
181 #define THRM1_TIN (1 << 31)
182 #define THRM1_TIV (1 << 30)
183 #define THRM1_THRES(x) (((x) & 0x7f) << 23)
184 #define THRM1_TID (1 << 2)
185 #define THRM1_TIE (1 << 1)
186 #define THRM1_V (1 << 0)
187 #define THRM3_E (1 << 0)
188
189 if (!(env->spr[SPR_THRM3] & THRM3_E)) {
190 return;
191 }
192
193 /* Note: Thermal interrupts are unimplemented */
194 for (i = SPR_THRM1; i <= SPR_THRM2; i++) {
195 v = env->spr[i];
196 if (!(v & THRM1_V)) {
197 continue;
198 }
199 v |= THRM1_TIV;
200 v &= ~THRM1_TIN;
201 t = v & THRM1_THRES(127);
202 if ((v & THRM1_TID) && t < THRM1_THRES(24)) {
203 v |= THRM1_TIN;
204 }
205 if (!(v & THRM1_TID) && t > THRM1_THRES(24)) {
206 v |= THRM1_TIN;
207 }
208 env->spr[i] = v;
209 }
210 }