tmp105: Correct handling of temperature limit checks
[qemu.git] / target / ppc / mmu-book3s-v3.h
1 /*
2 * PowerPC ISAV3 BookS emulation generic mmu definitions for qemu.
3 *
4 * Copyright (c) 2017 Suraj Jitindar Singh, IBM Corporation
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef PPC_MMU_BOOK3S_V3_H
21 #define PPC_MMU_BOOK3S_V3_H
22
23 #include "mmu-hash64.h"
24
25 #ifndef CONFIG_USER_ONLY
26
27 /*
28 * Partition table definitions
29 */
30 #define PTCR_PATB 0x0FFFFFFFFFFFF000ULL /* Partition Table Base */
31 #define PTCR_PATS 0x000000000000001FULL /* Partition Table Size */
32
33 /* Partition Table Entry Fields */
34 #define PATE0_HR 0x8000000000000000
35
36 /*
37 * WARNING: This field doesn't actually exist in the final version of
38 * the architecture and is unused by hardware. However, qemu uses it
39 * as an indication of a radix guest in the pseudo-PATB entry that it
40 * maintains for SPAPR guests and in the migration stream, so we need
41 * to keep it around
42 */
43 #define PATE1_GR 0x8000000000000000
44
45 /* Process Table Entry */
46 struct prtb_entry {
47 uint64_t prtbe0, prtbe1;
48 };
49
50 #ifdef TARGET_PPC64
51
52 static inline bool ppc64_use_proc_tbl(PowerPCCPU *cpu)
53 {
54 return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
55 }
56
57 bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid,
58 ppc_v3_pate_t *entry);
59
60 /*
61 * The LPCR:HR bit is a shortcut that avoids having to
62 * dig out the partition table in the fast path. This is
63 * also how the HW uses it.
64 */
65 static inline bool ppc64_v3_radix(PowerPCCPU *cpu)
66 {
67 return !!(cpu->env.spr[SPR_LPCR] & LPCR_HR);
68 }
69
70 hwaddr ppc64_v3_get_phys_page_debug(PowerPCCPU *cpu, vaddr eaddr);
71
72 int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
73 int mmu_idx);
74
75 static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
76 {
77 uint64_t base;
78
79 if (cpu->vhyp) {
80 return 0;
81 }
82 if (cpu->env.mmu_model == POWERPC_MMU_3_00) {
83 ppc_v3_pate_t pate;
84
85 if (!ppc64_v3_get_pate(cpu, cpu->env.spr[SPR_LPIDR], &pate)) {
86 return 0;
87 }
88 base = pate.dw0;
89 } else {
90 base = cpu->env.spr[SPR_SDR1];
91 }
92 return base & SDR_64_HTABORG;
93 }
94
95 static inline hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
96 {
97 uint64_t base;
98
99 if (cpu->vhyp) {
100 PPCVirtualHypervisorClass *vhc =
101 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
102 return vhc->hpt_mask(cpu->vhyp);
103 }
104 if (cpu->env.mmu_model == POWERPC_MMU_3_00) {
105 ppc_v3_pate_t pate;
106
107 if (!ppc64_v3_get_pate(cpu, cpu->env.spr[SPR_LPIDR], &pate)) {
108 return 0;
109 }
110 base = pate.dw0;
111 } else {
112 base = cpu->env.spr[SPR_SDR1];
113 }
114 return (1ULL << ((base & SDR_64_HTABSIZE) + 18 - 7)) - 1;
115 }
116
117 #endif /* TARGET_PPC64 */
118
119 #endif /* CONFIG_USER_ONLY */
120
121 #endif /* PPC_MMU_BOOK3S_V3_H */