Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
[qemu.git] / target / ppc / mmu-book3s-v3.h
1 /*
2 * PowerPC ISAV3 BookS emulation generic mmu definitions for qemu.
3 *
4 * Copyright (c) 2017 Suraj Jitindar Singh, IBM Corporation
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef PPC_MMU_BOOK3S_V3_H
21 #define PPC_MMU_BOOK3S_V3_H
22
23 #include "mmu-hash64.h"
24 #include "mmu-books.h"
25
26 #ifndef CONFIG_USER_ONLY
27
28 /*
29 * Partition table definitions
30 */
31 #define PTCR_PATB 0x0FFFFFFFFFFFF000ULL /* Partition Table Base */
32 #define PTCR_PATS 0x000000000000001FULL /* Partition Table Size */
33
34 /* Partition Table Entry Fields */
35 #define PATE0_HR 0x8000000000000000
36
37 /*
38 * WARNING: This field doesn't actually exist in the final version of
39 * the architecture and is unused by hardware. However, qemu uses it
40 * as an indication of a radix guest in the pseudo-PATB entry that it
41 * maintains for SPAPR guests and in the migration stream, so we need
42 * to keep it around
43 */
44 #define PATE1_GR 0x8000000000000000
45
46 /* Process Table Entry */
47 struct prtb_entry {
48 uint64_t prtbe0, prtbe1;
49 };
50
51 #ifdef TARGET_PPC64
52
53 static inline bool ppc64_use_proc_tbl(PowerPCCPU *cpu)
54 {
55 return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
56 }
57
58 bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid,
59 ppc_v3_pate_t *entry);
60
61 /*
62 * The LPCR:HR bit is a shortcut that avoids having to
63 * dig out the partition table in the fast path. This is
64 * also how the HW uses it.
65 */
66 static inline bool ppc64_v3_radix(PowerPCCPU *cpu)
67 {
68 return !!(cpu->env.spr[SPR_LPCR] & LPCR_HR);
69 }
70
71 static inline hwaddr ppc_hash64_hpt_base(PowerPCCPU *cpu)
72 {
73 uint64_t base;
74
75 if (cpu->vhyp) {
76 return 0;
77 }
78 if (cpu->env.mmu_model == POWERPC_MMU_3_00) {
79 ppc_v3_pate_t pate;
80
81 if (!ppc64_v3_get_pate(cpu, cpu->env.spr[SPR_LPIDR], &pate)) {
82 return 0;
83 }
84 base = pate.dw0;
85 } else {
86 base = cpu->env.spr[SPR_SDR1];
87 }
88 return base & SDR_64_HTABORG;
89 }
90
91 static inline hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
92 {
93 uint64_t base;
94
95 if (cpu->vhyp) {
96 PPCVirtualHypervisorClass *vhc =
97 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
98 return vhc->hpt_mask(cpu->vhyp);
99 }
100 if (cpu->env.mmu_model == POWERPC_MMU_3_00) {
101 ppc_v3_pate_t pate;
102
103 if (!ppc64_v3_get_pate(cpu, cpu->env.spr[SPR_LPIDR], &pate)) {
104 return 0;
105 }
106 base = pate.dw0;
107 } else {
108 base = cpu->env.spr[SPR_SDR1];
109 }
110 return (1ULL << ((base & SDR_64_HTABSIZE) + 18 - 7)) - 1;
111 }
112
113 #endif /* TARGET_PPC64 */
114
115 #endif /* CONFIG_USER_ONLY */
116
117 #endif /* PPC_MMU_BOOK3S_V3_H */