e500,book3s: mfspr 259: Register mapped/aliased SPRG3 user read
[qemu.git] / target / ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/bfd.h"
23 #include "exec/gdbstub.h"
24 #include "kvm_ppc.h"
25 #include "sysemu/arch_init.h"
26 #include "sysemu/cpus.h"
27 #include "sysemu/hw_accel.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qapi/visitor.h"
33 #include "hw/qdev-properties.h"
34 #include "hw/ppc/ppc.h"
35 #include "mmu-book3s-v3.h"
36
37 //#define PPC_DUMP_CPU
38 //#define PPC_DEBUG_SPR
39 //#define PPC_DUMP_SPR_ACCESSES
40 /* #define USE_APPLE_GDB */
41
42 /* Generic callbacks:
43 * do nothing but store/retrieve spr value
44 */
45 static void spr_load_dump_spr(int sprn)
46 {
47 #ifdef PPC_DUMP_SPR_ACCESSES
48 TCGv_i32 t0 = tcg_const_i32(sprn);
49 gen_helper_load_dump_spr(cpu_env, t0);
50 tcg_temp_free_i32(t0);
51 #endif
52 }
53
54 static void spr_read_generic (DisasContext *ctx, int gprn, int sprn)
55 {
56 gen_load_spr(cpu_gpr[gprn], sprn);
57 spr_load_dump_spr(sprn);
58 }
59
60 static void spr_store_dump_spr(int sprn)
61 {
62 #ifdef PPC_DUMP_SPR_ACCESSES
63 TCGv_i32 t0 = tcg_const_i32(sprn);
64 gen_helper_store_dump_spr(cpu_env, t0);
65 tcg_temp_free_i32(t0);
66 #endif
67 }
68
69 static void spr_write_generic (DisasContext *ctx, int sprn, int gprn)
70 {
71 gen_store_spr(sprn, cpu_gpr[gprn]);
72 spr_store_dump_spr(sprn);
73 }
74
75 #if !defined(CONFIG_USER_ONLY)
76 static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
77 {
78 #ifdef TARGET_PPC64
79 TCGv t0 = tcg_temp_new();
80 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
81 gen_store_spr(sprn, t0);
82 tcg_temp_free(t0);
83 spr_store_dump_spr(sprn);
84 #else
85 spr_write_generic(ctx, sprn, gprn);
86 #endif
87 }
88
89 static void spr_write_clear (DisasContext *ctx, int sprn, int gprn)
90 {
91 TCGv t0 = tcg_temp_new();
92 TCGv t1 = tcg_temp_new();
93 gen_load_spr(t0, sprn);
94 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
95 tcg_gen_and_tl(t0, t0, t1);
96 gen_store_spr(sprn, t0);
97 tcg_temp_free(t0);
98 tcg_temp_free(t1);
99 }
100
101 static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
102 {
103 }
104
105 #endif
106
107 /* SPR common to all PowerPC */
108 /* XER */
109 static void spr_read_xer (DisasContext *ctx, int gprn, int sprn)
110 {
111 gen_read_xer(ctx, cpu_gpr[gprn]);
112 }
113
114 static void spr_write_xer (DisasContext *ctx, int sprn, int gprn)
115 {
116 gen_write_xer(cpu_gpr[gprn]);
117 }
118
119 /* LR */
120 static void spr_read_lr (DisasContext *ctx, int gprn, int sprn)
121 {
122 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
123 }
124
125 static void spr_write_lr (DisasContext *ctx, int sprn, int gprn)
126 {
127 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
128 }
129
130 /* CFAR */
131 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
132 static void spr_read_cfar (DisasContext *ctx, int gprn, int sprn)
133 {
134 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
135 }
136
137 static void spr_write_cfar (DisasContext *ctx, int sprn, int gprn)
138 {
139 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
140 }
141 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
142
143 /* CTR */
144 static void spr_read_ctr (DisasContext *ctx, int gprn, int sprn)
145 {
146 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
147 }
148
149 static void spr_write_ctr (DisasContext *ctx, int sprn, int gprn)
150 {
151 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
152 }
153
154 /* User read access to SPR */
155 /* USPRx */
156 /* UMMCRx */
157 /* UPMCx */
158 /* USIA */
159 /* UDECR */
160 static void spr_read_ureg (DisasContext *ctx, int gprn, int sprn)
161 {
162 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
163 }
164
165 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
166 static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
167 {
168 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
169 }
170 #endif
171
172 /* SPR common to all non-embedded PowerPC */
173 /* DECR */
174 #if !defined(CONFIG_USER_ONLY)
175 static void spr_read_decr (DisasContext *ctx, int gprn, int sprn)
176 {
177 if (ctx->tb->cflags & CF_USE_ICOUNT) {
178 gen_io_start();
179 }
180 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
181 if (ctx->tb->cflags & CF_USE_ICOUNT) {
182 gen_io_end();
183 gen_stop_exception(ctx);
184 }
185 }
186
187 static void spr_write_decr (DisasContext *ctx, int sprn, int gprn)
188 {
189 if (ctx->tb->cflags & CF_USE_ICOUNT) {
190 gen_io_start();
191 }
192 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
193 if (ctx->tb->cflags & CF_USE_ICOUNT) {
194 gen_io_end();
195 gen_stop_exception(ctx);
196 }
197 }
198 #endif
199
200 /* SPR common to all non-embedded PowerPC, except 601 */
201 /* Time base */
202 static void spr_read_tbl (DisasContext *ctx, int gprn, int sprn)
203 {
204 if (ctx->tb->cflags & CF_USE_ICOUNT) {
205 gen_io_start();
206 }
207 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
208 if (ctx->tb->cflags & CF_USE_ICOUNT) {
209 gen_io_end();
210 gen_stop_exception(ctx);
211 }
212 }
213
214 static void spr_read_tbu (DisasContext *ctx, int gprn, int sprn)
215 {
216 if (ctx->tb->cflags & CF_USE_ICOUNT) {
217 gen_io_start();
218 }
219 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
220 if (ctx->tb->cflags & CF_USE_ICOUNT) {
221 gen_io_end();
222 gen_stop_exception(ctx);
223 }
224 }
225
226 __attribute__ (( unused ))
227 static void spr_read_atbl (DisasContext *ctx, int gprn, int sprn)
228 {
229 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
230 }
231
232 __attribute__ (( unused ))
233 static void spr_read_atbu (DisasContext *ctx, int gprn, int sprn)
234 {
235 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
236 }
237
238 #if !defined(CONFIG_USER_ONLY)
239 static void spr_write_tbl (DisasContext *ctx, int sprn, int gprn)
240 {
241 if (ctx->tb->cflags & CF_USE_ICOUNT) {
242 gen_io_start();
243 }
244 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
245 if (ctx->tb->cflags & CF_USE_ICOUNT) {
246 gen_io_end();
247 gen_stop_exception(ctx);
248 }
249 }
250
251 static void spr_write_tbu (DisasContext *ctx, int sprn, int gprn)
252 {
253 if (ctx->tb->cflags & CF_USE_ICOUNT) {
254 gen_io_start();
255 }
256 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
257 if (ctx->tb->cflags & CF_USE_ICOUNT) {
258 gen_io_end();
259 gen_stop_exception(ctx);
260 }
261 }
262
263 __attribute__ (( unused ))
264 static void spr_write_atbl (DisasContext *ctx, int sprn, int gprn)
265 {
266 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
267 }
268
269 __attribute__ (( unused ))
270 static void spr_write_atbu (DisasContext *ctx, int sprn, int gprn)
271 {
272 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
273 }
274
275 #if defined(TARGET_PPC64)
276 __attribute__ (( unused ))
277 static void spr_read_purr (DisasContext *ctx, int gprn, int sprn)
278 {
279 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
280 }
281
282 /* HDECR */
283 static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
284 {
285 if (ctx->tb->cflags & CF_USE_ICOUNT) {
286 gen_io_start();
287 }
288 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
289 if (ctx->tb->cflags & CF_USE_ICOUNT) {
290 gen_io_end();
291 gen_stop_exception(ctx);
292 }
293 }
294
295 static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
296 {
297 if (ctx->tb->cflags & CF_USE_ICOUNT) {
298 gen_io_start();
299 }
300 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
301 if (ctx->tb->cflags & CF_USE_ICOUNT) {
302 gen_io_end();
303 gen_stop_exception(ctx);
304 }
305 }
306
307 #endif
308 #endif
309
310 #if !defined(CONFIG_USER_ONLY)
311 /* IBAT0U...IBAT0U */
312 /* IBAT0L...IBAT7L */
313 static void spr_read_ibat (DisasContext *ctx, int gprn, int sprn)
314 {
315 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
316 }
317
318 static void spr_read_ibat_h (DisasContext *ctx, int gprn, int sprn)
319 {
320 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
321 }
322
323 static void spr_write_ibatu (DisasContext *ctx, int sprn, int gprn)
324 {
325 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
326 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
327 tcg_temp_free_i32(t0);
328 }
329
330 static void spr_write_ibatu_h (DisasContext *ctx, int sprn, int gprn)
331 {
332 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
333 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
334 tcg_temp_free_i32(t0);
335 }
336
337 static void spr_write_ibatl (DisasContext *ctx, int sprn, int gprn)
338 {
339 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
340 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
341 tcg_temp_free_i32(t0);
342 }
343
344 static void spr_write_ibatl_h (DisasContext *ctx, int sprn, int gprn)
345 {
346 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
347 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
348 tcg_temp_free_i32(t0);
349 }
350
351 /* DBAT0U...DBAT7U */
352 /* DBAT0L...DBAT7L */
353 static void spr_read_dbat (DisasContext *ctx, int gprn, int sprn)
354 {
355 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
356 }
357
358 static void spr_read_dbat_h (DisasContext *ctx, int gprn, int sprn)
359 {
360 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
361 }
362
363 static void spr_write_dbatu (DisasContext *ctx, int sprn, int gprn)
364 {
365 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
366 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
367 tcg_temp_free_i32(t0);
368 }
369
370 static void spr_write_dbatu_h (DisasContext *ctx, int sprn, int gprn)
371 {
372 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
373 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
374 tcg_temp_free_i32(t0);
375 }
376
377 static void spr_write_dbatl (DisasContext *ctx, int sprn, int gprn)
378 {
379 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
380 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
381 tcg_temp_free_i32(t0);
382 }
383
384 static void spr_write_dbatl_h (DisasContext *ctx, int sprn, int gprn)
385 {
386 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
387 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
388 tcg_temp_free_i32(t0);
389 }
390
391 /* SDR1 */
392 static void spr_write_sdr1 (DisasContext *ctx, int sprn, int gprn)
393 {
394 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
395 }
396
397 #if defined(TARGET_PPC64)
398 /* 64 bits PowerPC specific SPRs */
399 /* PIDR */
400 static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
401 {
402 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
403 }
404
405 static void spr_read_hior (DisasContext *ctx, int gprn, int sprn)
406 {
407 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
408 }
409
410 static void spr_write_hior (DisasContext *ctx, int sprn, int gprn)
411 {
412 TCGv t0 = tcg_temp_new();
413 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
414 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
415 tcg_temp_free(t0);
416 }
417 #endif
418 #endif
419
420 /* PowerPC 601 specific registers */
421 /* RTC */
422 static void spr_read_601_rtcl (DisasContext *ctx, int gprn, int sprn)
423 {
424 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
425 }
426
427 static void spr_read_601_rtcu (DisasContext *ctx, int gprn, int sprn)
428 {
429 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
430 }
431
432 #if !defined(CONFIG_USER_ONLY)
433 static void spr_write_601_rtcu (DisasContext *ctx, int sprn, int gprn)
434 {
435 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
436 }
437
438 static void spr_write_601_rtcl (DisasContext *ctx, int sprn, int gprn)
439 {
440 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
441 }
442
443 static void spr_write_hid0_601 (DisasContext *ctx, int sprn, int gprn)
444 {
445 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
446 /* Must stop the translation as endianness may have changed */
447 gen_stop_exception(ctx);
448 }
449 #endif
450
451 /* Unified bats */
452 #if !defined(CONFIG_USER_ONLY)
453 static void spr_read_601_ubat (DisasContext *ctx, int gprn, int sprn)
454 {
455 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
456 }
457
458 static void spr_write_601_ubatu (DisasContext *ctx, int sprn, int gprn)
459 {
460 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
461 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
462 tcg_temp_free_i32(t0);
463 }
464
465 static void spr_write_601_ubatl (DisasContext *ctx, int sprn, int gprn)
466 {
467 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
468 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
469 tcg_temp_free_i32(t0);
470 }
471 #endif
472
473 /* PowerPC 40x specific registers */
474 #if !defined(CONFIG_USER_ONLY)
475 static void spr_read_40x_pit (DisasContext *ctx, int gprn, int sprn)
476 {
477 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
478 }
479
480 static void spr_write_40x_pit (DisasContext *ctx, int sprn, int gprn)
481 {
482 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
483 }
484
485 static void spr_write_40x_dbcr0 (DisasContext *ctx, int sprn, int gprn)
486 {
487 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
488 /* We must stop translation as we may have rebooted */
489 gen_stop_exception(ctx);
490 }
491
492 static void spr_write_40x_sler (DisasContext *ctx, int sprn, int gprn)
493 {
494 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
495 }
496
497 static void spr_write_booke_tcr (DisasContext *ctx, int sprn, int gprn)
498 {
499 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
500 }
501
502 static void spr_write_booke_tsr (DisasContext *ctx, int sprn, int gprn)
503 {
504 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
505 }
506 #endif
507
508 /* PowerPC 403 specific registers */
509 /* PBL1 / PBU1 / PBL2 / PBU2 */
510 #if !defined(CONFIG_USER_ONLY)
511 static void spr_read_403_pbr (DisasContext *ctx, int gprn, int sprn)
512 {
513 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
514 }
515
516 static void spr_write_403_pbr (DisasContext *ctx, int sprn, int gprn)
517 {
518 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
519 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
520 tcg_temp_free_i32(t0);
521 }
522
523 static void spr_write_pir (DisasContext *ctx, int sprn, int gprn)
524 {
525 TCGv t0 = tcg_temp_new();
526 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
527 gen_store_spr(SPR_PIR, t0);
528 tcg_temp_free(t0);
529 }
530 #endif
531
532 /* SPE specific registers */
533 static void spr_read_spefscr (DisasContext *ctx, int gprn, int sprn)
534 {
535 TCGv_i32 t0 = tcg_temp_new_i32();
536 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
537 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
538 tcg_temp_free_i32(t0);
539 }
540
541 static void spr_write_spefscr (DisasContext *ctx, int sprn, int gprn)
542 {
543 TCGv_i32 t0 = tcg_temp_new_i32();
544 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
545 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
546 tcg_temp_free_i32(t0);
547 }
548
549 #if !defined(CONFIG_USER_ONLY)
550 /* Callback used to write the exception vector base */
551 static void spr_write_excp_prefix (DisasContext *ctx, int sprn, int gprn)
552 {
553 TCGv t0 = tcg_temp_new();
554 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
555 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
556 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
557 gen_store_spr(sprn, t0);
558 tcg_temp_free(t0);
559 }
560
561 static void spr_write_excp_vector (DisasContext *ctx, int sprn, int gprn)
562 {
563 int sprn_offs;
564
565 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
566 sprn_offs = sprn - SPR_BOOKE_IVOR0;
567 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
568 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
569 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
570 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
571 } else {
572 printf("Trying to write an unknown exception vector %d %03x\n",
573 sprn, sprn);
574 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
575 return;
576 }
577
578 TCGv t0 = tcg_temp_new();
579 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
580 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
581 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
582 gen_store_spr(sprn, t0);
583 tcg_temp_free(t0);
584 }
585 #endif
586
587 static inline void vscr_init (CPUPPCState *env, uint32_t val)
588 {
589 env->vscr = val;
590 /* Altivec always uses round-to-nearest */
591 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
592 set_flush_to_zero(vscr_nj, &env->vec_status);
593 }
594
595 #ifdef CONFIG_USER_ONLY
596 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
597 oea_read, oea_write, one_reg_id, initial_value) \
598 _spr_register(env, num, name, uea_read, uea_write, initial_value)
599 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
600 oea_read, oea_write, hea_read, hea_write, \
601 one_reg_id, initial_value) \
602 _spr_register(env, num, name, uea_read, uea_write, initial_value)
603 #else
604 #if !defined(CONFIG_KVM)
605 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
606 oea_read, oea_write, one_reg_id, initial_value) \
607 _spr_register(env, num, name, uea_read, uea_write, \
608 oea_read, oea_write, oea_read, oea_write, initial_value)
609 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
610 oea_read, oea_write, hea_read, hea_write, \
611 one_reg_id, initial_value) \
612 _spr_register(env, num, name, uea_read, uea_write, \
613 oea_read, oea_write, hea_read, hea_write, initial_value)
614 #else
615 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
616 oea_read, oea_write, one_reg_id, initial_value) \
617 _spr_register(env, num, name, uea_read, uea_write, \
618 oea_read, oea_write, oea_read, oea_write, \
619 one_reg_id, initial_value)
620 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
621 oea_read, oea_write, hea_read, hea_write, \
622 one_reg_id, initial_value) \
623 _spr_register(env, num, name, uea_read, uea_write, \
624 oea_read, oea_write, hea_read, hea_write, \
625 one_reg_id, initial_value)
626 #endif
627 #endif
628
629 #define spr_register(env, num, name, uea_read, uea_write, \
630 oea_read, oea_write, initial_value) \
631 spr_register_kvm(env, num, name, uea_read, uea_write, \
632 oea_read, oea_write, 0, initial_value)
633
634 #define spr_register_hv(env, num, name, uea_read, uea_write, \
635 oea_read, oea_write, hea_read, hea_write, \
636 initial_value) \
637 spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
638 oea_read, oea_write, hea_read, hea_write, \
639 0, initial_value)
640
641 static inline void _spr_register(CPUPPCState *env, int num,
642 const char *name,
643 void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
644 void (*uea_write)(DisasContext *ctx, int sprn, int gprn),
645 #if !defined(CONFIG_USER_ONLY)
646
647 void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
648 void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
649 void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
650 void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
651 #endif
652 #if defined(CONFIG_KVM)
653 uint64_t one_reg_id,
654 #endif
655 target_ulong initial_value)
656 {
657 ppc_spr_t *spr;
658
659 spr = &env->spr_cb[num];
660 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
661 #if !defined(CONFIG_USER_ONLY)
662 spr->oea_read != NULL || spr->oea_write != NULL ||
663 #endif
664 spr->uea_read != NULL || spr->uea_write != NULL) {
665 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
666 exit(1);
667 }
668 #if defined(PPC_DEBUG_SPR)
669 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
670 name, initial_value);
671 #endif
672 spr->name = name;
673 spr->uea_read = uea_read;
674 spr->uea_write = uea_write;
675 #if !defined(CONFIG_USER_ONLY)
676 spr->oea_read = oea_read;
677 spr->oea_write = oea_write;
678 spr->hea_read = hea_read;
679 spr->hea_write = hea_write;
680 #endif
681 #if defined(CONFIG_KVM)
682 spr->one_reg_id = one_reg_id,
683 #endif
684 env->spr[num] = spr->default_value = initial_value;
685 }
686
687 /* Generic PowerPC SPRs */
688 static void gen_spr_generic (CPUPPCState *env)
689 {
690 /* Integer processing */
691 spr_register(env, SPR_XER, "XER",
692 &spr_read_xer, &spr_write_xer,
693 &spr_read_xer, &spr_write_xer,
694 0x00000000);
695 /* Branch contol */
696 spr_register(env, SPR_LR, "LR",
697 &spr_read_lr, &spr_write_lr,
698 &spr_read_lr, &spr_write_lr,
699 0x00000000);
700 spr_register(env, SPR_CTR, "CTR",
701 &spr_read_ctr, &spr_write_ctr,
702 &spr_read_ctr, &spr_write_ctr,
703 0x00000000);
704 /* Interrupt processing */
705 spr_register(env, SPR_SRR0, "SRR0",
706 SPR_NOACCESS, SPR_NOACCESS,
707 &spr_read_generic, &spr_write_generic,
708 0x00000000);
709 spr_register(env, SPR_SRR1, "SRR1",
710 SPR_NOACCESS, SPR_NOACCESS,
711 &spr_read_generic, &spr_write_generic,
712 0x00000000);
713 /* Processor control */
714 spr_register(env, SPR_SPRG0, "SPRG0",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_generic, &spr_write_generic,
717 0x00000000);
718 spr_register(env, SPR_SPRG1, "SPRG1",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_generic, &spr_write_generic,
721 0x00000000);
722 spr_register(env, SPR_SPRG2, "SPRG2",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_generic, &spr_write_generic,
725 0x00000000);
726 spr_register(env, SPR_SPRG3, "SPRG3",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_generic, &spr_write_generic,
729 0x00000000);
730 }
731
732 /* SPR common to all non-embedded PowerPC, including 601 */
733 static void gen_spr_ne_601(CPUPPCState *env)
734 {
735 /* Exception processing */
736 spr_register_kvm(env, SPR_DSISR, "DSISR",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_generic, &spr_write_generic,
739 KVM_REG_PPC_DSISR, 0x00000000);
740 spr_register_kvm(env, SPR_DAR, "DAR",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_generic, &spr_write_generic,
743 KVM_REG_PPC_DAR, 0x00000000);
744 /* Timer */
745 spr_register(env, SPR_DECR, "DECR",
746 SPR_NOACCESS, SPR_NOACCESS,
747 &spr_read_decr, &spr_write_decr,
748 0x00000000);
749 }
750
751 /* Storage Description Register 1 */
752 static void gen_spr_sdr1(CPUPPCState *env)
753 {
754 #ifndef CONFIG_USER_ONLY
755 if (env->has_hv_mode) {
756 /* SDR1 is a hypervisor resource on CPUs which have a
757 * hypervisor mode */
758 spr_register_hv(env, SPR_SDR1, "SDR1",
759 SPR_NOACCESS, SPR_NOACCESS,
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_generic, &spr_write_sdr1,
762 0x00000000);
763 } else {
764 spr_register(env, SPR_SDR1, "SDR1",
765 SPR_NOACCESS, SPR_NOACCESS,
766 &spr_read_generic, &spr_write_sdr1,
767 0x00000000);
768 }
769 #endif
770 }
771
772 /* BATs 0-3 */
773 static void gen_low_BATs (CPUPPCState *env)
774 {
775 #if !defined(CONFIG_USER_ONLY)
776 spr_register(env, SPR_IBAT0U, "IBAT0U",
777 SPR_NOACCESS, SPR_NOACCESS,
778 &spr_read_ibat, &spr_write_ibatu,
779 0x00000000);
780 spr_register(env, SPR_IBAT0L, "IBAT0L",
781 SPR_NOACCESS, SPR_NOACCESS,
782 &spr_read_ibat, &spr_write_ibatl,
783 0x00000000);
784 spr_register(env, SPR_IBAT1U, "IBAT1U",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_ibat, &spr_write_ibatu,
787 0x00000000);
788 spr_register(env, SPR_IBAT1L, "IBAT1L",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_ibat, &spr_write_ibatl,
791 0x00000000);
792 spr_register(env, SPR_IBAT2U, "IBAT2U",
793 SPR_NOACCESS, SPR_NOACCESS,
794 &spr_read_ibat, &spr_write_ibatu,
795 0x00000000);
796 spr_register(env, SPR_IBAT2L, "IBAT2L",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_ibat, &spr_write_ibatl,
799 0x00000000);
800 spr_register(env, SPR_IBAT3U, "IBAT3U",
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_ibat, &spr_write_ibatu,
803 0x00000000);
804 spr_register(env, SPR_IBAT3L, "IBAT3L",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_ibat, &spr_write_ibatl,
807 0x00000000);
808 spr_register(env, SPR_DBAT0U, "DBAT0U",
809 SPR_NOACCESS, SPR_NOACCESS,
810 &spr_read_dbat, &spr_write_dbatu,
811 0x00000000);
812 spr_register(env, SPR_DBAT0L, "DBAT0L",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_dbat, &spr_write_dbatl,
815 0x00000000);
816 spr_register(env, SPR_DBAT1U, "DBAT1U",
817 SPR_NOACCESS, SPR_NOACCESS,
818 &spr_read_dbat, &spr_write_dbatu,
819 0x00000000);
820 spr_register(env, SPR_DBAT1L, "DBAT1L",
821 SPR_NOACCESS, SPR_NOACCESS,
822 &spr_read_dbat, &spr_write_dbatl,
823 0x00000000);
824 spr_register(env, SPR_DBAT2U, "DBAT2U",
825 SPR_NOACCESS, SPR_NOACCESS,
826 &spr_read_dbat, &spr_write_dbatu,
827 0x00000000);
828 spr_register(env, SPR_DBAT2L, "DBAT2L",
829 SPR_NOACCESS, SPR_NOACCESS,
830 &spr_read_dbat, &spr_write_dbatl,
831 0x00000000);
832 spr_register(env, SPR_DBAT3U, "DBAT3U",
833 SPR_NOACCESS, SPR_NOACCESS,
834 &spr_read_dbat, &spr_write_dbatu,
835 0x00000000);
836 spr_register(env, SPR_DBAT3L, "DBAT3L",
837 SPR_NOACCESS, SPR_NOACCESS,
838 &spr_read_dbat, &spr_write_dbatl,
839 0x00000000);
840 env->nb_BATs += 4;
841 #endif
842 }
843
844 /* BATs 4-7 */
845 static void gen_high_BATs (CPUPPCState *env)
846 {
847 #if !defined(CONFIG_USER_ONLY)
848 spr_register(env, SPR_IBAT4U, "IBAT4U",
849 SPR_NOACCESS, SPR_NOACCESS,
850 &spr_read_ibat_h, &spr_write_ibatu_h,
851 0x00000000);
852 spr_register(env, SPR_IBAT4L, "IBAT4L",
853 SPR_NOACCESS, SPR_NOACCESS,
854 &spr_read_ibat_h, &spr_write_ibatl_h,
855 0x00000000);
856 spr_register(env, SPR_IBAT5U, "IBAT5U",
857 SPR_NOACCESS, SPR_NOACCESS,
858 &spr_read_ibat_h, &spr_write_ibatu_h,
859 0x00000000);
860 spr_register(env, SPR_IBAT5L, "IBAT5L",
861 SPR_NOACCESS, SPR_NOACCESS,
862 &spr_read_ibat_h, &spr_write_ibatl_h,
863 0x00000000);
864 spr_register(env, SPR_IBAT6U, "IBAT6U",
865 SPR_NOACCESS, SPR_NOACCESS,
866 &spr_read_ibat_h, &spr_write_ibatu_h,
867 0x00000000);
868 spr_register(env, SPR_IBAT6L, "IBAT6L",
869 SPR_NOACCESS, SPR_NOACCESS,
870 &spr_read_ibat_h, &spr_write_ibatl_h,
871 0x00000000);
872 spr_register(env, SPR_IBAT7U, "IBAT7U",
873 SPR_NOACCESS, SPR_NOACCESS,
874 &spr_read_ibat_h, &spr_write_ibatu_h,
875 0x00000000);
876 spr_register(env, SPR_IBAT7L, "IBAT7L",
877 SPR_NOACCESS, SPR_NOACCESS,
878 &spr_read_ibat_h, &spr_write_ibatl_h,
879 0x00000000);
880 spr_register(env, SPR_DBAT4U, "DBAT4U",
881 SPR_NOACCESS, SPR_NOACCESS,
882 &spr_read_dbat_h, &spr_write_dbatu_h,
883 0x00000000);
884 spr_register(env, SPR_DBAT4L, "DBAT4L",
885 SPR_NOACCESS, SPR_NOACCESS,
886 &spr_read_dbat_h, &spr_write_dbatl_h,
887 0x00000000);
888 spr_register(env, SPR_DBAT5U, "DBAT5U",
889 SPR_NOACCESS, SPR_NOACCESS,
890 &spr_read_dbat_h, &spr_write_dbatu_h,
891 0x00000000);
892 spr_register(env, SPR_DBAT5L, "DBAT5L",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_dbat_h, &spr_write_dbatl_h,
895 0x00000000);
896 spr_register(env, SPR_DBAT6U, "DBAT6U",
897 SPR_NOACCESS, SPR_NOACCESS,
898 &spr_read_dbat_h, &spr_write_dbatu_h,
899 0x00000000);
900 spr_register(env, SPR_DBAT6L, "DBAT6L",
901 SPR_NOACCESS, SPR_NOACCESS,
902 &spr_read_dbat_h, &spr_write_dbatl_h,
903 0x00000000);
904 spr_register(env, SPR_DBAT7U, "DBAT7U",
905 SPR_NOACCESS, SPR_NOACCESS,
906 &spr_read_dbat_h, &spr_write_dbatu_h,
907 0x00000000);
908 spr_register(env, SPR_DBAT7L, "DBAT7L",
909 SPR_NOACCESS, SPR_NOACCESS,
910 &spr_read_dbat_h, &spr_write_dbatl_h,
911 0x00000000);
912 env->nb_BATs += 4;
913 #endif
914 }
915
916 /* Generic PowerPC time base */
917 static void gen_tbl (CPUPPCState *env)
918 {
919 spr_register(env, SPR_VTBL, "TBL",
920 &spr_read_tbl, SPR_NOACCESS,
921 &spr_read_tbl, SPR_NOACCESS,
922 0x00000000);
923 spr_register(env, SPR_TBL, "TBL",
924 &spr_read_tbl, SPR_NOACCESS,
925 &spr_read_tbl, &spr_write_tbl,
926 0x00000000);
927 spr_register(env, SPR_VTBU, "TBU",
928 &spr_read_tbu, SPR_NOACCESS,
929 &spr_read_tbu, SPR_NOACCESS,
930 0x00000000);
931 spr_register(env, SPR_TBU, "TBU",
932 &spr_read_tbu, SPR_NOACCESS,
933 &spr_read_tbu, &spr_write_tbu,
934 0x00000000);
935 }
936
937 /* Softare table search registers */
938 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
939 {
940 #if !defined(CONFIG_USER_ONLY)
941 env->nb_tlb = nb_tlbs;
942 env->nb_ways = nb_ways;
943 env->id_tlbs = 1;
944 env->tlb_type = TLB_6XX;
945 spr_register(env, SPR_DMISS, "DMISS",
946 SPR_NOACCESS, SPR_NOACCESS,
947 &spr_read_generic, SPR_NOACCESS,
948 0x00000000);
949 spr_register(env, SPR_DCMP, "DCMP",
950 SPR_NOACCESS, SPR_NOACCESS,
951 &spr_read_generic, SPR_NOACCESS,
952 0x00000000);
953 spr_register(env, SPR_HASH1, "HASH1",
954 SPR_NOACCESS, SPR_NOACCESS,
955 &spr_read_generic, SPR_NOACCESS,
956 0x00000000);
957 spr_register(env, SPR_HASH2, "HASH2",
958 SPR_NOACCESS, SPR_NOACCESS,
959 &spr_read_generic, SPR_NOACCESS,
960 0x00000000);
961 spr_register(env, SPR_IMISS, "IMISS",
962 SPR_NOACCESS, SPR_NOACCESS,
963 &spr_read_generic, SPR_NOACCESS,
964 0x00000000);
965 spr_register(env, SPR_ICMP, "ICMP",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, SPR_NOACCESS,
968 0x00000000);
969 spr_register(env, SPR_RPA, "RPA",
970 SPR_NOACCESS, SPR_NOACCESS,
971 &spr_read_generic, &spr_write_generic,
972 0x00000000);
973 #endif
974 }
975
976 /* SPR common to MPC755 and G2 */
977 static void gen_spr_G2_755 (CPUPPCState *env)
978 {
979 /* SGPRs */
980 spr_register(env, SPR_SPRG4, "SPRG4",
981 SPR_NOACCESS, SPR_NOACCESS,
982 &spr_read_generic, &spr_write_generic,
983 0x00000000);
984 spr_register(env, SPR_SPRG5, "SPRG5",
985 SPR_NOACCESS, SPR_NOACCESS,
986 &spr_read_generic, &spr_write_generic,
987 0x00000000);
988 spr_register(env, SPR_SPRG6, "SPRG6",
989 SPR_NOACCESS, SPR_NOACCESS,
990 &spr_read_generic, &spr_write_generic,
991 0x00000000);
992 spr_register(env, SPR_SPRG7, "SPRG7",
993 SPR_NOACCESS, SPR_NOACCESS,
994 &spr_read_generic, &spr_write_generic,
995 0x00000000);
996 }
997
998 /* SPR common to all 7xx PowerPC implementations */
999 static void gen_spr_7xx (CPUPPCState *env)
1000 {
1001 /* Breakpoints */
1002 /* XXX : not implemented */
1003 spr_register_kvm(env, SPR_DABR, "DABR",
1004 SPR_NOACCESS, SPR_NOACCESS,
1005 &spr_read_generic, &spr_write_generic,
1006 KVM_REG_PPC_DABR, 0x00000000);
1007 /* XXX : not implemented */
1008 spr_register(env, SPR_IABR, "IABR",
1009 SPR_NOACCESS, SPR_NOACCESS,
1010 &spr_read_generic, &spr_write_generic,
1011 0x00000000);
1012 /* Cache management */
1013 /* XXX : not implemented */
1014 spr_register(env, SPR_ICTC, "ICTC",
1015 SPR_NOACCESS, SPR_NOACCESS,
1016 &spr_read_generic, &spr_write_generic,
1017 0x00000000);
1018 /* Performance monitors */
1019 /* XXX : not implemented */
1020 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1021 SPR_NOACCESS, SPR_NOACCESS,
1022 &spr_read_generic, &spr_write_generic,
1023 0x00000000);
1024 /* XXX : not implemented */
1025 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_generic,
1028 0x00000000);
1029 /* XXX : not implemented */
1030 spr_register(env, SPR_7XX_PMC1, "PMC1",
1031 SPR_NOACCESS, SPR_NOACCESS,
1032 &spr_read_generic, &spr_write_generic,
1033 0x00000000);
1034 /* XXX : not implemented */
1035 spr_register(env, SPR_7XX_PMC2, "PMC2",
1036 SPR_NOACCESS, SPR_NOACCESS,
1037 &spr_read_generic, &spr_write_generic,
1038 0x00000000);
1039 /* XXX : not implemented */
1040 spr_register(env, SPR_7XX_PMC3, "PMC3",
1041 SPR_NOACCESS, SPR_NOACCESS,
1042 &spr_read_generic, &spr_write_generic,
1043 0x00000000);
1044 /* XXX : not implemented */
1045 spr_register(env, SPR_7XX_PMC4, "PMC4",
1046 SPR_NOACCESS, SPR_NOACCESS,
1047 &spr_read_generic, &spr_write_generic,
1048 0x00000000);
1049 /* XXX : not implemented */
1050 spr_register(env, SPR_7XX_SIAR, "SIAR",
1051 SPR_NOACCESS, SPR_NOACCESS,
1052 &spr_read_generic, SPR_NOACCESS,
1053 0x00000000);
1054 /* XXX : not implemented */
1055 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
1056 &spr_read_ureg, SPR_NOACCESS,
1057 &spr_read_ureg, SPR_NOACCESS,
1058 0x00000000);
1059 /* XXX : not implemented */
1060 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1061 &spr_read_ureg, SPR_NOACCESS,
1062 &spr_read_ureg, SPR_NOACCESS,
1063 0x00000000);
1064 /* XXX : not implemented */
1065 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1066 &spr_read_ureg, SPR_NOACCESS,
1067 &spr_read_ureg, SPR_NOACCESS,
1068 0x00000000);
1069 /* XXX : not implemented */
1070 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1071 &spr_read_ureg, SPR_NOACCESS,
1072 &spr_read_ureg, SPR_NOACCESS,
1073 0x00000000);
1074 /* XXX : not implemented */
1075 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1076 &spr_read_ureg, SPR_NOACCESS,
1077 &spr_read_ureg, SPR_NOACCESS,
1078 0x00000000);
1079 /* XXX : not implemented */
1080 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1081 &spr_read_ureg, SPR_NOACCESS,
1082 &spr_read_ureg, SPR_NOACCESS,
1083 0x00000000);
1084 /* XXX : not implemented */
1085 spr_register(env, SPR_7XX_USIAR, "USIAR",
1086 &spr_read_ureg, SPR_NOACCESS,
1087 &spr_read_ureg, SPR_NOACCESS,
1088 0x00000000);
1089 /* External access control */
1090 /* XXX : not implemented */
1091 spr_register(env, SPR_EAR, "EAR",
1092 SPR_NOACCESS, SPR_NOACCESS,
1093 &spr_read_generic, &spr_write_generic,
1094 0x00000000);
1095 }
1096
1097 #ifdef TARGET_PPC64
1098 #ifndef CONFIG_USER_ONLY
1099 static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1100 {
1101 TCGv t0 = tcg_temp_new();
1102 TCGv t1 = tcg_temp_new();
1103 TCGv t2 = tcg_temp_new();
1104
1105 /* Note, the HV=1 PR=0 case is handled earlier by simply using
1106 * spr_write_generic for HV mode in the SPR table
1107 */
1108
1109 /* Build insertion mask into t1 based on context */
1110 if (ctx->pr) {
1111 gen_load_spr(t1, SPR_UAMOR);
1112 } else {
1113 gen_load_spr(t1, SPR_AMOR);
1114 }
1115
1116 /* Mask new bits into t2 */
1117 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1118
1119 /* Load AMR and clear new bits in t0 */
1120 gen_load_spr(t0, SPR_AMR);
1121 tcg_gen_andc_tl(t0, t0, t1);
1122
1123 /* Or'in new bits and write it out */
1124 tcg_gen_or_tl(t0, t0, t2);
1125 gen_store_spr(SPR_AMR, t0);
1126 spr_store_dump_spr(SPR_AMR);
1127
1128 tcg_temp_free(t0);
1129 tcg_temp_free(t1);
1130 tcg_temp_free(t2);
1131 }
1132
1133 static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1134 {
1135 TCGv t0 = tcg_temp_new();
1136 TCGv t1 = tcg_temp_new();
1137 TCGv t2 = tcg_temp_new();
1138
1139 /* Note, the HV=1 case is handled earlier by simply using
1140 * spr_write_generic for HV mode in the SPR table
1141 */
1142
1143 /* Build insertion mask into t1 based on context */
1144 gen_load_spr(t1, SPR_AMOR);
1145
1146 /* Mask new bits into t2 */
1147 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1148
1149 /* Load AMR and clear new bits in t0 */
1150 gen_load_spr(t0, SPR_UAMOR);
1151 tcg_gen_andc_tl(t0, t0, t1);
1152
1153 /* Or'in new bits and write it out */
1154 tcg_gen_or_tl(t0, t0, t2);
1155 gen_store_spr(SPR_UAMOR, t0);
1156 spr_store_dump_spr(SPR_UAMOR);
1157
1158 tcg_temp_free(t0);
1159 tcg_temp_free(t1);
1160 tcg_temp_free(t2);
1161 }
1162
1163 static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1164 {
1165 TCGv t0 = tcg_temp_new();
1166 TCGv t1 = tcg_temp_new();
1167 TCGv t2 = tcg_temp_new();
1168
1169 /* Note, the HV=1 case is handled earlier by simply using
1170 * spr_write_generic for HV mode in the SPR table
1171 */
1172
1173 /* Build insertion mask into t1 based on context */
1174 gen_load_spr(t1, SPR_AMOR);
1175
1176 /* Mask new bits into t2 */
1177 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1178
1179 /* Load AMR and clear new bits in t0 */
1180 gen_load_spr(t0, SPR_IAMR);
1181 tcg_gen_andc_tl(t0, t0, t1);
1182
1183 /* Or'in new bits and write it out */
1184 tcg_gen_or_tl(t0, t0, t2);
1185 gen_store_spr(SPR_IAMR, t0);
1186 spr_store_dump_spr(SPR_IAMR);
1187
1188 tcg_temp_free(t0);
1189 tcg_temp_free(t1);
1190 tcg_temp_free(t2);
1191 }
1192 #endif /* CONFIG_USER_ONLY */
1193
1194 static void gen_spr_amr(CPUPPCState *env)
1195 {
1196 #ifndef CONFIG_USER_ONLY
1197 /* Virtual Page Class Key protection */
1198 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1199 * userspace accessible, 29 is privileged. So we only need to set
1200 * the kvm ONE_REG id on one of them, we use 29 */
1201 spr_register(env, SPR_UAMR, "UAMR",
1202 &spr_read_generic, &spr_write_amr,
1203 &spr_read_generic, &spr_write_amr,
1204 0);
1205 spr_register_kvm_hv(env, SPR_AMR, "AMR",
1206 SPR_NOACCESS, SPR_NOACCESS,
1207 &spr_read_generic, &spr_write_amr,
1208 &spr_read_generic, &spr_write_generic,
1209 KVM_REG_PPC_AMR, 0);
1210 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
1211 SPR_NOACCESS, SPR_NOACCESS,
1212 &spr_read_generic, &spr_write_uamor,
1213 &spr_read_generic, &spr_write_generic,
1214 KVM_REG_PPC_UAMOR, 0);
1215 spr_register_hv(env, SPR_AMOR, "AMOR",
1216 SPR_NOACCESS, SPR_NOACCESS,
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 &spr_read_generic, &spr_write_generic,
1219 0);
1220 #endif /* !CONFIG_USER_ONLY */
1221 }
1222
1223 static void gen_spr_iamr(CPUPPCState *env)
1224 {
1225 #ifndef CONFIG_USER_ONLY
1226 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
1227 SPR_NOACCESS, SPR_NOACCESS,
1228 &spr_read_generic, &spr_write_iamr,
1229 &spr_read_generic, &spr_write_generic,
1230 KVM_REG_PPC_IAMR, 0);
1231 #endif /* !CONFIG_USER_ONLY */
1232 }
1233 #endif /* TARGET_PPC64 */
1234
1235 #ifndef CONFIG_USER_ONLY
1236 static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1237 {
1238 gen_helper_fixup_thrm(cpu_env);
1239 gen_load_spr(cpu_gpr[gprn], sprn);
1240 spr_load_dump_spr(sprn);
1241 }
1242 #endif /* !CONFIG_USER_ONLY */
1243
1244 static void gen_spr_thrm (CPUPPCState *env)
1245 {
1246 /* Thermal management */
1247 /* XXX : not implemented */
1248 spr_register(env, SPR_THRM1, "THRM1",
1249 SPR_NOACCESS, SPR_NOACCESS,
1250 &spr_read_thrm, &spr_write_generic,
1251 0x00000000);
1252 /* XXX : not implemented */
1253 spr_register(env, SPR_THRM2, "THRM2",
1254 SPR_NOACCESS, SPR_NOACCESS,
1255 &spr_read_thrm, &spr_write_generic,
1256 0x00000000);
1257 /* XXX : not implemented */
1258 spr_register(env, SPR_THRM3, "THRM3",
1259 SPR_NOACCESS, SPR_NOACCESS,
1260 &spr_read_thrm, &spr_write_generic,
1261 0x00000000);
1262 }
1263
1264 /* SPR specific to PowerPC 604 implementation */
1265 static void gen_spr_604 (CPUPPCState *env)
1266 {
1267 /* Processor identification */
1268 spr_register(env, SPR_PIR, "PIR",
1269 SPR_NOACCESS, SPR_NOACCESS,
1270 &spr_read_generic, &spr_write_pir,
1271 0x00000000);
1272 /* Breakpoints */
1273 /* XXX : not implemented */
1274 spr_register(env, SPR_IABR, "IABR",
1275 SPR_NOACCESS, SPR_NOACCESS,
1276 &spr_read_generic, &spr_write_generic,
1277 0x00000000);
1278 /* XXX : not implemented */
1279 spr_register_kvm(env, SPR_DABR, "DABR",
1280 SPR_NOACCESS, SPR_NOACCESS,
1281 &spr_read_generic, &spr_write_generic,
1282 KVM_REG_PPC_DABR, 0x00000000);
1283 /* Performance counters */
1284 /* XXX : not implemented */
1285 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1286 SPR_NOACCESS, SPR_NOACCESS,
1287 &spr_read_generic, &spr_write_generic,
1288 0x00000000);
1289 /* XXX : not implemented */
1290 spr_register(env, SPR_7XX_PMC1, "PMC1",
1291 SPR_NOACCESS, SPR_NOACCESS,
1292 &spr_read_generic, &spr_write_generic,
1293 0x00000000);
1294 /* XXX : not implemented */
1295 spr_register(env, SPR_7XX_PMC2, "PMC2",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_generic, &spr_write_generic,
1298 0x00000000);
1299 /* XXX : not implemented */
1300 spr_register(env, SPR_7XX_SIAR, "SIAR",
1301 SPR_NOACCESS, SPR_NOACCESS,
1302 &spr_read_generic, SPR_NOACCESS,
1303 0x00000000);
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_SDA, "SDA",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, SPR_NOACCESS,
1308 0x00000000);
1309 /* External access control */
1310 /* XXX : not implemented */
1311 spr_register(env, SPR_EAR, "EAR",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_generic, &spr_write_generic,
1314 0x00000000);
1315 }
1316
1317 /* SPR specific to PowerPC 603 implementation */
1318 static void gen_spr_603 (CPUPPCState *env)
1319 {
1320 /* External access control */
1321 /* XXX : not implemented */
1322 spr_register(env, SPR_EAR, "EAR",
1323 SPR_NOACCESS, SPR_NOACCESS,
1324 &spr_read_generic, &spr_write_generic,
1325 0x00000000);
1326 /* Breakpoints */
1327 /* XXX : not implemented */
1328 spr_register(env, SPR_IABR, "IABR",
1329 SPR_NOACCESS, SPR_NOACCESS,
1330 &spr_read_generic, &spr_write_generic,
1331 0x00000000);
1332
1333 }
1334
1335 /* SPR specific to PowerPC G2 implementation */
1336 static void gen_spr_G2 (CPUPPCState *env)
1337 {
1338 /* Memory base address */
1339 /* MBAR */
1340 /* XXX : not implemented */
1341 spr_register(env, SPR_MBAR, "MBAR",
1342 SPR_NOACCESS, SPR_NOACCESS,
1343 &spr_read_generic, &spr_write_generic,
1344 0x00000000);
1345 /* Exception processing */
1346 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_generic,
1349 0x00000000);
1350 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_generic,
1353 0x00000000);
1354 /* Breakpoints */
1355 /* XXX : not implemented */
1356 spr_register(env, SPR_DABR, "DABR",
1357 SPR_NOACCESS, SPR_NOACCESS,
1358 &spr_read_generic, &spr_write_generic,
1359 0x00000000);
1360 /* XXX : not implemented */
1361 spr_register(env, SPR_DABR2, "DABR2",
1362 SPR_NOACCESS, SPR_NOACCESS,
1363 &spr_read_generic, &spr_write_generic,
1364 0x00000000);
1365 /* XXX : not implemented */
1366 spr_register(env, SPR_IABR, "IABR",
1367 SPR_NOACCESS, SPR_NOACCESS,
1368 &spr_read_generic, &spr_write_generic,
1369 0x00000000);
1370 /* XXX : not implemented */
1371 spr_register(env, SPR_IABR2, "IABR2",
1372 SPR_NOACCESS, SPR_NOACCESS,
1373 &spr_read_generic, &spr_write_generic,
1374 0x00000000);
1375 /* XXX : not implemented */
1376 spr_register(env, SPR_IBCR, "IBCR",
1377 SPR_NOACCESS, SPR_NOACCESS,
1378 &spr_read_generic, &spr_write_generic,
1379 0x00000000);
1380 /* XXX : not implemented */
1381 spr_register(env, SPR_DBCR, "DBCR",
1382 SPR_NOACCESS, SPR_NOACCESS,
1383 &spr_read_generic, &spr_write_generic,
1384 0x00000000);
1385 }
1386
1387 /* SPR specific to PowerPC 602 implementation */
1388 static void gen_spr_602 (CPUPPCState *env)
1389 {
1390 /* ESA registers */
1391 /* XXX : not implemented */
1392 spr_register(env, SPR_SER, "SER",
1393 SPR_NOACCESS, SPR_NOACCESS,
1394 &spr_read_generic, &spr_write_generic,
1395 0x00000000);
1396 /* XXX : not implemented */
1397 spr_register(env, SPR_SEBR, "SEBR",
1398 SPR_NOACCESS, SPR_NOACCESS,
1399 &spr_read_generic, &spr_write_generic,
1400 0x00000000);
1401 /* XXX : not implemented */
1402 spr_register(env, SPR_ESASRR, "ESASRR",
1403 SPR_NOACCESS, SPR_NOACCESS,
1404 &spr_read_generic, &spr_write_generic,
1405 0x00000000);
1406 /* Floating point status */
1407 /* XXX : not implemented */
1408 spr_register(env, SPR_SP, "SP",
1409 SPR_NOACCESS, SPR_NOACCESS,
1410 &spr_read_generic, &spr_write_generic,
1411 0x00000000);
1412 /* XXX : not implemented */
1413 spr_register(env, SPR_LT, "LT",
1414 SPR_NOACCESS, SPR_NOACCESS,
1415 &spr_read_generic, &spr_write_generic,
1416 0x00000000);
1417 /* Watchdog timer */
1418 /* XXX : not implemented */
1419 spr_register(env, SPR_TCR, "TCR",
1420 SPR_NOACCESS, SPR_NOACCESS,
1421 &spr_read_generic, &spr_write_generic,
1422 0x00000000);
1423 /* Interrupt base */
1424 spr_register(env, SPR_IBR, "IBR",
1425 SPR_NOACCESS, SPR_NOACCESS,
1426 &spr_read_generic, &spr_write_generic,
1427 0x00000000);
1428 /* XXX : not implemented */
1429 spr_register(env, SPR_IABR, "IABR",
1430 SPR_NOACCESS, SPR_NOACCESS,
1431 &spr_read_generic, &spr_write_generic,
1432 0x00000000);
1433 }
1434
1435 /* SPR specific to PowerPC 601 implementation */
1436 static void gen_spr_601 (CPUPPCState *env)
1437 {
1438 /* Multiplication/division register */
1439 /* MQ */
1440 spr_register(env, SPR_MQ, "MQ",
1441 &spr_read_generic, &spr_write_generic,
1442 &spr_read_generic, &spr_write_generic,
1443 0x00000000);
1444 /* RTC registers */
1445 spr_register(env, SPR_601_RTCU, "RTCU",
1446 SPR_NOACCESS, SPR_NOACCESS,
1447 SPR_NOACCESS, &spr_write_601_rtcu,
1448 0x00000000);
1449 spr_register(env, SPR_601_VRTCU, "RTCU",
1450 &spr_read_601_rtcu, SPR_NOACCESS,
1451 &spr_read_601_rtcu, SPR_NOACCESS,
1452 0x00000000);
1453 spr_register(env, SPR_601_RTCL, "RTCL",
1454 SPR_NOACCESS, SPR_NOACCESS,
1455 SPR_NOACCESS, &spr_write_601_rtcl,
1456 0x00000000);
1457 spr_register(env, SPR_601_VRTCL, "RTCL",
1458 &spr_read_601_rtcl, SPR_NOACCESS,
1459 &spr_read_601_rtcl, SPR_NOACCESS,
1460 0x00000000);
1461 /* Timer */
1462 #if 0 /* ? */
1463 spr_register(env, SPR_601_UDECR, "UDECR",
1464 &spr_read_decr, SPR_NOACCESS,
1465 &spr_read_decr, SPR_NOACCESS,
1466 0x00000000);
1467 #endif
1468 /* External access control */
1469 /* XXX : not implemented */
1470 spr_register(env, SPR_EAR, "EAR",
1471 SPR_NOACCESS, SPR_NOACCESS,
1472 &spr_read_generic, &spr_write_generic,
1473 0x00000000);
1474 /* Memory management */
1475 #if !defined(CONFIG_USER_ONLY)
1476 spr_register(env, SPR_IBAT0U, "IBAT0U",
1477 SPR_NOACCESS, SPR_NOACCESS,
1478 &spr_read_601_ubat, &spr_write_601_ubatu,
1479 0x00000000);
1480 spr_register(env, SPR_IBAT0L, "IBAT0L",
1481 SPR_NOACCESS, SPR_NOACCESS,
1482 &spr_read_601_ubat, &spr_write_601_ubatl,
1483 0x00000000);
1484 spr_register(env, SPR_IBAT1U, "IBAT1U",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_601_ubat, &spr_write_601_ubatu,
1487 0x00000000);
1488 spr_register(env, SPR_IBAT1L, "IBAT1L",
1489 SPR_NOACCESS, SPR_NOACCESS,
1490 &spr_read_601_ubat, &spr_write_601_ubatl,
1491 0x00000000);
1492 spr_register(env, SPR_IBAT2U, "IBAT2U",
1493 SPR_NOACCESS, SPR_NOACCESS,
1494 &spr_read_601_ubat, &spr_write_601_ubatu,
1495 0x00000000);
1496 spr_register(env, SPR_IBAT2L, "IBAT2L",
1497 SPR_NOACCESS, SPR_NOACCESS,
1498 &spr_read_601_ubat, &spr_write_601_ubatl,
1499 0x00000000);
1500 spr_register(env, SPR_IBAT3U, "IBAT3U",
1501 SPR_NOACCESS, SPR_NOACCESS,
1502 &spr_read_601_ubat, &spr_write_601_ubatu,
1503 0x00000000);
1504 spr_register(env, SPR_IBAT3L, "IBAT3L",
1505 SPR_NOACCESS, SPR_NOACCESS,
1506 &spr_read_601_ubat, &spr_write_601_ubatl,
1507 0x00000000);
1508 env->nb_BATs = 4;
1509 #endif
1510 }
1511
1512 static void gen_spr_74xx (CPUPPCState *env)
1513 {
1514 /* Processor identification */
1515 spr_register(env, SPR_PIR, "PIR",
1516 SPR_NOACCESS, SPR_NOACCESS,
1517 &spr_read_generic, &spr_write_pir,
1518 0x00000000);
1519 /* XXX : not implemented */
1520 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1521 SPR_NOACCESS, SPR_NOACCESS,
1522 &spr_read_generic, &spr_write_generic,
1523 0x00000000);
1524 /* XXX : not implemented */
1525 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1526 &spr_read_ureg, SPR_NOACCESS,
1527 &spr_read_ureg, SPR_NOACCESS,
1528 0x00000000);
1529 /* XXX: not implemented */
1530 spr_register(env, SPR_BAMR, "BAMR",
1531 SPR_NOACCESS, SPR_NOACCESS,
1532 &spr_read_generic, &spr_write_generic,
1533 0x00000000);
1534 /* XXX : not implemented */
1535 spr_register(env, SPR_MSSCR0, "MSSCR0",
1536 SPR_NOACCESS, SPR_NOACCESS,
1537 &spr_read_generic, &spr_write_generic,
1538 0x00000000);
1539 /* Hardware implementation registers */
1540 /* XXX : not implemented */
1541 spr_register(env, SPR_HID0, "HID0",
1542 SPR_NOACCESS, SPR_NOACCESS,
1543 &spr_read_generic, &spr_write_generic,
1544 0x00000000);
1545 /* XXX : not implemented */
1546 spr_register(env, SPR_HID1, "HID1",
1547 SPR_NOACCESS, SPR_NOACCESS,
1548 &spr_read_generic, &spr_write_generic,
1549 0x00000000);
1550 /* Altivec */
1551 spr_register(env, SPR_VRSAVE, "VRSAVE",
1552 &spr_read_generic, &spr_write_generic,
1553 &spr_read_generic, &spr_write_generic,
1554 0x00000000);
1555 /* XXX : not implemented */
1556 spr_register(env, SPR_L2CR, "L2CR",
1557 SPR_NOACCESS, SPR_NOACCESS,
1558 &spr_read_generic, spr_access_nop,
1559 0x00000000);
1560 /* Not strictly an SPR */
1561 vscr_init(env, 0x00010000);
1562 }
1563
1564 static void gen_l3_ctrl (CPUPPCState *env)
1565 {
1566 /* L3CR */
1567 /* XXX : not implemented */
1568 spr_register(env, SPR_L3CR, "L3CR",
1569 SPR_NOACCESS, SPR_NOACCESS,
1570 &spr_read_generic, &spr_write_generic,
1571 0x00000000);
1572 /* L3ITCR0 */
1573 /* XXX : not implemented */
1574 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 &spr_read_generic, &spr_write_generic,
1577 0x00000000);
1578 /* L3PM */
1579 /* XXX : not implemented */
1580 spr_register(env, SPR_L3PM, "L3PM",
1581 SPR_NOACCESS, SPR_NOACCESS,
1582 &spr_read_generic, &spr_write_generic,
1583 0x00000000);
1584 }
1585
1586 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1587 {
1588 #if !defined(CONFIG_USER_ONLY)
1589 env->nb_tlb = nb_tlbs;
1590 env->nb_ways = nb_ways;
1591 env->id_tlbs = 1;
1592 env->tlb_type = TLB_6XX;
1593 /* XXX : not implemented */
1594 spr_register(env, SPR_PTEHI, "PTEHI",
1595 SPR_NOACCESS, SPR_NOACCESS,
1596 &spr_read_generic, &spr_write_generic,
1597 0x00000000);
1598 /* XXX : not implemented */
1599 spr_register(env, SPR_PTELO, "PTELO",
1600 SPR_NOACCESS, SPR_NOACCESS,
1601 &spr_read_generic, &spr_write_generic,
1602 0x00000000);
1603 /* XXX : not implemented */
1604 spr_register(env, SPR_TLBMISS, "TLBMISS",
1605 SPR_NOACCESS, SPR_NOACCESS,
1606 &spr_read_generic, &spr_write_generic,
1607 0x00000000);
1608 #endif
1609 }
1610
1611 #if !defined(CONFIG_USER_ONLY)
1612 static void spr_write_e500_l1csr0 (DisasContext *ctx, int sprn, int gprn)
1613 {
1614 TCGv t0 = tcg_temp_new();
1615
1616 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1617 gen_store_spr(sprn, t0);
1618 tcg_temp_free(t0);
1619 }
1620
1621 static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1622 {
1623 TCGv t0 = tcg_temp_new();
1624
1625 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1626 gen_store_spr(sprn, t0);
1627 tcg_temp_free(t0);
1628 }
1629
1630 static void spr_write_booke206_mmucsr0 (DisasContext *ctx, int sprn, int gprn)
1631 {
1632 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1633 }
1634
1635 static void spr_write_booke_pid (DisasContext *ctx, int sprn, int gprn)
1636 {
1637 TCGv_i32 t0 = tcg_const_i32(sprn);
1638 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1639 tcg_temp_free_i32(t0);
1640 }
1641 #endif
1642
1643 static void gen_spr_usprg3 (CPUPPCState *env)
1644 {
1645 spr_register(env, SPR_USPRG3, "USPRG3",
1646 &spr_read_ureg, SPR_NOACCESS,
1647 &spr_read_ureg, SPR_NOACCESS,
1648 0x00000000);
1649 }
1650
1651 static void gen_spr_usprgh (CPUPPCState *env)
1652 {
1653 spr_register(env, SPR_USPRG4, "USPRG4",
1654 &spr_read_ureg, SPR_NOACCESS,
1655 &spr_read_ureg, SPR_NOACCESS,
1656 0x00000000);
1657 spr_register(env, SPR_USPRG5, "USPRG5",
1658 &spr_read_ureg, SPR_NOACCESS,
1659 &spr_read_ureg, SPR_NOACCESS,
1660 0x00000000);
1661 spr_register(env, SPR_USPRG6, "USPRG6",
1662 &spr_read_ureg, SPR_NOACCESS,
1663 &spr_read_ureg, SPR_NOACCESS,
1664 0x00000000);
1665 spr_register(env, SPR_USPRG7, "USPRG7",
1666 &spr_read_ureg, SPR_NOACCESS,
1667 &spr_read_ureg, SPR_NOACCESS,
1668 0x00000000);
1669 }
1670
1671 /* PowerPC BookE SPR */
1672 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1673 {
1674 const char *ivor_names[64] = {
1675 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1676 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1677 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1678 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1679 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1680 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1681 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1682 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1683 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1684 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1685 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1686 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1687 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1688 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1689 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1690 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1691 };
1692 #define SPR_BOOKE_IVORxx (-1)
1693 int ivor_sprn[64] = {
1694 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1695 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1696 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1697 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1698 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1699 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1700 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1701 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1702 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1703 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1704 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1705 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1706 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1707 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1708 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1709 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1710 };
1711 int i;
1712
1713 /* Interrupt processing */
1714 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1715 SPR_NOACCESS, SPR_NOACCESS,
1716 &spr_read_generic, &spr_write_generic,
1717 0x00000000);
1718 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1719 SPR_NOACCESS, SPR_NOACCESS,
1720 &spr_read_generic, &spr_write_generic,
1721 0x00000000);
1722 /* Debug */
1723 /* XXX : not implemented */
1724 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1725 SPR_NOACCESS, SPR_NOACCESS,
1726 &spr_read_generic, &spr_write_generic,
1727 0x00000000);
1728 /* XXX : not implemented */
1729 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1730 SPR_NOACCESS, SPR_NOACCESS,
1731 &spr_read_generic, &spr_write_generic,
1732 0x00000000);
1733 /* XXX : not implemented */
1734 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1735 SPR_NOACCESS, SPR_NOACCESS,
1736 &spr_read_generic, &spr_write_generic,
1737 0x00000000);
1738 /* XXX : not implemented */
1739 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1740 SPR_NOACCESS, SPR_NOACCESS,
1741 &spr_read_generic, &spr_write_generic,
1742 0x00000000);
1743 /* XXX : not implemented */
1744 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1745 SPR_NOACCESS, SPR_NOACCESS,
1746 &spr_read_generic, &spr_write_40x_dbcr0,
1747 0x00000000);
1748 /* XXX : not implemented */
1749 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1750 SPR_NOACCESS, SPR_NOACCESS,
1751 &spr_read_generic, &spr_write_generic,
1752 0x00000000);
1753 /* XXX : not implemented */
1754 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1755 SPR_NOACCESS, SPR_NOACCESS,
1756 &spr_read_generic, &spr_write_generic,
1757 0x00000000);
1758 /* XXX : not implemented */
1759 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1760 SPR_NOACCESS, SPR_NOACCESS,
1761 &spr_read_generic, &spr_write_clear,
1762 0x00000000);
1763 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1764 SPR_NOACCESS, SPR_NOACCESS,
1765 &spr_read_generic, &spr_write_generic,
1766 0x00000000);
1767 spr_register(env, SPR_BOOKE_ESR, "ESR",
1768 SPR_NOACCESS, SPR_NOACCESS,
1769 &spr_read_generic, &spr_write_generic,
1770 0x00000000);
1771 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1772 SPR_NOACCESS, SPR_NOACCESS,
1773 &spr_read_generic, &spr_write_excp_prefix,
1774 0x00000000);
1775 /* Exception vectors */
1776 for (i = 0; i < 64; i++) {
1777 if (ivor_mask & (1ULL << i)) {
1778 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1779 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1780 exit(1);
1781 }
1782 spr_register(env, ivor_sprn[i], ivor_names[i],
1783 SPR_NOACCESS, SPR_NOACCESS,
1784 &spr_read_generic, &spr_write_excp_vector,
1785 0x00000000);
1786 }
1787 }
1788 spr_register(env, SPR_BOOKE_PID, "PID",
1789 SPR_NOACCESS, SPR_NOACCESS,
1790 &spr_read_generic, &spr_write_booke_pid,
1791 0x00000000);
1792 spr_register(env, SPR_BOOKE_TCR, "TCR",
1793 SPR_NOACCESS, SPR_NOACCESS,
1794 &spr_read_generic, &spr_write_booke_tcr,
1795 0x00000000);
1796 spr_register(env, SPR_BOOKE_TSR, "TSR",
1797 SPR_NOACCESS, SPR_NOACCESS,
1798 &spr_read_generic, &spr_write_booke_tsr,
1799 0x00000000);
1800 /* Timer */
1801 spr_register(env, SPR_DECR, "DECR",
1802 SPR_NOACCESS, SPR_NOACCESS,
1803 &spr_read_decr, &spr_write_decr,
1804 0x00000000);
1805 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1806 SPR_NOACCESS, SPR_NOACCESS,
1807 SPR_NOACCESS, &spr_write_generic,
1808 0x00000000);
1809 /* SPRGs */
1810 spr_register(env, SPR_USPRG0, "USPRG0",
1811 &spr_read_generic, &spr_write_generic,
1812 &spr_read_generic, &spr_write_generic,
1813 0x00000000);
1814 spr_register(env, SPR_SPRG4, "SPRG4",
1815 SPR_NOACCESS, SPR_NOACCESS,
1816 &spr_read_generic, &spr_write_generic,
1817 0x00000000);
1818 spr_register(env, SPR_SPRG5, "SPRG5",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_generic,
1821 0x00000000);
1822 spr_register(env, SPR_SPRG6, "SPRG6",
1823 SPR_NOACCESS, SPR_NOACCESS,
1824 &spr_read_generic, &spr_write_generic,
1825 0x00000000);
1826 spr_register(env, SPR_SPRG7, "SPRG7",
1827 SPR_NOACCESS, SPR_NOACCESS,
1828 &spr_read_generic, &spr_write_generic,
1829 0x00000000);
1830 }
1831
1832 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1833 uint32_t maxsize, uint32_t flags,
1834 uint32_t nentries)
1835 {
1836 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1837 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1838 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1839 flags | nentries;
1840 }
1841
1842 /* BookE 2.06 storage control registers */
1843 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1844 uint32_t *tlbncfg)
1845 {
1846 #if !defined(CONFIG_USER_ONLY)
1847 const char *mas_names[8] = {
1848 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1849 };
1850 int mas_sprn[8] = {
1851 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1852 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1853 };
1854 int i;
1855
1856 /* TLB assist registers */
1857 /* XXX : not implemented */
1858 for (i = 0; i < 8; i++) {
1859 void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32;
1860 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1861 uea_write = &spr_write_generic;
1862 }
1863 if (mas_mask & (1 << i)) {
1864 spr_register(env, mas_sprn[i], mas_names[i],
1865 SPR_NOACCESS, SPR_NOACCESS,
1866 &spr_read_generic, uea_write,
1867 0x00000000);
1868 }
1869 }
1870 if (env->nb_pids > 1) {
1871 /* XXX : not implemented */
1872 spr_register(env, SPR_BOOKE_PID1, "PID1",
1873 SPR_NOACCESS, SPR_NOACCESS,
1874 &spr_read_generic, &spr_write_booke_pid,
1875 0x00000000);
1876 }
1877 if (env->nb_pids > 2) {
1878 /* XXX : not implemented */
1879 spr_register(env, SPR_BOOKE_PID2, "PID2",
1880 SPR_NOACCESS, SPR_NOACCESS,
1881 &spr_read_generic, &spr_write_booke_pid,
1882 0x00000000);
1883 }
1884 /* XXX : not implemented */
1885 spr_register(env, SPR_MMUCFG, "MMUCFG",
1886 SPR_NOACCESS, SPR_NOACCESS,
1887 &spr_read_generic, SPR_NOACCESS,
1888 0x00000000); /* TOFIX */
1889 switch (env->nb_ways) {
1890 case 4:
1891 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1892 SPR_NOACCESS, SPR_NOACCESS,
1893 &spr_read_generic, SPR_NOACCESS,
1894 tlbncfg[3]);
1895 /* Fallthru */
1896 case 3:
1897 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1898 SPR_NOACCESS, SPR_NOACCESS,
1899 &spr_read_generic, SPR_NOACCESS,
1900 tlbncfg[2]);
1901 /* Fallthru */
1902 case 2:
1903 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1904 SPR_NOACCESS, SPR_NOACCESS,
1905 &spr_read_generic, SPR_NOACCESS,
1906 tlbncfg[1]);
1907 /* Fallthru */
1908 case 1:
1909 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1910 SPR_NOACCESS, SPR_NOACCESS,
1911 &spr_read_generic, SPR_NOACCESS,
1912 tlbncfg[0]);
1913 /* Fallthru */
1914 case 0:
1915 default:
1916 break;
1917 }
1918 #endif
1919
1920 gen_spr_usprgh(env);
1921 }
1922
1923 /* SPR specific to PowerPC 440 implementation */
1924 static void gen_spr_440 (CPUPPCState *env)
1925 {
1926 /* Cache control */
1927 /* XXX : not implemented */
1928 spr_register(env, SPR_440_DNV0, "DNV0",
1929 SPR_NOACCESS, SPR_NOACCESS,
1930 &spr_read_generic, &spr_write_generic,
1931 0x00000000);
1932 /* XXX : not implemented */
1933 spr_register(env, SPR_440_DNV1, "DNV1",
1934 SPR_NOACCESS, SPR_NOACCESS,
1935 &spr_read_generic, &spr_write_generic,
1936 0x00000000);
1937 /* XXX : not implemented */
1938 spr_register(env, SPR_440_DNV2, "DNV2",
1939 SPR_NOACCESS, SPR_NOACCESS,
1940 &spr_read_generic, &spr_write_generic,
1941 0x00000000);
1942 /* XXX : not implemented */
1943 spr_register(env, SPR_440_DNV3, "DNV3",
1944 SPR_NOACCESS, SPR_NOACCESS,
1945 &spr_read_generic, &spr_write_generic,
1946 0x00000000);
1947 /* XXX : not implemented */
1948 spr_register(env, SPR_440_DTV0, "DTV0",
1949 SPR_NOACCESS, SPR_NOACCESS,
1950 &spr_read_generic, &spr_write_generic,
1951 0x00000000);
1952 /* XXX : not implemented */
1953 spr_register(env, SPR_440_DTV1, "DTV1",
1954 SPR_NOACCESS, SPR_NOACCESS,
1955 &spr_read_generic, &spr_write_generic,
1956 0x00000000);
1957 /* XXX : not implemented */
1958 spr_register(env, SPR_440_DTV2, "DTV2",
1959 SPR_NOACCESS, SPR_NOACCESS,
1960 &spr_read_generic, &spr_write_generic,
1961 0x00000000);
1962 /* XXX : not implemented */
1963 spr_register(env, SPR_440_DTV3, "DTV3",
1964 SPR_NOACCESS, SPR_NOACCESS,
1965 &spr_read_generic, &spr_write_generic,
1966 0x00000000);
1967 /* XXX : not implemented */
1968 spr_register(env, SPR_440_DVLIM, "DVLIM",
1969 SPR_NOACCESS, SPR_NOACCESS,
1970 &spr_read_generic, &spr_write_generic,
1971 0x00000000);
1972 /* XXX : not implemented */
1973 spr_register(env, SPR_440_INV0, "INV0",
1974 SPR_NOACCESS, SPR_NOACCESS,
1975 &spr_read_generic, &spr_write_generic,
1976 0x00000000);
1977 /* XXX : not implemented */
1978 spr_register(env, SPR_440_INV1, "INV1",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_generic, &spr_write_generic,
1981 0x00000000);
1982 /* XXX : not implemented */
1983 spr_register(env, SPR_440_INV2, "INV2",
1984 SPR_NOACCESS, SPR_NOACCESS,
1985 &spr_read_generic, &spr_write_generic,
1986 0x00000000);
1987 /* XXX : not implemented */
1988 spr_register(env, SPR_440_INV3, "INV3",
1989 SPR_NOACCESS, SPR_NOACCESS,
1990 &spr_read_generic, &spr_write_generic,
1991 0x00000000);
1992 /* XXX : not implemented */
1993 spr_register(env, SPR_440_ITV0, "ITV0",
1994 SPR_NOACCESS, SPR_NOACCESS,
1995 &spr_read_generic, &spr_write_generic,
1996 0x00000000);
1997 /* XXX : not implemented */
1998 spr_register(env, SPR_440_ITV1, "ITV1",
1999 SPR_NOACCESS, SPR_NOACCESS,
2000 &spr_read_generic, &spr_write_generic,
2001 0x00000000);
2002 /* XXX : not implemented */
2003 spr_register(env, SPR_440_ITV2, "ITV2",
2004 SPR_NOACCESS, SPR_NOACCESS,
2005 &spr_read_generic, &spr_write_generic,
2006 0x00000000);
2007 /* XXX : not implemented */
2008 spr_register(env, SPR_440_ITV3, "ITV3",
2009 SPR_NOACCESS, SPR_NOACCESS,
2010 &spr_read_generic, &spr_write_generic,
2011 0x00000000);
2012 /* XXX : not implemented */
2013 spr_register(env, SPR_440_IVLIM, "IVLIM",
2014 SPR_NOACCESS, SPR_NOACCESS,
2015 &spr_read_generic, &spr_write_generic,
2016 0x00000000);
2017 /* Cache debug */
2018 /* XXX : not implemented */
2019 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
2020 SPR_NOACCESS, SPR_NOACCESS,
2021 &spr_read_generic, SPR_NOACCESS,
2022 0x00000000);
2023 /* XXX : not implemented */
2024 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
2025 SPR_NOACCESS, SPR_NOACCESS,
2026 &spr_read_generic, SPR_NOACCESS,
2027 0x00000000);
2028 /* XXX : not implemented */
2029 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2030 SPR_NOACCESS, SPR_NOACCESS,
2031 &spr_read_generic, SPR_NOACCESS,
2032 0x00000000);
2033 /* XXX : not implemented */
2034 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
2035 SPR_NOACCESS, SPR_NOACCESS,
2036 &spr_read_generic, SPR_NOACCESS,
2037 0x00000000);
2038 /* XXX : not implemented */
2039 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
2040 SPR_NOACCESS, SPR_NOACCESS,
2041 &spr_read_generic, SPR_NOACCESS,
2042 0x00000000);
2043 /* XXX : not implemented */
2044 spr_register(env, SPR_440_DBDR, "DBDR",
2045 SPR_NOACCESS, SPR_NOACCESS,
2046 &spr_read_generic, &spr_write_generic,
2047 0x00000000);
2048 /* Processor control */
2049 spr_register(env, SPR_4xx_CCR0, "CCR0",
2050 SPR_NOACCESS, SPR_NOACCESS,
2051 &spr_read_generic, &spr_write_generic,
2052 0x00000000);
2053 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
2054 SPR_NOACCESS, SPR_NOACCESS,
2055 &spr_read_generic, SPR_NOACCESS,
2056 0x00000000);
2057 /* Storage control */
2058 spr_register(env, SPR_440_MMUCR, "MMUCR",
2059 SPR_NOACCESS, SPR_NOACCESS,
2060 &spr_read_generic, &spr_write_generic,
2061 0x00000000);
2062 }
2063
2064 /* SPR shared between PowerPC 40x implementations */
2065 static void gen_spr_40x (CPUPPCState *env)
2066 {
2067 /* Cache */
2068 /* not emulated, as QEMU do not emulate caches */
2069 spr_register(env, SPR_40x_DCCR, "DCCR",
2070 SPR_NOACCESS, SPR_NOACCESS,
2071 &spr_read_generic, &spr_write_generic,
2072 0x00000000);
2073 /* not emulated, as QEMU do not emulate caches */
2074 spr_register(env, SPR_40x_ICCR, "ICCR",
2075 SPR_NOACCESS, SPR_NOACCESS,
2076 &spr_read_generic, &spr_write_generic,
2077 0x00000000);
2078 /* not emulated, as QEMU do not emulate caches */
2079 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2080 SPR_NOACCESS, SPR_NOACCESS,
2081 &spr_read_generic, SPR_NOACCESS,
2082 0x00000000);
2083 /* Exception */
2084 spr_register(env, SPR_40x_DEAR, "DEAR",
2085 SPR_NOACCESS, SPR_NOACCESS,
2086 &spr_read_generic, &spr_write_generic,
2087 0x00000000);
2088 spr_register(env, SPR_40x_ESR, "ESR",
2089 SPR_NOACCESS, SPR_NOACCESS,
2090 &spr_read_generic, &spr_write_generic,
2091 0x00000000);
2092 spr_register(env, SPR_40x_EVPR, "EVPR",
2093 SPR_NOACCESS, SPR_NOACCESS,
2094 &spr_read_generic, &spr_write_excp_prefix,
2095 0x00000000);
2096 spr_register(env, SPR_40x_SRR2, "SRR2",
2097 &spr_read_generic, &spr_write_generic,
2098 &spr_read_generic, &spr_write_generic,
2099 0x00000000);
2100 spr_register(env, SPR_40x_SRR3, "SRR3",
2101 &spr_read_generic, &spr_write_generic,
2102 &spr_read_generic, &spr_write_generic,
2103 0x00000000);
2104 /* Timers */
2105 spr_register(env, SPR_40x_PIT, "PIT",
2106 SPR_NOACCESS, SPR_NOACCESS,
2107 &spr_read_40x_pit, &spr_write_40x_pit,
2108 0x00000000);
2109 spr_register(env, SPR_40x_TCR, "TCR",
2110 SPR_NOACCESS, SPR_NOACCESS,
2111 &spr_read_generic, &spr_write_booke_tcr,
2112 0x00000000);
2113 spr_register(env, SPR_40x_TSR, "TSR",
2114 SPR_NOACCESS, SPR_NOACCESS,
2115 &spr_read_generic, &spr_write_booke_tsr,
2116 0x00000000);
2117 }
2118
2119 /* SPR specific to PowerPC 405 implementation */
2120 static void gen_spr_405 (CPUPPCState *env)
2121 {
2122 /* MMU */
2123 spr_register(env, SPR_40x_PID, "PID",
2124 SPR_NOACCESS, SPR_NOACCESS,
2125 &spr_read_generic, &spr_write_generic,
2126 0x00000000);
2127 spr_register(env, SPR_4xx_CCR0, "CCR0",
2128 SPR_NOACCESS, SPR_NOACCESS,
2129 &spr_read_generic, &spr_write_generic,
2130 0x00700000);
2131 /* Debug interface */
2132 /* XXX : not implemented */
2133 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2134 SPR_NOACCESS, SPR_NOACCESS,
2135 &spr_read_generic, &spr_write_40x_dbcr0,
2136 0x00000000);
2137 /* XXX : not implemented */
2138 spr_register(env, SPR_405_DBCR1, "DBCR1",
2139 SPR_NOACCESS, SPR_NOACCESS,
2140 &spr_read_generic, &spr_write_generic,
2141 0x00000000);
2142 /* XXX : not implemented */
2143 spr_register(env, SPR_40x_DBSR, "DBSR",
2144 SPR_NOACCESS, SPR_NOACCESS,
2145 &spr_read_generic, &spr_write_clear,
2146 /* Last reset was system reset */
2147 0x00000300);
2148 /* XXX : not implemented */
2149 spr_register(env, SPR_40x_DAC1, "DAC1",
2150 SPR_NOACCESS, SPR_NOACCESS,
2151 &spr_read_generic, &spr_write_generic,
2152 0x00000000);
2153 spr_register(env, SPR_40x_DAC2, "DAC2",
2154 SPR_NOACCESS, SPR_NOACCESS,
2155 &spr_read_generic, &spr_write_generic,
2156 0x00000000);
2157 /* XXX : not implemented */
2158 spr_register(env, SPR_405_DVC1, "DVC1",
2159 SPR_NOACCESS, SPR_NOACCESS,
2160 &spr_read_generic, &spr_write_generic,
2161 0x00000000);
2162 /* XXX : not implemented */
2163 spr_register(env, SPR_405_DVC2, "DVC2",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_generic, &spr_write_generic,
2166 0x00000000);
2167 /* XXX : not implemented */
2168 spr_register(env, SPR_40x_IAC1, "IAC1",
2169 SPR_NOACCESS, SPR_NOACCESS,
2170 &spr_read_generic, &spr_write_generic,
2171 0x00000000);
2172 spr_register(env, SPR_40x_IAC2, "IAC2",
2173 SPR_NOACCESS, SPR_NOACCESS,
2174 &spr_read_generic, &spr_write_generic,
2175 0x00000000);
2176 /* XXX : not implemented */
2177 spr_register(env, SPR_405_IAC3, "IAC3",
2178 SPR_NOACCESS, SPR_NOACCESS,
2179 &spr_read_generic, &spr_write_generic,
2180 0x00000000);
2181 /* XXX : not implemented */
2182 spr_register(env, SPR_405_IAC4, "IAC4",
2183 SPR_NOACCESS, SPR_NOACCESS,
2184 &spr_read_generic, &spr_write_generic,
2185 0x00000000);
2186 /* Storage control */
2187 /* XXX: TODO: not implemented */
2188 spr_register(env, SPR_405_SLER, "SLER",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_generic, &spr_write_40x_sler,
2191 0x00000000);
2192 spr_register(env, SPR_40x_ZPR, "ZPR",
2193 SPR_NOACCESS, SPR_NOACCESS,
2194 &spr_read_generic, &spr_write_generic,
2195 0x00000000);
2196 /* XXX : not implemented */
2197 spr_register(env, SPR_405_SU0R, "SU0R",
2198 SPR_NOACCESS, SPR_NOACCESS,
2199 &spr_read_generic, &spr_write_generic,
2200 0x00000000);
2201 /* SPRG */
2202 spr_register(env, SPR_USPRG0, "USPRG0",
2203 &spr_read_ureg, SPR_NOACCESS,
2204 &spr_read_ureg, SPR_NOACCESS,
2205 0x00000000);
2206 spr_register(env, SPR_SPRG4, "SPRG4",
2207 SPR_NOACCESS, SPR_NOACCESS,
2208 &spr_read_generic, &spr_write_generic,
2209 0x00000000);
2210 spr_register(env, SPR_SPRG5, "SPRG5",
2211 SPR_NOACCESS, SPR_NOACCESS,
2212 spr_read_generic, &spr_write_generic,
2213 0x00000000);
2214 spr_register(env, SPR_SPRG6, "SPRG6",
2215 SPR_NOACCESS, SPR_NOACCESS,
2216 spr_read_generic, &spr_write_generic,
2217 0x00000000);
2218 spr_register(env, SPR_SPRG7, "SPRG7",
2219 SPR_NOACCESS, SPR_NOACCESS,
2220 spr_read_generic, &spr_write_generic,
2221 0x00000000);
2222 gen_spr_usprgh(env);
2223 }
2224
2225 /* SPR shared between PowerPC 401 & 403 implementations */
2226 static void gen_spr_401_403 (CPUPPCState *env)
2227 {
2228 /* Time base */
2229 spr_register(env, SPR_403_VTBL, "TBL",
2230 &spr_read_tbl, SPR_NOACCESS,
2231 &spr_read_tbl, SPR_NOACCESS,
2232 0x00000000);
2233 spr_register(env, SPR_403_TBL, "TBL",
2234 SPR_NOACCESS, SPR_NOACCESS,
2235 SPR_NOACCESS, &spr_write_tbl,
2236 0x00000000);
2237 spr_register(env, SPR_403_VTBU, "TBU",
2238 &spr_read_tbu, SPR_NOACCESS,
2239 &spr_read_tbu, SPR_NOACCESS,
2240 0x00000000);
2241 spr_register(env, SPR_403_TBU, "TBU",
2242 SPR_NOACCESS, SPR_NOACCESS,
2243 SPR_NOACCESS, &spr_write_tbu,
2244 0x00000000);
2245 /* Debug */
2246 /* not emulated, as QEMU do not emulate caches */
2247 spr_register(env, SPR_403_CDBCR, "CDBCR",
2248 SPR_NOACCESS, SPR_NOACCESS,
2249 &spr_read_generic, &spr_write_generic,
2250 0x00000000);
2251 }
2252
2253 /* SPR specific to PowerPC 401 implementation */
2254 static void gen_spr_401 (CPUPPCState *env)
2255 {
2256 /* Debug interface */
2257 /* XXX : not implemented */
2258 spr_register(env, SPR_40x_DBCR0, "DBCR",
2259 SPR_NOACCESS, SPR_NOACCESS,
2260 &spr_read_generic, &spr_write_40x_dbcr0,
2261 0x00000000);
2262 /* XXX : not implemented */
2263 spr_register(env, SPR_40x_DBSR, "DBSR",
2264 SPR_NOACCESS, SPR_NOACCESS,
2265 &spr_read_generic, &spr_write_clear,
2266 /* Last reset was system reset */
2267 0x00000300);
2268 /* XXX : not implemented */
2269 spr_register(env, SPR_40x_DAC1, "DAC",
2270 SPR_NOACCESS, SPR_NOACCESS,
2271 &spr_read_generic, &spr_write_generic,
2272 0x00000000);
2273 /* XXX : not implemented */
2274 spr_register(env, SPR_40x_IAC1, "IAC",
2275 SPR_NOACCESS, SPR_NOACCESS,
2276 &spr_read_generic, &spr_write_generic,
2277 0x00000000);
2278 /* Storage control */
2279 /* XXX: TODO: not implemented */
2280 spr_register(env, SPR_405_SLER, "SLER",
2281 SPR_NOACCESS, SPR_NOACCESS,
2282 &spr_read_generic, &spr_write_40x_sler,
2283 0x00000000);
2284 /* not emulated, as QEMU never does speculative access */
2285 spr_register(env, SPR_40x_SGR, "SGR",
2286 SPR_NOACCESS, SPR_NOACCESS,
2287 &spr_read_generic, &spr_write_generic,
2288 0xFFFFFFFF);
2289 /* not emulated, as QEMU do not emulate caches */
2290 spr_register(env, SPR_40x_DCWR, "DCWR",
2291 SPR_NOACCESS, SPR_NOACCESS,
2292 &spr_read_generic, &spr_write_generic,
2293 0x00000000);
2294 }
2295
2296 static void gen_spr_401x2 (CPUPPCState *env)
2297 {
2298 gen_spr_401(env);
2299 spr_register(env, SPR_40x_PID, "PID",
2300 SPR_NOACCESS, SPR_NOACCESS,
2301 &spr_read_generic, &spr_write_generic,
2302 0x00000000);
2303 spr_register(env, SPR_40x_ZPR, "ZPR",
2304 SPR_NOACCESS, SPR_NOACCESS,
2305 &spr_read_generic, &spr_write_generic,
2306 0x00000000);
2307 }
2308
2309 /* SPR specific to PowerPC 403 implementation */
2310 static void gen_spr_403 (CPUPPCState *env)
2311 {
2312 /* Debug interface */
2313 /* XXX : not implemented */
2314 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2315 SPR_NOACCESS, SPR_NOACCESS,
2316 &spr_read_generic, &spr_write_40x_dbcr0,
2317 0x00000000);
2318 /* XXX : not implemented */
2319 spr_register(env, SPR_40x_DBSR, "DBSR",
2320 SPR_NOACCESS, SPR_NOACCESS,
2321 &spr_read_generic, &spr_write_clear,
2322 /* Last reset was system reset */
2323 0x00000300);
2324 /* XXX : not implemented */
2325 spr_register(env, SPR_40x_DAC1, "DAC1",
2326 SPR_NOACCESS, SPR_NOACCESS,
2327 &spr_read_generic, &spr_write_generic,
2328 0x00000000);
2329 /* XXX : not implemented */
2330 spr_register(env, SPR_40x_DAC2, "DAC2",
2331 SPR_NOACCESS, SPR_NOACCESS,
2332 &spr_read_generic, &spr_write_generic,
2333 0x00000000);
2334 /* XXX : not implemented */
2335 spr_register(env, SPR_40x_IAC1, "IAC1",
2336 SPR_NOACCESS, SPR_NOACCESS,
2337 &spr_read_generic, &spr_write_generic,
2338 0x00000000);
2339 /* XXX : not implemented */
2340 spr_register(env, SPR_40x_IAC2, "IAC2",
2341 SPR_NOACCESS, SPR_NOACCESS,
2342 &spr_read_generic, &spr_write_generic,
2343 0x00000000);
2344 }
2345
2346 static void gen_spr_403_real (CPUPPCState *env)
2347 {
2348 spr_register(env, SPR_403_PBL1, "PBL1",
2349 SPR_NOACCESS, SPR_NOACCESS,
2350 &spr_read_403_pbr, &spr_write_403_pbr,
2351 0x00000000);
2352 spr_register(env, SPR_403_PBU1, "PBU1",
2353 SPR_NOACCESS, SPR_NOACCESS,
2354 &spr_read_403_pbr, &spr_write_403_pbr,
2355 0x00000000);
2356 spr_register(env, SPR_403_PBL2, "PBL2",
2357 SPR_NOACCESS, SPR_NOACCESS,
2358 &spr_read_403_pbr, &spr_write_403_pbr,
2359 0x00000000);
2360 spr_register(env, SPR_403_PBU2, "PBU2",
2361 SPR_NOACCESS, SPR_NOACCESS,
2362 &spr_read_403_pbr, &spr_write_403_pbr,
2363 0x00000000);
2364 }
2365
2366 static void gen_spr_403_mmu (CPUPPCState *env)
2367 {
2368 /* MMU */
2369 spr_register(env, SPR_40x_PID, "PID",
2370 SPR_NOACCESS, SPR_NOACCESS,
2371 &spr_read_generic, &spr_write_generic,
2372 0x00000000);
2373 spr_register(env, SPR_40x_ZPR, "ZPR",
2374 SPR_NOACCESS, SPR_NOACCESS,
2375 &spr_read_generic, &spr_write_generic,
2376 0x00000000);
2377 }
2378
2379 /* SPR specific to PowerPC compression coprocessor extension */
2380 static void gen_spr_compress (CPUPPCState *env)
2381 {
2382 /* XXX : not implemented */
2383 spr_register(env, SPR_401_SKR, "SKR",
2384 SPR_NOACCESS, SPR_NOACCESS,
2385 &spr_read_generic, &spr_write_generic,
2386 0x00000000);
2387 }
2388
2389 static void gen_spr_5xx_8xx (CPUPPCState *env)
2390 {
2391 /* Exception processing */
2392 spr_register_kvm(env, SPR_DSISR, "DSISR",
2393 SPR_NOACCESS, SPR_NOACCESS,
2394 &spr_read_generic, &spr_write_generic,
2395 KVM_REG_PPC_DSISR, 0x00000000);
2396 spr_register_kvm(env, SPR_DAR, "DAR",
2397 SPR_NOACCESS, SPR_NOACCESS,
2398 &spr_read_generic, &spr_write_generic,
2399 KVM_REG_PPC_DAR, 0x00000000);
2400 /* Timer */
2401 spr_register(env, SPR_DECR, "DECR",
2402 SPR_NOACCESS, SPR_NOACCESS,
2403 &spr_read_decr, &spr_write_decr,
2404 0x00000000);
2405 /* XXX : not implemented */
2406 spr_register(env, SPR_MPC_EIE, "EIE",
2407 SPR_NOACCESS, SPR_NOACCESS,
2408 &spr_read_generic, &spr_write_generic,
2409 0x00000000);
2410 /* XXX : not implemented */
2411 spr_register(env, SPR_MPC_EID, "EID",
2412 SPR_NOACCESS, SPR_NOACCESS,
2413 &spr_read_generic, &spr_write_generic,
2414 0x00000000);
2415 /* XXX : not implemented */
2416 spr_register(env, SPR_MPC_NRI, "NRI",
2417 SPR_NOACCESS, SPR_NOACCESS,
2418 &spr_read_generic, &spr_write_generic,
2419 0x00000000);
2420 /* XXX : not implemented */
2421 spr_register(env, SPR_MPC_CMPA, "CMPA",
2422 SPR_NOACCESS, SPR_NOACCESS,
2423 &spr_read_generic, &spr_write_generic,
2424 0x00000000);
2425 /* XXX : not implemented */
2426 spr_register(env, SPR_MPC_CMPB, "CMPB",
2427 SPR_NOACCESS, SPR_NOACCESS,
2428 &spr_read_generic, &spr_write_generic,
2429 0x00000000);
2430 /* XXX : not implemented */
2431 spr_register(env, SPR_MPC_CMPC, "CMPC",
2432 SPR_NOACCESS, SPR_NOACCESS,
2433 &spr_read_generic, &spr_write_generic,
2434 0x00000000);
2435 /* XXX : not implemented */
2436 spr_register(env, SPR_MPC_CMPD, "CMPD",
2437 SPR_NOACCESS, SPR_NOACCESS,
2438 &spr_read_generic, &spr_write_generic,
2439 0x00000000);
2440 /* XXX : not implemented */
2441 spr_register(env, SPR_MPC_ECR, "ECR",
2442 SPR_NOACCESS, SPR_NOACCESS,
2443 &spr_read_generic, &spr_write_generic,
2444 0x00000000);
2445 /* XXX : not implemented */
2446 spr_register(env, SPR_MPC_DER, "DER",
2447 SPR_NOACCESS, SPR_NOACCESS,
2448 &spr_read_generic, &spr_write_generic,
2449 0x00000000);
2450 /* XXX : not implemented */
2451 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2452 SPR_NOACCESS, SPR_NOACCESS,
2453 &spr_read_generic, &spr_write_generic,
2454 0x00000000);
2455 /* XXX : not implemented */
2456 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2457 SPR_NOACCESS, SPR_NOACCESS,
2458 &spr_read_generic, &spr_write_generic,
2459 0x00000000);
2460 /* XXX : not implemented */
2461 spr_register(env, SPR_MPC_CMPE, "CMPE",
2462 SPR_NOACCESS, SPR_NOACCESS,
2463 &spr_read_generic, &spr_write_generic,
2464 0x00000000);
2465 /* XXX : not implemented */
2466 spr_register(env, SPR_MPC_CMPF, "CMPF",
2467 SPR_NOACCESS, SPR_NOACCESS,
2468 &spr_read_generic, &spr_write_generic,
2469 0x00000000);
2470 /* XXX : not implemented */
2471 spr_register(env, SPR_MPC_CMPG, "CMPG",
2472 SPR_NOACCESS, SPR_NOACCESS,
2473 &spr_read_generic, &spr_write_generic,
2474 0x00000000);
2475 /* XXX : not implemented */
2476 spr_register(env, SPR_MPC_CMPH, "CMPH",
2477 SPR_NOACCESS, SPR_NOACCESS,
2478 &spr_read_generic, &spr_write_generic,
2479 0x00000000);
2480 /* XXX : not implemented */
2481 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2482 SPR_NOACCESS, SPR_NOACCESS,
2483 &spr_read_generic, &spr_write_generic,
2484 0x00000000);
2485 /* XXX : not implemented */
2486 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2487 SPR_NOACCESS, SPR_NOACCESS,
2488 &spr_read_generic, &spr_write_generic,
2489 0x00000000);
2490 /* XXX : not implemented */
2491 spr_register(env, SPR_MPC_BAR, "BAR",
2492 SPR_NOACCESS, SPR_NOACCESS,
2493 &spr_read_generic, &spr_write_generic,
2494 0x00000000);
2495 /* XXX : not implemented */
2496 spr_register(env, SPR_MPC_DPDR, "DPDR",
2497 SPR_NOACCESS, SPR_NOACCESS,
2498 &spr_read_generic, &spr_write_generic,
2499 0x00000000);
2500 /* XXX : not implemented */
2501 spr_register(env, SPR_MPC_IMMR, "IMMR",
2502 SPR_NOACCESS, SPR_NOACCESS,
2503 &spr_read_generic, &spr_write_generic,
2504 0x00000000);
2505 }
2506
2507 static void gen_spr_5xx (CPUPPCState *env)
2508 {
2509 /* XXX : not implemented */
2510 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2511 SPR_NOACCESS, SPR_NOACCESS,
2512 &spr_read_generic, &spr_write_generic,
2513 0x00000000);
2514 /* XXX : not implemented */
2515 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2516 SPR_NOACCESS, SPR_NOACCESS,
2517 &spr_read_generic, &spr_write_generic,
2518 0x00000000);
2519 /* XXX : not implemented */
2520 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2521 SPR_NOACCESS, SPR_NOACCESS,
2522 &spr_read_generic, &spr_write_generic,
2523 0x00000000);
2524 /* XXX : not implemented */
2525 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2526 SPR_NOACCESS, SPR_NOACCESS,
2527 &spr_read_generic, &spr_write_generic,
2528 0x00000000);
2529 /* XXX : not implemented */
2530 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2531 SPR_NOACCESS, SPR_NOACCESS,
2532 &spr_read_generic, &spr_write_generic,
2533 0x00000000);
2534 /* XXX : not implemented */
2535 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2536 SPR_NOACCESS, SPR_NOACCESS,
2537 &spr_read_generic, &spr_write_generic,
2538 0x00000000);
2539 /* XXX : not implemented */
2540 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2541 SPR_NOACCESS, SPR_NOACCESS,
2542 &spr_read_generic, &spr_write_generic,
2543 0x00000000);
2544 /* XXX : not implemented */
2545 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2546 SPR_NOACCESS, SPR_NOACCESS,
2547 &spr_read_generic, &spr_write_generic,
2548 0x00000000);
2549 /* XXX : not implemented */
2550 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2551 SPR_NOACCESS, SPR_NOACCESS,
2552 &spr_read_generic, &spr_write_generic,
2553 0x00000000);
2554 /* XXX : not implemented */
2555 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2556 SPR_NOACCESS, SPR_NOACCESS,
2557 &spr_read_generic, &spr_write_generic,
2558 0x00000000);
2559 /* XXX : not implemented */
2560 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2561 SPR_NOACCESS, SPR_NOACCESS,
2562 &spr_read_generic, &spr_write_generic,
2563 0x00000000);
2564 /* XXX : not implemented */
2565 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2566 SPR_NOACCESS, SPR_NOACCESS,
2567 &spr_read_generic, &spr_write_generic,
2568 0x00000000);
2569 /* XXX : not implemented */
2570 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2571 SPR_NOACCESS, SPR_NOACCESS,
2572 &spr_read_generic, &spr_write_generic,
2573 0x00000000);
2574 /* XXX : not implemented */
2575 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2576 SPR_NOACCESS, SPR_NOACCESS,
2577 &spr_read_generic, &spr_write_generic,
2578 0x00000000);
2579 /* XXX : not implemented */
2580 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2581 SPR_NOACCESS, SPR_NOACCESS,
2582 &spr_read_generic, &spr_write_generic,
2583 0x00000000);
2584 /* XXX : not implemented */
2585 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2586 SPR_NOACCESS, SPR_NOACCESS,
2587 &spr_read_generic, &spr_write_generic,
2588 0x00000000);
2589 /* XXX : not implemented */
2590 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2591 SPR_NOACCESS, SPR_NOACCESS,
2592 &spr_read_generic, &spr_write_generic,
2593 0x00000000);
2594 /* XXX : not implemented */
2595 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2596 SPR_NOACCESS, SPR_NOACCESS,
2597 &spr_read_generic, &spr_write_generic,
2598 0x00000000);
2599 /* XXX : not implemented */
2600 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2601 SPR_NOACCESS, SPR_NOACCESS,
2602 &spr_read_generic, &spr_write_generic,
2603 0x00000000);
2604 /* XXX : not implemented */
2605 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2606 SPR_NOACCESS, SPR_NOACCESS,
2607 &spr_read_generic, &spr_write_generic,
2608 0x00000000);
2609 /* XXX : not implemented */
2610 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2611 SPR_NOACCESS, SPR_NOACCESS,
2612 &spr_read_generic, &spr_write_generic,
2613 0x00000000);
2614 }
2615
2616 static void gen_spr_8xx (CPUPPCState *env)
2617 {
2618 /* XXX : not implemented */
2619 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2620 SPR_NOACCESS, SPR_NOACCESS,
2621 &spr_read_generic, &spr_write_generic,
2622 0x00000000);
2623 /* XXX : not implemented */
2624 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2625 SPR_NOACCESS, SPR_NOACCESS,
2626 &spr_read_generic, &spr_write_generic,
2627 0x00000000);
2628 /* XXX : not implemented */
2629 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2630 SPR_NOACCESS, SPR_NOACCESS,
2631 &spr_read_generic, &spr_write_generic,
2632 0x00000000);
2633 /* XXX : not implemented */
2634 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2635 SPR_NOACCESS, SPR_NOACCESS,
2636 &spr_read_generic, &spr_write_generic,
2637 0x00000000);
2638 /* XXX : not implemented */
2639 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2640 SPR_NOACCESS, SPR_NOACCESS,
2641 &spr_read_generic, &spr_write_generic,
2642 0x00000000);
2643 /* XXX : not implemented */
2644 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2645 SPR_NOACCESS, SPR_NOACCESS,
2646 &spr_read_generic, &spr_write_generic,
2647 0x00000000);
2648 /* XXX : not implemented */
2649 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2650 SPR_NOACCESS, SPR_NOACCESS,
2651 &spr_read_generic, &spr_write_generic,
2652 0x00000000);
2653 /* XXX : not implemented */
2654 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2655 SPR_NOACCESS, SPR_NOACCESS,
2656 &spr_read_generic, &spr_write_generic,
2657 0x00000000);
2658 /* XXX : not implemented */
2659 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2660 SPR_NOACCESS, SPR_NOACCESS,
2661 &spr_read_generic, &spr_write_generic,
2662 0x00000000);
2663 /* XXX : not implemented */
2664 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2665 SPR_NOACCESS, SPR_NOACCESS,
2666 &spr_read_generic, &spr_write_generic,
2667 0x00000000);
2668 /* XXX : not implemented */
2669 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2670 SPR_NOACCESS, SPR_NOACCESS,
2671 &spr_read_generic, &spr_write_generic,
2672 0x00000000);
2673 /* XXX : not implemented */
2674 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2675 SPR_NOACCESS, SPR_NOACCESS,
2676 &spr_read_generic, &spr_write_generic,
2677 0x00000000);
2678 /* XXX : not implemented */
2679 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2680 SPR_NOACCESS, SPR_NOACCESS,
2681 &spr_read_generic, &spr_write_generic,
2682 0x00000000);
2683 /* XXX : not implemented */
2684 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2685 SPR_NOACCESS, SPR_NOACCESS,
2686 &spr_read_generic, &spr_write_generic,
2687 0x00000000);
2688 /* XXX : not implemented */
2689 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2690 SPR_NOACCESS, SPR_NOACCESS,
2691 &spr_read_generic, &spr_write_generic,
2692 0x00000000);
2693 /* XXX : not implemented */
2694 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2695 SPR_NOACCESS, SPR_NOACCESS,
2696 &spr_read_generic, &spr_write_generic,
2697 0x00000000);
2698 /* XXX : not implemented */
2699 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2700 SPR_NOACCESS, SPR_NOACCESS,
2701 &spr_read_generic, &spr_write_generic,
2702 0x00000000);
2703 /* XXX : not implemented */
2704 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2705 SPR_NOACCESS, SPR_NOACCESS,
2706 &spr_read_generic, &spr_write_generic,
2707 0x00000000);
2708 /* XXX : not implemented */
2709 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2710 SPR_NOACCESS, SPR_NOACCESS,
2711 &spr_read_generic, &spr_write_generic,
2712 0x00000000);
2713 /* XXX : not implemented */
2714 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2715 SPR_NOACCESS, SPR_NOACCESS,
2716 &spr_read_generic, &spr_write_generic,
2717 0x00000000);
2718 /* XXX : not implemented */
2719 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2720 SPR_NOACCESS, SPR_NOACCESS,
2721 &spr_read_generic, &spr_write_generic,
2722 0x00000000);
2723 /* XXX : not implemented */
2724 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2725 SPR_NOACCESS, SPR_NOACCESS,
2726 &spr_read_generic, &spr_write_generic,
2727 0x00000000);
2728 /* XXX : not implemented */
2729 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2730 SPR_NOACCESS, SPR_NOACCESS,
2731 &spr_read_generic, &spr_write_generic,
2732 0x00000000);
2733 /* XXX : not implemented */
2734 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2735 SPR_NOACCESS, SPR_NOACCESS,
2736 &spr_read_generic, &spr_write_generic,
2737 0x00000000);
2738 /* XXX : not implemented */
2739 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2740 SPR_NOACCESS, SPR_NOACCESS,
2741 &spr_read_generic, &spr_write_generic,
2742 0x00000000);
2743 }
2744
2745 // XXX: TODO
2746 /*
2747 * AMR => SPR 29 (Power 2.04)
2748 * CTRL => SPR 136 (Power 2.04)
2749 * CTRL => SPR 152 (Power 2.04)
2750 * SCOMC => SPR 276 (64 bits ?)
2751 * SCOMD => SPR 277 (64 bits ?)
2752 * TBU40 => SPR 286 (Power 2.04 hypv)
2753 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2754 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2755 * HDSISR => SPR 306 (Power 2.04 hypv)
2756 * HDAR => SPR 307 (Power 2.04 hypv)
2757 * PURR => SPR 309 (Power 2.04 hypv)
2758 * HDEC => SPR 310 (Power 2.04 hypv)
2759 * HIOR => SPR 311 (hypv)
2760 * RMOR => SPR 312 (970)
2761 * HRMOR => SPR 313 (Power 2.04 hypv)
2762 * HSRR0 => SPR 314 (Power 2.04 hypv)
2763 * HSRR1 => SPR 315 (Power 2.04 hypv)
2764 * LPIDR => SPR 317 (970)
2765 * EPR => SPR 702 (Power 2.04 emb)
2766 * perf => 768-783 (Power 2.04)
2767 * perf => 784-799 (Power 2.04)
2768 * PPR => SPR 896 (Power 2.04)
2769 * EPLC => SPR 947 (Power 2.04 emb)
2770 * EPSC => SPR 948 (Power 2.04 emb)
2771 * DABRX => 1015 (Power 2.04 hypv)
2772 * FPECR => SPR 1022 (?)
2773 * ... and more (thermal management, performance counters, ...)
2774 */
2775
2776 /*****************************************************************************/
2777 /* Exception vectors models */
2778 static void init_excp_4xx_real (CPUPPCState *env)
2779 {
2780 #if !defined(CONFIG_USER_ONLY)
2781 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2782 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2783 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2784 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2785 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2786 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2787 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2788 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2789 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2790 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2791 env->ivor_mask = 0x0000FFF0UL;
2792 env->ivpr_mask = 0xFFFF0000UL;
2793 /* Hardware reset vector */
2794 env->hreset_vector = 0xFFFFFFFCUL;
2795 #endif
2796 }
2797
2798 static void init_excp_4xx_softmmu (CPUPPCState *env)
2799 {
2800 #if !defined(CONFIG_USER_ONLY)
2801 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2802 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2803 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2804 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2805 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2806 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2807 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2808 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2809 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2810 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2811 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2812 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2813 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2814 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2815 env->ivor_mask = 0x0000FFF0UL;
2816 env->ivpr_mask = 0xFFFF0000UL;
2817 /* Hardware reset vector */
2818 env->hreset_vector = 0xFFFFFFFCUL;
2819 #endif
2820 }
2821
2822 static void init_excp_MPC5xx (CPUPPCState *env)
2823 {
2824 #if !defined(CONFIG_USER_ONLY)
2825 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2826 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2827 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2828 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2829 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2830 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2831 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2832 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2833 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2834 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2835 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2836 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2837 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2838 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2839 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2840 env->ivor_mask = 0x0000FFF0UL;
2841 env->ivpr_mask = 0xFFFF0000UL;
2842 /* Hardware reset vector */
2843 env->hreset_vector = 0x00000100UL;
2844 #endif
2845 }
2846
2847 static void init_excp_MPC8xx (CPUPPCState *env)
2848 {
2849 #if !defined(CONFIG_USER_ONLY)
2850 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2851 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2852 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2853 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2854 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2855 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2856 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2857 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2858 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2859 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2860 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2861 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2862 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2863 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2864 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2865 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2866 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2867 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2868 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2869 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2870 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2871 env->ivor_mask = 0x0000FFF0UL;
2872 env->ivpr_mask = 0xFFFF0000UL;
2873 /* Hardware reset vector */
2874 env->hreset_vector = 0x00000100UL;
2875 #endif
2876 }
2877
2878 static void init_excp_G2 (CPUPPCState *env)
2879 {
2880 #if !defined(CONFIG_USER_ONLY)
2881 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2882 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2883 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2884 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2885 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2886 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2887 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2888 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2889 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2890 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2891 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2892 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2893 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2894 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2895 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2896 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2897 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2898 /* Hardware reset vector */
2899 env->hreset_vector = 0x00000100UL;
2900 #endif
2901 }
2902
2903 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2904 {
2905 #if !defined(CONFIG_USER_ONLY)
2906 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2907 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2908 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2909 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2910 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2911 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2912 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2913 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2914 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2915 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2916 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2917 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2918 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2919 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2920 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2921 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2922 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2923 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2924 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2925 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2926 env->ivor_mask = 0x0000FFF7UL;
2927 env->ivpr_mask = ivpr_mask;
2928 /* Hardware reset vector */
2929 env->hreset_vector = 0xFFFFFFFCUL;
2930 #endif
2931 }
2932
2933 static void init_excp_BookE (CPUPPCState *env)
2934 {
2935 #if !defined(CONFIG_USER_ONLY)
2936 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2937 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2938 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2939 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2940 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2941 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2942 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2943 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2944 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2945 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2946 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2947 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2948 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2949 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2950 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2951 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2952 env->ivor_mask = 0x0000FFF0UL;
2953 env->ivpr_mask = 0xFFFF0000UL;
2954 /* Hardware reset vector */
2955 env->hreset_vector = 0xFFFFFFFCUL;
2956 #endif
2957 }
2958
2959 static void init_excp_601 (CPUPPCState *env)
2960 {
2961 #if !defined(CONFIG_USER_ONLY)
2962 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2963 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2964 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2965 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2966 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2967 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2968 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2969 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2970 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2971 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2972 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2973 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2974 /* Hardware reset vector */
2975 env->hreset_vector = 0x00000100UL;
2976 #endif
2977 }
2978
2979 static void init_excp_602 (CPUPPCState *env)
2980 {
2981 #if !defined(CONFIG_USER_ONLY)
2982 /* XXX: exception prefix has a special behavior on 602 */
2983 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2984 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2985 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2986 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2987 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2988 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2989 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2990 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2991 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2992 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2993 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2994 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2995 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2996 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2997 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2998 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2999 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
3000 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
3001 /* Hardware reset vector */
3002 env->hreset_vector = 0x00000100UL;
3003 #endif
3004 }
3005
3006 static void init_excp_603 (CPUPPCState *env)
3007 {
3008 #if !defined(CONFIG_USER_ONLY)
3009 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3010 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3011 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3012 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3013 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3014 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3015 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3016 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3017 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3018 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3019 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3020 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3021 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3022 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3023 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3024 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3025 /* Hardware reset vector */
3026 env->hreset_vector = 0x00000100UL;
3027 #endif
3028 }
3029
3030 static void init_excp_604 (CPUPPCState *env)
3031 {
3032 #if !defined(CONFIG_USER_ONLY)
3033 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3034 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3035 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3036 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3037 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3038 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3039 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3040 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3041 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3042 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3043 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3044 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3045 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3046 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3047 /* Hardware reset vector */
3048 env->hreset_vector = 0x00000100UL;
3049 #endif
3050 }
3051
3052 static void init_excp_7x0 (CPUPPCState *env)
3053 {
3054 #if !defined(CONFIG_USER_ONLY)
3055 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3056 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3057 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3058 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3059 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3060 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3061 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3062 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3063 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3064 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3065 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3066 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3067 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3068 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3069 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3070 /* Hardware reset vector */
3071 env->hreset_vector = 0x00000100UL;
3072 #endif
3073 }
3074
3075 static void init_excp_750cl (CPUPPCState *env)
3076 {
3077 #if !defined(CONFIG_USER_ONLY)
3078 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3079 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3080 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3081 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3082 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3083 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3084 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3085 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3086 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3087 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3088 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3089 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3090 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3091 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3092 /* Hardware reset vector */
3093 env->hreset_vector = 0x00000100UL;
3094 #endif
3095 }
3096
3097 static void init_excp_750cx (CPUPPCState *env)
3098 {
3099 #if !defined(CONFIG_USER_ONLY)
3100 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3101 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3102 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3103 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3104 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3105 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3106 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3107 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3108 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3109 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3110 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3111 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3112 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3113 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3114 /* Hardware reset vector */
3115 env->hreset_vector = 0x00000100UL;
3116 #endif
3117 }
3118
3119 /* XXX: Check if this is correct */
3120 static void init_excp_7x5 (CPUPPCState *env)
3121 {
3122 #if !defined(CONFIG_USER_ONLY)
3123 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3124 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3125 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3126 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3127 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3128 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3129 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3130 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3131 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3132 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3133 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;